1 /* Intel 386 target-dependent stuff. 2 3 Copyright (C) 1988-2016 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "opcode/i386.h" 22 #include "arch-utils.h" 23 #include "command.h" 24 #include "dummy-frame.h" 25 #include "dwarf2-frame.h" 26 #include "doublest.h" 27 #include "frame.h" 28 #include "frame-base.h" 29 #include "frame-unwind.h" 30 #include "inferior.h" 31 #include "infrun.h" 32 #include "gdbcmd.h" 33 #include "gdbcore.h" 34 #include "gdbtypes.h" 35 #include "objfiles.h" 36 #include "osabi.h" 37 #include "regcache.h" 38 #include "reggroups.h" 39 #include "regset.h" 40 #include "symfile.h" 41 #include "symtab.h" 42 #include "target.h" 43 #include "value.h" 44 #include "dis-asm.h" 45 #include "disasm.h" 46 #include "remote.h" 47 #include "i386-tdep.h" 48 #include "i387-tdep.h" 49 #include "x86-xstate.h" 50 51 #include "record.h" 52 #include "record-full.h" 53 #include "features/i386/i386.c" 54 #include "features/i386/i386-avx.c" 55 #include "features/i386/i386-mpx.c" 56 #include "features/i386/i386-avx-mpx.c" 57 #include "features/i386/i386-avx512.c" 58 #include "features/i386/i386-mmx.c" 59 60 #include "ax.h" 61 #include "ax-gdb.h" 62 63 #include "stap-probe.h" 64 #include "user-regs.h" 65 #include "cli/cli-utils.h" 66 #include "expression.h" 67 #include "parser-defs.h" 68 #include <ctype.h> 69 70 /* Register names. */ 71 72 static const char *i386_register_names[] = 73 { 74 "eax", "ecx", "edx", "ebx", 75 "esp", "ebp", "esi", "edi", 76 "eip", "eflags", "cs", "ss", 77 "ds", "es", "fs", "gs", 78 "st0", "st1", "st2", "st3", 79 "st4", "st5", "st6", "st7", 80 "fctrl", "fstat", "ftag", "fiseg", 81 "fioff", "foseg", "fooff", "fop", 82 "xmm0", "xmm1", "xmm2", "xmm3", 83 "xmm4", "xmm5", "xmm6", "xmm7", 84 "mxcsr" 85 }; 86 87 static const char *i386_zmm_names[] = 88 { 89 "zmm0", "zmm1", "zmm2", "zmm3", 90 "zmm4", "zmm5", "zmm6", "zmm7" 91 }; 92 93 static const char *i386_zmmh_names[] = 94 { 95 "zmm0h", "zmm1h", "zmm2h", "zmm3h", 96 "zmm4h", "zmm5h", "zmm6h", "zmm7h" 97 }; 98 99 static const char *i386_k_names[] = 100 { 101 "k0", "k1", "k2", "k3", 102 "k4", "k5", "k6", "k7" 103 }; 104 105 static const char *i386_ymm_names[] = 106 { 107 "ymm0", "ymm1", "ymm2", "ymm3", 108 "ymm4", "ymm5", "ymm6", "ymm7", 109 }; 110 111 static const char *i386_ymmh_names[] = 112 { 113 "ymm0h", "ymm1h", "ymm2h", "ymm3h", 114 "ymm4h", "ymm5h", "ymm6h", "ymm7h", 115 }; 116 117 static const char *i386_mpx_names[] = 118 { 119 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" 120 }; 121 122 /* Register names for MPX pseudo-registers. */ 123 124 static const char *i386_bnd_names[] = 125 { 126 "bnd0", "bnd1", "bnd2", "bnd3" 127 }; 128 129 /* Register names for MMX pseudo-registers. */ 130 131 static const char *i386_mmx_names[] = 132 { 133 "mm0", "mm1", "mm2", "mm3", 134 "mm4", "mm5", "mm6", "mm7" 135 }; 136 137 /* Register names for byte pseudo-registers. */ 138 139 static const char *i386_byte_names[] = 140 { 141 "al", "cl", "dl", "bl", 142 "ah", "ch", "dh", "bh" 143 }; 144 145 /* Register names for word pseudo-registers. */ 146 147 static const char *i386_word_names[] = 148 { 149 "ax", "cx", "dx", "bx", 150 "", "bp", "si", "di" 151 }; 152 153 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have 154 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition, 155 we have 16 upper ZMM regs that have to be handled differently. */ 156 157 const int num_lower_zmm_regs = 16; 158 159 /* MMX register? */ 160 161 static int 162 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) 163 { 164 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 165 int mm0_regnum = tdep->mm0_regnum; 166 167 if (mm0_regnum < 0) 168 return 0; 169 170 regnum -= mm0_regnum; 171 return regnum >= 0 && regnum < tdep->num_mmx_regs; 172 } 173 174 /* Byte register? */ 175 176 int 177 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) 178 { 179 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 180 181 regnum -= tdep->al_regnum; 182 return regnum >= 0 && regnum < tdep->num_byte_regs; 183 } 184 185 /* Word register? */ 186 187 int 188 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) 189 { 190 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 191 192 regnum -= tdep->ax_regnum; 193 return regnum >= 0 && regnum < tdep->num_word_regs; 194 } 195 196 /* Dword register? */ 197 198 int 199 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) 200 { 201 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 202 int eax_regnum = tdep->eax_regnum; 203 204 if (eax_regnum < 0) 205 return 0; 206 207 regnum -= eax_regnum; 208 return regnum >= 0 && regnum < tdep->num_dword_regs; 209 } 210 211 /* AVX512 register? */ 212 213 int 214 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum) 215 { 216 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 217 int zmm0h_regnum = tdep->zmm0h_regnum; 218 219 if (zmm0h_regnum < 0) 220 return 0; 221 222 regnum -= zmm0h_regnum; 223 return regnum >= 0 && regnum < tdep->num_zmm_regs; 224 } 225 226 int 227 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum) 228 { 229 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 230 int zmm0_regnum = tdep->zmm0_regnum; 231 232 if (zmm0_regnum < 0) 233 return 0; 234 235 regnum -= zmm0_regnum; 236 return regnum >= 0 && regnum < tdep->num_zmm_regs; 237 } 238 239 int 240 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum) 241 { 242 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 243 int k0_regnum = tdep->k0_regnum; 244 245 if (k0_regnum < 0) 246 return 0; 247 248 regnum -= k0_regnum; 249 return regnum >= 0 && regnum < I387_NUM_K_REGS; 250 } 251 252 static int 253 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) 254 { 255 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 256 int ymm0h_regnum = tdep->ymm0h_regnum; 257 258 if (ymm0h_regnum < 0) 259 return 0; 260 261 regnum -= ymm0h_regnum; 262 return regnum >= 0 && regnum < tdep->num_ymm_regs; 263 } 264 265 /* AVX register? */ 266 267 int 268 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) 269 { 270 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 271 int ymm0_regnum = tdep->ymm0_regnum; 272 273 if (ymm0_regnum < 0) 274 return 0; 275 276 regnum -= ymm0_regnum; 277 return regnum >= 0 && regnum < tdep->num_ymm_regs; 278 } 279 280 static int 281 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) 282 { 283 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 284 int ymm16h_regnum = tdep->ymm16h_regnum; 285 286 if (ymm16h_regnum < 0) 287 return 0; 288 289 regnum -= ymm16h_regnum; 290 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; 291 } 292 293 int 294 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) 295 { 296 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 297 int ymm16_regnum = tdep->ymm16_regnum; 298 299 if (ymm16_regnum < 0) 300 return 0; 301 302 regnum -= ymm16_regnum; 303 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; 304 } 305 306 /* BND register? */ 307 308 int 309 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum) 310 { 311 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 312 int bnd0_regnum = tdep->bnd0_regnum; 313 314 if (bnd0_regnum < 0) 315 return 0; 316 317 regnum -= bnd0_regnum; 318 return regnum >= 0 && regnum < I387_NUM_BND_REGS; 319 } 320 321 /* SSE register? */ 322 323 int 324 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) 325 { 326 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 327 int num_xmm_regs = I387_NUM_XMM_REGS (tdep); 328 329 if (num_xmm_regs == 0) 330 return 0; 331 332 regnum -= I387_XMM0_REGNUM (tdep); 333 return regnum >= 0 && regnum < num_xmm_regs; 334 } 335 336 /* XMM_512 register? */ 337 338 int 339 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) 340 { 341 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 342 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep); 343 344 if (num_xmm_avx512_regs == 0) 345 return 0; 346 347 regnum -= I387_XMM16_REGNUM (tdep); 348 return regnum >= 0 && regnum < num_xmm_avx512_regs; 349 } 350 351 static int 352 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) 353 { 354 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 355 356 if (I387_NUM_XMM_REGS (tdep) == 0) 357 return 0; 358 359 return (regnum == I387_MXCSR_REGNUM (tdep)); 360 } 361 362 /* FP register? */ 363 364 int 365 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) 366 { 367 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 368 369 if (I387_ST0_REGNUM (tdep) < 0) 370 return 0; 371 372 return (I387_ST0_REGNUM (tdep) <= regnum 373 && regnum < I387_FCTRL_REGNUM (tdep)); 374 } 375 376 int 377 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) 378 { 379 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 380 381 if (I387_ST0_REGNUM (tdep) < 0) 382 return 0; 383 384 return (I387_FCTRL_REGNUM (tdep) <= regnum 385 && regnum < I387_XMM0_REGNUM (tdep)); 386 } 387 388 /* BNDr (raw) register? */ 389 390 static int 391 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum) 392 { 393 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 394 395 if (I387_BND0R_REGNUM (tdep) < 0) 396 return 0; 397 398 regnum -= tdep->bnd0r_regnum; 399 return regnum >= 0 && regnum < I387_NUM_BND_REGS; 400 } 401 402 /* BND control register? */ 403 404 static int 405 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum) 406 { 407 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 408 409 if (I387_BNDCFGU_REGNUM (tdep) < 0) 410 return 0; 411 412 regnum -= I387_BNDCFGU_REGNUM (tdep); 413 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS; 414 } 415 416 /* Return the name of register REGNUM, or the empty string if it is 417 an anonymous register. */ 418 419 static const char * 420 i386_register_name (struct gdbarch *gdbarch, int regnum) 421 { 422 /* Hide the upper YMM registers. */ 423 if (i386_ymmh_regnum_p (gdbarch, regnum)) 424 return ""; 425 426 /* Hide the upper YMM16-31 registers. */ 427 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum)) 428 return ""; 429 430 /* Hide the upper ZMM registers. */ 431 if (i386_zmmh_regnum_p (gdbarch, regnum)) 432 return ""; 433 434 return tdesc_register_name (gdbarch, regnum); 435 } 436 437 /* Return the name of register REGNUM. */ 438 439 const char * 440 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) 441 { 442 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 443 if (i386_bnd_regnum_p (gdbarch, regnum)) 444 return i386_bnd_names[regnum - tdep->bnd0_regnum]; 445 if (i386_mmx_regnum_p (gdbarch, regnum)) 446 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; 447 else if (i386_ymm_regnum_p (gdbarch, regnum)) 448 return i386_ymm_names[regnum - tdep->ymm0_regnum]; 449 else if (i386_zmm_regnum_p (gdbarch, regnum)) 450 return i386_zmm_names[regnum - tdep->zmm0_regnum]; 451 else if (i386_byte_regnum_p (gdbarch, regnum)) 452 return i386_byte_names[regnum - tdep->al_regnum]; 453 else if (i386_word_regnum_p (gdbarch, regnum)) 454 return i386_word_names[regnum - tdep->ax_regnum]; 455 456 internal_error (__FILE__, __LINE__, _("invalid regnum")); 457 } 458 459 /* Convert a dbx register number REG to the appropriate register 460 number used by GDB. */ 461 462 static int 463 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) 464 { 465 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 466 467 /* This implements what GCC calls the "default" register map 468 (dbx_register_map[]). */ 469 470 if (reg >= 0 && reg <= 7) 471 { 472 /* General-purpose registers. The debug info calls %ebp 473 register 4, and %esp register 5. */ 474 if (reg == 4) 475 return 5; 476 else if (reg == 5) 477 return 4; 478 else return reg; 479 } 480 else if (reg >= 12 && reg <= 19) 481 { 482 /* Floating-point registers. */ 483 return reg - 12 + I387_ST0_REGNUM (tdep); 484 } 485 else if (reg >= 21 && reg <= 28) 486 { 487 /* SSE registers. */ 488 int ymm0_regnum = tdep->ymm0_regnum; 489 490 if (ymm0_regnum >= 0 491 && i386_xmm_regnum_p (gdbarch, reg)) 492 return reg - 21 + ymm0_regnum; 493 else 494 return reg - 21 + I387_XMM0_REGNUM (tdep); 495 } 496 else if (reg >= 29 && reg <= 36) 497 { 498 /* MMX registers. */ 499 return reg - 29 + I387_MM0_REGNUM (tdep); 500 } 501 502 /* This will hopefully provoke a warning. */ 503 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); 504 } 505 506 /* Convert SVR4 DWARF register number REG to the appropriate register number 507 used by GDB. */ 508 509 static int 510 i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) 511 { 512 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 513 514 /* This implements the GCC register map that tries to be compatible 515 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ 516 517 /* The SVR4 register numbering includes %eip and %eflags, and 518 numbers the floating point registers differently. */ 519 if (reg >= 0 && reg <= 9) 520 { 521 /* General-purpose registers. */ 522 return reg; 523 } 524 else if (reg >= 11 && reg <= 18) 525 { 526 /* Floating-point registers. */ 527 return reg - 11 + I387_ST0_REGNUM (tdep); 528 } 529 else if (reg >= 21 && reg <= 36) 530 { 531 /* The SSE and MMX registers have the same numbers as with dbx. */ 532 return i386_dbx_reg_to_regnum (gdbarch, reg); 533 } 534 535 switch (reg) 536 { 537 case 37: return I387_FCTRL_REGNUM (tdep); 538 case 38: return I387_FSTAT_REGNUM (tdep); 539 case 39: return I387_MXCSR_REGNUM (tdep); 540 case 40: return I386_ES_REGNUM; 541 case 41: return I386_CS_REGNUM; 542 case 42: return I386_SS_REGNUM; 543 case 43: return I386_DS_REGNUM; 544 case 44: return I386_FS_REGNUM; 545 case 45: return I386_GS_REGNUM; 546 } 547 548 return -1; 549 } 550 551 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return 552 num_regs + num_pseudo_regs for other debug formats. */ 553 554 static int 555 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) 556 { 557 int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg); 558 559 if (regnum == -1) 560 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); 561 return regnum; 562 } 563 564 565 566 /* This is the variable that is set with "set disassembly-flavor", and 567 its legitimate values. */ 568 static const char att_flavor[] = "att"; 569 static const char intel_flavor[] = "intel"; 570 static const char *const valid_flavors[] = 571 { 572 att_flavor, 573 intel_flavor, 574 NULL 575 }; 576 static const char *disassembly_flavor = att_flavor; 577 578 579 /* Use the program counter to determine the contents and size of a 580 breakpoint instruction. Return a pointer to a string of bytes that 581 encode a breakpoint instruction, store the length of the string in 582 *LEN and optionally adjust *PC to point to the correct memory 583 location for inserting the breakpoint. 584 585 On the i386 we have a single breakpoint that fits in a single byte 586 and can be inserted anywhere. 587 588 This function is 64-bit safe. */ 589 590 static const gdb_byte * 591 i386_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) 592 { 593 static gdb_byte break_insn[] = { 0xcc }; /* int 3 */ 594 595 *len = sizeof (break_insn); 596 return break_insn; 597 } 598 599 /* Displaced instruction handling. */ 600 601 /* Skip the legacy instruction prefixes in INSN. 602 Not all prefixes are valid for any particular insn 603 but we needn't care, the insn will fault if it's invalid. 604 The result is a pointer to the first opcode byte, 605 or NULL if we run off the end of the buffer. */ 606 607 static gdb_byte * 608 i386_skip_prefixes (gdb_byte *insn, size_t max_len) 609 { 610 gdb_byte *end = insn + max_len; 611 612 while (insn < end) 613 { 614 switch (*insn) 615 { 616 case DATA_PREFIX_OPCODE: 617 case ADDR_PREFIX_OPCODE: 618 case CS_PREFIX_OPCODE: 619 case DS_PREFIX_OPCODE: 620 case ES_PREFIX_OPCODE: 621 case FS_PREFIX_OPCODE: 622 case GS_PREFIX_OPCODE: 623 case SS_PREFIX_OPCODE: 624 case LOCK_PREFIX_OPCODE: 625 case REPE_PREFIX_OPCODE: 626 case REPNE_PREFIX_OPCODE: 627 ++insn; 628 continue; 629 default: 630 return insn; 631 } 632 } 633 634 return NULL; 635 } 636 637 static int 638 i386_absolute_jmp_p (const gdb_byte *insn) 639 { 640 /* jmp far (absolute address in operand). */ 641 if (insn[0] == 0xea) 642 return 1; 643 644 if (insn[0] == 0xff) 645 { 646 /* jump near, absolute indirect (/4). */ 647 if ((insn[1] & 0x38) == 0x20) 648 return 1; 649 650 /* jump far, absolute indirect (/5). */ 651 if ((insn[1] & 0x38) == 0x28) 652 return 1; 653 } 654 655 return 0; 656 } 657 658 /* Return non-zero if INSN is a jump, zero otherwise. */ 659 660 static int 661 i386_jmp_p (const gdb_byte *insn) 662 { 663 /* jump short, relative. */ 664 if (insn[0] == 0xeb) 665 return 1; 666 667 /* jump near, relative. */ 668 if (insn[0] == 0xe9) 669 return 1; 670 671 return i386_absolute_jmp_p (insn); 672 } 673 674 static int 675 i386_absolute_call_p (const gdb_byte *insn) 676 { 677 /* call far, absolute. */ 678 if (insn[0] == 0x9a) 679 return 1; 680 681 if (insn[0] == 0xff) 682 { 683 /* Call near, absolute indirect (/2). */ 684 if ((insn[1] & 0x38) == 0x10) 685 return 1; 686 687 /* Call far, absolute indirect (/3). */ 688 if ((insn[1] & 0x38) == 0x18) 689 return 1; 690 } 691 692 return 0; 693 } 694 695 static int 696 i386_ret_p (const gdb_byte *insn) 697 { 698 switch (insn[0]) 699 { 700 case 0xc2: /* ret near, pop N bytes. */ 701 case 0xc3: /* ret near */ 702 case 0xca: /* ret far, pop N bytes. */ 703 case 0xcb: /* ret far */ 704 case 0xcf: /* iret */ 705 return 1; 706 707 default: 708 return 0; 709 } 710 } 711 712 static int 713 i386_call_p (const gdb_byte *insn) 714 { 715 if (i386_absolute_call_p (insn)) 716 return 1; 717 718 /* call near, relative. */ 719 if (insn[0] == 0xe8) 720 return 1; 721 722 return 0; 723 } 724 725 /* Return non-zero if INSN is a system call, and set *LENGTHP to its 726 length in bytes. Otherwise, return zero. */ 727 728 static int 729 i386_syscall_p (const gdb_byte *insn, int *lengthp) 730 { 731 /* Is it 'int $0x80'? */ 732 if ((insn[0] == 0xcd && insn[1] == 0x80) 733 /* Or is it 'sysenter'? */ 734 || (insn[0] == 0x0f && insn[1] == 0x34) 735 /* Or is it 'syscall'? */ 736 || (insn[0] == 0x0f && insn[1] == 0x05)) 737 { 738 *lengthp = 2; 739 return 1; 740 } 741 742 return 0; 743 } 744 745 /* The gdbarch insn_is_call method. */ 746 747 static int 748 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) 749 { 750 gdb_byte buf[I386_MAX_INSN_LEN], *insn; 751 752 read_code (addr, buf, I386_MAX_INSN_LEN); 753 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); 754 755 return i386_call_p (insn); 756 } 757 758 /* The gdbarch insn_is_ret method. */ 759 760 static int 761 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) 762 { 763 gdb_byte buf[I386_MAX_INSN_LEN], *insn; 764 765 read_code (addr, buf, I386_MAX_INSN_LEN); 766 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); 767 768 return i386_ret_p (insn); 769 } 770 771 /* The gdbarch insn_is_jump method. */ 772 773 static int 774 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) 775 { 776 gdb_byte buf[I386_MAX_INSN_LEN], *insn; 777 778 read_code (addr, buf, I386_MAX_INSN_LEN); 779 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); 780 781 return i386_jmp_p (insn); 782 } 783 784 /* Some kernels may run one past a syscall insn, so we have to cope. 785 Otherwise this is just simple_displaced_step_copy_insn. */ 786 787 struct displaced_step_closure * 788 i386_displaced_step_copy_insn (struct gdbarch *gdbarch, 789 CORE_ADDR from, CORE_ADDR to, 790 struct regcache *regs) 791 { 792 size_t len = gdbarch_max_insn_length (gdbarch); 793 gdb_byte *buf = (gdb_byte *) xmalloc (len); 794 795 read_memory (from, buf, len); 796 797 /* GDB may get control back after the insn after the syscall. 798 Presumably this is a kernel bug. 799 If this is a syscall, make sure there's a nop afterwards. */ 800 { 801 int syscall_length; 802 gdb_byte *insn; 803 804 insn = i386_skip_prefixes (buf, len); 805 if (insn != NULL && i386_syscall_p (insn, &syscall_length)) 806 insn[syscall_length] = NOP_OPCODE; 807 } 808 809 write_memory (to, buf, len); 810 811 if (debug_displaced) 812 { 813 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", 814 paddress (gdbarch, from), paddress (gdbarch, to)); 815 displaced_step_dump_bytes (gdb_stdlog, buf, len); 816 } 817 818 return (struct displaced_step_closure *) buf; 819 } 820 821 /* Fix up the state of registers and memory after having single-stepped 822 a displaced instruction. */ 823 824 void 825 i386_displaced_step_fixup (struct gdbarch *gdbarch, 826 struct displaced_step_closure *closure, 827 CORE_ADDR from, CORE_ADDR to, 828 struct regcache *regs) 829 { 830 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 831 832 /* The offset we applied to the instruction's address. 833 This could well be negative (when viewed as a signed 32-bit 834 value), but ULONGEST won't reflect that, so take care when 835 applying it. */ 836 ULONGEST insn_offset = to - from; 837 838 /* Since we use simple_displaced_step_copy_insn, our closure is a 839 copy of the instruction. */ 840 gdb_byte *insn = (gdb_byte *) closure; 841 /* The start of the insn, needed in case we see some prefixes. */ 842 gdb_byte *insn_start = insn; 843 844 if (debug_displaced) 845 fprintf_unfiltered (gdb_stdlog, 846 "displaced: fixup (%s, %s), " 847 "insn = 0x%02x 0x%02x ...\n", 848 paddress (gdbarch, from), paddress (gdbarch, to), 849 insn[0], insn[1]); 850 851 /* The list of issues to contend with here is taken from 852 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. 853 Yay for Free Software! */ 854 855 /* Relocate the %eip, if necessary. */ 856 857 /* The instruction recognizers we use assume any leading prefixes 858 have been skipped. */ 859 { 860 /* This is the size of the buffer in closure. */ 861 size_t max_insn_len = gdbarch_max_insn_length (gdbarch); 862 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); 863 /* If there are too many prefixes, just ignore the insn. 864 It will fault when run. */ 865 if (opcode != NULL) 866 insn = opcode; 867 } 868 869 /* Except in the case of absolute or indirect jump or call 870 instructions, or a return instruction, the new eip is relative to 871 the displaced instruction; make it relative. Well, signal 872 handler returns don't need relocation either, but we use the 873 value of %eip to recognize those; see below. */ 874 if (! i386_absolute_jmp_p (insn) 875 && ! i386_absolute_call_p (insn) 876 && ! i386_ret_p (insn)) 877 { 878 ULONGEST orig_eip; 879 int insn_len; 880 881 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); 882 883 /* A signal trampoline system call changes the %eip, resuming 884 execution of the main program after the signal handler has 885 returned. That makes them like 'return' instructions; we 886 shouldn't relocate %eip. 887 888 But most system calls don't, and we do need to relocate %eip. 889 890 Our heuristic for distinguishing these cases: if stepping 891 over the system call instruction left control directly after 892 the instruction, the we relocate --- control almost certainly 893 doesn't belong in the displaced copy. Otherwise, we assume 894 the instruction has put control where it belongs, and leave 895 it unrelocated. Goodness help us if there are PC-relative 896 system calls. */ 897 if (i386_syscall_p (insn, &insn_len) 898 && orig_eip != to + (insn - insn_start) + insn_len 899 /* GDB can get control back after the insn after the syscall. 900 Presumably this is a kernel bug. 901 i386_displaced_step_copy_insn ensures its a nop, 902 we add one to the length for it. */ 903 && orig_eip != to + (insn - insn_start) + insn_len + 1) 904 { 905 if (debug_displaced) 906 fprintf_unfiltered (gdb_stdlog, 907 "displaced: syscall changed %%eip; " 908 "not relocating\n"); 909 } 910 else 911 { 912 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; 913 914 /* If we just stepped over a breakpoint insn, we don't backup 915 the pc on purpose; this is to match behaviour without 916 stepping. */ 917 918 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); 919 920 if (debug_displaced) 921 fprintf_unfiltered (gdb_stdlog, 922 "displaced: " 923 "relocated %%eip from %s to %s\n", 924 paddress (gdbarch, orig_eip), 925 paddress (gdbarch, eip)); 926 } 927 } 928 929 /* If the instruction was PUSHFL, then the TF bit will be set in the 930 pushed value, and should be cleared. We'll leave this for later, 931 since GDB already messes up the TF flag when stepping over a 932 pushfl. */ 933 934 /* If the instruction was a call, the return address now atop the 935 stack is the address following the copied instruction. We need 936 to make it the address following the original instruction. */ 937 if (i386_call_p (insn)) 938 { 939 ULONGEST esp; 940 ULONGEST retaddr; 941 const ULONGEST retaddr_len = 4; 942 943 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); 944 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); 945 retaddr = (retaddr - insn_offset) & 0xffffffffUL; 946 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); 947 948 if (debug_displaced) 949 fprintf_unfiltered (gdb_stdlog, 950 "displaced: relocated return addr at %s to %s\n", 951 paddress (gdbarch, esp), 952 paddress (gdbarch, retaddr)); 953 } 954 } 955 956 static void 957 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) 958 { 959 target_write_memory (*to, buf, len); 960 *to += len; 961 } 962 963 static void 964 i386_relocate_instruction (struct gdbarch *gdbarch, 965 CORE_ADDR *to, CORE_ADDR oldloc) 966 { 967 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 968 gdb_byte buf[I386_MAX_INSN_LEN]; 969 int offset = 0, rel32, newrel; 970 int insn_length; 971 gdb_byte *insn = buf; 972 973 read_memory (oldloc, buf, I386_MAX_INSN_LEN); 974 975 insn_length = gdb_buffered_insn_length (gdbarch, insn, 976 I386_MAX_INSN_LEN, oldloc); 977 978 /* Get past the prefixes. */ 979 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); 980 981 /* Adjust calls with 32-bit relative addresses as push/jump, with 982 the address pushed being the location where the original call in 983 the user program would return to. */ 984 if (insn[0] == 0xe8) 985 { 986 gdb_byte push_buf[16]; 987 unsigned int ret_addr; 988 989 /* Where "ret" in the original code will return to. */ 990 ret_addr = oldloc + insn_length; 991 push_buf[0] = 0x68; /* pushq $... */ 992 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); 993 /* Push the push. */ 994 append_insns (to, 5, push_buf); 995 996 /* Convert the relative call to a relative jump. */ 997 insn[0] = 0xe9; 998 999 /* Adjust the destination offset. */ 1000 rel32 = extract_signed_integer (insn + 1, 4, byte_order); 1001 newrel = (oldloc - *to) + rel32; 1002 store_signed_integer (insn + 1, 4, byte_order, newrel); 1003 1004 if (debug_displaced) 1005 fprintf_unfiltered (gdb_stdlog, 1006 "Adjusted insn rel32=%s at %s to" 1007 " rel32=%s at %s\n", 1008 hex_string (rel32), paddress (gdbarch, oldloc), 1009 hex_string (newrel), paddress (gdbarch, *to)); 1010 1011 /* Write the adjusted jump into its displaced location. */ 1012 append_insns (to, 5, insn); 1013 return; 1014 } 1015 1016 /* Adjust jumps with 32-bit relative addresses. Calls are already 1017 handled above. */ 1018 if (insn[0] == 0xe9) 1019 offset = 1; 1020 /* Adjust conditional jumps. */ 1021 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) 1022 offset = 2; 1023 1024 if (offset) 1025 { 1026 rel32 = extract_signed_integer (insn + offset, 4, byte_order); 1027 newrel = (oldloc - *to) + rel32; 1028 store_signed_integer (insn + offset, 4, byte_order, newrel); 1029 if (debug_displaced) 1030 fprintf_unfiltered (gdb_stdlog, 1031 "Adjusted insn rel32=%s at %s to" 1032 " rel32=%s at %s\n", 1033 hex_string (rel32), paddress (gdbarch, oldloc), 1034 hex_string (newrel), paddress (gdbarch, *to)); 1035 } 1036 1037 /* Write the adjusted instructions into their displaced 1038 location. */ 1039 append_insns (to, insn_length, buf); 1040 } 1041 1042 1043 #ifdef I386_REGNO_TO_SYMMETRY 1044 #error "The Sequent Symmetry is no longer supported." 1045 #endif 1046 1047 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi 1048 and %esp "belong" to the calling function. Therefore these 1049 registers should be saved if they're going to be modified. */ 1050 1051 /* The maximum number of saved registers. This should include all 1052 registers mentioned above, and %eip. */ 1053 #define I386_NUM_SAVED_REGS I386_NUM_GREGS 1054 1055 struct i386_frame_cache 1056 { 1057 /* Base address. */ 1058 CORE_ADDR base; 1059 int base_p; 1060 LONGEST sp_offset; 1061 CORE_ADDR pc; 1062 1063 /* Saved registers. */ 1064 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; 1065 CORE_ADDR saved_sp; 1066 int saved_sp_reg; 1067 int pc_in_eax; 1068 1069 /* Stack space reserved for local variables. */ 1070 long locals; 1071 }; 1072 1073 /* Allocate and initialize a frame cache. */ 1074 1075 static struct i386_frame_cache * 1076 i386_alloc_frame_cache (void) 1077 { 1078 struct i386_frame_cache *cache; 1079 int i; 1080 1081 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); 1082 1083 /* Base address. */ 1084 cache->base_p = 0; 1085 cache->base = 0; 1086 cache->sp_offset = -4; 1087 cache->pc = 0; 1088 1089 /* Saved registers. We initialize these to -1 since zero is a valid 1090 offset (that's where %ebp is supposed to be stored). */ 1091 for (i = 0; i < I386_NUM_SAVED_REGS; i++) 1092 cache->saved_regs[i] = -1; 1093 cache->saved_sp = 0; 1094 cache->saved_sp_reg = -1; 1095 cache->pc_in_eax = 0; 1096 1097 /* Frameless until proven otherwise. */ 1098 cache->locals = -1; 1099 1100 return cache; 1101 } 1102 1103 /* If the instruction at PC is a jump, return the address of its 1104 target. Otherwise, return PC. */ 1105 1106 static CORE_ADDR 1107 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) 1108 { 1109 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1110 gdb_byte op; 1111 long delta = 0; 1112 int data16 = 0; 1113 1114 if (target_read_code (pc, &op, 1)) 1115 return pc; 1116 1117 if (op == 0x66) 1118 { 1119 data16 = 1; 1120 1121 op = read_code_unsigned_integer (pc + 1, 1, byte_order); 1122 } 1123 1124 switch (op) 1125 { 1126 case 0xe9: 1127 /* Relative jump: if data16 == 0, disp32, else disp16. */ 1128 if (data16) 1129 { 1130 delta = read_memory_integer (pc + 2, 2, byte_order); 1131 1132 /* Include the size of the jmp instruction (including the 1133 0x66 prefix). */ 1134 delta += 4; 1135 } 1136 else 1137 { 1138 delta = read_memory_integer (pc + 1, 4, byte_order); 1139 1140 /* Include the size of the jmp instruction. */ 1141 delta += 5; 1142 } 1143 break; 1144 case 0xeb: 1145 /* Relative jump, disp8 (ignore data16). */ 1146 delta = read_memory_integer (pc + data16 + 1, 1, byte_order); 1147 1148 delta += data16 + 2; 1149 break; 1150 } 1151 1152 return pc + delta; 1153 } 1154 1155 /* Check whether PC points at a prologue for a function returning a 1156 structure or union. If so, it updates CACHE and returns the 1157 address of the first instruction after the code sequence that 1158 removes the "hidden" argument from the stack or CURRENT_PC, 1159 whichever is smaller. Otherwise, return PC. */ 1160 1161 static CORE_ADDR 1162 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, 1163 struct i386_frame_cache *cache) 1164 { 1165 /* Functions that return a structure or union start with: 1166 1167 popl %eax 0x58 1168 xchgl %eax, (%esp) 0x87 0x04 0x24 1169 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 1170 1171 (the System V compiler puts out the second `xchg' instruction, 1172 and the assembler doesn't try to optimize it, so the 'sib' form 1173 gets generated). This sequence is used to get the address of the 1174 return buffer for a function that returns a structure. */ 1175 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; 1176 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; 1177 gdb_byte buf[4]; 1178 gdb_byte op; 1179 1180 if (current_pc <= pc) 1181 return pc; 1182 1183 if (target_read_code (pc, &op, 1)) 1184 return pc; 1185 1186 if (op != 0x58) /* popl %eax */ 1187 return pc; 1188 1189 if (target_read_code (pc + 1, buf, 4)) 1190 return pc; 1191 1192 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) 1193 return pc; 1194 1195 if (current_pc == pc) 1196 { 1197 cache->sp_offset += 4; 1198 return current_pc; 1199 } 1200 1201 if (current_pc == pc + 1) 1202 { 1203 cache->pc_in_eax = 1; 1204 return current_pc; 1205 } 1206 1207 if (buf[1] == proto1[1]) 1208 return pc + 4; 1209 else 1210 return pc + 5; 1211 } 1212 1213 static CORE_ADDR 1214 i386_skip_probe (CORE_ADDR pc) 1215 { 1216 /* A function may start with 1217 1218 pushl constant 1219 call _probe 1220 addl $4, %esp 1221 1222 followed by 1223 1224 pushl %ebp 1225 1226 etc. */ 1227 gdb_byte buf[8]; 1228 gdb_byte op; 1229 1230 if (target_read_code (pc, &op, 1)) 1231 return pc; 1232 1233 if (op == 0x68 || op == 0x6a) 1234 { 1235 int delta; 1236 1237 /* Skip past the `pushl' instruction; it has either a one-byte or a 1238 four-byte operand, depending on the opcode. */ 1239 if (op == 0x68) 1240 delta = 5; 1241 else 1242 delta = 2; 1243 1244 /* Read the following 8 bytes, which should be `call _probe' (6 1245 bytes) followed by `addl $4,%esp' (2 bytes). */ 1246 read_memory (pc + delta, buf, sizeof (buf)); 1247 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) 1248 pc += delta + sizeof (buf); 1249 } 1250 1251 return pc; 1252 } 1253 1254 /* GCC 4.1 and later, can put code in the prologue to realign the 1255 stack pointer. Check whether PC points to such code, and update 1256 CACHE accordingly. Return the first instruction after the code 1257 sequence or CURRENT_PC, whichever is smaller. If we don't 1258 recognize the code, return PC. */ 1259 1260 static CORE_ADDR 1261 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, 1262 struct i386_frame_cache *cache) 1263 { 1264 /* There are 2 code sequences to re-align stack before the frame 1265 gets set up: 1266 1267 1. Use a caller-saved saved register: 1268 1269 leal 4(%esp), %reg 1270 andl $-XXX, %esp 1271 pushl -4(%reg) 1272 1273 2. Use a callee-saved saved register: 1274 1275 pushl %reg 1276 leal 8(%esp), %reg 1277 andl $-XXX, %esp 1278 pushl -4(%reg) 1279 1280 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: 1281 1282 0x83 0xe4 0xf0 andl $-16, %esp 1283 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp 1284 */ 1285 1286 gdb_byte buf[14]; 1287 int reg; 1288 int offset, offset_and; 1289 static int regnums[8] = { 1290 I386_EAX_REGNUM, /* %eax */ 1291 I386_ECX_REGNUM, /* %ecx */ 1292 I386_EDX_REGNUM, /* %edx */ 1293 I386_EBX_REGNUM, /* %ebx */ 1294 I386_ESP_REGNUM, /* %esp */ 1295 I386_EBP_REGNUM, /* %ebp */ 1296 I386_ESI_REGNUM, /* %esi */ 1297 I386_EDI_REGNUM /* %edi */ 1298 }; 1299 1300 if (target_read_code (pc, buf, sizeof buf)) 1301 return pc; 1302 1303 /* Check caller-saved saved register. The first instruction has 1304 to be "leal 4(%esp), %reg". */ 1305 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) 1306 { 1307 /* MOD must be binary 10 and R/M must be binary 100. */ 1308 if ((buf[1] & 0xc7) != 0x44) 1309 return pc; 1310 1311 /* REG has register number. */ 1312 reg = (buf[1] >> 3) & 7; 1313 offset = 4; 1314 } 1315 else 1316 { 1317 /* Check callee-saved saved register. The first instruction 1318 has to be "pushl %reg". */ 1319 if ((buf[0] & 0xf8) != 0x50) 1320 return pc; 1321 1322 /* Get register. */ 1323 reg = buf[0] & 0x7; 1324 1325 /* The next instruction has to be "leal 8(%esp), %reg". */ 1326 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) 1327 return pc; 1328 1329 /* MOD must be binary 10 and R/M must be binary 100. */ 1330 if ((buf[2] & 0xc7) != 0x44) 1331 return pc; 1332 1333 /* REG has register number. Registers in pushl and leal have to 1334 be the same. */ 1335 if (reg != ((buf[2] >> 3) & 7)) 1336 return pc; 1337 1338 offset = 5; 1339 } 1340 1341 /* Rigister can't be %esp nor %ebp. */ 1342 if (reg == 4 || reg == 5) 1343 return pc; 1344 1345 /* The next instruction has to be "andl $-XXX, %esp". */ 1346 if (buf[offset + 1] != 0xe4 1347 || (buf[offset] != 0x81 && buf[offset] != 0x83)) 1348 return pc; 1349 1350 offset_and = offset; 1351 offset += buf[offset] == 0x81 ? 6 : 3; 1352 1353 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is 1354 0xfc. REG must be binary 110 and MOD must be binary 01. */ 1355 if (buf[offset] != 0xff 1356 || buf[offset + 2] != 0xfc 1357 || (buf[offset + 1] & 0xf8) != 0x70) 1358 return pc; 1359 1360 /* R/M has register. Registers in leal and pushl have to be the 1361 same. */ 1362 if (reg != (buf[offset + 1] & 7)) 1363 return pc; 1364 1365 if (current_pc > pc + offset_and) 1366 cache->saved_sp_reg = regnums[reg]; 1367 1368 return min (pc + offset + 3, current_pc); 1369 } 1370 1371 /* Maximum instruction length we need to handle. */ 1372 #define I386_MAX_MATCHED_INSN_LEN 6 1373 1374 /* Instruction description. */ 1375 struct i386_insn 1376 { 1377 size_t len; 1378 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; 1379 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; 1380 }; 1381 1382 /* Return whether instruction at PC matches PATTERN. */ 1383 1384 static int 1385 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) 1386 { 1387 gdb_byte op; 1388 1389 if (target_read_code (pc, &op, 1)) 1390 return 0; 1391 1392 if ((op & pattern.mask[0]) == pattern.insn[0]) 1393 { 1394 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; 1395 int insn_matched = 1; 1396 size_t i; 1397 1398 gdb_assert (pattern.len > 1); 1399 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); 1400 1401 if (target_read_code (pc + 1, buf, pattern.len - 1)) 1402 return 0; 1403 1404 for (i = 1; i < pattern.len; i++) 1405 { 1406 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) 1407 insn_matched = 0; 1408 } 1409 return insn_matched; 1410 } 1411 return 0; 1412 } 1413 1414 /* Search for the instruction at PC in the list INSN_PATTERNS. Return 1415 the first instruction description that matches. Otherwise, return 1416 NULL. */ 1417 1418 static struct i386_insn * 1419 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) 1420 { 1421 struct i386_insn *pattern; 1422 1423 for (pattern = insn_patterns; pattern->len > 0; pattern++) 1424 { 1425 if (i386_match_pattern (pc, *pattern)) 1426 return pattern; 1427 } 1428 1429 return NULL; 1430 } 1431 1432 /* Return whether PC points inside a sequence of instructions that 1433 matches INSN_PATTERNS. */ 1434 1435 static int 1436 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) 1437 { 1438 CORE_ADDR current_pc; 1439 int ix, i; 1440 struct i386_insn *insn; 1441 1442 insn = i386_match_insn (pc, insn_patterns); 1443 if (insn == NULL) 1444 return 0; 1445 1446 current_pc = pc; 1447 ix = insn - insn_patterns; 1448 for (i = ix - 1; i >= 0; i--) 1449 { 1450 current_pc -= insn_patterns[i].len; 1451 1452 if (!i386_match_pattern (current_pc, insn_patterns[i])) 1453 return 0; 1454 } 1455 1456 current_pc = pc + insn->len; 1457 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) 1458 { 1459 if (!i386_match_pattern (current_pc, *insn)) 1460 return 0; 1461 1462 current_pc += insn->len; 1463 } 1464 1465 return 1; 1466 } 1467 1468 /* Some special instructions that might be migrated by GCC into the 1469 part of the prologue that sets up the new stack frame. Because the 1470 stack frame hasn't been setup yet, no registers have been saved 1471 yet, and only the scratch registers %eax, %ecx and %edx can be 1472 touched. */ 1473 1474 struct i386_insn i386_frame_setup_skip_insns[] = 1475 { 1476 /* Check for `movb imm8, r' and `movl imm32, r'. 1477 1478 ??? Should we handle 16-bit operand-sizes here? */ 1479 1480 /* `movb imm8, %al' and `movb imm8, %ah' */ 1481 /* `movb imm8, %cl' and `movb imm8, %ch' */ 1482 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, 1483 /* `movb imm8, %dl' and `movb imm8, %dh' */ 1484 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, 1485 /* `movl imm32, %eax' and `movl imm32, %ecx' */ 1486 { 5, { 0xb8 }, { 0xfe } }, 1487 /* `movl imm32, %edx' */ 1488 { 5, { 0xba }, { 0xff } }, 1489 1490 /* Check for `mov imm32, r32'. Note that there is an alternative 1491 encoding for `mov m32, %eax'. 1492 1493 ??? Should we handle SIB adressing here? 1494 ??? Should we handle 16-bit operand-sizes here? */ 1495 1496 /* `movl m32, %eax' */ 1497 { 5, { 0xa1 }, { 0xff } }, 1498 /* `movl m32, %eax' and `mov; m32, %ecx' */ 1499 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, 1500 /* `movl m32, %edx' */ 1501 { 6, { 0x89, 0x15 }, {0xff, 0xff } }, 1502 1503 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. 1504 Because of the symmetry, there are actually two ways to encode 1505 these instructions; opcode bytes 0x29 and 0x2b for `subl' and 1506 opcode bytes 0x31 and 0x33 for `xorl'. */ 1507 1508 /* `subl %eax, %eax' */ 1509 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, 1510 /* `subl %ecx, %ecx' */ 1511 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, 1512 /* `subl %edx, %edx' */ 1513 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, 1514 /* `xorl %eax, %eax' */ 1515 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, 1516 /* `xorl %ecx, %ecx' */ 1517 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, 1518 /* `xorl %edx, %edx' */ 1519 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, 1520 { 0 } 1521 }; 1522 1523 1524 /* Check whether PC points to a no-op instruction. */ 1525 static CORE_ADDR 1526 i386_skip_noop (CORE_ADDR pc) 1527 { 1528 gdb_byte op; 1529 int check = 1; 1530 1531 if (target_read_code (pc, &op, 1)) 1532 return pc; 1533 1534 while (check) 1535 { 1536 check = 0; 1537 /* Ignore `nop' instruction. */ 1538 if (op == 0x90) 1539 { 1540 pc += 1; 1541 if (target_read_code (pc, &op, 1)) 1542 return pc; 1543 check = 1; 1544 } 1545 /* Ignore no-op instruction `mov %edi, %edi'. 1546 Microsoft system dlls often start with 1547 a `mov %edi,%edi' instruction. 1548 The 5 bytes before the function start are 1549 filled with `nop' instructions. 1550 This pattern can be used for hot-patching: 1551 The `mov %edi, %edi' instruction can be replaced by a 1552 near jump to the location of the 5 `nop' instructions 1553 which can be replaced by a 32-bit jump to anywhere 1554 in the 32-bit address space. */ 1555 1556 else if (op == 0x8b) 1557 { 1558 if (target_read_code (pc + 1, &op, 1)) 1559 return pc; 1560 1561 if (op == 0xff) 1562 { 1563 pc += 2; 1564 if (target_read_code (pc, &op, 1)) 1565 return pc; 1566 1567 check = 1; 1568 } 1569 } 1570 } 1571 return pc; 1572 } 1573 1574 /* Check whether PC points at a code that sets up a new stack frame. 1575 If so, it updates CACHE and returns the address of the first 1576 instruction after the sequence that sets up the frame or LIMIT, 1577 whichever is smaller. If we don't recognize the code, return PC. */ 1578 1579 static CORE_ADDR 1580 i386_analyze_frame_setup (struct gdbarch *gdbarch, 1581 CORE_ADDR pc, CORE_ADDR limit, 1582 struct i386_frame_cache *cache) 1583 { 1584 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1585 struct i386_insn *insn; 1586 gdb_byte op; 1587 int skip = 0; 1588 1589 if (limit <= pc) 1590 return limit; 1591 1592 if (target_read_code (pc, &op, 1)) 1593 return pc; 1594 1595 if (op == 0x55) /* pushl %ebp */ 1596 { 1597 /* Take into account that we've executed the `pushl %ebp' that 1598 starts this instruction sequence. */ 1599 cache->saved_regs[I386_EBP_REGNUM] = 0; 1600 cache->sp_offset += 4; 1601 pc++; 1602 1603 /* If that's all, return now. */ 1604 if (limit <= pc) 1605 return limit; 1606 1607 /* Check for some special instructions that might be migrated by 1608 GCC into the prologue and skip them. At this point in the 1609 prologue, code should only touch the scratch registers %eax, 1610 %ecx and %edx, so while the number of posibilities is sheer, 1611 it is limited. 1612 1613 Make sure we only skip these instructions if we later see the 1614 `movl %esp, %ebp' that actually sets up the frame. */ 1615 while (pc + skip < limit) 1616 { 1617 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); 1618 if (insn == NULL) 1619 break; 1620 1621 skip += insn->len; 1622 } 1623 1624 /* If that's all, return now. */ 1625 if (limit <= pc + skip) 1626 return limit; 1627 1628 if (target_read_code (pc + skip, &op, 1)) 1629 return pc + skip; 1630 1631 /* The i386 prologue looks like 1632 1633 push %ebp 1634 mov %esp,%ebp 1635 sub $0x10,%esp 1636 1637 and a different prologue can be generated for atom. 1638 1639 push %ebp 1640 lea (%esp),%ebp 1641 lea -0x10(%esp),%esp 1642 1643 We handle both of them here. */ 1644 1645 switch (op) 1646 { 1647 /* Check for `movl %esp, %ebp' -- can be written in two ways. */ 1648 case 0x8b: 1649 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) 1650 != 0xec) 1651 return pc; 1652 pc += (skip + 2); 1653 break; 1654 case 0x89: 1655 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) 1656 != 0xe5) 1657 return pc; 1658 pc += (skip + 2); 1659 break; 1660 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */ 1661 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order) 1662 != 0x242c) 1663 return pc; 1664 pc += (skip + 3); 1665 break; 1666 default: 1667 return pc; 1668 } 1669 1670 /* OK, we actually have a frame. We just don't know how large 1671 it is yet. Set its size to zero. We'll adjust it if 1672 necessary. We also now commit to skipping the special 1673 instructions mentioned before. */ 1674 cache->locals = 0; 1675 1676 /* If that's all, return now. */ 1677 if (limit <= pc) 1678 return limit; 1679 1680 /* Check for stack adjustment 1681 1682 subl $XXX, %esp 1683 or 1684 lea -XXX(%esp),%esp 1685 1686 NOTE: You can't subtract a 16-bit immediate from a 32-bit 1687 reg, so we don't have to worry about a data16 prefix. */ 1688 if (target_read_code (pc, &op, 1)) 1689 return pc; 1690 if (op == 0x83) 1691 { 1692 /* `subl' with 8-bit immediate. */ 1693 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) 1694 /* Some instruction starting with 0x83 other than `subl'. */ 1695 return pc; 1696 1697 /* `subl' with signed 8-bit immediate (though it wouldn't 1698 make sense to be negative). */ 1699 cache->locals = read_code_integer (pc + 2, 1, byte_order); 1700 return pc + 3; 1701 } 1702 else if (op == 0x81) 1703 { 1704 /* Maybe it is `subl' with a 32-bit immediate. */ 1705 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) 1706 /* Some instruction starting with 0x81 other than `subl'. */ 1707 return pc; 1708 1709 /* It is `subl' with a 32-bit immediate. */ 1710 cache->locals = read_code_integer (pc + 2, 4, byte_order); 1711 return pc + 6; 1712 } 1713 else if (op == 0x8d) 1714 { 1715 /* The ModR/M byte is 0x64. */ 1716 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64) 1717 return pc; 1718 /* 'lea' with 8-bit displacement. */ 1719 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order); 1720 return pc + 4; 1721 } 1722 else 1723 { 1724 /* Some instruction other than `subl' nor 'lea'. */ 1725 return pc; 1726 } 1727 } 1728 else if (op == 0xc8) /* enter */ 1729 { 1730 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order); 1731 return pc + 4; 1732 } 1733 1734 return pc; 1735 } 1736 1737 /* Check whether PC points at code that saves registers on the stack. 1738 If so, it updates CACHE and returns the address of the first 1739 instruction after the register saves or CURRENT_PC, whichever is 1740 smaller. Otherwise, return PC. */ 1741 1742 static CORE_ADDR 1743 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, 1744 struct i386_frame_cache *cache) 1745 { 1746 CORE_ADDR offset = 0; 1747 gdb_byte op; 1748 int i; 1749 1750 if (cache->locals > 0) 1751 offset -= cache->locals; 1752 for (i = 0; i < 8 && pc < current_pc; i++) 1753 { 1754 if (target_read_code (pc, &op, 1)) 1755 return pc; 1756 if (op < 0x50 || op > 0x57) 1757 break; 1758 1759 offset -= 4; 1760 cache->saved_regs[op - 0x50] = offset; 1761 cache->sp_offset += 4; 1762 pc++; 1763 } 1764 1765 return pc; 1766 } 1767 1768 /* Do a full analysis of the prologue at PC and update CACHE 1769 accordingly. Bail out early if CURRENT_PC is reached. Return the 1770 address where the analysis stopped. 1771 1772 We handle these cases: 1773 1774 The startup sequence can be at the start of the function, or the 1775 function can start with a branch to startup code at the end. 1776 1777 %ebp can be set up with either the 'enter' instruction, or "pushl 1778 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was 1779 once used in the System V compiler). 1780 1781 Local space is allocated just below the saved %ebp by either the 1782 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a 1783 16-bit unsigned argument for space to allocate, and the 'addl' 1784 instruction could have either a signed byte, or 32-bit immediate. 1785 1786 Next, the registers used by this function are pushed. With the 1787 System V compiler they will always be in the order: %edi, %esi, 1788 %ebx (and sometimes a harmless bug causes it to also save but not 1789 restore %eax); however, the code below is willing to see the pushes 1790 in any order, and will handle up to 8 of them. 1791 1792 If the setup sequence is at the end of the function, then the next 1793 instruction will be a branch back to the start. */ 1794 1795 static CORE_ADDR 1796 i386_analyze_prologue (struct gdbarch *gdbarch, 1797 CORE_ADDR pc, CORE_ADDR current_pc, 1798 struct i386_frame_cache *cache) 1799 { 1800 pc = i386_skip_noop (pc); 1801 pc = i386_follow_jump (gdbarch, pc); 1802 pc = i386_analyze_struct_return (pc, current_pc, cache); 1803 pc = i386_skip_probe (pc); 1804 pc = i386_analyze_stack_align (pc, current_pc, cache); 1805 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); 1806 return i386_analyze_register_saves (pc, current_pc, cache); 1807 } 1808 1809 /* Return PC of first real instruction. */ 1810 1811 static CORE_ADDR 1812 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 1813 { 1814 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1815 1816 static gdb_byte pic_pat[6] = 1817 { 1818 0xe8, 0, 0, 0, 0, /* call 0x0 */ 1819 0x5b, /* popl %ebx */ 1820 }; 1821 struct i386_frame_cache cache; 1822 CORE_ADDR pc; 1823 gdb_byte op; 1824 int i; 1825 CORE_ADDR func_addr; 1826 1827 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) 1828 { 1829 CORE_ADDR post_prologue_pc 1830 = skip_prologue_using_sal (gdbarch, func_addr); 1831 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); 1832 1833 /* Clang always emits a line note before the prologue and another 1834 one after. We trust clang to emit usable line notes. */ 1835 if (post_prologue_pc 1836 && (cust != NULL 1837 && COMPUNIT_PRODUCER (cust) != NULL 1838 && startswith (COMPUNIT_PRODUCER (cust), "clang "))) 1839 return max (start_pc, post_prologue_pc); 1840 } 1841 1842 cache.locals = -1; 1843 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); 1844 if (cache.locals < 0) 1845 return start_pc; 1846 1847 /* Found valid frame setup. */ 1848 1849 /* The native cc on SVR4 in -K PIC mode inserts the following code 1850 to get the address of the global offset table (GOT) into register 1851 %ebx: 1852 1853 call 0x0 1854 popl %ebx 1855 movl %ebx,x(%ebp) (optional) 1856 addl y,%ebx 1857 1858 This code is with the rest of the prologue (at the end of the 1859 function), so we have to skip it to get to the first real 1860 instruction at the start of the function. */ 1861 1862 for (i = 0; i < 6; i++) 1863 { 1864 if (target_read_code (pc + i, &op, 1)) 1865 return pc; 1866 1867 if (pic_pat[i] != op) 1868 break; 1869 } 1870 if (i == 6) 1871 { 1872 int delta = 6; 1873 1874 if (target_read_code (pc + delta, &op, 1)) 1875 return pc; 1876 1877 if (op == 0x89) /* movl %ebx, x(%ebp) */ 1878 { 1879 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order); 1880 1881 if (op == 0x5d) /* One byte offset from %ebp. */ 1882 delta += 3; 1883 else if (op == 0x9d) /* Four byte offset from %ebp. */ 1884 delta += 6; 1885 else /* Unexpected instruction. */ 1886 delta = 0; 1887 1888 if (target_read_code (pc + delta, &op, 1)) 1889 return pc; 1890 } 1891 1892 /* addl y,%ebx */ 1893 if (delta > 0 && op == 0x81 1894 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order) 1895 == 0xc3) 1896 { 1897 pc += delta + 6; 1898 } 1899 } 1900 1901 /* If the function starts with a branch (to startup code at the end) 1902 the last instruction should bring us back to the first 1903 instruction of the real code. */ 1904 if (i386_follow_jump (gdbarch, start_pc) != start_pc) 1905 pc = i386_follow_jump (gdbarch, pc); 1906 1907 return pc; 1908 } 1909 1910 /* Check that the code pointed to by PC corresponds to a call to 1911 __main, skip it if so. Return PC otherwise. */ 1912 1913 CORE_ADDR 1914 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 1915 { 1916 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1917 gdb_byte op; 1918 1919 if (target_read_code (pc, &op, 1)) 1920 return pc; 1921 if (op == 0xe8) 1922 { 1923 gdb_byte buf[4]; 1924 1925 if (target_read_code (pc + 1, buf, sizeof buf) == 0) 1926 { 1927 /* Make sure address is computed correctly as a 32bit 1928 integer even if CORE_ADDR is 64 bit wide. */ 1929 struct bound_minimal_symbol s; 1930 CORE_ADDR call_dest; 1931 1932 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); 1933 call_dest = call_dest & 0xffffffffU; 1934 s = lookup_minimal_symbol_by_pc (call_dest); 1935 if (s.minsym != NULL 1936 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL 1937 && strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__main") == 0) 1938 pc += 5; 1939 } 1940 } 1941 1942 return pc; 1943 } 1944 1945 /* This function is 64-bit safe. */ 1946 1947 static CORE_ADDR 1948 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1949 { 1950 gdb_byte buf[8]; 1951 1952 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); 1953 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); 1954 } 1955 1956 1957 /* Normal frames. */ 1958 1959 static void 1960 i386_frame_cache_1 (struct frame_info *this_frame, 1961 struct i386_frame_cache *cache) 1962 { 1963 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1964 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1965 gdb_byte buf[4]; 1966 int i; 1967 1968 cache->pc = get_frame_func (this_frame); 1969 1970 /* In principle, for normal frames, %ebp holds the frame pointer, 1971 which holds the base address for the current stack frame. 1972 However, for functions that don't need it, the frame pointer is 1973 optional. For these "frameless" functions the frame pointer is 1974 actually the frame pointer of the calling frame. Signal 1975 trampolines are just a special case of a "frameless" function. 1976 They (usually) share their frame pointer with the frame that was 1977 in progress when the signal occurred. */ 1978 1979 get_frame_register (this_frame, I386_EBP_REGNUM, buf); 1980 cache->base = extract_unsigned_integer (buf, 4, byte_order); 1981 if (cache->base == 0) 1982 { 1983 cache->base_p = 1; 1984 return; 1985 } 1986 1987 /* For normal frames, %eip is stored at 4(%ebp). */ 1988 cache->saved_regs[I386_EIP_REGNUM] = 4; 1989 1990 if (cache->pc != 0) 1991 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), 1992 cache); 1993 1994 if (cache->locals < 0) 1995 { 1996 /* We didn't find a valid frame, which means that CACHE->base 1997 currently holds the frame pointer for our calling frame. If 1998 we're at the start of a function, or somewhere half-way its 1999 prologue, the function's frame probably hasn't been fully 2000 setup yet. Try to reconstruct the base address for the stack 2001 frame by looking at the stack pointer. For truly "frameless" 2002 functions this might work too. */ 2003 2004 if (cache->saved_sp_reg != -1) 2005 { 2006 /* Saved stack pointer has been saved. */ 2007 get_frame_register (this_frame, cache->saved_sp_reg, buf); 2008 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); 2009 2010 /* We're halfway aligning the stack. */ 2011 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; 2012 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; 2013 2014 /* This will be added back below. */ 2015 cache->saved_regs[I386_EIP_REGNUM] -= cache->base; 2016 } 2017 else if (cache->pc != 0 2018 || target_read_code (get_frame_pc (this_frame), buf, 1)) 2019 { 2020 /* We're in a known function, but did not find a frame 2021 setup. Assume that the function does not use %ebp. 2022 Alternatively, we may have jumped to an invalid 2023 address; in that case there is definitely no new 2024 frame in %ebp. */ 2025 get_frame_register (this_frame, I386_ESP_REGNUM, buf); 2026 cache->base = extract_unsigned_integer (buf, 4, byte_order) 2027 + cache->sp_offset; 2028 } 2029 else 2030 /* We're in an unknown function. We could not find the start 2031 of the function to analyze the prologue; our best option is 2032 to assume a typical frame layout with the caller's %ebp 2033 saved. */ 2034 cache->saved_regs[I386_EBP_REGNUM] = 0; 2035 } 2036 2037 if (cache->saved_sp_reg != -1) 2038 { 2039 /* Saved stack pointer has been saved (but the SAVED_SP_REG 2040 register may be unavailable). */ 2041 if (cache->saved_sp == 0 2042 && deprecated_frame_register_read (this_frame, 2043 cache->saved_sp_reg, buf)) 2044 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); 2045 } 2046 /* Now that we have the base address for the stack frame we can 2047 calculate the value of %esp in the calling frame. */ 2048 else if (cache->saved_sp == 0) 2049 cache->saved_sp = cache->base + 8; 2050 2051 /* Adjust all the saved registers such that they contain addresses 2052 instead of offsets. */ 2053 for (i = 0; i < I386_NUM_SAVED_REGS; i++) 2054 if (cache->saved_regs[i] != -1) 2055 cache->saved_regs[i] += cache->base; 2056 2057 cache->base_p = 1; 2058 } 2059 2060 static struct i386_frame_cache * 2061 i386_frame_cache (struct frame_info *this_frame, void **this_cache) 2062 { 2063 struct i386_frame_cache *cache; 2064 2065 if (*this_cache) 2066 return (struct i386_frame_cache *) *this_cache; 2067 2068 cache = i386_alloc_frame_cache (); 2069 *this_cache = cache; 2070 2071 TRY 2072 { 2073 i386_frame_cache_1 (this_frame, cache); 2074 } 2075 CATCH (ex, RETURN_MASK_ERROR) 2076 { 2077 if (ex.error != NOT_AVAILABLE_ERROR) 2078 throw_exception (ex); 2079 } 2080 END_CATCH 2081 2082 return cache; 2083 } 2084 2085 static void 2086 i386_frame_this_id (struct frame_info *this_frame, void **this_cache, 2087 struct frame_id *this_id) 2088 { 2089 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); 2090 2091 if (!cache->base_p) 2092 (*this_id) = frame_id_build_unavailable_stack (cache->pc); 2093 else if (cache->base == 0) 2094 { 2095 /* This marks the outermost frame. */ 2096 } 2097 else 2098 { 2099 /* See the end of i386_push_dummy_call. */ 2100 (*this_id) = frame_id_build (cache->base + 8, cache->pc); 2101 } 2102 } 2103 2104 static enum unwind_stop_reason 2105 i386_frame_unwind_stop_reason (struct frame_info *this_frame, 2106 void **this_cache) 2107 { 2108 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); 2109 2110 if (!cache->base_p) 2111 return UNWIND_UNAVAILABLE; 2112 2113 /* This marks the outermost frame. */ 2114 if (cache->base == 0) 2115 return UNWIND_OUTERMOST; 2116 2117 return UNWIND_NO_REASON; 2118 } 2119 2120 static struct value * 2121 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, 2122 int regnum) 2123 { 2124 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); 2125 2126 gdb_assert (regnum >= 0); 2127 2128 /* The System V ABI says that: 2129 2130 "The flags register contains the system flags, such as the 2131 direction flag and the carry flag. The direction flag must be 2132 set to the forward (that is, zero) direction before entry and 2133 upon exit from a function. Other user flags have no specified 2134 role in the standard calling sequence and are not preserved." 2135 2136 To guarantee the "upon exit" part of that statement we fake a 2137 saved flags register that has its direction flag cleared. 2138 2139 Note that GCC doesn't seem to rely on the fact that the direction 2140 flag is cleared after a function return; it always explicitly 2141 clears the flag before operations where it matters. 2142 2143 FIXME: kettenis/20030316: I'm not quite sure whether this is the 2144 right thing to do. The way we fake the flags register here makes 2145 it impossible to change it. */ 2146 2147 if (regnum == I386_EFLAGS_REGNUM) 2148 { 2149 ULONGEST val; 2150 2151 val = get_frame_register_unsigned (this_frame, regnum); 2152 val &= ~(1 << 10); 2153 return frame_unwind_got_constant (this_frame, regnum, val); 2154 } 2155 2156 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) 2157 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); 2158 2159 if (regnum == I386_ESP_REGNUM 2160 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) 2161 { 2162 /* If the SP has been saved, but we don't know where, then this 2163 means that SAVED_SP_REG register was found unavailable back 2164 when we built the cache. */ 2165 if (cache->saved_sp == 0) 2166 return frame_unwind_got_register (this_frame, regnum, 2167 cache->saved_sp_reg); 2168 else 2169 return frame_unwind_got_constant (this_frame, regnum, 2170 cache->saved_sp); 2171 } 2172 2173 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) 2174 return frame_unwind_got_memory (this_frame, regnum, 2175 cache->saved_regs[regnum]); 2176 2177 return frame_unwind_got_register (this_frame, regnum, regnum); 2178 } 2179 2180 static const struct frame_unwind i386_frame_unwind = 2181 { 2182 NORMAL_FRAME, 2183 i386_frame_unwind_stop_reason, 2184 i386_frame_this_id, 2185 i386_frame_prev_register, 2186 NULL, 2187 default_frame_sniffer 2188 }; 2189 2190 /* Normal frames, but in a function epilogue. */ 2191 2192 /* Implement the stack_frame_destroyed_p gdbarch method. 2193 2194 The epilogue is defined here as the 'ret' instruction, which will 2195 follow any instruction such as 'leave' or 'pop %ebp' that destroys 2196 the function's stack frame. */ 2197 2198 static int 2199 i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 2200 { 2201 gdb_byte insn; 2202 struct compunit_symtab *cust; 2203 2204 cust = find_pc_compunit_symtab (pc); 2205 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust)) 2206 return 0; 2207 2208 if (target_read_memory (pc, &insn, 1)) 2209 return 0; /* Can't read memory at pc. */ 2210 2211 if (insn != 0xc3) /* 'ret' instruction. */ 2212 return 0; 2213 2214 return 1; 2215 } 2216 2217 static int 2218 i386_epilogue_frame_sniffer (const struct frame_unwind *self, 2219 struct frame_info *this_frame, 2220 void **this_prologue_cache) 2221 { 2222 if (frame_relative_level (this_frame) == 0) 2223 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame), 2224 get_frame_pc (this_frame)); 2225 else 2226 return 0; 2227 } 2228 2229 static struct i386_frame_cache * 2230 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) 2231 { 2232 struct i386_frame_cache *cache; 2233 CORE_ADDR sp; 2234 2235 if (*this_cache) 2236 return (struct i386_frame_cache *) *this_cache; 2237 2238 cache = i386_alloc_frame_cache (); 2239 *this_cache = cache; 2240 2241 TRY 2242 { 2243 cache->pc = get_frame_func (this_frame); 2244 2245 /* At this point the stack looks as if we just entered the 2246 function, with the return address at the top of the 2247 stack. */ 2248 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); 2249 cache->base = sp + cache->sp_offset; 2250 cache->saved_sp = cache->base + 8; 2251 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; 2252 2253 cache->base_p = 1; 2254 } 2255 CATCH (ex, RETURN_MASK_ERROR) 2256 { 2257 if (ex.error != NOT_AVAILABLE_ERROR) 2258 throw_exception (ex); 2259 } 2260 END_CATCH 2261 2262 return cache; 2263 } 2264 2265 static enum unwind_stop_reason 2266 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, 2267 void **this_cache) 2268 { 2269 struct i386_frame_cache *cache = 2270 i386_epilogue_frame_cache (this_frame, this_cache); 2271 2272 if (!cache->base_p) 2273 return UNWIND_UNAVAILABLE; 2274 2275 return UNWIND_NO_REASON; 2276 } 2277 2278 static void 2279 i386_epilogue_frame_this_id (struct frame_info *this_frame, 2280 void **this_cache, 2281 struct frame_id *this_id) 2282 { 2283 struct i386_frame_cache *cache = 2284 i386_epilogue_frame_cache (this_frame, this_cache); 2285 2286 if (!cache->base_p) 2287 (*this_id) = frame_id_build_unavailable_stack (cache->pc); 2288 else 2289 (*this_id) = frame_id_build (cache->base + 8, cache->pc); 2290 } 2291 2292 static struct value * 2293 i386_epilogue_frame_prev_register (struct frame_info *this_frame, 2294 void **this_cache, int regnum) 2295 { 2296 /* Make sure we've initialized the cache. */ 2297 i386_epilogue_frame_cache (this_frame, this_cache); 2298 2299 return i386_frame_prev_register (this_frame, this_cache, regnum); 2300 } 2301 2302 static const struct frame_unwind i386_epilogue_frame_unwind = 2303 { 2304 NORMAL_FRAME, 2305 i386_epilogue_frame_unwind_stop_reason, 2306 i386_epilogue_frame_this_id, 2307 i386_epilogue_frame_prev_register, 2308 NULL, 2309 i386_epilogue_frame_sniffer 2310 }; 2311 2312 2313 /* Stack-based trampolines. */ 2314 2315 /* These trampolines are used on cross x86 targets, when taking the 2316 address of a nested function. When executing these trampolines, 2317 no stack frame is set up, so we are in a similar situation as in 2318 epilogues and i386_epilogue_frame_this_id can be re-used. */ 2319 2320 /* Static chain passed in register. */ 2321 2322 struct i386_insn i386_tramp_chain_in_reg_insns[] = 2323 { 2324 /* `movl imm32, %eax' and `movl imm32, %ecx' */ 2325 { 5, { 0xb8 }, { 0xfe } }, 2326 2327 /* `jmp imm32' */ 2328 { 5, { 0xe9 }, { 0xff } }, 2329 2330 {0} 2331 }; 2332 2333 /* Static chain passed on stack (when regparm=3). */ 2334 2335 struct i386_insn i386_tramp_chain_on_stack_insns[] = 2336 { 2337 /* `push imm32' */ 2338 { 5, { 0x68 }, { 0xff } }, 2339 2340 /* `jmp imm32' */ 2341 { 5, { 0xe9 }, { 0xff } }, 2342 2343 {0} 2344 }; 2345 2346 /* Return whether PC points inside a stack trampoline. */ 2347 2348 static int 2349 i386_in_stack_tramp_p (CORE_ADDR pc) 2350 { 2351 gdb_byte insn; 2352 const char *name; 2353 2354 /* A stack trampoline is detected if no name is associated 2355 to the current pc and if it points inside a trampoline 2356 sequence. */ 2357 2358 find_pc_partial_function (pc, &name, NULL, NULL); 2359 if (name) 2360 return 0; 2361 2362 if (target_read_memory (pc, &insn, 1)) 2363 return 0; 2364 2365 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) 2366 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) 2367 return 0; 2368 2369 return 1; 2370 } 2371 2372 static int 2373 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, 2374 struct frame_info *this_frame, 2375 void **this_cache) 2376 { 2377 if (frame_relative_level (this_frame) == 0) 2378 return i386_in_stack_tramp_p (get_frame_pc (this_frame)); 2379 else 2380 return 0; 2381 } 2382 2383 static const struct frame_unwind i386_stack_tramp_frame_unwind = 2384 { 2385 NORMAL_FRAME, 2386 i386_epilogue_frame_unwind_stop_reason, 2387 i386_epilogue_frame_this_id, 2388 i386_epilogue_frame_prev_register, 2389 NULL, 2390 i386_stack_tramp_frame_sniffer 2391 }; 2392 2393 /* Generate a bytecode expression to get the value of the saved PC. */ 2394 2395 static void 2396 i386_gen_return_address (struct gdbarch *gdbarch, 2397 struct agent_expr *ax, struct axs_value *value, 2398 CORE_ADDR scope) 2399 { 2400 /* The following sequence assumes the traditional use of the base 2401 register. */ 2402 ax_reg (ax, I386_EBP_REGNUM); 2403 ax_const_l (ax, 4); 2404 ax_simple (ax, aop_add); 2405 value->type = register_type (gdbarch, I386_EIP_REGNUM); 2406 value->kind = axs_lvalue_memory; 2407 } 2408 2409 2410 /* Signal trampolines. */ 2411 2412 static struct i386_frame_cache * 2413 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) 2414 { 2415 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2416 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2417 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2418 struct i386_frame_cache *cache; 2419 CORE_ADDR addr; 2420 gdb_byte buf[4]; 2421 2422 if (*this_cache) 2423 return (struct i386_frame_cache *) *this_cache; 2424 2425 cache = i386_alloc_frame_cache (); 2426 2427 TRY 2428 { 2429 get_frame_register (this_frame, I386_ESP_REGNUM, buf); 2430 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; 2431 2432 addr = tdep->sigcontext_addr (this_frame); 2433 if (tdep->sc_reg_offset) 2434 { 2435 int i; 2436 2437 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); 2438 2439 for (i = 0; i < tdep->sc_num_regs; i++) 2440 if (tdep->sc_reg_offset[i] != -1) 2441 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; 2442 } 2443 else 2444 { 2445 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; 2446 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; 2447 } 2448 2449 cache->base_p = 1; 2450 } 2451 CATCH (ex, RETURN_MASK_ERROR) 2452 { 2453 if (ex.error != NOT_AVAILABLE_ERROR) 2454 throw_exception (ex); 2455 } 2456 END_CATCH 2457 2458 *this_cache = cache; 2459 return cache; 2460 } 2461 2462 static enum unwind_stop_reason 2463 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, 2464 void **this_cache) 2465 { 2466 struct i386_frame_cache *cache = 2467 i386_sigtramp_frame_cache (this_frame, this_cache); 2468 2469 if (!cache->base_p) 2470 return UNWIND_UNAVAILABLE; 2471 2472 return UNWIND_NO_REASON; 2473 } 2474 2475 static void 2476 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, 2477 struct frame_id *this_id) 2478 { 2479 struct i386_frame_cache *cache = 2480 i386_sigtramp_frame_cache (this_frame, this_cache); 2481 2482 if (!cache->base_p) 2483 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); 2484 else 2485 { 2486 /* See the end of i386_push_dummy_call. */ 2487 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); 2488 } 2489 } 2490 2491 static struct value * 2492 i386_sigtramp_frame_prev_register (struct frame_info *this_frame, 2493 void **this_cache, int regnum) 2494 { 2495 /* Make sure we've initialized the cache. */ 2496 i386_sigtramp_frame_cache (this_frame, this_cache); 2497 2498 return i386_frame_prev_register (this_frame, this_cache, regnum); 2499 } 2500 2501 static int 2502 i386_sigtramp_frame_sniffer (const struct frame_unwind *self, 2503 struct frame_info *this_frame, 2504 void **this_prologue_cache) 2505 { 2506 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); 2507 2508 /* We shouldn't even bother if we don't have a sigcontext_addr 2509 handler. */ 2510 if (tdep->sigcontext_addr == NULL) 2511 return 0; 2512 2513 if (tdep->sigtramp_p != NULL) 2514 { 2515 if (tdep->sigtramp_p (this_frame)) 2516 return 1; 2517 } 2518 2519 if (tdep->sigtramp_start != 0) 2520 { 2521 CORE_ADDR pc = get_frame_pc (this_frame); 2522 2523 gdb_assert (tdep->sigtramp_end != 0); 2524 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) 2525 return 1; 2526 } 2527 2528 return 0; 2529 } 2530 2531 static const struct frame_unwind i386_sigtramp_frame_unwind = 2532 { 2533 SIGTRAMP_FRAME, 2534 i386_sigtramp_frame_unwind_stop_reason, 2535 i386_sigtramp_frame_this_id, 2536 i386_sigtramp_frame_prev_register, 2537 NULL, 2538 i386_sigtramp_frame_sniffer 2539 }; 2540 2541 2542 static CORE_ADDR 2543 i386_frame_base_address (struct frame_info *this_frame, void **this_cache) 2544 { 2545 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); 2546 2547 return cache->base; 2548 } 2549 2550 static const struct frame_base i386_frame_base = 2551 { 2552 &i386_frame_unwind, 2553 i386_frame_base_address, 2554 i386_frame_base_address, 2555 i386_frame_base_address 2556 }; 2557 2558 static struct frame_id 2559 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 2560 { 2561 CORE_ADDR fp; 2562 2563 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); 2564 2565 /* See the end of i386_push_dummy_call. */ 2566 return frame_id_build (fp + 8, get_frame_pc (this_frame)); 2567 } 2568 2569 /* _Decimal128 function return values need 16-byte alignment on the 2570 stack. */ 2571 2572 static CORE_ADDR 2573 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 2574 { 2575 return sp & -(CORE_ADDR)16; 2576 } 2577 2578 2579 /* Figure out where the longjmp will land. Slurp the args out of the 2580 stack. We expect the first arg to be a pointer to the jmp_buf 2581 structure from which we extract the address that we will land at. 2582 This address is copied into PC. This routine returns non-zero on 2583 success. */ 2584 2585 static int 2586 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 2587 { 2588 gdb_byte buf[4]; 2589 CORE_ADDR sp, jb_addr; 2590 struct gdbarch *gdbarch = get_frame_arch (frame); 2591 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2592 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; 2593 2594 /* If JB_PC_OFFSET is -1, we have no way to find out where the 2595 longjmp will land. */ 2596 if (jb_pc_offset == -1) 2597 return 0; 2598 2599 get_frame_register (frame, I386_ESP_REGNUM, buf); 2600 sp = extract_unsigned_integer (buf, 4, byte_order); 2601 if (target_read_memory (sp + 4, buf, 4)) 2602 return 0; 2603 2604 jb_addr = extract_unsigned_integer (buf, 4, byte_order); 2605 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) 2606 return 0; 2607 2608 *pc = extract_unsigned_integer (buf, 4, byte_order); 2609 return 1; 2610 } 2611 2612 2613 /* Check whether TYPE must be 16-byte-aligned when passed as a 2614 function argument. 16-byte vectors, _Decimal128 and structures or 2615 unions containing such types must be 16-byte-aligned; other 2616 arguments are 4-byte-aligned. */ 2617 2618 static int 2619 i386_16_byte_align_p (struct type *type) 2620 { 2621 type = check_typedef (type); 2622 if ((TYPE_CODE (type) == TYPE_CODE_DECFLOAT 2623 || (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) 2624 && TYPE_LENGTH (type) == 16) 2625 return 1; 2626 if (TYPE_CODE (type) == TYPE_CODE_ARRAY) 2627 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); 2628 if (TYPE_CODE (type) == TYPE_CODE_STRUCT 2629 || TYPE_CODE (type) == TYPE_CODE_UNION) 2630 { 2631 int i; 2632 for (i = 0; i < TYPE_NFIELDS (type); i++) 2633 { 2634 if (i386_16_byte_align_p (TYPE_FIELD_TYPE (type, i))) 2635 return 1; 2636 } 2637 } 2638 return 0; 2639 } 2640 2641 /* Implementation for set_gdbarch_push_dummy_code. */ 2642 2643 static CORE_ADDR 2644 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, 2645 struct value **args, int nargs, struct type *value_type, 2646 CORE_ADDR *real_pc, CORE_ADDR *bp_addr, 2647 struct regcache *regcache) 2648 { 2649 /* Use 0xcc breakpoint - 1 byte. */ 2650 *bp_addr = sp - 1; 2651 *real_pc = funaddr; 2652 2653 /* Keep the stack aligned. */ 2654 return sp - 16; 2655 } 2656 2657 static CORE_ADDR 2658 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 2659 struct regcache *regcache, CORE_ADDR bp_addr, int nargs, 2660 struct value **args, CORE_ADDR sp, int struct_return, 2661 CORE_ADDR struct_addr) 2662 { 2663 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2664 gdb_byte buf[4]; 2665 int i; 2666 int write_pass; 2667 int args_space = 0; 2668 2669 /* Determine the total space required for arguments and struct 2670 return address in a first pass (allowing for 16-byte-aligned 2671 arguments), then push arguments in a second pass. */ 2672 2673 for (write_pass = 0; write_pass < 2; write_pass++) 2674 { 2675 int args_space_used = 0; 2676 2677 if (struct_return) 2678 { 2679 if (write_pass) 2680 { 2681 /* Push value address. */ 2682 store_unsigned_integer (buf, 4, byte_order, struct_addr); 2683 write_memory (sp, buf, 4); 2684 args_space_used += 4; 2685 } 2686 else 2687 args_space += 4; 2688 } 2689 2690 for (i = 0; i < nargs; i++) 2691 { 2692 int len = TYPE_LENGTH (value_enclosing_type (args[i])); 2693 2694 if (write_pass) 2695 { 2696 if (i386_16_byte_align_p (value_enclosing_type (args[i]))) 2697 args_space_used = align_up (args_space_used, 16); 2698 2699 write_memory (sp + args_space_used, 2700 value_contents_all (args[i]), len); 2701 /* The System V ABI says that: 2702 2703 "An argument's size is increased, if necessary, to make it a 2704 multiple of [32-bit] words. This may require tail padding, 2705 depending on the size of the argument." 2706 2707 This makes sure the stack stays word-aligned. */ 2708 args_space_used += align_up (len, 4); 2709 } 2710 else 2711 { 2712 if (i386_16_byte_align_p (value_enclosing_type (args[i]))) 2713 args_space = align_up (args_space, 16); 2714 args_space += align_up (len, 4); 2715 } 2716 } 2717 2718 if (!write_pass) 2719 { 2720 sp -= args_space; 2721 2722 /* The original System V ABI only requires word alignment, 2723 but modern incarnations need 16-byte alignment in order 2724 to support SSE. Since wasting a few bytes here isn't 2725 harmful we unconditionally enforce 16-byte alignment. */ 2726 sp &= ~0xf; 2727 } 2728 } 2729 2730 /* Store return address. */ 2731 sp -= 4; 2732 store_unsigned_integer (buf, 4, byte_order, bp_addr); 2733 write_memory (sp, buf, 4); 2734 2735 /* Finally, update the stack pointer... */ 2736 store_unsigned_integer (buf, 4, byte_order, sp); 2737 regcache_cooked_write (regcache, I386_ESP_REGNUM, buf); 2738 2739 /* ...and fake a frame pointer. */ 2740 regcache_cooked_write (regcache, I386_EBP_REGNUM, buf); 2741 2742 /* MarkK wrote: This "+ 8" is all over the place: 2743 (i386_frame_this_id, i386_sigtramp_frame_this_id, 2744 i386_dummy_id). It's there, since all frame unwinders for 2745 a given target have to agree (within a certain margin) on the 2746 definition of the stack address of a frame. Otherwise frame id 2747 comparison might not work correctly. Since DWARF2/GCC uses the 2748 stack address *before* the function call as a frame's CFA. On 2749 the i386, when %ebp is used as a frame pointer, the offset 2750 between the contents %ebp and the CFA as defined by GCC. */ 2751 return sp + 8; 2752 } 2753 2754 /* These registers are used for returning integers (and on some 2755 targets also for returning `struct' and `union' values when their 2756 size and alignment match an integer type). */ 2757 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ 2758 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ 2759 2760 /* Read, for architecture GDBARCH, a function return value of TYPE 2761 from REGCACHE, and copy that into VALBUF. */ 2762 2763 static void 2764 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, 2765 struct regcache *regcache, gdb_byte *valbuf) 2766 { 2767 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2768 int len = TYPE_LENGTH (type); 2769 gdb_byte buf[I386_MAX_REGISTER_SIZE]; 2770 2771 if (TYPE_CODE (type) == TYPE_CODE_FLT) 2772 { 2773 if (tdep->st0_regnum < 0) 2774 { 2775 warning (_("Cannot find floating-point return value.")); 2776 memset (valbuf, 0, len); 2777 return; 2778 } 2779 2780 /* Floating-point return values can be found in %st(0). Convert 2781 its contents to the desired type. This is probably not 2782 exactly how it would happen on the target itself, but it is 2783 the best we can do. */ 2784 regcache_raw_read (regcache, I386_ST0_REGNUM, buf); 2785 convert_typed_floating (buf, i387_ext_type (gdbarch), valbuf, type); 2786 } 2787 else 2788 { 2789 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); 2790 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); 2791 2792 if (len <= low_size) 2793 { 2794 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); 2795 memcpy (valbuf, buf, len); 2796 } 2797 else if (len <= (low_size + high_size)) 2798 { 2799 regcache_raw_read (regcache, LOW_RETURN_REGNUM, buf); 2800 memcpy (valbuf, buf, low_size); 2801 regcache_raw_read (regcache, HIGH_RETURN_REGNUM, buf); 2802 memcpy (valbuf + low_size, buf, len - low_size); 2803 } 2804 else 2805 internal_error (__FILE__, __LINE__, 2806 _("Cannot extract return value of %d bytes long."), 2807 len); 2808 } 2809 } 2810 2811 /* Write, for architecture GDBARCH, a function return value of TYPE 2812 from VALBUF into REGCACHE. */ 2813 2814 static void 2815 i386_store_return_value (struct gdbarch *gdbarch, struct type *type, 2816 struct regcache *regcache, const gdb_byte *valbuf) 2817 { 2818 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2819 int len = TYPE_LENGTH (type); 2820 2821 if (TYPE_CODE (type) == TYPE_CODE_FLT) 2822 { 2823 ULONGEST fstat; 2824 gdb_byte buf[I386_MAX_REGISTER_SIZE]; 2825 2826 if (tdep->st0_regnum < 0) 2827 { 2828 warning (_("Cannot set floating-point return value.")); 2829 return; 2830 } 2831 2832 /* Returning floating-point values is a bit tricky. Apart from 2833 storing the return value in %st(0), we have to simulate the 2834 state of the FPU at function return point. */ 2835 2836 /* Convert the value found in VALBUF to the extended 2837 floating-point format used by the FPU. This is probably 2838 not exactly how it would happen on the target itself, but 2839 it is the best we can do. */ 2840 convert_typed_floating (valbuf, type, buf, i387_ext_type (gdbarch)); 2841 regcache_raw_write (regcache, I386_ST0_REGNUM, buf); 2842 2843 /* Set the top of the floating-point register stack to 7. The 2844 actual value doesn't really matter, but 7 is what a normal 2845 function return would end up with if the program started out 2846 with a freshly initialized FPU. */ 2847 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); 2848 fstat |= (7 << 11); 2849 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); 2850 2851 /* Mark %st(1) through %st(7) as empty. Since we set the top of 2852 the floating-point register stack to 7, the appropriate value 2853 for the tag word is 0x3fff. */ 2854 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); 2855 } 2856 else 2857 { 2858 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); 2859 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); 2860 2861 if (len <= low_size) 2862 regcache_raw_write_part (regcache, LOW_RETURN_REGNUM, 0, len, valbuf); 2863 else if (len <= (low_size + high_size)) 2864 { 2865 regcache_raw_write (regcache, LOW_RETURN_REGNUM, valbuf); 2866 regcache_raw_write_part (regcache, HIGH_RETURN_REGNUM, 0, 2867 len - low_size, valbuf + low_size); 2868 } 2869 else 2870 internal_error (__FILE__, __LINE__, 2871 _("Cannot store return value of %d bytes long."), len); 2872 } 2873 } 2874 2875 2876 /* This is the variable that is set with "set struct-convention", and 2877 its legitimate values. */ 2878 static const char default_struct_convention[] = "default"; 2879 static const char pcc_struct_convention[] = "pcc"; 2880 static const char reg_struct_convention[] = "reg"; 2881 static const char *const valid_conventions[] = 2882 { 2883 default_struct_convention, 2884 pcc_struct_convention, 2885 reg_struct_convention, 2886 NULL 2887 }; 2888 static const char *struct_convention = default_struct_convention; 2889 2890 /* Return non-zero if TYPE, which is assumed to be a structure, 2891 a union type, or an array type, should be returned in registers 2892 for architecture GDBARCH. */ 2893 2894 static int 2895 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) 2896 { 2897 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2898 enum type_code code = TYPE_CODE (type); 2899 int len = TYPE_LENGTH (type); 2900 2901 gdb_assert (code == TYPE_CODE_STRUCT 2902 || code == TYPE_CODE_UNION 2903 || code == TYPE_CODE_ARRAY); 2904 2905 if (struct_convention == pcc_struct_convention 2906 || (struct_convention == default_struct_convention 2907 && tdep->struct_return == pcc_struct_return)) 2908 return 0; 2909 2910 /* Structures consisting of a single `float', `double' or 'long 2911 double' member are returned in %st(0). */ 2912 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) 2913 { 2914 type = check_typedef (TYPE_FIELD_TYPE (type, 0)); 2915 if (TYPE_CODE (type) == TYPE_CODE_FLT) 2916 return (len == 4 || len == 8 || len == 12); 2917 } 2918 2919 return (len == 1 || len == 2 || len == 4 || len == 8); 2920 } 2921 2922 /* Determine, for architecture GDBARCH, how a return value of TYPE 2923 should be returned. If it is supposed to be returned in registers, 2924 and READBUF is non-zero, read the appropriate value from REGCACHE, 2925 and copy it into READBUF. If WRITEBUF is non-zero, write the value 2926 from WRITEBUF into REGCACHE. */ 2927 2928 static enum return_value_convention 2929 i386_return_value (struct gdbarch *gdbarch, struct value *function, 2930 struct type *type, struct regcache *regcache, 2931 gdb_byte *readbuf, const gdb_byte *writebuf) 2932 { 2933 enum type_code code = TYPE_CODE (type); 2934 2935 if (((code == TYPE_CODE_STRUCT 2936 || code == TYPE_CODE_UNION 2937 || code == TYPE_CODE_ARRAY) 2938 && !i386_reg_struct_return_p (gdbarch, type)) 2939 /* Complex double and long double uses the struct return covention. */ 2940 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16) 2941 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24) 2942 /* 128-bit decimal float uses the struct return convention. */ 2943 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) 2944 { 2945 /* The System V ABI says that: 2946 2947 "A function that returns a structure or union also sets %eax 2948 to the value of the original address of the caller's area 2949 before it returns. Thus when the caller receives control 2950 again, the address of the returned object resides in register 2951 %eax and can be used to access the object." 2952 2953 So the ABI guarantees that we can always find the return 2954 value just after the function has returned. */ 2955 2956 /* Note that the ABI doesn't mention functions returning arrays, 2957 which is something possible in certain languages such as Ada. 2958 In this case, the value is returned as if it was wrapped in 2959 a record, so the convention applied to records also applies 2960 to arrays. */ 2961 2962 if (readbuf) 2963 { 2964 ULONGEST addr; 2965 2966 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); 2967 read_memory (addr, readbuf, TYPE_LENGTH (type)); 2968 } 2969 2970 return RETURN_VALUE_ABI_RETURNS_ADDRESS; 2971 } 2972 2973 /* This special case is for structures consisting of a single 2974 `float', `double' or 'long double' member. These structures are 2975 returned in %st(0). For these structures, we call ourselves 2976 recursively, changing TYPE into the type of the first member of 2977 the structure. Since that should work for all structures that 2978 have only one member, we don't bother to check the member's type 2979 here. */ 2980 if (code == TYPE_CODE_STRUCT && TYPE_NFIELDS (type) == 1) 2981 { 2982 type = check_typedef (TYPE_FIELD_TYPE (type, 0)); 2983 return i386_return_value (gdbarch, function, type, regcache, 2984 readbuf, writebuf); 2985 } 2986 2987 if (readbuf) 2988 i386_extract_return_value (gdbarch, type, regcache, readbuf); 2989 if (writebuf) 2990 i386_store_return_value (gdbarch, type, regcache, writebuf); 2991 2992 return RETURN_VALUE_REGISTER_CONVENTION; 2993 } 2994 2995 2996 struct type * 2997 i387_ext_type (struct gdbarch *gdbarch) 2998 { 2999 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3000 3001 if (!tdep->i387_ext_type) 3002 { 3003 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); 3004 gdb_assert (tdep->i387_ext_type != NULL); 3005 } 3006 3007 return tdep->i387_ext_type; 3008 } 3009 3010 /* Construct type for pseudo BND registers. We can't use 3011 tdesc_find_type since a complement of one value has to be used 3012 to describe the upper bound. */ 3013 3014 static struct type * 3015 i386_bnd_type (struct gdbarch *gdbarch) 3016 { 3017 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3018 3019 3020 if (!tdep->i386_bnd_type) 3021 { 3022 struct type *t; 3023 const struct builtin_type *bt = builtin_type (gdbarch); 3024 3025 /* The type we're building is described bellow: */ 3026 #if 0 3027 struct __bound128 3028 { 3029 void *lbound; 3030 void *ubound; /* One complement of raw ubound field. */ 3031 }; 3032 #endif 3033 3034 t = arch_composite_type (gdbarch, 3035 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT); 3036 3037 append_composite_type_field (t, "lbound", bt->builtin_data_ptr); 3038 append_composite_type_field (t, "ubound", bt->builtin_data_ptr); 3039 3040 TYPE_NAME (t) = "builtin_type_bound128"; 3041 tdep->i386_bnd_type = t; 3042 } 3043 3044 return tdep->i386_bnd_type; 3045 } 3046 3047 /* Construct vector type for pseudo ZMM registers. We can't use 3048 tdesc_find_type since ZMM isn't described in target description. */ 3049 3050 static struct type * 3051 i386_zmm_type (struct gdbarch *gdbarch) 3052 { 3053 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3054 3055 if (!tdep->i386_zmm_type) 3056 { 3057 const struct builtin_type *bt = builtin_type (gdbarch); 3058 3059 /* The type we're building is this: */ 3060 #if 0 3061 union __gdb_builtin_type_vec512i 3062 { 3063 int128_t uint128[4]; 3064 int64_t v4_int64[8]; 3065 int32_t v8_int32[16]; 3066 int16_t v16_int16[32]; 3067 int8_t v32_int8[64]; 3068 double v4_double[8]; 3069 float v8_float[16]; 3070 }; 3071 #endif 3072 3073 struct type *t; 3074 3075 t = arch_composite_type (gdbarch, 3076 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION); 3077 append_composite_type_field (t, "v16_float", 3078 init_vector_type (bt->builtin_float, 16)); 3079 append_composite_type_field (t, "v8_double", 3080 init_vector_type (bt->builtin_double, 8)); 3081 append_composite_type_field (t, "v64_int8", 3082 init_vector_type (bt->builtin_int8, 64)); 3083 append_composite_type_field (t, "v32_int16", 3084 init_vector_type (bt->builtin_int16, 32)); 3085 append_composite_type_field (t, "v16_int32", 3086 init_vector_type (bt->builtin_int32, 16)); 3087 append_composite_type_field (t, "v8_int64", 3088 init_vector_type (bt->builtin_int64, 8)); 3089 append_composite_type_field (t, "v4_int128", 3090 init_vector_type (bt->builtin_int128, 4)); 3091 3092 TYPE_VECTOR (t) = 1; 3093 TYPE_NAME (t) = "builtin_type_vec512i"; 3094 tdep->i386_zmm_type = t; 3095 } 3096 3097 return tdep->i386_zmm_type; 3098 } 3099 3100 /* Construct vector type for pseudo YMM registers. We can't use 3101 tdesc_find_type since YMM isn't described in target description. */ 3102 3103 static struct type * 3104 i386_ymm_type (struct gdbarch *gdbarch) 3105 { 3106 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3107 3108 if (!tdep->i386_ymm_type) 3109 { 3110 const struct builtin_type *bt = builtin_type (gdbarch); 3111 3112 /* The type we're building is this: */ 3113 #if 0 3114 union __gdb_builtin_type_vec256i 3115 { 3116 int128_t uint128[2]; 3117 int64_t v2_int64[4]; 3118 int32_t v4_int32[8]; 3119 int16_t v8_int16[16]; 3120 int8_t v16_int8[32]; 3121 double v2_double[4]; 3122 float v4_float[8]; 3123 }; 3124 #endif 3125 3126 struct type *t; 3127 3128 t = arch_composite_type (gdbarch, 3129 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); 3130 append_composite_type_field (t, "v8_float", 3131 init_vector_type (bt->builtin_float, 8)); 3132 append_composite_type_field (t, "v4_double", 3133 init_vector_type (bt->builtin_double, 4)); 3134 append_composite_type_field (t, "v32_int8", 3135 init_vector_type (bt->builtin_int8, 32)); 3136 append_composite_type_field (t, "v16_int16", 3137 init_vector_type (bt->builtin_int16, 16)); 3138 append_composite_type_field (t, "v8_int32", 3139 init_vector_type (bt->builtin_int32, 8)); 3140 append_composite_type_field (t, "v4_int64", 3141 init_vector_type (bt->builtin_int64, 4)); 3142 append_composite_type_field (t, "v2_int128", 3143 init_vector_type (bt->builtin_int128, 2)); 3144 3145 TYPE_VECTOR (t) = 1; 3146 TYPE_NAME (t) = "builtin_type_vec256i"; 3147 tdep->i386_ymm_type = t; 3148 } 3149 3150 return tdep->i386_ymm_type; 3151 } 3152 3153 /* Construct vector type for MMX registers. */ 3154 static struct type * 3155 i386_mmx_type (struct gdbarch *gdbarch) 3156 { 3157 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3158 3159 if (!tdep->i386_mmx_type) 3160 { 3161 const struct builtin_type *bt = builtin_type (gdbarch); 3162 3163 /* The type we're building is this: */ 3164 #if 0 3165 union __gdb_builtin_type_vec64i 3166 { 3167 int64_t uint64; 3168 int32_t v2_int32[2]; 3169 int16_t v4_int16[4]; 3170 int8_t v8_int8[8]; 3171 }; 3172 #endif 3173 3174 struct type *t; 3175 3176 t = arch_composite_type (gdbarch, 3177 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); 3178 3179 append_composite_type_field (t, "uint64", bt->builtin_int64); 3180 append_composite_type_field (t, "v2_int32", 3181 init_vector_type (bt->builtin_int32, 2)); 3182 append_composite_type_field (t, "v4_int16", 3183 init_vector_type (bt->builtin_int16, 4)); 3184 append_composite_type_field (t, "v8_int8", 3185 init_vector_type (bt->builtin_int8, 8)); 3186 3187 TYPE_VECTOR (t) = 1; 3188 TYPE_NAME (t) = "builtin_type_vec64i"; 3189 tdep->i386_mmx_type = t; 3190 } 3191 3192 return tdep->i386_mmx_type; 3193 } 3194 3195 /* Return the GDB type object for the "standard" data type of data in 3196 register REGNUM. */ 3197 3198 struct type * 3199 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) 3200 { 3201 if (i386_bnd_regnum_p (gdbarch, regnum)) 3202 return i386_bnd_type (gdbarch); 3203 if (i386_mmx_regnum_p (gdbarch, regnum)) 3204 return i386_mmx_type (gdbarch); 3205 else if (i386_ymm_regnum_p (gdbarch, regnum)) 3206 return i386_ymm_type (gdbarch); 3207 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) 3208 return i386_ymm_type (gdbarch); 3209 else if (i386_zmm_regnum_p (gdbarch, regnum)) 3210 return i386_zmm_type (gdbarch); 3211 else 3212 { 3213 const struct builtin_type *bt = builtin_type (gdbarch); 3214 if (i386_byte_regnum_p (gdbarch, regnum)) 3215 return bt->builtin_int8; 3216 else if (i386_word_regnum_p (gdbarch, regnum)) 3217 return bt->builtin_int16; 3218 else if (i386_dword_regnum_p (gdbarch, regnum)) 3219 return bt->builtin_int32; 3220 else if (i386_k_regnum_p (gdbarch, regnum)) 3221 return bt->builtin_int64; 3222 } 3223 3224 internal_error (__FILE__, __LINE__, _("invalid regnum")); 3225 } 3226 3227 /* Map a cooked register onto a raw register or memory. For the i386, 3228 the MMX registers need to be mapped onto floating point registers. */ 3229 3230 static int 3231 i386_mmx_regnum_to_fp_regnum (struct regcache *regcache, int regnum) 3232 { 3233 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); 3234 int mmxreg, fpreg; 3235 ULONGEST fstat; 3236 int tos; 3237 3238 mmxreg = regnum - tdep->mm0_regnum; 3239 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); 3240 tos = (fstat >> 11) & 0x7; 3241 fpreg = (mmxreg + tos) % 8; 3242 3243 return (I387_ST0_REGNUM (tdep) + fpreg); 3244 } 3245 3246 /* A helper function for us by i386_pseudo_register_read_value and 3247 amd64_pseudo_register_read_value. It does all the work but reads 3248 the data into an already-allocated value. */ 3249 3250 void 3251 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, 3252 struct regcache *regcache, 3253 int regnum, 3254 struct value *result_value) 3255 { 3256 gdb_byte raw_buf[MAX_REGISTER_SIZE]; 3257 enum register_status status; 3258 gdb_byte *buf = value_contents_raw (result_value); 3259 3260 if (i386_mmx_regnum_p (gdbarch, regnum)) 3261 { 3262 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); 3263 3264 /* Extract (always little endian). */ 3265 status = regcache_raw_read (regcache, fpnum, raw_buf); 3266 if (status != REG_VALID) 3267 mark_value_bytes_unavailable (result_value, 0, 3268 TYPE_LENGTH (value_type (result_value))); 3269 else 3270 memcpy (buf, raw_buf, register_size (gdbarch, regnum)); 3271 } 3272 else 3273 { 3274 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3275 if (i386_bnd_regnum_p (gdbarch, regnum)) 3276 { 3277 regnum -= tdep->bnd0_regnum; 3278 3279 /* Extract (always little endian). Read lower 128bits. */ 3280 status = regcache_raw_read (regcache, 3281 I387_BND0R_REGNUM (tdep) + regnum, 3282 raw_buf); 3283 if (status != REG_VALID) 3284 mark_value_bytes_unavailable (result_value, 0, 16); 3285 else 3286 { 3287 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); 3288 LONGEST upper, lower; 3289 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); 3290 3291 lower = extract_unsigned_integer (raw_buf, 8, byte_order); 3292 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order); 3293 upper = ~upper; 3294 3295 memcpy (buf, &lower, size); 3296 memcpy (buf + size, &upper, size); 3297 } 3298 } 3299 else if (i386_k_regnum_p (gdbarch, regnum)) 3300 { 3301 regnum -= tdep->k0_regnum; 3302 3303 /* Extract (always little endian). */ 3304 status = regcache_raw_read (regcache, 3305 tdep->k0_regnum + regnum, 3306 raw_buf); 3307 if (status != REG_VALID) 3308 mark_value_bytes_unavailable (result_value, 0, 8); 3309 else 3310 memcpy (buf, raw_buf, 8); 3311 } 3312 else if (i386_zmm_regnum_p (gdbarch, regnum)) 3313 { 3314 regnum -= tdep->zmm0_regnum; 3315 3316 if (regnum < num_lower_zmm_regs) 3317 { 3318 /* Extract (always little endian). Read lower 128bits. */ 3319 status = regcache_raw_read (regcache, 3320 I387_XMM0_REGNUM (tdep) + regnum, 3321 raw_buf); 3322 if (status != REG_VALID) 3323 mark_value_bytes_unavailable (result_value, 0, 16); 3324 else 3325 memcpy (buf, raw_buf, 16); 3326 3327 /* Extract (always little endian). Read upper 128bits. */ 3328 status = regcache_raw_read (regcache, 3329 tdep->ymm0h_regnum + regnum, 3330 raw_buf); 3331 if (status != REG_VALID) 3332 mark_value_bytes_unavailable (result_value, 16, 16); 3333 else 3334 memcpy (buf + 16, raw_buf, 16); 3335 } 3336 else 3337 { 3338 /* Extract (always little endian). Read lower 128bits. */ 3339 status = regcache_raw_read (regcache, 3340 I387_XMM16_REGNUM (tdep) + regnum 3341 - num_lower_zmm_regs, 3342 raw_buf); 3343 if (status != REG_VALID) 3344 mark_value_bytes_unavailable (result_value, 0, 16); 3345 else 3346 memcpy (buf, raw_buf, 16); 3347 3348 /* Extract (always little endian). Read upper 128bits. */ 3349 status = regcache_raw_read (regcache, 3350 I387_YMM16H_REGNUM (tdep) + regnum 3351 - num_lower_zmm_regs, 3352 raw_buf); 3353 if (status != REG_VALID) 3354 mark_value_bytes_unavailable (result_value, 16, 16); 3355 else 3356 memcpy (buf + 16, raw_buf, 16); 3357 } 3358 3359 /* Read upper 256bits. */ 3360 status = regcache_raw_read (regcache, 3361 tdep->zmm0h_regnum + regnum, 3362 raw_buf); 3363 if (status != REG_VALID) 3364 mark_value_bytes_unavailable (result_value, 32, 32); 3365 else 3366 memcpy (buf + 32, raw_buf, 32); 3367 } 3368 else if (i386_ymm_regnum_p (gdbarch, regnum)) 3369 { 3370 regnum -= tdep->ymm0_regnum; 3371 3372 /* Extract (always little endian). Read lower 128bits. */ 3373 status = regcache_raw_read (regcache, 3374 I387_XMM0_REGNUM (tdep) + regnum, 3375 raw_buf); 3376 if (status != REG_VALID) 3377 mark_value_bytes_unavailable (result_value, 0, 16); 3378 else 3379 memcpy (buf, raw_buf, 16); 3380 /* Read upper 128bits. */ 3381 status = regcache_raw_read (regcache, 3382 tdep->ymm0h_regnum + regnum, 3383 raw_buf); 3384 if (status != REG_VALID) 3385 mark_value_bytes_unavailable (result_value, 16, 32); 3386 else 3387 memcpy (buf + 16, raw_buf, 16); 3388 } 3389 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) 3390 { 3391 regnum -= tdep->ymm16_regnum; 3392 /* Extract (always little endian). Read lower 128bits. */ 3393 status = regcache_raw_read (regcache, 3394 I387_XMM16_REGNUM (tdep) + regnum, 3395 raw_buf); 3396 if (status != REG_VALID) 3397 mark_value_bytes_unavailable (result_value, 0, 16); 3398 else 3399 memcpy (buf, raw_buf, 16); 3400 /* Read upper 128bits. */ 3401 status = regcache_raw_read (regcache, 3402 tdep->ymm16h_regnum + regnum, 3403 raw_buf); 3404 if (status != REG_VALID) 3405 mark_value_bytes_unavailable (result_value, 16, 16); 3406 else 3407 memcpy (buf + 16, raw_buf, 16); 3408 } 3409 else if (i386_word_regnum_p (gdbarch, regnum)) 3410 { 3411 int gpnum = regnum - tdep->ax_regnum; 3412 3413 /* Extract (always little endian). */ 3414 status = regcache_raw_read (regcache, gpnum, raw_buf); 3415 if (status != REG_VALID) 3416 mark_value_bytes_unavailable (result_value, 0, 3417 TYPE_LENGTH (value_type (result_value))); 3418 else 3419 memcpy (buf, raw_buf, 2); 3420 } 3421 else if (i386_byte_regnum_p (gdbarch, regnum)) 3422 { 3423 int gpnum = regnum - tdep->al_regnum; 3424 3425 /* Extract (always little endian). We read both lower and 3426 upper registers. */ 3427 status = regcache_raw_read (regcache, gpnum % 4, raw_buf); 3428 if (status != REG_VALID) 3429 mark_value_bytes_unavailable (result_value, 0, 3430 TYPE_LENGTH (value_type (result_value))); 3431 else if (gpnum >= 4) 3432 memcpy (buf, raw_buf + 1, 1); 3433 else 3434 memcpy (buf, raw_buf, 1); 3435 } 3436 else 3437 internal_error (__FILE__, __LINE__, _("invalid regnum")); 3438 } 3439 } 3440 3441 static struct value * 3442 i386_pseudo_register_read_value (struct gdbarch *gdbarch, 3443 struct regcache *regcache, 3444 int regnum) 3445 { 3446 struct value *result; 3447 3448 result = allocate_value (register_type (gdbarch, regnum)); 3449 VALUE_LVAL (result) = lval_register; 3450 VALUE_REGNUM (result) = regnum; 3451 3452 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); 3453 3454 return result; 3455 } 3456 3457 void 3458 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 3459 int regnum, const gdb_byte *buf) 3460 { 3461 gdb_byte raw_buf[MAX_REGISTER_SIZE]; 3462 3463 if (i386_mmx_regnum_p (gdbarch, regnum)) 3464 { 3465 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); 3466 3467 /* Read ... */ 3468 regcache_raw_read (regcache, fpnum, raw_buf); 3469 /* ... Modify ... (always little endian). */ 3470 memcpy (raw_buf, buf, register_size (gdbarch, regnum)); 3471 /* ... Write. */ 3472 regcache_raw_write (regcache, fpnum, raw_buf); 3473 } 3474 else 3475 { 3476 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3477 3478 if (i386_bnd_regnum_p (gdbarch, regnum)) 3479 { 3480 ULONGEST upper, lower; 3481 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); 3482 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); 3483 3484 /* New values from input value. */ 3485 regnum -= tdep->bnd0_regnum; 3486 lower = extract_unsigned_integer (buf, size, byte_order); 3487 upper = extract_unsigned_integer (buf + size, size, byte_order); 3488 3489 /* Fetching register buffer. */ 3490 regcache_raw_read (regcache, 3491 I387_BND0R_REGNUM (tdep) + regnum, 3492 raw_buf); 3493 3494 upper = ~upper; 3495 3496 /* Set register bits. */ 3497 memcpy (raw_buf, &lower, 8); 3498 memcpy (raw_buf + 8, &upper, 8); 3499 3500 3501 regcache_raw_write (regcache, 3502 I387_BND0R_REGNUM (tdep) + regnum, 3503 raw_buf); 3504 } 3505 else if (i386_k_regnum_p (gdbarch, regnum)) 3506 { 3507 regnum -= tdep->k0_regnum; 3508 3509 regcache_raw_write (regcache, 3510 tdep->k0_regnum + regnum, 3511 buf); 3512 } 3513 else if (i386_zmm_regnum_p (gdbarch, regnum)) 3514 { 3515 regnum -= tdep->zmm0_regnum; 3516 3517 if (regnum < num_lower_zmm_regs) 3518 { 3519 /* Write lower 128bits. */ 3520 regcache_raw_write (regcache, 3521 I387_XMM0_REGNUM (tdep) + regnum, 3522 buf); 3523 /* Write upper 128bits. */ 3524 regcache_raw_write (regcache, 3525 I387_YMM0_REGNUM (tdep) + regnum, 3526 buf + 16); 3527 } 3528 else 3529 { 3530 /* Write lower 128bits. */ 3531 regcache_raw_write (regcache, 3532 I387_XMM16_REGNUM (tdep) + regnum 3533 - num_lower_zmm_regs, 3534 buf); 3535 /* Write upper 128bits. */ 3536 regcache_raw_write (regcache, 3537 I387_YMM16H_REGNUM (tdep) + regnum 3538 - num_lower_zmm_regs, 3539 buf + 16); 3540 } 3541 /* Write upper 256bits. */ 3542 regcache_raw_write (regcache, 3543 tdep->zmm0h_regnum + regnum, 3544 buf + 32); 3545 } 3546 else if (i386_ymm_regnum_p (gdbarch, regnum)) 3547 { 3548 regnum -= tdep->ymm0_regnum; 3549 3550 /* ... Write lower 128bits. */ 3551 regcache_raw_write (regcache, 3552 I387_XMM0_REGNUM (tdep) + regnum, 3553 buf); 3554 /* ... Write upper 128bits. */ 3555 regcache_raw_write (regcache, 3556 tdep->ymm0h_regnum + regnum, 3557 buf + 16); 3558 } 3559 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) 3560 { 3561 regnum -= tdep->ymm16_regnum; 3562 3563 /* ... Write lower 128bits. */ 3564 regcache_raw_write (regcache, 3565 I387_XMM16_REGNUM (tdep) + regnum, 3566 buf); 3567 /* ... Write upper 128bits. */ 3568 regcache_raw_write (regcache, 3569 tdep->ymm16h_regnum + regnum, 3570 buf + 16); 3571 } 3572 else if (i386_word_regnum_p (gdbarch, regnum)) 3573 { 3574 int gpnum = regnum - tdep->ax_regnum; 3575 3576 /* Read ... */ 3577 regcache_raw_read (regcache, gpnum, raw_buf); 3578 /* ... Modify ... (always little endian). */ 3579 memcpy (raw_buf, buf, 2); 3580 /* ... Write. */ 3581 regcache_raw_write (regcache, gpnum, raw_buf); 3582 } 3583 else if (i386_byte_regnum_p (gdbarch, regnum)) 3584 { 3585 int gpnum = regnum - tdep->al_regnum; 3586 3587 /* Read ... We read both lower and upper registers. */ 3588 regcache_raw_read (regcache, gpnum % 4, raw_buf); 3589 /* ... Modify ... (always little endian). */ 3590 if (gpnum >= 4) 3591 memcpy (raw_buf + 1, buf, 1); 3592 else 3593 memcpy (raw_buf, buf, 1); 3594 /* ... Write. */ 3595 regcache_raw_write (regcache, gpnum % 4, raw_buf); 3596 } 3597 else 3598 internal_error (__FILE__, __LINE__, _("invalid regnum")); 3599 } 3600 } 3601 3602 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */ 3603 3604 int 3605 i386_ax_pseudo_register_collect (struct gdbarch *gdbarch, 3606 struct agent_expr *ax, int regnum) 3607 { 3608 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3609 3610 if (i386_mmx_regnum_p (gdbarch, regnum)) 3611 { 3612 /* MMX to FPU register mapping depends on current TOS. Let's just 3613 not care and collect everything... */ 3614 int i; 3615 3616 ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep)); 3617 for (i = 0; i < 8; i++) 3618 ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i); 3619 return 0; 3620 } 3621 else if (i386_bnd_regnum_p (gdbarch, regnum)) 3622 { 3623 regnum -= tdep->bnd0_regnum; 3624 ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum); 3625 return 0; 3626 } 3627 else if (i386_k_regnum_p (gdbarch, regnum)) 3628 { 3629 regnum -= tdep->k0_regnum; 3630 ax_reg_mask (ax, tdep->k0_regnum + regnum); 3631 return 0; 3632 } 3633 else if (i386_zmm_regnum_p (gdbarch, regnum)) 3634 { 3635 regnum -= tdep->zmm0_regnum; 3636 if (regnum < num_lower_zmm_regs) 3637 { 3638 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); 3639 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); 3640 } 3641 else 3642 { 3643 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum 3644 - num_lower_zmm_regs); 3645 ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum 3646 - num_lower_zmm_regs); 3647 } 3648 ax_reg_mask (ax, tdep->zmm0h_regnum + regnum); 3649 return 0; 3650 } 3651 else if (i386_ymm_regnum_p (gdbarch, regnum)) 3652 { 3653 regnum -= tdep->ymm0_regnum; 3654 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); 3655 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); 3656 return 0; 3657 } 3658 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) 3659 { 3660 regnum -= tdep->ymm16_regnum; 3661 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum); 3662 ax_reg_mask (ax, tdep->ymm16h_regnum + regnum); 3663 return 0; 3664 } 3665 else if (i386_word_regnum_p (gdbarch, regnum)) 3666 { 3667 int gpnum = regnum - tdep->ax_regnum; 3668 3669 ax_reg_mask (ax, gpnum); 3670 return 0; 3671 } 3672 else if (i386_byte_regnum_p (gdbarch, regnum)) 3673 { 3674 int gpnum = regnum - tdep->al_regnum; 3675 3676 ax_reg_mask (ax, gpnum % 4); 3677 return 0; 3678 } 3679 else 3680 internal_error (__FILE__, __LINE__, _("invalid regnum")); 3681 return 1; 3682 } 3683 3684 3685 /* Return the register number of the register allocated by GCC after 3686 REGNUM, or -1 if there is no such register. */ 3687 3688 static int 3689 i386_next_regnum (int regnum) 3690 { 3691 /* GCC allocates the registers in the order: 3692 3693 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... 3694 3695 Since storing a variable in %esp doesn't make any sense we return 3696 -1 for %ebp and for %esp itself. */ 3697 static int next_regnum[] = 3698 { 3699 I386_EDX_REGNUM, /* Slot for %eax. */ 3700 I386_EBX_REGNUM, /* Slot for %ecx. */ 3701 I386_ECX_REGNUM, /* Slot for %edx. */ 3702 I386_ESI_REGNUM, /* Slot for %ebx. */ 3703 -1, -1, /* Slots for %esp and %ebp. */ 3704 I386_EDI_REGNUM, /* Slot for %esi. */ 3705 I386_EBP_REGNUM /* Slot for %edi. */ 3706 }; 3707 3708 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) 3709 return next_regnum[regnum]; 3710 3711 return -1; 3712 } 3713 3714 /* Return nonzero if a value of type TYPE stored in register REGNUM 3715 needs any special handling. */ 3716 3717 static int 3718 i386_convert_register_p (struct gdbarch *gdbarch, 3719 int regnum, struct type *type) 3720 { 3721 int len = TYPE_LENGTH (type); 3722 3723 /* Values may be spread across multiple registers. Most debugging 3724 formats aren't expressive enough to specify the locations, so 3725 some heuristics is involved. Right now we only handle types that 3726 have a length that is a multiple of the word size, since GCC 3727 doesn't seem to put any other types into registers. */ 3728 if (len > 4 && len % 4 == 0) 3729 { 3730 int last_regnum = regnum; 3731 3732 while (len > 4) 3733 { 3734 last_regnum = i386_next_regnum (last_regnum); 3735 len -= 4; 3736 } 3737 3738 if (last_regnum != -1) 3739 return 1; 3740 } 3741 3742 return i387_convert_register_p (gdbarch, regnum, type); 3743 } 3744 3745 /* Read a value of type TYPE from register REGNUM in frame FRAME, and 3746 return its contents in TO. */ 3747 3748 static int 3749 i386_register_to_value (struct frame_info *frame, int regnum, 3750 struct type *type, gdb_byte *to, 3751 int *optimizedp, int *unavailablep) 3752 { 3753 struct gdbarch *gdbarch = get_frame_arch (frame); 3754 int len = TYPE_LENGTH (type); 3755 3756 if (i386_fp_regnum_p (gdbarch, regnum)) 3757 return i387_register_to_value (frame, regnum, type, to, 3758 optimizedp, unavailablep); 3759 3760 /* Read a value spread across multiple registers. */ 3761 3762 gdb_assert (len > 4 && len % 4 == 0); 3763 3764 while (len > 0) 3765 { 3766 gdb_assert (regnum != -1); 3767 gdb_assert (register_size (gdbarch, regnum) == 4); 3768 3769 if (!get_frame_register_bytes (frame, regnum, 0, 3770 register_size (gdbarch, regnum), 3771 to, optimizedp, unavailablep)) 3772 return 0; 3773 3774 regnum = i386_next_regnum (regnum); 3775 len -= 4; 3776 to += 4; 3777 } 3778 3779 *optimizedp = *unavailablep = 0; 3780 return 1; 3781 } 3782 3783 /* Write the contents FROM of a value of type TYPE into register 3784 REGNUM in frame FRAME. */ 3785 3786 static void 3787 i386_value_to_register (struct frame_info *frame, int regnum, 3788 struct type *type, const gdb_byte *from) 3789 { 3790 int len = TYPE_LENGTH (type); 3791 3792 if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) 3793 { 3794 i387_value_to_register (frame, regnum, type, from); 3795 return; 3796 } 3797 3798 /* Write a value spread across multiple registers. */ 3799 3800 gdb_assert (len > 4 && len % 4 == 0); 3801 3802 while (len > 0) 3803 { 3804 gdb_assert (regnum != -1); 3805 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); 3806 3807 put_frame_register (frame, regnum, from); 3808 regnum = i386_next_regnum (regnum); 3809 len -= 4; 3810 from += 4; 3811 } 3812 } 3813 3814 /* Supply register REGNUM from the buffer specified by GREGS and LEN 3815 in the general-purpose register set REGSET to register cache 3816 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 3817 3818 void 3819 i386_supply_gregset (const struct regset *regset, struct regcache *regcache, 3820 int regnum, const void *gregs, size_t len) 3821 { 3822 struct gdbarch *gdbarch = get_regcache_arch (regcache); 3823 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3824 const gdb_byte *regs = (const gdb_byte *) gregs; 3825 int i; 3826 3827 gdb_assert (len >= tdep->sizeof_gregset); 3828 3829 for (i = 0; i < tdep->gregset_num_regs; i++) 3830 { 3831 if ((regnum == i || regnum == -1) 3832 && tdep->gregset_reg_offset[i] != -1) 3833 regcache_raw_supply (regcache, i, regs + tdep->gregset_reg_offset[i]); 3834 } 3835 } 3836 3837 /* Collect register REGNUM from the register cache REGCACHE and store 3838 it in the buffer specified by GREGS and LEN as described by the 3839 general-purpose register set REGSET. If REGNUM is -1, do this for 3840 all registers in REGSET. */ 3841 3842 static void 3843 i386_collect_gregset (const struct regset *regset, 3844 const struct regcache *regcache, 3845 int regnum, void *gregs, size_t len) 3846 { 3847 struct gdbarch *gdbarch = get_regcache_arch (regcache); 3848 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3849 gdb_byte *regs = (gdb_byte *) gregs; 3850 int i; 3851 3852 gdb_assert (len >= tdep->sizeof_gregset); 3853 3854 for (i = 0; i < tdep->gregset_num_regs; i++) 3855 { 3856 if ((regnum == i || regnum == -1) 3857 && tdep->gregset_reg_offset[i] != -1) 3858 regcache_raw_collect (regcache, i, regs + tdep->gregset_reg_offset[i]); 3859 } 3860 } 3861 3862 /* Supply register REGNUM from the buffer specified by FPREGS and LEN 3863 in the floating-point register set REGSET to register cache 3864 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 3865 3866 static void 3867 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, 3868 int regnum, const void *fpregs, size_t len) 3869 { 3870 struct gdbarch *gdbarch = get_regcache_arch (regcache); 3871 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3872 3873 if (len == I387_SIZEOF_FXSAVE) 3874 { 3875 i387_supply_fxsave (regcache, regnum, fpregs); 3876 return; 3877 } 3878 3879 gdb_assert (len >= tdep->sizeof_fpregset); 3880 i387_supply_fsave (regcache, regnum, fpregs); 3881 } 3882 3883 /* Collect register REGNUM from the register cache REGCACHE and store 3884 it in the buffer specified by FPREGS and LEN as described by the 3885 floating-point register set REGSET. If REGNUM is -1, do this for 3886 all registers in REGSET. */ 3887 3888 static void 3889 i386_collect_fpregset (const struct regset *regset, 3890 const struct regcache *regcache, 3891 int regnum, void *fpregs, size_t len) 3892 { 3893 struct gdbarch *gdbarch = get_regcache_arch (regcache); 3894 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3895 3896 if (len == I387_SIZEOF_FXSAVE) 3897 { 3898 i387_collect_fxsave (regcache, regnum, fpregs); 3899 return; 3900 } 3901 3902 gdb_assert (len >= tdep->sizeof_fpregset); 3903 i387_collect_fsave (regcache, regnum, fpregs); 3904 } 3905 3906 /* Register set definitions. */ 3907 3908 const struct regset i386_gregset = 3909 { 3910 NULL, i386_supply_gregset, i386_collect_gregset 3911 }; 3912 3913 const struct regset i386_fpregset = 3914 { 3915 NULL, i386_supply_fpregset, i386_collect_fpregset 3916 }; 3917 3918 /* Default iterator over core file register note sections. */ 3919 3920 void 3921 i386_iterate_over_regset_sections (struct gdbarch *gdbarch, 3922 iterate_over_regset_sections_cb *cb, 3923 void *cb_data, 3924 const struct regcache *regcache) 3925 { 3926 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3927 3928 cb (".reg", tdep->sizeof_gregset, &i386_gregset, NULL, cb_data); 3929 if (tdep->sizeof_fpregset) 3930 cb (".reg2", tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); 3931 } 3932 3933 3934 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ 3935 3936 CORE_ADDR 3937 i386_pe_skip_trampoline_code (struct frame_info *frame, 3938 CORE_ADDR pc, char *name) 3939 { 3940 struct gdbarch *gdbarch = get_frame_arch (frame); 3941 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 3942 3943 /* jmp *(dest) */ 3944 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) 3945 { 3946 unsigned long indirect = 3947 read_memory_unsigned_integer (pc + 2, 4, byte_order); 3948 struct minimal_symbol *indsym = 3949 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0; 3950 const char *symname = indsym ? MSYMBOL_LINKAGE_NAME (indsym) : 0; 3951 3952 if (symname) 3953 { 3954 if (startswith (symname, "__imp_") 3955 || startswith (symname, "_imp_")) 3956 return name ? 1 : 3957 read_memory_unsigned_integer (indirect, 4, byte_order); 3958 } 3959 } 3960 return 0; /* Not a trampoline. */ 3961 } 3962 3963 3964 /* Return whether the THIS_FRAME corresponds to a sigtramp 3965 routine. */ 3966 3967 int 3968 i386_sigtramp_p (struct frame_info *this_frame) 3969 { 3970 CORE_ADDR pc = get_frame_pc (this_frame); 3971 const char *name; 3972 3973 find_pc_partial_function (pc, &name, NULL, NULL); 3974 return (name && strcmp ("_sigtramp", name) == 0); 3975 } 3976 3977 3978 /* We have two flavours of disassembly. The machinery on this page 3979 deals with switching between those. */ 3980 3981 static int 3982 i386_print_insn (bfd_vma pc, struct disassemble_info *info) 3983 { 3984 gdb_assert (disassembly_flavor == att_flavor 3985 || disassembly_flavor == intel_flavor); 3986 3987 /* FIXME: kettenis/20020915: Until disassembler_options is properly 3988 constified, cast to prevent a compiler warning. */ 3989 info->disassembler_options = (char *) disassembly_flavor; 3990 3991 return print_insn_i386 (pc, info); 3992 } 3993 3994 3995 /* There are a few i386 architecture variants that differ only 3996 slightly from the generic i386 target. For now, we don't give them 3997 their own source file, but include them here. As a consequence, 3998 they'll always be included. */ 3999 4000 /* System V Release 4 (SVR4). */ 4001 4002 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp 4003 routine. */ 4004 4005 static int 4006 i386_svr4_sigtramp_p (struct frame_info *this_frame) 4007 { 4008 CORE_ADDR pc = get_frame_pc (this_frame); 4009 const char *name; 4010 4011 /* The origin of these symbols is currently unknown. */ 4012 find_pc_partial_function (pc, &name, NULL, NULL); 4013 return (name && (strcmp ("_sigreturn", name) == 0 4014 || strcmp ("sigvechandler", name) == 0)); 4015 } 4016 4017 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the 4018 address of the associated sigcontext (ucontext) structure. */ 4019 4020 static CORE_ADDR 4021 i386_svr4_sigcontext_addr (struct frame_info *this_frame) 4022 { 4023 struct gdbarch *gdbarch = get_frame_arch (this_frame); 4024 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 4025 gdb_byte buf[4]; 4026 CORE_ADDR sp; 4027 4028 get_frame_register (this_frame, I386_ESP_REGNUM, buf); 4029 sp = extract_unsigned_integer (buf, 4, byte_order); 4030 4031 return read_memory_unsigned_integer (sp + 8, 4, byte_order); 4032 } 4033 4034 4035 4036 /* Implementation of `gdbarch_stap_is_single_operand', as defined in 4037 gdbarch.h. */ 4038 4039 int 4040 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) 4041 { 4042 return (*s == '$' /* Literal number. */ 4043 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ 4044 || (*s == '(' && s[1] == '%') /* Register indirection. */ 4045 || (*s == '%' && isalpha (s[1]))); /* Register access. */ 4046 } 4047 4048 /* Helper function for i386_stap_parse_special_token. 4049 4050 This function parses operands of the form `-8+3+1(%rbp)', which 4051 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'. 4052 4053 Return 1 if the operand was parsed successfully, zero 4054 otherwise. */ 4055 4056 static int 4057 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch, 4058 struct stap_parse_info *p) 4059 { 4060 const char *s = p->arg; 4061 4062 if (isdigit (*s) || *s == '-' || *s == '+') 4063 { 4064 int got_minus[3]; 4065 int i; 4066 long displacements[3]; 4067 const char *start; 4068 char *regname; 4069 int len; 4070 struct stoken str; 4071 char *endp; 4072 4073 got_minus[0] = 0; 4074 if (*s == '+') 4075 ++s; 4076 else if (*s == '-') 4077 { 4078 ++s; 4079 got_minus[0] = 1; 4080 } 4081 4082 if (!isdigit ((unsigned char) *s)) 4083 return 0; 4084 4085 displacements[0] = strtol (s, &endp, 10); 4086 s = endp; 4087 4088 if (*s != '+' && *s != '-') 4089 { 4090 /* We are not dealing with a triplet. */ 4091 return 0; 4092 } 4093 4094 got_minus[1] = 0; 4095 if (*s == '+') 4096 ++s; 4097 else 4098 { 4099 ++s; 4100 got_minus[1] = 1; 4101 } 4102 4103 if (!isdigit ((unsigned char) *s)) 4104 return 0; 4105 4106 displacements[1] = strtol (s, &endp, 10); 4107 s = endp; 4108 4109 if (*s != '+' && *s != '-') 4110 { 4111 /* We are not dealing with a triplet. */ 4112 return 0; 4113 } 4114 4115 got_minus[2] = 0; 4116 if (*s == '+') 4117 ++s; 4118 else 4119 { 4120 ++s; 4121 got_minus[2] = 1; 4122 } 4123 4124 if (!isdigit ((unsigned char) *s)) 4125 return 0; 4126 4127 displacements[2] = strtol (s, &endp, 10); 4128 s = endp; 4129 4130 if (*s != '(' || s[1] != '%') 4131 return 0; 4132 4133 s += 2; 4134 start = s; 4135 4136 while (isalnum (*s)) 4137 ++s; 4138 4139 if (*s++ != ')') 4140 return 0; 4141 4142 len = s - start - 1; 4143 regname = (char *) alloca (len + 1); 4144 4145 strncpy (regname, start, len); 4146 regname[len] = '\0'; 4147 4148 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1) 4149 error (_("Invalid register name `%s' on expression `%s'."), 4150 regname, p->saved_arg); 4151 4152 for (i = 0; i < 3; i++) 4153 { 4154 write_exp_elt_opcode (&p->pstate, OP_LONG); 4155 write_exp_elt_type 4156 (&p->pstate, builtin_type (gdbarch)->builtin_long); 4157 write_exp_elt_longcst (&p->pstate, displacements[i]); 4158 write_exp_elt_opcode (&p->pstate, OP_LONG); 4159 if (got_minus[i]) 4160 write_exp_elt_opcode (&p->pstate, UNOP_NEG); 4161 } 4162 4163 write_exp_elt_opcode (&p->pstate, OP_REGISTER); 4164 str.ptr = regname; 4165 str.length = len; 4166 write_exp_string (&p->pstate, str); 4167 write_exp_elt_opcode (&p->pstate, OP_REGISTER); 4168 4169 write_exp_elt_opcode (&p->pstate, UNOP_CAST); 4170 write_exp_elt_type (&p->pstate, 4171 builtin_type (gdbarch)->builtin_data_ptr); 4172 write_exp_elt_opcode (&p->pstate, UNOP_CAST); 4173 4174 write_exp_elt_opcode (&p->pstate, BINOP_ADD); 4175 write_exp_elt_opcode (&p->pstate, BINOP_ADD); 4176 write_exp_elt_opcode (&p->pstate, BINOP_ADD); 4177 4178 write_exp_elt_opcode (&p->pstate, UNOP_CAST); 4179 write_exp_elt_type (&p->pstate, 4180 lookup_pointer_type (p->arg_type)); 4181 write_exp_elt_opcode (&p->pstate, UNOP_CAST); 4182 4183 write_exp_elt_opcode (&p->pstate, UNOP_IND); 4184 4185 p->arg = s; 4186 4187 return 1; 4188 } 4189 4190 return 0; 4191 } 4192 4193 /* Helper function for i386_stap_parse_special_token. 4194 4195 This function parses operands of the form `register base + 4196 (register index * size) + offset', as represented in 4197 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. 4198 4199 Return 1 if the operand was parsed successfully, zero 4200 otherwise. */ 4201 4202 static int 4203 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch, 4204 struct stap_parse_info *p) 4205 { 4206 const char *s = p->arg; 4207 4208 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') 4209 { 4210 int offset_minus = 0; 4211 long offset = 0; 4212 int size_minus = 0; 4213 long size = 0; 4214 const char *start; 4215 char *base; 4216 int len_base; 4217 char *index; 4218 int len_index; 4219 struct stoken base_token, index_token; 4220 4221 if (*s == '+') 4222 ++s; 4223 else if (*s == '-') 4224 { 4225 ++s; 4226 offset_minus = 1; 4227 } 4228 4229 if (offset_minus && !isdigit (*s)) 4230 return 0; 4231 4232 if (isdigit (*s)) 4233 { 4234 char *endp; 4235 4236 offset = strtol (s, &endp, 10); 4237 s = endp; 4238 } 4239 4240 if (*s != '(' || s[1] != '%') 4241 return 0; 4242 4243 s += 2; 4244 start = s; 4245 4246 while (isalnum (*s)) 4247 ++s; 4248 4249 if (*s != ',' || s[1] != '%') 4250 return 0; 4251 4252 len_base = s - start; 4253 base = (char *) alloca (len_base + 1); 4254 strncpy (base, start, len_base); 4255 base[len_base] = '\0'; 4256 4257 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1) 4258 error (_("Invalid register name `%s' on expression `%s'."), 4259 base, p->saved_arg); 4260 4261 s += 2; 4262 start = s; 4263 4264 while (isalnum (*s)) 4265 ++s; 4266 4267 len_index = s - start; 4268 index = (char *) alloca (len_index + 1); 4269 strncpy (index, start, len_index); 4270 index[len_index] = '\0'; 4271 4272 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1) 4273 error (_("Invalid register name `%s' on expression `%s'."), 4274 index, p->saved_arg); 4275 4276 if (*s != ',' && *s != ')') 4277 return 0; 4278 4279 if (*s == ',') 4280 { 4281 char *endp; 4282 4283 ++s; 4284 if (*s == '+') 4285 ++s; 4286 else if (*s == '-') 4287 { 4288 ++s; 4289 size_minus = 1; 4290 } 4291 4292 size = strtol (s, &endp, 10); 4293 s = endp; 4294 4295 if (*s != ')') 4296 return 0; 4297 } 4298 4299 ++s; 4300 4301 if (offset) 4302 { 4303 write_exp_elt_opcode (&p->pstate, OP_LONG); 4304 write_exp_elt_type (&p->pstate, 4305 builtin_type (gdbarch)->builtin_long); 4306 write_exp_elt_longcst (&p->pstate, offset); 4307 write_exp_elt_opcode (&p->pstate, OP_LONG); 4308 if (offset_minus) 4309 write_exp_elt_opcode (&p->pstate, UNOP_NEG); 4310 } 4311 4312 write_exp_elt_opcode (&p->pstate, OP_REGISTER); 4313 base_token.ptr = base; 4314 base_token.length = len_base; 4315 write_exp_string (&p->pstate, base_token); 4316 write_exp_elt_opcode (&p->pstate, OP_REGISTER); 4317 4318 if (offset) 4319 write_exp_elt_opcode (&p->pstate, BINOP_ADD); 4320 4321 write_exp_elt_opcode (&p->pstate, OP_REGISTER); 4322 index_token.ptr = index; 4323 index_token.length = len_index; 4324 write_exp_string (&p->pstate, index_token); 4325 write_exp_elt_opcode (&p->pstate, OP_REGISTER); 4326 4327 if (size) 4328 { 4329 write_exp_elt_opcode (&p->pstate, OP_LONG); 4330 write_exp_elt_type (&p->pstate, 4331 builtin_type (gdbarch)->builtin_long); 4332 write_exp_elt_longcst (&p->pstate, size); 4333 write_exp_elt_opcode (&p->pstate, OP_LONG); 4334 if (size_minus) 4335 write_exp_elt_opcode (&p->pstate, UNOP_NEG); 4336 write_exp_elt_opcode (&p->pstate, BINOP_MUL); 4337 } 4338 4339 write_exp_elt_opcode (&p->pstate, BINOP_ADD); 4340 4341 write_exp_elt_opcode (&p->pstate, UNOP_CAST); 4342 write_exp_elt_type (&p->pstate, 4343 lookup_pointer_type (p->arg_type)); 4344 write_exp_elt_opcode (&p->pstate, UNOP_CAST); 4345 4346 write_exp_elt_opcode (&p->pstate, UNOP_IND); 4347 4348 p->arg = s; 4349 4350 return 1; 4351 } 4352 4353 return 0; 4354 } 4355 4356 /* Implementation of `gdbarch_stap_parse_special_token', as defined in 4357 gdbarch.h. */ 4358 4359 int 4360 i386_stap_parse_special_token (struct gdbarch *gdbarch, 4361 struct stap_parse_info *p) 4362 { 4363 /* In order to parse special tokens, we use a state-machine that go 4364 through every known token and try to get a match. */ 4365 enum 4366 { 4367 TRIPLET, 4368 THREE_ARG_DISPLACEMENT, 4369 DONE 4370 }; 4371 int current_state; 4372 4373 current_state = TRIPLET; 4374 4375 /* The special tokens to be parsed here are: 4376 4377 - `register base + (register index * size) + offset', as represented 4378 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. 4379 4380 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as 4381 `*(-8 + 3 - 1 + (void *) $eax)'. */ 4382 4383 while (current_state != DONE) 4384 { 4385 switch (current_state) 4386 { 4387 case TRIPLET: 4388 if (i386_stap_parse_special_token_triplet (gdbarch, p)) 4389 return 1; 4390 break; 4391 4392 case THREE_ARG_DISPLACEMENT: 4393 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p)) 4394 return 1; 4395 break; 4396 } 4397 4398 /* Advancing to the next state. */ 4399 ++current_state; 4400 } 4401 4402 return 0; 4403 } 4404 4405 4406 4407 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always 4408 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */ 4409 4410 static const char * 4411 i386_gnu_triplet_regexp (struct gdbarch *gdbarch) 4412 { 4413 return "(x86_64|i.86)"; 4414 } 4415 4416 4417 4418 /* Generic ELF. */ 4419 4420 void 4421 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 4422 { 4423 static const char *const stap_integer_prefixes[] = { "$", NULL }; 4424 static const char *const stap_register_prefixes[] = { "%", NULL }; 4425 static const char *const stap_register_indirection_prefixes[] = { "(", 4426 NULL }; 4427 static const char *const stap_register_indirection_suffixes[] = { ")", 4428 NULL }; 4429 4430 /* We typically use stabs-in-ELF with the SVR4 register numbering. */ 4431 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); 4432 4433 /* Registering SystemTap handlers. */ 4434 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); 4435 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); 4436 set_gdbarch_stap_register_indirection_prefixes (gdbarch, 4437 stap_register_indirection_prefixes); 4438 set_gdbarch_stap_register_indirection_suffixes (gdbarch, 4439 stap_register_indirection_suffixes); 4440 set_gdbarch_stap_is_single_operand (gdbarch, 4441 i386_stap_is_single_operand); 4442 set_gdbarch_stap_parse_special_token (gdbarch, 4443 i386_stap_parse_special_token); 4444 4445 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); 4446 } 4447 4448 /* System V Release 4 (SVR4). */ 4449 4450 void 4451 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 4452 { 4453 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 4454 4455 /* System V Release 4 uses ELF. */ 4456 i386_elf_init_abi (info, gdbarch); 4457 4458 /* System V Release 4 has shared libraries. */ 4459 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); 4460 4461 tdep->sigtramp_p = i386_svr4_sigtramp_p; 4462 tdep->sigcontext_addr = i386_svr4_sigcontext_addr; 4463 tdep->sc_pc_offset = 36 + 14 * 4; 4464 tdep->sc_sp_offset = 36 + 17 * 4; 4465 4466 tdep->jb_pc_offset = 20; 4467 } 4468 4469 /* DJGPP. */ 4470 4471 static void 4472 i386_go32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 4473 { 4474 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 4475 4476 /* DJGPP doesn't have any special frames for signal handlers. */ 4477 tdep->sigtramp_p = NULL; 4478 4479 tdep->jb_pc_offset = 36; 4480 4481 /* DJGPP does not support the SSE registers. */ 4482 if (! tdesc_has_registers (info.target_desc)) 4483 tdep->tdesc = tdesc_i386_mmx; 4484 4485 /* Native compiler is GCC, which uses the SVR4 register numbering 4486 even in COFF and STABS. See the comment in i386_gdbarch_init, 4487 before the calls to set_gdbarch_stab_reg_to_regnum and 4488 set_gdbarch_sdb_reg_to_regnum. */ 4489 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); 4490 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); 4491 4492 set_gdbarch_has_dos_based_file_system (gdbarch, 1); 4493 4494 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); 4495 } 4496 4497 4498 /* i386 register groups. In addition to the normal groups, add "mmx" 4499 and "sse". */ 4500 4501 static struct reggroup *i386_sse_reggroup; 4502 static struct reggroup *i386_mmx_reggroup; 4503 4504 static void 4505 i386_init_reggroups (void) 4506 { 4507 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); 4508 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); 4509 } 4510 4511 static void 4512 i386_add_reggroups (struct gdbarch *gdbarch) 4513 { 4514 reggroup_add (gdbarch, i386_sse_reggroup); 4515 reggroup_add (gdbarch, i386_mmx_reggroup); 4516 reggroup_add (gdbarch, general_reggroup); 4517 reggroup_add (gdbarch, float_reggroup); 4518 reggroup_add (gdbarch, all_reggroup); 4519 reggroup_add (gdbarch, save_reggroup); 4520 reggroup_add (gdbarch, restore_reggroup); 4521 reggroup_add (gdbarch, vector_reggroup); 4522 reggroup_add (gdbarch, system_reggroup); 4523 } 4524 4525 int 4526 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 4527 struct reggroup *group) 4528 { 4529 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 4530 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, 4531 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p, 4532 bndr_regnum_p, bnd_regnum_p, k_regnum_p, zmm_regnum_p, zmmh_regnum_p, 4533 zmm_avx512_regnum_p, mpx_ctrl_regnum_p, xmm_avx512_regnum_p, 4534 avx512_p, avx_p, sse_p; 4535 4536 /* Don't include pseudo registers, except for MMX, in any register 4537 groups. */ 4538 if (i386_byte_regnum_p (gdbarch, regnum)) 4539 return 0; 4540 4541 if (i386_word_regnum_p (gdbarch, regnum)) 4542 return 0; 4543 4544 if (i386_dword_regnum_p (gdbarch, regnum)) 4545 return 0; 4546 4547 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); 4548 if (group == i386_mmx_reggroup) 4549 return mmx_regnum_p; 4550 4551 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); 4552 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum); 4553 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); 4554 if (group == i386_sse_reggroup) 4555 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p; 4556 4557 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); 4558 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum); 4559 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum); 4560 4561 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK) 4562 == X86_XSTATE_AVX512_MASK); 4563 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK) 4564 == X86_XSTATE_AVX_MASK) && !avx512_p; 4565 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX512_MASK) 4566 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p; 4567 4568 if (group == vector_reggroup) 4569 return (mmx_regnum_p 4570 || (zmm_regnum_p && avx512_p) 4571 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p) 4572 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p) 4573 || mxcsr_regnum_p); 4574 4575 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) 4576 || i386_fpc_regnum_p (gdbarch, regnum)); 4577 if (group == float_reggroup) 4578 return fp_regnum_p; 4579 4580 /* For "info reg all", don't include upper YMM registers nor XMM 4581 registers when AVX is supported. */ 4582 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); 4583 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum); 4584 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum); 4585 if (group == all_reggroup 4586 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p) 4587 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p) 4588 || ymmh_regnum_p 4589 || ymmh_avx512_regnum_p 4590 || zmmh_regnum_p)) 4591 return 0; 4592 4593 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum); 4594 if (group == all_reggroup 4595 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) 4596 return bnd_regnum_p; 4597 4598 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum); 4599 if (group == all_reggroup 4600 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) 4601 return 0; 4602 4603 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum); 4604 if (group == all_reggroup 4605 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) 4606 return mpx_ctrl_regnum_p; 4607 4608 if (group == general_reggroup) 4609 return (!fp_regnum_p 4610 && !mmx_regnum_p 4611 && !mxcsr_regnum_p 4612 && !xmm_regnum_p 4613 && !xmm_avx512_regnum_p 4614 && !ymm_regnum_p 4615 && !ymmh_regnum_p 4616 && !ymm_avx512_regnum_p 4617 && !ymmh_avx512_regnum_p 4618 && !bndr_regnum_p 4619 && !bnd_regnum_p 4620 && !mpx_ctrl_regnum_p 4621 && !zmm_regnum_p 4622 && !zmmh_regnum_p); 4623 4624 return default_register_reggroup_p (gdbarch, regnum, group); 4625 } 4626 4627 4628 /* Get the ARGIth function argument for the current function. */ 4629 4630 static CORE_ADDR 4631 i386_fetch_pointer_argument (struct frame_info *frame, int argi, 4632 struct type *type) 4633 { 4634 struct gdbarch *gdbarch = get_frame_arch (frame); 4635 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 4636 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); 4637 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); 4638 } 4639 4640 #define PREFIX_REPZ 0x01 4641 #define PREFIX_REPNZ 0x02 4642 #define PREFIX_LOCK 0x04 4643 #define PREFIX_DATA 0x08 4644 #define PREFIX_ADDR 0x10 4645 4646 /* operand size */ 4647 enum 4648 { 4649 OT_BYTE = 0, 4650 OT_WORD, 4651 OT_LONG, 4652 OT_QUAD, 4653 OT_DQUAD, 4654 }; 4655 4656 /* i386 arith/logic operations */ 4657 enum 4658 { 4659 OP_ADDL, 4660 OP_ORL, 4661 OP_ADCL, 4662 OP_SBBL, 4663 OP_ANDL, 4664 OP_SUBL, 4665 OP_XORL, 4666 OP_CMPL, 4667 }; 4668 4669 struct i386_record_s 4670 { 4671 struct gdbarch *gdbarch; 4672 struct regcache *regcache; 4673 CORE_ADDR orig_addr; 4674 CORE_ADDR addr; 4675 int aflag; 4676 int dflag; 4677 int override; 4678 uint8_t modrm; 4679 uint8_t mod, reg, rm; 4680 int ot; 4681 uint8_t rex_x; 4682 uint8_t rex_b; 4683 int rip_offset; 4684 int popl_esp_hack; 4685 const int *regmap; 4686 }; 4687 4688 /* Parse the "modrm" part of the memory address irp->addr points at. 4689 Returns -1 if something goes wrong, 0 otherwise. */ 4690 4691 static int 4692 i386_record_modrm (struct i386_record_s *irp) 4693 { 4694 struct gdbarch *gdbarch = irp->gdbarch; 4695 4696 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1)) 4697 return -1; 4698 4699 irp->addr++; 4700 irp->mod = (irp->modrm >> 6) & 3; 4701 irp->reg = (irp->modrm >> 3) & 7; 4702 irp->rm = irp->modrm & 7; 4703 4704 return 0; 4705 } 4706 4707 /* Extract the memory address that the current instruction writes to, 4708 and return it in *ADDR. Return -1 if something goes wrong. */ 4709 4710 static int 4711 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) 4712 { 4713 struct gdbarch *gdbarch = irp->gdbarch; 4714 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 4715 gdb_byte buf[4]; 4716 ULONGEST offset64; 4717 4718 *addr = 0; 4719 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM]) 4720 { 4721 /* 32/64 bits */ 4722 int havesib = 0; 4723 uint8_t scale = 0; 4724 uint8_t byte; 4725 uint8_t index = 0; 4726 uint8_t base = irp->rm; 4727 4728 if (base == 4) 4729 { 4730 havesib = 1; 4731 if (record_read_memory (gdbarch, irp->addr, &byte, 1)) 4732 return -1; 4733 irp->addr++; 4734 scale = (byte >> 6) & 3; 4735 index = ((byte >> 3) & 7) | irp->rex_x; 4736 base = (byte & 7); 4737 } 4738 base |= irp->rex_b; 4739 4740 switch (irp->mod) 4741 { 4742 case 0: 4743 if ((base & 7) == 5) 4744 { 4745 base = 0xff; 4746 if (record_read_memory (gdbarch, irp->addr, buf, 4)) 4747 return -1; 4748 irp->addr += 4; 4749 *addr = extract_signed_integer (buf, 4, byte_order); 4750 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) 4751 *addr += irp->addr + irp->rip_offset; 4752 } 4753 break; 4754 case 1: 4755 if (record_read_memory (gdbarch, irp->addr, buf, 1)) 4756 return -1; 4757 irp->addr++; 4758 *addr = (int8_t) buf[0]; 4759 break; 4760 case 2: 4761 if (record_read_memory (gdbarch, irp->addr, buf, 4)) 4762 return -1; 4763 *addr = extract_signed_integer (buf, 4, byte_order); 4764 irp->addr += 4; 4765 break; 4766 } 4767 4768 offset64 = 0; 4769 if (base != 0xff) 4770 { 4771 if (base == 4 && irp->popl_esp_hack) 4772 *addr += irp->popl_esp_hack; 4773 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], 4774 &offset64); 4775 } 4776 if (irp->aflag == 2) 4777 { 4778 *addr += offset64; 4779 } 4780 else 4781 *addr = (uint32_t) (offset64 + *addr); 4782 4783 if (havesib && (index != 4 || scale != 0)) 4784 { 4785 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], 4786 &offset64); 4787 if (irp->aflag == 2) 4788 *addr += offset64 << scale; 4789 else 4790 *addr = (uint32_t) (*addr + (offset64 << scale)); 4791 } 4792 4793 if (!irp->aflag) 4794 { 4795 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend 4796 address from 32-bit to 64-bit. */ 4797 *addr = (uint32_t) *addr; 4798 } 4799 } 4800 else 4801 { 4802 /* 16 bits */ 4803 switch (irp->mod) 4804 { 4805 case 0: 4806 if (irp->rm == 6) 4807 { 4808 if (record_read_memory (gdbarch, irp->addr, buf, 2)) 4809 return -1; 4810 irp->addr += 2; 4811 *addr = extract_signed_integer (buf, 2, byte_order); 4812 irp->rm = 0; 4813 goto no_rm; 4814 } 4815 break; 4816 case 1: 4817 if (record_read_memory (gdbarch, irp->addr, buf, 1)) 4818 return -1; 4819 irp->addr++; 4820 *addr = (int8_t) buf[0]; 4821 break; 4822 case 2: 4823 if (record_read_memory (gdbarch, irp->addr, buf, 2)) 4824 return -1; 4825 irp->addr += 2; 4826 *addr = extract_signed_integer (buf, 2, byte_order); 4827 break; 4828 } 4829 4830 switch (irp->rm) 4831 { 4832 case 0: 4833 regcache_raw_read_unsigned (irp->regcache, 4834 irp->regmap[X86_RECORD_REBX_REGNUM], 4835 &offset64); 4836 *addr = (uint32_t) (*addr + offset64); 4837 regcache_raw_read_unsigned (irp->regcache, 4838 irp->regmap[X86_RECORD_RESI_REGNUM], 4839 &offset64); 4840 *addr = (uint32_t) (*addr + offset64); 4841 break; 4842 case 1: 4843 regcache_raw_read_unsigned (irp->regcache, 4844 irp->regmap[X86_RECORD_REBX_REGNUM], 4845 &offset64); 4846 *addr = (uint32_t) (*addr + offset64); 4847 regcache_raw_read_unsigned (irp->regcache, 4848 irp->regmap[X86_RECORD_REDI_REGNUM], 4849 &offset64); 4850 *addr = (uint32_t) (*addr + offset64); 4851 break; 4852 case 2: 4853 regcache_raw_read_unsigned (irp->regcache, 4854 irp->regmap[X86_RECORD_REBP_REGNUM], 4855 &offset64); 4856 *addr = (uint32_t) (*addr + offset64); 4857 regcache_raw_read_unsigned (irp->regcache, 4858 irp->regmap[X86_RECORD_RESI_REGNUM], 4859 &offset64); 4860 *addr = (uint32_t) (*addr + offset64); 4861 break; 4862 case 3: 4863 regcache_raw_read_unsigned (irp->regcache, 4864 irp->regmap[X86_RECORD_REBP_REGNUM], 4865 &offset64); 4866 *addr = (uint32_t) (*addr + offset64); 4867 regcache_raw_read_unsigned (irp->regcache, 4868 irp->regmap[X86_RECORD_REDI_REGNUM], 4869 &offset64); 4870 *addr = (uint32_t) (*addr + offset64); 4871 break; 4872 case 4: 4873 regcache_raw_read_unsigned (irp->regcache, 4874 irp->regmap[X86_RECORD_RESI_REGNUM], 4875 &offset64); 4876 *addr = (uint32_t) (*addr + offset64); 4877 break; 4878 case 5: 4879 regcache_raw_read_unsigned (irp->regcache, 4880 irp->regmap[X86_RECORD_REDI_REGNUM], 4881 &offset64); 4882 *addr = (uint32_t) (*addr + offset64); 4883 break; 4884 case 6: 4885 regcache_raw_read_unsigned (irp->regcache, 4886 irp->regmap[X86_RECORD_REBP_REGNUM], 4887 &offset64); 4888 *addr = (uint32_t) (*addr + offset64); 4889 break; 4890 case 7: 4891 regcache_raw_read_unsigned (irp->regcache, 4892 irp->regmap[X86_RECORD_REBX_REGNUM], 4893 &offset64); 4894 *addr = (uint32_t) (*addr + offset64); 4895 break; 4896 } 4897 *addr &= 0xffff; 4898 } 4899 4900 no_rm: 4901 return 0; 4902 } 4903 4904 /* Record the address and contents of the memory that will be changed 4905 by the current instruction. Return -1 if something goes wrong, 0 4906 otherwise. */ 4907 4908 static int 4909 i386_record_lea_modrm (struct i386_record_s *irp) 4910 { 4911 struct gdbarch *gdbarch = irp->gdbarch; 4912 uint64_t addr; 4913 4914 if (irp->override >= 0) 4915 { 4916 if (record_full_memory_query) 4917 { 4918 if (yquery (_("\ 4919 Process record ignores the memory change of instruction at address %s\n\ 4920 because it can't get the value of the segment register.\n\ 4921 Do you want to stop the program?"), 4922 paddress (gdbarch, irp->orig_addr))) 4923 return -1; 4924 } 4925 4926 return 0; 4927 } 4928 4929 if (i386_record_lea_modrm_addr (irp, &addr)) 4930 return -1; 4931 4932 if (record_full_arch_list_add_mem (addr, 1 << irp->ot)) 4933 return -1; 4934 4935 return 0; 4936 } 4937 4938 /* Record the effects of a push operation. Return -1 if something 4939 goes wrong, 0 otherwise. */ 4940 4941 static int 4942 i386_record_push (struct i386_record_s *irp, int size) 4943 { 4944 ULONGEST addr; 4945 4946 if (record_full_arch_list_add_reg (irp->regcache, 4947 irp->regmap[X86_RECORD_RESP_REGNUM])) 4948 return -1; 4949 regcache_raw_read_unsigned (irp->regcache, 4950 irp->regmap[X86_RECORD_RESP_REGNUM], 4951 &addr); 4952 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size)) 4953 return -1; 4954 4955 return 0; 4956 } 4957 4958 4959 /* Defines contents to record. */ 4960 #define I386_SAVE_FPU_REGS 0xfffd 4961 #define I386_SAVE_FPU_ENV 0xfffe 4962 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff 4963 4964 /* Record the values of the floating point registers which will be 4965 changed by the current instruction. Returns -1 if something is 4966 wrong, 0 otherwise. */ 4967 4968 static int i386_record_floats (struct gdbarch *gdbarch, 4969 struct i386_record_s *ir, 4970 uint32_t iregnum) 4971 { 4972 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 4973 int i; 4974 4975 /* Oza: Because of floating point insn push/pop of fpu stack is going to 4976 happen. Currently we store st0-st7 registers, but we need not store all 4977 registers all the time, in future we use ftag register and record only 4978 those who are not marked as an empty. */ 4979 4980 if (I386_SAVE_FPU_REGS == iregnum) 4981 { 4982 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) 4983 { 4984 if (record_full_arch_list_add_reg (ir->regcache, i)) 4985 return -1; 4986 } 4987 } 4988 else if (I386_SAVE_FPU_ENV == iregnum) 4989 { 4990 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) 4991 { 4992 if (record_full_arch_list_add_reg (ir->regcache, i)) 4993 return -1; 4994 } 4995 } 4996 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) 4997 { 4998 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) 4999 { 5000 if (record_full_arch_list_add_reg (ir->regcache, i)) 5001 return -1; 5002 } 5003 } 5004 else if ((iregnum >= I387_ST0_REGNUM (tdep)) && 5005 (iregnum <= I387_FOP_REGNUM (tdep))) 5006 { 5007 if (record_full_arch_list_add_reg (ir->regcache,iregnum)) 5008 return -1; 5009 } 5010 else 5011 { 5012 /* Parameter error. */ 5013 return -1; 5014 } 5015 if(I386_SAVE_FPU_ENV != iregnum) 5016 { 5017 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) 5018 { 5019 if (record_full_arch_list_add_reg (ir->regcache, i)) 5020 return -1; 5021 } 5022 } 5023 return 0; 5024 } 5025 5026 /* Parse the current instruction, and record the values of the 5027 registers and memory that will be changed by the current 5028 instruction. Returns -1 if something goes wrong, 0 otherwise. */ 5029 5030 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \ 5031 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) 5032 5033 int 5034 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, 5035 CORE_ADDR input_addr) 5036 { 5037 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 5038 int prefixes = 0; 5039 int regnum = 0; 5040 uint32_t opcode; 5041 uint8_t opcode8; 5042 ULONGEST addr; 5043 gdb_byte buf[MAX_REGISTER_SIZE]; 5044 struct i386_record_s ir; 5045 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 5046 uint8_t rex_w = -1; 5047 uint8_t rex_r = 0; 5048 5049 memset (&ir, 0, sizeof (struct i386_record_s)); 5050 ir.regcache = regcache; 5051 ir.addr = input_addr; 5052 ir.orig_addr = input_addr; 5053 ir.aflag = 1; 5054 ir.dflag = 1; 5055 ir.override = -1; 5056 ir.popl_esp_hack = 0; 5057 ir.regmap = tdep->record_regmap; 5058 ir.gdbarch = gdbarch; 5059 5060 if (record_debug > 1) 5061 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " 5062 "addr = %s\n", 5063 paddress (gdbarch, ir.addr)); 5064 5065 /* prefixes */ 5066 while (1) 5067 { 5068 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) 5069 return -1; 5070 ir.addr++; 5071 switch (opcode8) /* Instruction prefixes */ 5072 { 5073 case REPE_PREFIX_OPCODE: 5074 prefixes |= PREFIX_REPZ; 5075 break; 5076 case REPNE_PREFIX_OPCODE: 5077 prefixes |= PREFIX_REPNZ; 5078 break; 5079 case LOCK_PREFIX_OPCODE: 5080 prefixes |= PREFIX_LOCK; 5081 break; 5082 case CS_PREFIX_OPCODE: 5083 ir.override = X86_RECORD_CS_REGNUM; 5084 break; 5085 case SS_PREFIX_OPCODE: 5086 ir.override = X86_RECORD_SS_REGNUM; 5087 break; 5088 case DS_PREFIX_OPCODE: 5089 ir.override = X86_RECORD_DS_REGNUM; 5090 break; 5091 case ES_PREFIX_OPCODE: 5092 ir.override = X86_RECORD_ES_REGNUM; 5093 break; 5094 case FS_PREFIX_OPCODE: 5095 ir.override = X86_RECORD_FS_REGNUM; 5096 break; 5097 case GS_PREFIX_OPCODE: 5098 ir.override = X86_RECORD_GS_REGNUM; 5099 break; 5100 case DATA_PREFIX_OPCODE: 5101 prefixes |= PREFIX_DATA; 5102 break; 5103 case ADDR_PREFIX_OPCODE: 5104 prefixes |= PREFIX_ADDR; 5105 break; 5106 case 0x40: /* i386 inc %eax */ 5107 case 0x41: /* i386 inc %ecx */ 5108 case 0x42: /* i386 inc %edx */ 5109 case 0x43: /* i386 inc %ebx */ 5110 case 0x44: /* i386 inc %esp */ 5111 case 0x45: /* i386 inc %ebp */ 5112 case 0x46: /* i386 inc %esi */ 5113 case 0x47: /* i386 inc %edi */ 5114 case 0x48: /* i386 dec %eax */ 5115 case 0x49: /* i386 dec %ecx */ 5116 case 0x4a: /* i386 dec %edx */ 5117 case 0x4b: /* i386 dec %ebx */ 5118 case 0x4c: /* i386 dec %esp */ 5119 case 0x4d: /* i386 dec %ebp */ 5120 case 0x4e: /* i386 dec %esi */ 5121 case 0x4f: /* i386 dec %edi */ 5122 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ 5123 { 5124 /* REX */ 5125 rex_w = (opcode8 >> 3) & 1; 5126 rex_r = (opcode8 & 0x4) << 1; 5127 ir.rex_x = (opcode8 & 0x2) << 2; 5128 ir.rex_b = (opcode8 & 0x1) << 3; 5129 } 5130 else /* 32 bit target */ 5131 goto out_prefixes; 5132 break; 5133 default: 5134 goto out_prefixes; 5135 break; 5136 } 5137 } 5138 out_prefixes: 5139 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) 5140 { 5141 ir.dflag = 2; 5142 } 5143 else 5144 { 5145 if (prefixes & PREFIX_DATA) 5146 ir.dflag ^= 1; 5147 } 5148 if (prefixes & PREFIX_ADDR) 5149 ir.aflag ^= 1; 5150 else if (ir.regmap[X86_RECORD_R8_REGNUM]) 5151 ir.aflag = 2; 5152 5153 /* Now check op code. */ 5154 opcode = (uint32_t) opcode8; 5155 reswitch: 5156 switch (opcode) 5157 { 5158 case 0x0f: 5159 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) 5160 return -1; 5161 ir.addr++; 5162 opcode = (uint32_t) opcode8 | 0x0f00; 5163 goto reswitch; 5164 break; 5165 5166 case 0x00: /* arith & logic */ 5167 case 0x01: 5168 case 0x02: 5169 case 0x03: 5170 case 0x04: 5171 case 0x05: 5172 case 0x08: 5173 case 0x09: 5174 case 0x0a: 5175 case 0x0b: 5176 case 0x0c: 5177 case 0x0d: 5178 case 0x10: 5179 case 0x11: 5180 case 0x12: 5181 case 0x13: 5182 case 0x14: 5183 case 0x15: 5184 case 0x18: 5185 case 0x19: 5186 case 0x1a: 5187 case 0x1b: 5188 case 0x1c: 5189 case 0x1d: 5190 case 0x20: 5191 case 0x21: 5192 case 0x22: 5193 case 0x23: 5194 case 0x24: 5195 case 0x25: 5196 case 0x28: 5197 case 0x29: 5198 case 0x2a: 5199 case 0x2b: 5200 case 0x2c: 5201 case 0x2d: 5202 case 0x30: 5203 case 0x31: 5204 case 0x32: 5205 case 0x33: 5206 case 0x34: 5207 case 0x35: 5208 case 0x38: 5209 case 0x39: 5210 case 0x3a: 5211 case 0x3b: 5212 case 0x3c: 5213 case 0x3d: 5214 if (((opcode >> 3) & 7) != OP_CMPL) 5215 { 5216 if ((opcode & 1) == 0) 5217 ir.ot = OT_BYTE; 5218 else 5219 ir.ot = ir.dflag + OT_WORD; 5220 5221 switch ((opcode >> 1) & 3) 5222 { 5223 case 0: /* OP Ev, Gv */ 5224 if (i386_record_modrm (&ir)) 5225 return -1; 5226 if (ir.mod != 3) 5227 { 5228 if (i386_record_lea_modrm (&ir)) 5229 return -1; 5230 } 5231 else 5232 { 5233 ir.rm |= ir.rex_b; 5234 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5235 ir.rm &= 0x3; 5236 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 5237 } 5238 break; 5239 case 1: /* OP Gv, Ev */ 5240 if (i386_record_modrm (&ir)) 5241 return -1; 5242 ir.reg |= rex_r; 5243 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5244 ir.reg &= 0x3; 5245 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5246 break; 5247 case 2: /* OP A, Iv */ 5248 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5249 break; 5250 } 5251 } 5252 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5253 break; 5254 5255 case 0x80: /* GRP1 */ 5256 case 0x81: 5257 case 0x82: 5258 case 0x83: 5259 if (i386_record_modrm (&ir)) 5260 return -1; 5261 5262 if (ir.reg != OP_CMPL) 5263 { 5264 if ((opcode & 1) == 0) 5265 ir.ot = OT_BYTE; 5266 else 5267 ir.ot = ir.dflag + OT_WORD; 5268 5269 if (ir.mod != 3) 5270 { 5271 if (opcode == 0x83) 5272 ir.rip_offset = 1; 5273 else 5274 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 5275 if (i386_record_lea_modrm (&ir)) 5276 return -1; 5277 } 5278 else 5279 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 5280 } 5281 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5282 break; 5283 5284 case 0x40: /* inc */ 5285 case 0x41: 5286 case 0x42: 5287 case 0x43: 5288 case 0x44: 5289 case 0x45: 5290 case 0x46: 5291 case 0x47: 5292 5293 case 0x48: /* dec */ 5294 case 0x49: 5295 case 0x4a: 5296 case 0x4b: 5297 case 0x4c: 5298 case 0x4d: 5299 case 0x4e: 5300 case 0x4f: 5301 5302 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7); 5303 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5304 break; 5305 5306 case 0xf6: /* GRP3 */ 5307 case 0xf7: 5308 if ((opcode & 1) == 0) 5309 ir.ot = OT_BYTE; 5310 else 5311 ir.ot = ir.dflag + OT_WORD; 5312 if (i386_record_modrm (&ir)) 5313 return -1; 5314 5315 if (ir.mod != 3 && ir.reg == 0) 5316 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 5317 5318 switch (ir.reg) 5319 { 5320 case 0: /* test */ 5321 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5322 break; 5323 case 2: /* not */ 5324 case 3: /* neg */ 5325 if (ir.mod != 3) 5326 { 5327 if (i386_record_lea_modrm (&ir)) 5328 return -1; 5329 } 5330 else 5331 { 5332 ir.rm |= ir.rex_b; 5333 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5334 ir.rm &= 0x3; 5335 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 5336 } 5337 if (ir.reg == 3) /* neg */ 5338 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5339 break; 5340 case 4: /* mul */ 5341 case 5: /* imul */ 5342 case 6: /* div */ 5343 case 7: /* idiv */ 5344 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5345 if (ir.ot != OT_BYTE) 5346 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 5347 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5348 break; 5349 default: 5350 ir.addr -= 2; 5351 opcode = opcode << 8 | ir.modrm; 5352 goto no_support; 5353 break; 5354 } 5355 break; 5356 5357 case 0xfe: /* GRP4 */ 5358 case 0xff: /* GRP5 */ 5359 if (i386_record_modrm (&ir)) 5360 return -1; 5361 if (ir.reg >= 2 && opcode == 0xfe) 5362 { 5363 ir.addr -= 2; 5364 opcode = opcode << 8 | ir.modrm; 5365 goto no_support; 5366 } 5367 switch (ir.reg) 5368 { 5369 case 0: /* inc */ 5370 case 1: /* dec */ 5371 if ((opcode & 1) == 0) 5372 ir.ot = OT_BYTE; 5373 else 5374 ir.ot = ir.dflag + OT_WORD; 5375 if (ir.mod != 3) 5376 { 5377 if (i386_record_lea_modrm (&ir)) 5378 return -1; 5379 } 5380 else 5381 { 5382 ir.rm |= ir.rex_b; 5383 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5384 ir.rm &= 0x3; 5385 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 5386 } 5387 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5388 break; 5389 case 2: /* call */ 5390 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 5391 ir.dflag = 2; 5392 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5393 return -1; 5394 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5395 break; 5396 case 3: /* lcall */ 5397 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); 5398 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5399 return -1; 5400 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5401 break; 5402 case 4: /* jmp */ 5403 case 5: /* ljmp */ 5404 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5405 break; 5406 case 6: /* push */ 5407 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 5408 ir.dflag = 2; 5409 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5410 return -1; 5411 break; 5412 default: 5413 ir.addr -= 2; 5414 opcode = opcode << 8 | ir.modrm; 5415 goto no_support; 5416 break; 5417 } 5418 break; 5419 5420 case 0x84: /* test */ 5421 case 0x85: 5422 case 0xa8: 5423 case 0xa9: 5424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5425 break; 5426 5427 case 0x98: /* CWDE/CBW */ 5428 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5429 break; 5430 5431 case 0x99: /* CDQ/CWD */ 5432 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5433 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 5434 break; 5435 5436 case 0x0faf: /* imul */ 5437 case 0x69: 5438 case 0x6b: 5439 ir.ot = ir.dflag + OT_WORD; 5440 if (i386_record_modrm (&ir)) 5441 return -1; 5442 if (opcode == 0x69) 5443 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 5444 else if (opcode == 0x6b) 5445 ir.rip_offset = 1; 5446 ir.reg |= rex_r; 5447 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5448 ir.reg &= 0x3; 5449 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5450 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5451 break; 5452 5453 case 0x0fc0: /* xadd */ 5454 case 0x0fc1: 5455 if ((opcode & 1) == 0) 5456 ir.ot = OT_BYTE; 5457 else 5458 ir.ot = ir.dflag + OT_WORD; 5459 if (i386_record_modrm (&ir)) 5460 return -1; 5461 ir.reg |= rex_r; 5462 if (ir.mod == 3) 5463 { 5464 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5465 ir.reg &= 0x3; 5466 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5467 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5468 ir.rm &= 0x3; 5469 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 5470 } 5471 else 5472 { 5473 if (i386_record_lea_modrm (&ir)) 5474 return -1; 5475 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5476 ir.reg &= 0x3; 5477 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5478 } 5479 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5480 break; 5481 5482 case 0x0fb0: /* cmpxchg */ 5483 case 0x0fb1: 5484 if ((opcode & 1) == 0) 5485 ir.ot = OT_BYTE; 5486 else 5487 ir.ot = ir.dflag + OT_WORD; 5488 if (i386_record_modrm (&ir)) 5489 return -1; 5490 if (ir.mod == 3) 5491 { 5492 ir.reg |= rex_r; 5493 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5494 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5495 ir.reg &= 0x3; 5496 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5497 } 5498 else 5499 { 5500 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5501 if (i386_record_lea_modrm (&ir)) 5502 return -1; 5503 } 5504 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5505 break; 5506 5507 case 0x0fc7: /* cmpxchg8b */ 5508 if (i386_record_modrm (&ir)) 5509 return -1; 5510 if (ir.mod == 3) 5511 { 5512 ir.addr -= 2; 5513 opcode = opcode << 8 | ir.modrm; 5514 goto no_support; 5515 } 5516 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5517 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 5518 if (i386_record_lea_modrm (&ir)) 5519 return -1; 5520 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5521 break; 5522 5523 case 0x50: /* push */ 5524 case 0x51: 5525 case 0x52: 5526 case 0x53: 5527 case 0x54: 5528 case 0x55: 5529 case 0x56: 5530 case 0x57: 5531 case 0x68: 5532 case 0x6a: 5533 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 5534 ir.dflag = 2; 5535 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5536 return -1; 5537 break; 5538 5539 case 0x06: /* push es */ 5540 case 0x0e: /* push cs */ 5541 case 0x16: /* push ss */ 5542 case 0x1e: /* push ds */ 5543 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5544 { 5545 ir.addr -= 1; 5546 goto no_support; 5547 } 5548 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5549 return -1; 5550 break; 5551 5552 case 0x0fa0: /* push fs */ 5553 case 0x0fa8: /* push gs */ 5554 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5555 { 5556 ir.addr -= 2; 5557 goto no_support; 5558 } 5559 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5560 return -1; 5561 break; 5562 5563 case 0x60: /* pusha */ 5564 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5565 { 5566 ir.addr -= 1; 5567 goto no_support; 5568 } 5569 if (i386_record_push (&ir, 1 << (ir.dflag + 4))) 5570 return -1; 5571 break; 5572 5573 case 0x58: /* pop */ 5574 case 0x59: 5575 case 0x5a: 5576 case 0x5b: 5577 case 0x5c: 5578 case 0x5d: 5579 case 0x5e: 5580 case 0x5f: 5581 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5582 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); 5583 break; 5584 5585 case 0x61: /* popa */ 5586 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5587 { 5588 ir.addr -= 1; 5589 goto no_support; 5590 } 5591 for (regnum = X86_RECORD_REAX_REGNUM; 5592 regnum <= X86_RECORD_REDI_REGNUM; 5593 regnum++) 5594 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); 5595 break; 5596 5597 case 0x8f: /* pop */ 5598 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5599 ir.ot = ir.dflag ? OT_QUAD : OT_WORD; 5600 else 5601 ir.ot = ir.dflag + OT_WORD; 5602 if (i386_record_modrm (&ir)) 5603 return -1; 5604 if (ir.mod == 3) 5605 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 5606 else 5607 { 5608 ir.popl_esp_hack = 1 << ir.ot; 5609 if (i386_record_lea_modrm (&ir)) 5610 return -1; 5611 } 5612 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5613 break; 5614 5615 case 0xc8: /* enter */ 5616 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); 5617 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 5618 ir.dflag = 2; 5619 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5620 return -1; 5621 break; 5622 5623 case 0xc9: /* leave */ 5624 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5625 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); 5626 break; 5627 5628 case 0x07: /* pop es */ 5629 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5630 { 5631 ir.addr -= 1; 5632 goto no_support; 5633 } 5634 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5635 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); 5636 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5637 break; 5638 5639 case 0x17: /* pop ss */ 5640 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5641 { 5642 ir.addr -= 1; 5643 goto no_support; 5644 } 5645 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5646 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); 5647 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5648 break; 5649 5650 case 0x1f: /* pop ds */ 5651 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5652 { 5653 ir.addr -= 1; 5654 goto no_support; 5655 } 5656 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5657 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); 5658 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5659 break; 5660 5661 case 0x0fa1: /* pop fs */ 5662 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5663 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); 5664 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5665 break; 5666 5667 case 0x0fa9: /* pop gs */ 5668 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5669 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); 5670 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5671 break; 5672 5673 case 0x88: /* mov */ 5674 case 0x89: 5675 case 0xc6: 5676 case 0xc7: 5677 if ((opcode & 1) == 0) 5678 ir.ot = OT_BYTE; 5679 else 5680 ir.ot = ir.dflag + OT_WORD; 5681 5682 if (i386_record_modrm (&ir)) 5683 return -1; 5684 5685 if (ir.mod != 3) 5686 { 5687 if (opcode == 0xc6 || opcode == 0xc7) 5688 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 5689 if (i386_record_lea_modrm (&ir)) 5690 return -1; 5691 } 5692 else 5693 { 5694 if (opcode == 0xc6 || opcode == 0xc7) 5695 ir.rm |= ir.rex_b; 5696 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5697 ir.rm &= 0x3; 5698 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 5699 } 5700 break; 5701 5702 case 0x8a: /* mov */ 5703 case 0x8b: 5704 if ((opcode & 1) == 0) 5705 ir.ot = OT_BYTE; 5706 else 5707 ir.ot = ir.dflag + OT_WORD; 5708 if (i386_record_modrm (&ir)) 5709 return -1; 5710 ir.reg |= rex_r; 5711 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5712 ir.reg &= 0x3; 5713 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5714 break; 5715 5716 case 0x8c: /* mov seg */ 5717 if (i386_record_modrm (&ir)) 5718 return -1; 5719 if (ir.reg > 5) 5720 { 5721 ir.addr -= 2; 5722 opcode = opcode << 8 | ir.modrm; 5723 goto no_support; 5724 } 5725 5726 if (ir.mod == 3) 5727 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 5728 else 5729 { 5730 ir.ot = OT_WORD; 5731 if (i386_record_lea_modrm (&ir)) 5732 return -1; 5733 } 5734 break; 5735 5736 case 0x8e: /* mov seg */ 5737 if (i386_record_modrm (&ir)) 5738 return -1; 5739 switch (ir.reg) 5740 { 5741 case 0: 5742 regnum = X86_RECORD_ES_REGNUM; 5743 break; 5744 case 2: 5745 regnum = X86_RECORD_SS_REGNUM; 5746 break; 5747 case 3: 5748 regnum = X86_RECORD_DS_REGNUM; 5749 break; 5750 case 4: 5751 regnum = X86_RECORD_FS_REGNUM; 5752 break; 5753 case 5: 5754 regnum = X86_RECORD_GS_REGNUM; 5755 break; 5756 default: 5757 ir.addr -= 2; 5758 opcode = opcode << 8 | ir.modrm; 5759 goto no_support; 5760 break; 5761 } 5762 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); 5763 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5764 break; 5765 5766 case 0x0fb6: /* movzbS */ 5767 case 0x0fb7: /* movzwS */ 5768 case 0x0fbe: /* movsbS */ 5769 case 0x0fbf: /* movswS */ 5770 if (i386_record_modrm (&ir)) 5771 return -1; 5772 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); 5773 break; 5774 5775 case 0x8d: /* lea */ 5776 if (i386_record_modrm (&ir)) 5777 return -1; 5778 if (ir.mod == 3) 5779 { 5780 ir.addr -= 2; 5781 opcode = opcode << 8 | ir.modrm; 5782 goto no_support; 5783 } 5784 ir.ot = ir.dflag; 5785 ir.reg |= rex_r; 5786 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5787 ir.reg &= 0x3; 5788 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5789 break; 5790 5791 case 0xa0: /* mov EAX */ 5792 case 0xa1: 5793 5794 case 0xd7: /* xlat */ 5795 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5796 break; 5797 5798 case 0xa2: /* mov EAX */ 5799 case 0xa3: 5800 if (ir.override >= 0) 5801 { 5802 if (record_full_memory_query) 5803 { 5804 if (yquery (_("\ 5805 Process record ignores the memory change of instruction at address %s\n\ 5806 because it can't get the value of the segment register.\n\ 5807 Do you want to stop the program?"), 5808 paddress (gdbarch, ir.orig_addr))) 5809 return -1; 5810 } 5811 } 5812 else 5813 { 5814 if ((opcode & 1) == 0) 5815 ir.ot = OT_BYTE; 5816 else 5817 ir.ot = ir.dflag + OT_WORD; 5818 if (ir.aflag == 2) 5819 { 5820 if (record_read_memory (gdbarch, ir.addr, buf, 8)) 5821 return -1; 5822 ir.addr += 8; 5823 addr = extract_unsigned_integer (buf, 8, byte_order); 5824 } 5825 else if (ir.aflag) 5826 { 5827 if (record_read_memory (gdbarch, ir.addr, buf, 4)) 5828 return -1; 5829 ir.addr += 4; 5830 addr = extract_unsigned_integer (buf, 4, byte_order); 5831 } 5832 else 5833 { 5834 if (record_read_memory (gdbarch, ir.addr, buf, 2)) 5835 return -1; 5836 ir.addr += 2; 5837 addr = extract_unsigned_integer (buf, 2, byte_order); 5838 } 5839 if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) 5840 return -1; 5841 } 5842 break; 5843 5844 case 0xb0: /* mov R, Ib */ 5845 case 0xb1: 5846 case 0xb2: 5847 case 0xb3: 5848 case 0xb4: 5849 case 0xb5: 5850 case 0xb6: 5851 case 0xb7: 5852 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) 5853 ? ((opcode & 0x7) | ir.rex_b) 5854 : ((opcode & 0x7) & 0x3)); 5855 break; 5856 5857 case 0xb8: /* mov R, Iv */ 5858 case 0xb9: 5859 case 0xba: 5860 case 0xbb: 5861 case 0xbc: 5862 case 0xbd: 5863 case 0xbe: 5864 case 0xbf: 5865 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); 5866 break; 5867 5868 case 0x91: /* xchg R, EAX */ 5869 case 0x92: 5870 case 0x93: 5871 case 0x94: 5872 case 0x95: 5873 case 0x96: 5874 case 0x97: 5875 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5876 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7); 5877 break; 5878 5879 case 0x86: /* xchg Ev, Gv */ 5880 case 0x87: 5881 if ((opcode & 1) == 0) 5882 ir.ot = OT_BYTE; 5883 else 5884 ir.ot = ir.dflag + OT_WORD; 5885 if (i386_record_modrm (&ir)) 5886 return -1; 5887 if (ir.mod == 3) 5888 { 5889 ir.rm |= ir.rex_b; 5890 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5891 ir.rm &= 0x3; 5892 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 5893 } 5894 else 5895 { 5896 if (i386_record_lea_modrm (&ir)) 5897 return -1; 5898 } 5899 ir.reg |= rex_r; 5900 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5901 ir.reg &= 0x3; 5902 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5903 break; 5904 5905 case 0xc4: /* les Gv */ 5906 case 0xc5: /* lds Gv */ 5907 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5908 { 5909 ir.addr -= 1; 5910 goto no_support; 5911 } 5912 /* FALLTHROUGH */ 5913 case 0x0fb2: /* lss Gv */ 5914 case 0x0fb4: /* lfs Gv */ 5915 case 0x0fb5: /* lgs Gv */ 5916 if (i386_record_modrm (&ir)) 5917 return -1; 5918 if (ir.mod == 3) 5919 { 5920 if (opcode > 0xff) 5921 ir.addr -= 3; 5922 else 5923 ir.addr -= 2; 5924 opcode = opcode << 8 | ir.modrm; 5925 goto no_support; 5926 } 5927 switch (opcode) 5928 { 5929 case 0xc4: /* les Gv */ 5930 regnum = X86_RECORD_ES_REGNUM; 5931 break; 5932 case 0xc5: /* lds Gv */ 5933 regnum = X86_RECORD_DS_REGNUM; 5934 break; 5935 case 0x0fb2: /* lss Gv */ 5936 regnum = X86_RECORD_SS_REGNUM; 5937 break; 5938 case 0x0fb4: /* lfs Gv */ 5939 regnum = X86_RECORD_FS_REGNUM; 5940 break; 5941 case 0x0fb5: /* lgs Gv */ 5942 regnum = X86_RECORD_GS_REGNUM; 5943 break; 5944 } 5945 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); 5946 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); 5947 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5948 break; 5949 5950 case 0xc0: /* shifts */ 5951 case 0xc1: 5952 case 0xd0: 5953 case 0xd1: 5954 case 0xd2: 5955 case 0xd3: 5956 if ((opcode & 1) == 0) 5957 ir.ot = OT_BYTE; 5958 else 5959 ir.ot = ir.dflag + OT_WORD; 5960 if (i386_record_modrm (&ir)) 5961 return -1; 5962 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) 5963 { 5964 if (i386_record_lea_modrm (&ir)) 5965 return -1; 5966 } 5967 else 5968 { 5969 ir.rm |= ir.rex_b; 5970 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5971 ir.rm &= 0x3; 5972 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 5973 } 5974 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5975 break; 5976 5977 case 0x0fa4: 5978 case 0x0fa5: 5979 case 0x0fac: 5980 case 0x0fad: 5981 if (i386_record_modrm (&ir)) 5982 return -1; 5983 if (ir.mod == 3) 5984 { 5985 if (record_full_arch_list_add_reg (ir.regcache, ir.rm)) 5986 return -1; 5987 } 5988 else 5989 { 5990 if (i386_record_lea_modrm (&ir)) 5991 return -1; 5992 } 5993 break; 5994 5995 case 0xd8: /* Floats. */ 5996 case 0xd9: 5997 case 0xda: 5998 case 0xdb: 5999 case 0xdc: 6000 case 0xdd: 6001 case 0xde: 6002 case 0xdf: 6003 if (i386_record_modrm (&ir)) 6004 return -1; 6005 ir.reg |= ((opcode & 7) << 3); 6006 if (ir.mod != 3) 6007 { 6008 /* Memory. */ 6009 uint64_t addr64; 6010 6011 if (i386_record_lea_modrm_addr (&ir, &addr64)) 6012 return -1; 6013 switch (ir.reg) 6014 { 6015 case 0x02: 6016 case 0x12: 6017 case 0x22: 6018 case 0x32: 6019 /* For fcom, ficom nothing to do. */ 6020 break; 6021 case 0x03: 6022 case 0x13: 6023 case 0x23: 6024 case 0x33: 6025 /* For fcomp, ficomp pop FPU stack, store all. */ 6026 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 6027 return -1; 6028 break; 6029 case 0x00: 6030 case 0x01: 6031 case 0x04: 6032 case 0x05: 6033 case 0x06: 6034 case 0x07: 6035 case 0x10: 6036 case 0x11: 6037 case 0x14: 6038 case 0x15: 6039 case 0x16: 6040 case 0x17: 6041 case 0x20: 6042 case 0x21: 6043 case 0x24: 6044 case 0x25: 6045 case 0x26: 6046 case 0x27: 6047 case 0x30: 6048 case 0x31: 6049 case 0x34: 6050 case 0x35: 6051 case 0x36: 6052 case 0x37: 6053 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, 6054 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension 6055 of code, always affects st(0) register. */ 6056 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) 6057 return -1; 6058 break; 6059 case 0x08: 6060 case 0x0a: 6061 case 0x0b: 6062 case 0x18: 6063 case 0x19: 6064 case 0x1a: 6065 case 0x1b: 6066 case 0x1d: 6067 case 0x28: 6068 case 0x29: 6069 case 0x2a: 6070 case 0x2b: 6071 case 0x38: 6072 case 0x39: 6073 case 0x3a: 6074 case 0x3b: 6075 case 0x3c: 6076 case 0x3d: 6077 switch (ir.reg & 7) 6078 { 6079 case 0: 6080 /* Handling fld, fild. */ 6081 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 6082 return -1; 6083 break; 6084 case 1: 6085 switch (ir.reg >> 4) 6086 { 6087 case 0: 6088 if (record_full_arch_list_add_mem (addr64, 4)) 6089 return -1; 6090 break; 6091 case 2: 6092 if (record_full_arch_list_add_mem (addr64, 8)) 6093 return -1; 6094 break; 6095 case 3: 6096 break; 6097 default: 6098 if (record_full_arch_list_add_mem (addr64, 2)) 6099 return -1; 6100 break; 6101 } 6102 break; 6103 default: 6104 switch (ir.reg >> 4) 6105 { 6106 case 0: 6107 if (record_full_arch_list_add_mem (addr64, 4)) 6108 return -1; 6109 if (3 == (ir.reg & 7)) 6110 { 6111 /* For fstp m32fp. */ 6112 if (i386_record_floats (gdbarch, &ir, 6113 I386_SAVE_FPU_REGS)) 6114 return -1; 6115 } 6116 break; 6117 case 1: 6118 if (record_full_arch_list_add_mem (addr64, 4)) 6119 return -1; 6120 if ((3 == (ir.reg & 7)) 6121 || (5 == (ir.reg & 7)) 6122 || (7 == (ir.reg & 7))) 6123 { 6124 /* For fstp insn. */ 6125 if (i386_record_floats (gdbarch, &ir, 6126 I386_SAVE_FPU_REGS)) 6127 return -1; 6128 } 6129 break; 6130 case 2: 6131 if (record_full_arch_list_add_mem (addr64, 8)) 6132 return -1; 6133 if (3 == (ir.reg & 7)) 6134 { 6135 /* For fstp m64fp. */ 6136 if (i386_record_floats (gdbarch, &ir, 6137 I386_SAVE_FPU_REGS)) 6138 return -1; 6139 } 6140 break; 6141 case 3: 6142 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) 6143 { 6144 /* For fistp, fbld, fild, fbstp. */ 6145 if (i386_record_floats (gdbarch, &ir, 6146 I386_SAVE_FPU_REGS)) 6147 return -1; 6148 } 6149 /* Fall through */ 6150 default: 6151 if (record_full_arch_list_add_mem (addr64, 2)) 6152 return -1; 6153 break; 6154 } 6155 break; 6156 } 6157 break; 6158 case 0x0c: 6159 /* Insn fldenv. */ 6160 if (i386_record_floats (gdbarch, &ir, 6161 I386_SAVE_FPU_ENV_REG_STACK)) 6162 return -1; 6163 break; 6164 case 0x0d: 6165 /* Insn fldcw. */ 6166 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) 6167 return -1; 6168 break; 6169 case 0x2c: 6170 /* Insn frstor. */ 6171 if (i386_record_floats (gdbarch, &ir, 6172 I386_SAVE_FPU_ENV_REG_STACK)) 6173 return -1; 6174 break; 6175 case 0x0e: 6176 if (ir.dflag) 6177 { 6178 if (record_full_arch_list_add_mem (addr64, 28)) 6179 return -1; 6180 } 6181 else 6182 { 6183 if (record_full_arch_list_add_mem (addr64, 14)) 6184 return -1; 6185 } 6186 break; 6187 case 0x0f: 6188 case 0x2f: 6189 if (record_full_arch_list_add_mem (addr64, 2)) 6190 return -1; 6191 /* Insn fstp, fbstp. */ 6192 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 6193 return -1; 6194 break; 6195 case 0x1f: 6196 case 0x3e: 6197 if (record_full_arch_list_add_mem (addr64, 10)) 6198 return -1; 6199 break; 6200 case 0x2e: 6201 if (ir.dflag) 6202 { 6203 if (record_full_arch_list_add_mem (addr64, 28)) 6204 return -1; 6205 addr64 += 28; 6206 } 6207 else 6208 { 6209 if (record_full_arch_list_add_mem (addr64, 14)) 6210 return -1; 6211 addr64 += 14; 6212 } 6213 if (record_full_arch_list_add_mem (addr64, 80)) 6214 return -1; 6215 /* Insn fsave. */ 6216 if (i386_record_floats (gdbarch, &ir, 6217 I386_SAVE_FPU_ENV_REG_STACK)) 6218 return -1; 6219 break; 6220 case 0x3f: 6221 if (record_full_arch_list_add_mem (addr64, 8)) 6222 return -1; 6223 /* Insn fistp. */ 6224 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 6225 return -1; 6226 break; 6227 default: 6228 ir.addr -= 2; 6229 opcode = opcode << 8 | ir.modrm; 6230 goto no_support; 6231 break; 6232 } 6233 } 6234 /* Opcode is an extension of modR/M byte. */ 6235 else 6236 { 6237 switch (opcode) 6238 { 6239 case 0xd8: 6240 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) 6241 return -1; 6242 break; 6243 case 0xd9: 6244 if (0x0c == (ir.modrm >> 4)) 6245 { 6246 if ((ir.modrm & 0x0f) <= 7) 6247 { 6248 if (i386_record_floats (gdbarch, &ir, 6249 I386_SAVE_FPU_REGS)) 6250 return -1; 6251 } 6252 else 6253 { 6254 if (i386_record_floats (gdbarch, &ir, 6255 I387_ST0_REGNUM (tdep))) 6256 return -1; 6257 /* If only st(0) is changing, then we have already 6258 recorded. */ 6259 if ((ir.modrm & 0x0f) - 0x08) 6260 { 6261 if (i386_record_floats (gdbarch, &ir, 6262 I387_ST0_REGNUM (tdep) + 6263 ((ir.modrm & 0x0f) - 0x08))) 6264 return -1; 6265 } 6266 } 6267 } 6268 else 6269 { 6270 switch (ir.modrm) 6271 { 6272 case 0xe0: 6273 case 0xe1: 6274 case 0xf0: 6275 case 0xf5: 6276 case 0xf8: 6277 case 0xfa: 6278 case 0xfc: 6279 case 0xfe: 6280 case 0xff: 6281 if (i386_record_floats (gdbarch, &ir, 6282 I387_ST0_REGNUM (tdep))) 6283 return -1; 6284 break; 6285 case 0xf1: 6286 case 0xf2: 6287 case 0xf3: 6288 case 0xf4: 6289 case 0xf6: 6290 case 0xf7: 6291 case 0xe8: 6292 case 0xe9: 6293 case 0xea: 6294 case 0xeb: 6295 case 0xec: 6296 case 0xed: 6297 case 0xee: 6298 case 0xf9: 6299 case 0xfb: 6300 if (i386_record_floats (gdbarch, &ir, 6301 I386_SAVE_FPU_REGS)) 6302 return -1; 6303 break; 6304 case 0xfd: 6305 if (i386_record_floats (gdbarch, &ir, 6306 I387_ST0_REGNUM (tdep))) 6307 return -1; 6308 if (i386_record_floats (gdbarch, &ir, 6309 I387_ST0_REGNUM (tdep) + 1)) 6310 return -1; 6311 break; 6312 } 6313 } 6314 break; 6315 case 0xda: 6316 if (0xe9 == ir.modrm) 6317 { 6318 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 6319 return -1; 6320 } 6321 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) 6322 { 6323 if (i386_record_floats (gdbarch, &ir, 6324 I387_ST0_REGNUM (tdep))) 6325 return -1; 6326 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) 6327 { 6328 if (i386_record_floats (gdbarch, &ir, 6329 I387_ST0_REGNUM (tdep) + 6330 (ir.modrm & 0x0f))) 6331 return -1; 6332 } 6333 else if ((ir.modrm & 0x0f) - 0x08) 6334 { 6335 if (i386_record_floats (gdbarch, &ir, 6336 I387_ST0_REGNUM (tdep) + 6337 ((ir.modrm & 0x0f) - 0x08))) 6338 return -1; 6339 } 6340 } 6341 break; 6342 case 0xdb: 6343 if (0xe3 == ir.modrm) 6344 { 6345 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) 6346 return -1; 6347 } 6348 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) 6349 { 6350 if (i386_record_floats (gdbarch, &ir, 6351 I387_ST0_REGNUM (tdep))) 6352 return -1; 6353 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) 6354 { 6355 if (i386_record_floats (gdbarch, &ir, 6356 I387_ST0_REGNUM (tdep) + 6357 (ir.modrm & 0x0f))) 6358 return -1; 6359 } 6360 else if ((ir.modrm & 0x0f) - 0x08) 6361 { 6362 if (i386_record_floats (gdbarch, &ir, 6363 I387_ST0_REGNUM (tdep) + 6364 ((ir.modrm & 0x0f) - 0x08))) 6365 return -1; 6366 } 6367 } 6368 break; 6369 case 0xdc: 6370 if ((0x0c == ir.modrm >> 4) 6371 || (0x0d == ir.modrm >> 4) 6372 || (0x0f == ir.modrm >> 4)) 6373 { 6374 if ((ir.modrm & 0x0f) <= 7) 6375 { 6376 if (i386_record_floats (gdbarch, &ir, 6377 I387_ST0_REGNUM (tdep) + 6378 (ir.modrm & 0x0f))) 6379 return -1; 6380 } 6381 else 6382 { 6383 if (i386_record_floats (gdbarch, &ir, 6384 I387_ST0_REGNUM (tdep) + 6385 ((ir.modrm & 0x0f) - 0x08))) 6386 return -1; 6387 } 6388 } 6389 break; 6390 case 0xdd: 6391 if (0x0c == ir.modrm >> 4) 6392 { 6393 if (i386_record_floats (gdbarch, &ir, 6394 I387_FTAG_REGNUM (tdep))) 6395 return -1; 6396 } 6397 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) 6398 { 6399 if ((ir.modrm & 0x0f) <= 7) 6400 { 6401 if (i386_record_floats (gdbarch, &ir, 6402 I387_ST0_REGNUM (tdep) + 6403 (ir.modrm & 0x0f))) 6404 return -1; 6405 } 6406 else 6407 { 6408 if (i386_record_floats (gdbarch, &ir, 6409 I386_SAVE_FPU_REGS)) 6410 return -1; 6411 } 6412 } 6413 break; 6414 case 0xde: 6415 if ((0x0c == ir.modrm >> 4) 6416 || (0x0e == ir.modrm >> 4) 6417 || (0x0f == ir.modrm >> 4) 6418 || (0xd9 == ir.modrm)) 6419 { 6420 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 6421 return -1; 6422 } 6423 break; 6424 case 0xdf: 6425 if (0xe0 == ir.modrm) 6426 { 6427 if (record_full_arch_list_add_reg (ir.regcache, 6428 I386_EAX_REGNUM)) 6429 return -1; 6430 } 6431 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) 6432 { 6433 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 6434 return -1; 6435 } 6436 break; 6437 } 6438 } 6439 break; 6440 /* string ops */ 6441 case 0xa4: /* movsS */ 6442 case 0xa5: 6443 case 0xaa: /* stosS */ 6444 case 0xab: 6445 case 0x6c: /* insS */ 6446 case 0x6d: 6447 regcache_raw_read_unsigned (ir.regcache, 6448 ir.regmap[X86_RECORD_RECX_REGNUM], 6449 &addr); 6450 if (addr) 6451 { 6452 ULONGEST es, ds; 6453 6454 if ((opcode & 1) == 0) 6455 ir.ot = OT_BYTE; 6456 else 6457 ir.ot = ir.dflag + OT_WORD; 6458 regcache_raw_read_unsigned (ir.regcache, 6459 ir.regmap[X86_RECORD_REDI_REGNUM], 6460 &addr); 6461 6462 regcache_raw_read_unsigned (ir.regcache, 6463 ir.regmap[X86_RECORD_ES_REGNUM], 6464 &es); 6465 regcache_raw_read_unsigned (ir.regcache, 6466 ir.regmap[X86_RECORD_DS_REGNUM], 6467 &ds); 6468 if (ir.aflag && (es != ds)) 6469 { 6470 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ 6471 if (record_full_memory_query) 6472 { 6473 if (yquery (_("\ 6474 Process record ignores the memory change of instruction at address %s\n\ 6475 because it can't get the value of the segment register.\n\ 6476 Do you want to stop the program?"), 6477 paddress (gdbarch, ir.orig_addr))) 6478 return -1; 6479 } 6480 } 6481 else 6482 { 6483 if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) 6484 return -1; 6485 } 6486 6487 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 6488 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 6489 if (opcode == 0xa4 || opcode == 0xa5) 6490 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 6491 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 6492 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6493 } 6494 break; 6495 6496 case 0xa6: /* cmpsS */ 6497 case 0xa7: 6498 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 6499 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 6500 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 6501 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 6502 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6503 break; 6504 6505 case 0xac: /* lodsS */ 6506 case 0xad: 6507 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 6508 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 6509 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 6510 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 6511 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6512 break; 6513 6514 case 0xae: /* scasS */ 6515 case 0xaf: 6516 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 6517 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 6518 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 6519 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6520 break; 6521 6522 case 0x6e: /* outsS */ 6523 case 0x6f: 6524 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 6525 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 6526 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 6527 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6528 break; 6529 6530 case 0xe4: /* port I/O */ 6531 case 0xe5: 6532 case 0xec: 6533 case 0xed: 6534 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6535 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 6536 break; 6537 6538 case 0xe6: 6539 case 0xe7: 6540 case 0xee: 6541 case 0xef: 6542 break; 6543 6544 /* control */ 6545 case 0xc2: /* ret im */ 6546 case 0xc3: /* ret */ 6547 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 6548 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6549 break; 6550 6551 case 0xca: /* lret im */ 6552 case 0xcb: /* lret */ 6553 case 0xcf: /* iret */ 6554 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); 6555 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 6556 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6557 break; 6558 6559 case 0xe8: /* call im */ 6560 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 6561 ir.dflag = 2; 6562 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 6563 return -1; 6564 break; 6565 6566 case 0x9a: /* lcall im */ 6567 if (ir.regmap[X86_RECORD_R8_REGNUM]) 6568 { 6569 ir.addr -= 1; 6570 goto no_support; 6571 } 6572 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); 6573 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 6574 return -1; 6575 break; 6576 6577 case 0xe9: /* jmp im */ 6578 case 0xea: /* ljmp im */ 6579 case 0xeb: /* jmp Jb */ 6580 case 0x70: /* jcc Jb */ 6581 case 0x71: 6582 case 0x72: 6583 case 0x73: 6584 case 0x74: 6585 case 0x75: 6586 case 0x76: 6587 case 0x77: 6588 case 0x78: 6589 case 0x79: 6590 case 0x7a: 6591 case 0x7b: 6592 case 0x7c: 6593 case 0x7d: 6594 case 0x7e: 6595 case 0x7f: 6596 case 0x0f80: /* jcc Jv */ 6597 case 0x0f81: 6598 case 0x0f82: 6599 case 0x0f83: 6600 case 0x0f84: 6601 case 0x0f85: 6602 case 0x0f86: 6603 case 0x0f87: 6604 case 0x0f88: 6605 case 0x0f89: 6606 case 0x0f8a: 6607 case 0x0f8b: 6608 case 0x0f8c: 6609 case 0x0f8d: 6610 case 0x0f8e: 6611 case 0x0f8f: 6612 break; 6613 6614 case 0x0f90: /* setcc Gv */ 6615 case 0x0f91: 6616 case 0x0f92: 6617 case 0x0f93: 6618 case 0x0f94: 6619 case 0x0f95: 6620 case 0x0f96: 6621 case 0x0f97: 6622 case 0x0f98: 6623 case 0x0f99: 6624 case 0x0f9a: 6625 case 0x0f9b: 6626 case 0x0f9c: 6627 case 0x0f9d: 6628 case 0x0f9e: 6629 case 0x0f9f: 6630 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6631 ir.ot = OT_BYTE; 6632 if (i386_record_modrm (&ir)) 6633 return -1; 6634 if (ir.mod == 3) 6635 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) 6636 : (ir.rm & 0x3)); 6637 else 6638 { 6639 if (i386_record_lea_modrm (&ir)) 6640 return -1; 6641 } 6642 break; 6643 6644 case 0x0f40: /* cmov Gv, Ev */ 6645 case 0x0f41: 6646 case 0x0f42: 6647 case 0x0f43: 6648 case 0x0f44: 6649 case 0x0f45: 6650 case 0x0f46: 6651 case 0x0f47: 6652 case 0x0f48: 6653 case 0x0f49: 6654 case 0x0f4a: 6655 case 0x0f4b: 6656 case 0x0f4c: 6657 case 0x0f4d: 6658 case 0x0f4e: 6659 case 0x0f4f: 6660 if (i386_record_modrm (&ir)) 6661 return -1; 6662 ir.reg |= rex_r; 6663 if (ir.dflag == OT_BYTE) 6664 ir.reg &= 0x3; 6665 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 6666 break; 6667 6668 /* flags */ 6669 case 0x9c: /* pushf */ 6670 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6671 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 6672 ir.dflag = 2; 6673 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 6674 return -1; 6675 break; 6676 6677 case 0x9d: /* popf */ 6678 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 6679 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6680 break; 6681 6682 case 0x9e: /* sahf */ 6683 if (ir.regmap[X86_RECORD_R8_REGNUM]) 6684 { 6685 ir.addr -= 1; 6686 goto no_support; 6687 } 6688 /* FALLTHROUGH */ 6689 case 0xf5: /* cmc */ 6690 case 0xf8: /* clc */ 6691 case 0xf9: /* stc */ 6692 case 0xfc: /* cld */ 6693 case 0xfd: /* std */ 6694 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6695 break; 6696 6697 case 0x9f: /* lahf */ 6698 if (ir.regmap[X86_RECORD_R8_REGNUM]) 6699 { 6700 ir.addr -= 1; 6701 goto no_support; 6702 } 6703 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6704 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 6705 break; 6706 6707 /* bit operations */ 6708 case 0x0fba: /* bt/bts/btr/btc Gv, im */ 6709 ir.ot = ir.dflag + OT_WORD; 6710 if (i386_record_modrm (&ir)) 6711 return -1; 6712 if (ir.reg < 4) 6713 { 6714 ir.addr -= 2; 6715 opcode = opcode << 8 | ir.modrm; 6716 goto no_support; 6717 } 6718 if (ir.reg != 4) 6719 { 6720 if (ir.mod == 3) 6721 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 6722 else 6723 { 6724 if (i386_record_lea_modrm (&ir)) 6725 return -1; 6726 } 6727 } 6728 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6729 break; 6730 6731 case 0x0fa3: /* bt Gv, Ev */ 6732 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6733 break; 6734 6735 case 0x0fab: /* bts */ 6736 case 0x0fb3: /* btr */ 6737 case 0x0fbb: /* btc */ 6738 ir.ot = ir.dflag + OT_WORD; 6739 if (i386_record_modrm (&ir)) 6740 return -1; 6741 if (ir.mod == 3) 6742 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 6743 else 6744 { 6745 uint64_t addr64; 6746 if (i386_record_lea_modrm_addr (&ir, &addr64)) 6747 return -1; 6748 regcache_raw_read_unsigned (ir.regcache, 6749 ir.regmap[ir.reg | rex_r], 6750 &addr); 6751 switch (ir.dflag) 6752 { 6753 case 0: 6754 addr64 += ((int16_t) addr >> 4) << 4; 6755 break; 6756 case 1: 6757 addr64 += ((int32_t) addr >> 5) << 5; 6758 break; 6759 case 2: 6760 addr64 += ((int64_t) addr >> 6) << 6; 6761 break; 6762 } 6763 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot)) 6764 return -1; 6765 if (i386_record_lea_modrm (&ir)) 6766 return -1; 6767 } 6768 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6769 break; 6770 6771 case 0x0fbc: /* bsf */ 6772 case 0x0fbd: /* bsr */ 6773 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); 6774 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6775 break; 6776 6777 /* bcd */ 6778 case 0x27: /* daa */ 6779 case 0x2f: /* das */ 6780 case 0x37: /* aaa */ 6781 case 0x3f: /* aas */ 6782 case 0xd4: /* aam */ 6783 case 0xd5: /* aad */ 6784 if (ir.regmap[X86_RECORD_R8_REGNUM]) 6785 { 6786 ir.addr -= 1; 6787 goto no_support; 6788 } 6789 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 6790 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6791 break; 6792 6793 /* misc */ 6794 case 0x90: /* nop */ 6795 if (prefixes & PREFIX_LOCK) 6796 { 6797 ir.addr -= 1; 6798 goto no_support; 6799 } 6800 break; 6801 6802 case 0x9b: /* fwait */ 6803 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) 6804 return -1; 6805 opcode = (uint32_t) opcode8; 6806 ir.addr++; 6807 goto reswitch; 6808 break; 6809 6810 /* XXX */ 6811 case 0xcc: /* int3 */ 6812 printf_unfiltered (_("Process record does not support instruction " 6813 "int3.\n")); 6814 ir.addr -= 1; 6815 goto no_support; 6816 break; 6817 6818 /* XXX */ 6819 case 0xcd: /* int */ 6820 { 6821 int ret; 6822 uint8_t interrupt; 6823 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1)) 6824 return -1; 6825 ir.addr++; 6826 if (interrupt != 0x80 6827 || tdep->i386_intx80_record == NULL) 6828 { 6829 printf_unfiltered (_("Process record does not support " 6830 "instruction int 0x%02x.\n"), 6831 interrupt); 6832 ir.addr -= 2; 6833 goto no_support; 6834 } 6835 ret = tdep->i386_intx80_record (ir.regcache); 6836 if (ret) 6837 return ret; 6838 } 6839 break; 6840 6841 /* XXX */ 6842 case 0xce: /* into */ 6843 printf_unfiltered (_("Process record does not support " 6844 "instruction into.\n")); 6845 ir.addr -= 1; 6846 goto no_support; 6847 break; 6848 6849 case 0xfa: /* cli */ 6850 case 0xfb: /* sti */ 6851 break; 6852 6853 case 0x62: /* bound */ 6854 printf_unfiltered (_("Process record does not support " 6855 "instruction bound.\n")); 6856 ir.addr -= 1; 6857 goto no_support; 6858 break; 6859 6860 case 0x0fc8: /* bswap reg */ 6861 case 0x0fc9: 6862 case 0x0fca: 6863 case 0x0fcb: 6864 case 0x0fcc: 6865 case 0x0fcd: 6866 case 0x0fce: 6867 case 0x0fcf: 6868 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); 6869 break; 6870 6871 case 0xd6: /* salc */ 6872 if (ir.regmap[X86_RECORD_R8_REGNUM]) 6873 { 6874 ir.addr -= 1; 6875 goto no_support; 6876 } 6877 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 6878 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6879 break; 6880 6881 case 0xe0: /* loopnz */ 6882 case 0xe1: /* loopz */ 6883 case 0xe2: /* loop */ 6884 case 0xe3: /* jecxz */ 6885 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 6886 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6887 break; 6888 6889 case 0x0f30: /* wrmsr */ 6890 printf_unfiltered (_("Process record does not support " 6891 "instruction wrmsr.\n")); 6892 ir.addr -= 2; 6893 goto no_support; 6894 break; 6895 6896 case 0x0f32: /* rdmsr */ 6897 printf_unfiltered (_("Process record does not support " 6898 "instruction rdmsr.\n")); 6899 ir.addr -= 2; 6900 goto no_support; 6901 break; 6902 6903 case 0x0f31: /* rdtsc */ 6904 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 6905 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 6906 break; 6907 6908 case 0x0f34: /* sysenter */ 6909 { 6910 int ret; 6911 if (ir.regmap[X86_RECORD_R8_REGNUM]) 6912 { 6913 ir.addr -= 2; 6914 goto no_support; 6915 } 6916 if (tdep->i386_sysenter_record == NULL) 6917 { 6918 printf_unfiltered (_("Process record does not support " 6919 "instruction sysenter.\n")); 6920 ir.addr -= 2; 6921 goto no_support; 6922 } 6923 ret = tdep->i386_sysenter_record (ir.regcache); 6924 if (ret) 6925 return ret; 6926 } 6927 break; 6928 6929 case 0x0f35: /* sysexit */ 6930 printf_unfiltered (_("Process record does not support " 6931 "instruction sysexit.\n")); 6932 ir.addr -= 2; 6933 goto no_support; 6934 break; 6935 6936 case 0x0f05: /* syscall */ 6937 { 6938 int ret; 6939 if (tdep->i386_syscall_record == NULL) 6940 { 6941 printf_unfiltered (_("Process record does not support " 6942 "instruction syscall.\n")); 6943 ir.addr -= 2; 6944 goto no_support; 6945 } 6946 ret = tdep->i386_syscall_record (ir.regcache); 6947 if (ret) 6948 return ret; 6949 } 6950 break; 6951 6952 case 0x0f07: /* sysret */ 6953 printf_unfiltered (_("Process record does not support " 6954 "instruction sysret.\n")); 6955 ir.addr -= 2; 6956 goto no_support; 6957 break; 6958 6959 case 0x0fa2: /* cpuid */ 6960 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 6961 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 6962 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 6963 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); 6964 break; 6965 6966 case 0xf4: /* hlt */ 6967 printf_unfiltered (_("Process record does not support " 6968 "instruction hlt.\n")); 6969 ir.addr -= 1; 6970 goto no_support; 6971 break; 6972 6973 case 0x0f00: 6974 if (i386_record_modrm (&ir)) 6975 return -1; 6976 switch (ir.reg) 6977 { 6978 case 0: /* sldt */ 6979 case 1: /* str */ 6980 if (ir.mod == 3) 6981 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 6982 else 6983 { 6984 ir.ot = OT_WORD; 6985 if (i386_record_lea_modrm (&ir)) 6986 return -1; 6987 } 6988 break; 6989 case 2: /* lldt */ 6990 case 3: /* ltr */ 6991 break; 6992 case 4: /* verr */ 6993 case 5: /* verw */ 6994 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6995 break; 6996 default: 6997 ir.addr -= 3; 6998 opcode = opcode << 8 | ir.modrm; 6999 goto no_support; 7000 break; 7001 } 7002 break; 7003 7004 case 0x0f01: 7005 if (i386_record_modrm (&ir)) 7006 return -1; 7007 switch (ir.reg) 7008 { 7009 case 0: /* sgdt */ 7010 { 7011 uint64_t addr64; 7012 7013 if (ir.mod == 3) 7014 { 7015 ir.addr -= 3; 7016 opcode = opcode << 8 | ir.modrm; 7017 goto no_support; 7018 } 7019 if (ir.override >= 0) 7020 { 7021 if (record_full_memory_query) 7022 { 7023 if (yquery (_("\ 7024 Process record ignores the memory change of instruction at address %s\n\ 7025 because it can't get the value of the segment register.\n\ 7026 Do you want to stop the program?"), 7027 paddress (gdbarch, ir.orig_addr))) 7028 return -1; 7029 } 7030 } 7031 else 7032 { 7033 if (i386_record_lea_modrm_addr (&ir, &addr64)) 7034 return -1; 7035 if (record_full_arch_list_add_mem (addr64, 2)) 7036 return -1; 7037 addr64 += 2; 7038 if (ir.regmap[X86_RECORD_R8_REGNUM]) 7039 { 7040 if (record_full_arch_list_add_mem (addr64, 8)) 7041 return -1; 7042 } 7043 else 7044 { 7045 if (record_full_arch_list_add_mem (addr64, 4)) 7046 return -1; 7047 } 7048 } 7049 } 7050 break; 7051 case 1: 7052 if (ir.mod == 3) 7053 { 7054 switch (ir.rm) 7055 { 7056 case 0: /* monitor */ 7057 break; 7058 case 1: /* mwait */ 7059 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7060 break; 7061 default: 7062 ir.addr -= 3; 7063 opcode = opcode << 8 | ir.modrm; 7064 goto no_support; 7065 break; 7066 } 7067 } 7068 else 7069 { 7070 /* sidt */ 7071 if (ir.override >= 0) 7072 { 7073 if (record_full_memory_query) 7074 { 7075 if (yquery (_("\ 7076 Process record ignores the memory change of instruction at address %s\n\ 7077 because it can't get the value of the segment register.\n\ 7078 Do you want to stop the program?"), 7079 paddress (gdbarch, ir.orig_addr))) 7080 return -1; 7081 } 7082 } 7083 else 7084 { 7085 uint64_t addr64; 7086 7087 if (i386_record_lea_modrm_addr (&ir, &addr64)) 7088 return -1; 7089 if (record_full_arch_list_add_mem (addr64, 2)) 7090 return -1; 7091 addr64 += 2; 7092 if (ir.regmap[X86_RECORD_R8_REGNUM]) 7093 { 7094 if (record_full_arch_list_add_mem (addr64, 8)) 7095 return -1; 7096 } 7097 else 7098 { 7099 if (record_full_arch_list_add_mem (addr64, 4)) 7100 return -1; 7101 } 7102 } 7103 } 7104 break; 7105 case 2: /* lgdt */ 7106 if (ir.mod == 3) 7107 { 7108 /* xgetbv */ 7109 if (ir.rm == 0) 7110 { 7111 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 7112 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 7113 break; 7114 } 7115 /* xsetbv */ 7116 else if (ir.rm == 1) 7117 break; 7118 } 7119 case 3: /* lidt */ 7120 if (ir.mod == 3) 7121 { 7122 ir.addr -= 3; 7123 opcode = opcode << 8 | ir.modrm; 7124 goto no_support; 7125 } 7126 break; 7127 case 4: /* smsw */ 7128 if (ir.mod == 3) 7129 { 7130 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) 7131 return -1; 7132 } 7133 else 7134 { 7135 ir.ot = OT_WORD; 7136 if (i386_record_lea_modrm (&ir)) 7137 return -1; 7138 } 7139 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7140 break; 7141 case 6: /* lmsw */ 7142 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7143 break; 7144 case 7: /* invlpg */ 7145 if (ir.mod == 3) 7146 { 7147 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) 7148 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); 7149 else 7150 { 7151 ir.addr -= 3; 7152 opcode = opcode << 8 | ir.modrm; 7153 goto no_support; 7154 } 7155 } 7156 else 7157 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7158 break; 7159 default: 7160 ir.addr -= 3; 7161 opcode = opcode << 8 | ir.modrm; 7162 goto no_support; 7163 break; 7164 } 7165 break; 7166 7167 case 0x0f08: /* invd */ 7168 case 0x0f09: /* wbinvd */ 7169 break; 7170 7171 case 0x63: /* arpl */ 7172 if (i386_record_modrm (&ir)) 7173 return -1; 7174 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) 7175 { 7176 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] 7177 ? (ir.reg | rex_r) : ir.rm); 7178 } 7179 else 7180 { 7181 ir.ot = ir.dflag ? OT_LONG : OT_WORD; 7182 if (i386_record_lea_modrm (&ir)) 7183 return -1; 7184 } 7185 if (!ir.regmap[X86_RECORD_R8_REGNUM]) 7186 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7187 break; 7188 7189 case 0x0f02: /* lar */ 7190 case 0x0f03: /* lsl */ 7191 if (i386_record_modrm (&ir)) 7192 return -1; 7193 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); 7194 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7195 break; 7196 7197 case 0x0f18: 7198 if (i386_record_modrm (&ir)) 7199 return -1; 7200 if (ir.mod == 3 && ir.reg == 3) 7201 { 7202 ir.addr -= 3; 7203 opcode = opcode << 8 | ir.modrm; 7204 goto no_support; 7205 } 7206 break; 7207 7208 case 0x0f19: 7209 case 0x0f1a: 7210 case 0x0f1b: 7211 case 0x0f1c: 7212 case 0x0f1d: 7213 case 0x0f1e: 7214 case 0x0f1f: 7215 /* nop (multi byte) */ 7216 break; 7217 7218 case 0x0f20: /* mov reg, crN */ 7219 case 0x0f22: /* mov crN, reg */ 7220 if (i386_record_modrm (&ir)) 7221 return -1; 7222 if ((ir.modrm & 0xc0) != 0xc0) 7223 { 7224 ir.addr -= 3; 7225 opcode = opcode << 8 | ir.modrm; 7226 goto no_support; 7227 } 7228 switch (ir.reg) 7229 { 7230 case 0: 7231 case 2: 7232 case 3: 7233 case 4: 7234 case 8: 7235 if (opcode & 2) 7236 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7237 else 7238 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 7239 break; 7240 default: 7241 ir.addr -= 3; 7242 opcode = opcode << 8 | ir.modrm; 7243 goto no_support; 7244 break; 7245 } 7246 break; 7247 7248 case 0x0f21: /* mov reg, drN */ 7249 case 0x0f23: /* mov drN, reg */ 7250 if (i386_record_modrm (&ir)) 7251 return -1; 7252 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 7253 || ir.reg == 5 || ir.reg >= 8) 7254 { 7255 ir.addr -= 3; 7256 opcode = opcode << 8 | ir.modrm; 7257 goto no_support; 7258 } 7259 if (opcode & 2) 7260 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7261 else 7262 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 7263 break; 7264 7265 case 0x0f06: /* clts */ 7266 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7267 break; 7268 7269 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ 7270 7271 case 0x0f0d: /* 3DNow! prefetch */ 7272 break; 7273 7274 case 0x0f0e: /* 3DNow! femms */ 7275 case 0x0f77: /* emms */ 7276 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) 7277 goto no_support; 7278 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); 7279 break; 7280 7281 case 0x0f0f: /* 3DNow! data */ 7282 if (i386_record_modrm (&ir)) 7283 return -1; 7284 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) 7285 return -1; 7286 ir.addr++; 7287 switch (opcode8) 7288 { 7289 case 0x0c: /* 3DNow! pi2fw */ 7290 case 0x0d: /* 3DNow! pi2fd */ 7291 case 0x1c: /* 3DNow! pf2iw */ 7292 case 0x1d: /* 3DNow! pf2id */ 7293 case 0x8a: /* 3DNow! pfnacc */ 7294 case 0x8e: /* 3DNow! pfpnacc */ 7295 case 0x90: /* 3DNow! pfcmpge */ 7296 case 0x94: /* 3DNow! pfmin */ 7297 case 0x96: /* 3DNow! pfrcp */ 7298 case 0x97: /* 3DNow! pfrsqrt */ 7299 case 0x9a: /* 3DNow! pfsub */ 7300 case 0x9e: /* 3DNow! pfadd */ 7301 case 0xa0: /* 3DNow! pfcmpgt */ 7302 case 0xa4: /* 3DNow! pfmax */ 7303 case 0xa6: /* 3DNow! pfrcpit1 */ 7304 case 0xa7: /* 3DNow! pfrsqit1 */ 7305 case 0xaa: /* 3DNow! pfsubr */ 7306 case 0xae: /* 3DNow! pfacc */ 7307 case 0xb0: /* 3DNow! pfcmpeq */ 7308 case 0xb4: /* 3DNow! pfmul */ 7309 case 0xb6: /* 3DNow! pfrcpit2 */ 7310 case 0xb7: /* 3DNow! pmulhrw */ 7311 case 0xbb: /* 3DNow! pswapd */ 7312 case 0xbf: /* 3DNow! pavgusb */ 7313 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) 7314 goto no_support_3dnow_data; 7315 record_full_arch_list_add_reg (ir.regcache, ir.reg); 7316 break; 7317 7318 default: 7319 no_support_3dnow_data: 7320 opcode = (opcode << 8) | opcode8; 7321 goto no_support; 7322 break; 7323 } 7324 break; 7325 7326 case 0x0faa: /* rsm */ 7327 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7328 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 7329 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 7330 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 7331 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); 7332 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 7333 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); 7334 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 7335 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 7336 break; 7337 7338 case 0x0fae: 7339 if (i386_record_modrm (&ir)) 7340 return -1; 7341 switch(ir.reg) 7342 { 7343 case 0: /* fxsave */ 7344 { 7345 uint64_t tmpu64; 7346 7347 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7348 if (i386_record_lea_modrm_addr (&ir, &tmpu64)) 7349 return -1; 7350 if (record_full_arch_list_add_mem (tmpu64, 512)) 7351 return -1; 7352 } 7353 break; 7354 7355 case 1: /* fxrstor */ 7356 { 7357 int i; 7358 7359 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7360 7361 for (i = I387_MM0_REGNUM (tdep); 7362 i386_mmx_regnum_p (gdbarch, i); i++) 7363 record_full_arch_list_add_reg (ir.regcache, i); 7364 7365 for (i = I387_XMM0_REGNUM (tdep); 7366 i386_xmm_regnum_p (gdbarch, i); i++) 7367 record_full_arch_list_add_reg (ir.regcache, i); 7368 7369 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) 7370 record_full_arch_list_add_reg (ir.regcache, 7371 I387_MXCSR_REGNUM(tdep)); 7372 7373 for (i = I387_ST0_REGNUM (tdep); 7374 i386_fp_regnum_p (gdbarch, i); i++) 7375 record_full_arch_list_add_reg (ir.regcache, i); 7376 7377 for (i = I387_FCTRL_REGNUM (tdep); 7378 i386_fpc_regnum_p (gdbarch, i); i++) 7379 record_full_arch_list_add_reg (ir.regcache, i); 7380 } 7381 break; 7382 7383 case 2: /* ldmxcsr */ 7384 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) 7385 goto no_support; 7386 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); 7387 break; 7388 7389 case 3: /* stmxcsr */ 7390 ir.ot = OT_LONG; 7391 if (i386_record_lea_modrm (&ir)) 7392 return -1; 7393 break; 7394 7395 case 5: /* lfence */ 7396 case 6: /* mfence */ 7397 case 7: /* sfence clflush */ 7398 break; 7399 7400 default: 7401 opcode = (opcode << 8) | ir.modrm; 7402 goto no_support; 7403 break; 7404 } 7405 break; 7406 7407 case 0x0fc3: /* movnti */ 7408 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; 7409 if (i386_record_modrm (&ir)) 7410 return -1; 7411 if (ir.mod == 3) 7412 goto no_support; 7413 ir.reg |= rex_r; 7414 if (i386_record_lea_modrm (&ir)) 7415 return -1; 7416 break; 7417 7418 /* Add prefix to opcode. */ 7419 case 0x0f10: 7420 case 0x0f11: 7421 case 0x0f12: 7422 case 0x0f13: 7423 case 0x0f14: 7424 case 0x0f15: 7425 case 0x0f16: 7426 case 0x0f17: 7427 case 0x0f28: 7428 case 0x0f29: 7429 case 0x0f2a: 7430 case 0x0f2b: 7431 case 0x0f2c: 7432 case 0x0f2d: 7433 case 0x0f2e: 7434 case 0x0f2f: 7435 case 0x0f38: 7436 case 0x0f39: 7437 case 0x0f3a: 7438 case 0x0f50: 7439 case 0x0f51: 7440 case 0x0f52: 7441 case 0x0f53: 7442 case 0x0f54: 7443 case 0x0f55: 7444 case 0x0f56: 7445 case 0x0f57: 7446 case 0x0f58: 7447 case 0x0f59: 7448 case 0x0f5a: 7449 case 0x0f5b: 7450 case 0x0f5c: 7451 case 0x0f5d: 7452 case 0x0f5e: 7453 case 0x0f5f: 7454 case 0x0f60: 7455 case 0x0f61: 7456 case 0x0f62: 7457 case 0x0f63: 7458 case 0x0f64: 7459 case 0x0f65: 7460 case 0x0f66: 7461 case 0x0f67: 7462 case 0x0f68: 7463 case 0x0f69: 7464 case 0x0f6a: 7465 case 0x0f6b: 7466 case 0x0f6c: 7467 case 0x0f6d: 7468 case 0x0f6e: 7469 case 0x0f6f: 7470 case 0x0f70: 7471 case 0x0f71: 7472 case 0x0f72: 7473 case 0x0f73: 7474 case 0x0f74: 7475 case 0x0f75: 7476 case 0x0f76: 7477 case 0x0f7c: 7478 case 0x0f7d: 7479 case 0x0f7e: 7480 case 0x0f7f: 7481 case 0x0fb8: 7482 case 0x0fc2: 7483 case 0x0fc4: 7484 case 0x0fc5: 7485 case 0x0fc6: 7486 case 0x0fd0: 7487 case 0x0fd1: 7488 case 0x0fd2: 7489 case 0x0fd3: 7490 case 0x0fd4: 7491 case 0x0fd5: 7492 case 0x0fd6: 7493 case 0x0fd7: 7494 case 0x0fd8: 7495 case 0x0fd9: 7496 case 0x0fda: 7497 case 0x0fdb: 7498 case 0x0fdc: 7499 case 0x0fdd: 7500 case 0x0fde: 7501 case 0x0fdf: 7502 case 0x0fe0: 7503 case 0x0fe1: 7504 case 0x0fe2: 7505 case 0x0fe3: 7506 case 0x0fe4: 7507 case 0x0fe5: 7508 case 0x0fe6: 7509 case 0x0fe7: 7510 case 0x0fe8: 7511 case 0x0fe9: 7512 case 0x0fea: 7513 case 0x0feb: 7514 case 0x0fec: 7515 case 0x0fed: 7516 case 0x0fee: 7517 case 0x0fef: 7518 case 0x0ff0: 7519 case 0x0ff1: 7520 case 0x0ff2: 7521 case 0x0ff3: 7522 case 0x0ff4: 7523 case 0x0ff5: 7524 case 0x0ff6: 7525 case 0x0ff7: 7526 case 0x0ff8: 7527 case 0x0ff9: 7528 case 0x0ffa: 7529 case 0x0ffb: 7530 case 0x0ffc: 7531 case 0x0ffd: 7532 case 0x0ffe: 7533 /* Mask out PREFIX_ADDR. */ 7534 switch ((prefixes & ~PREFIX_ADDR)) 7535 { 7536 case PREFIX_REPNZ: 7537 opcode |= 0xf20000; 7538 break; 7539 case PREFIX_DATA: 7540 opcode |= 0x660000; 7541 break; 7542 case PREFIX_REPZ: 7543 opcode |= 0xf30000; 7544 break; 7545 } 7546 reswitch_prefix_add: 7547 switch (opcode) 7548 { 7549 case 0x0f38: 7550 case 0x660f38: 7551 case 0xf20f38: 7552 case 0x0f3a: 7553 case 0x660f3a: 7554 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) 7555 return -1; 7556 ir.addr++; 7557 opcode = (uint32_t) opcode8 | opcode << 8; 7558 goto reswitch_prefix_add; 7559 break; 7560 7561 case 0x0f10: /* movups */ 7562 case 0x660f10: /* movupd */ 7563 case 0xf30f10: /* movss */ 7564 case 0xf20f10: /* movsd */ 7565 case 0x0f12: /* movlps */ 7566 case 0x660f12: /* movlpd */ 7567 case 0xf30f12: /* movsldup */ 7568 case 0xf20f12: /* movddup */ 7569 case 0x0f14: /* unpcklps */ 7570 case 0x660f14: /* unpcklpd */ 7571 case 0x0f15: /* unpckhps */ 7572 case 0x660f15: /* unpckhpd */ 7573 case 0x0f16: /* movhps */ 7574 case 0x660f16: /* movhpd */ 7575 case 0xf30f16: /* movshdup */ 7576 case 0x0f28: /* movaps */ 7577 case 0x660f28: /* movapd */ 7578 case 0x0f2a: /* cvtpi2ps */ 7579 case 0x660f2a: /* cvtpi2pd */ 7580 case 0xf30f2a: /* cvtsi2ss */ 7581 case 0xf20f2a: /* cvtsi2sd */ 7582 case 0x0f2c: /* cvttps2pi */ 7583 case 0x660f2c: /* cvttpd2pi */ 7584 case 0x0f2d: /* cvtps2pi */ 7585 case 0x660f2d: /* cvtpd2pi */ 7586 case 0x660f3800: /* pshufb */ 7587 case 0x660f3801: /* phaddw */ 7588 case 0x660f3802: /* phaddd */ 7589 case 0x660f3803: /* phaddsw */ 7590 case 0x660f3804: /* pmaddubsw */ 7591 case 0x660f3805: /* phsubw */ 7592 case 0x660f3806: /* phsubd */ 7593 case 0x660f3807: /* phsubsw */ 7594 case 0x660f3808: /* psignb */ 7595 case 0x660f3809: /* psignw */ 7596 case 0x660f380a: /* psignd */ 7597 case 0x660f380b: /* pmulhrsw */ 7598 case 0x660f3810: /* pblendvb */ 7599 case 0x660f3814: /* blendvps */ 7600 case 0x660f3815: /* blendvpd */ 7601 case 0x660f381c: /* pabsb */ 7602 case 0x660f381d: /* pabsw */ 7603 case 0x660f381e: /* pabsd */ 7604 case 0x660f3820: /* pmovsxbw */ 7605 case 0x660f3821: /* pmovsxbd */ 7606 case 0x660f3822: /* pmovsxbq */ 7607 case 0x660f3823: /* pmovsxwd */ 7608 case 0x660f3824: /* pmovsxwq */ 7609 case 0x660f3825: /* pmovsxdq */ 7610 case 0x660f3828: /* pmuldq */ 7611 case 0x660f3829: /* pcmpeqq */ 7612 case 0x660f382a: /* movntdqa */ 7613 case 0x660f3a08: /* roundps */ 7614 case 0x660f3a09: /* roundpd */ 7615 case 0x660f3a0a: /* roundss */ 7616 case 0x660f3a0b: /* roundsd */ 7617 case 0x660f3a0c: /* blendps */ 7618 case 0x660f3a0d: /* blendpd */ 7619 case 0x660f3a0e: /* pblendw */ 7620 case 0x660f3a0f: /* palignr */ 7621 case 0x660f3a20: /* pinsrb */ 7622 case 0x660f3a21: /* insertps */ 7623 case 0x660f3a22: /* pinsrd pinsrq */ 7624 case 0x660f3a40: /* dpps */ 7625 case 0x660f3a41: /* dppd */ 7626 case 0x660f3a42: /* mpsadbw */ 7627 case 0x660f3a60: /* pcmpestrm */ 7628 case 0x660f3a61: /* pcmpestri */ 7629 case 0x660f3a62: /* pcmpistrm */ 7630 case 0x660f3a63: /* pcmpistri */ 7631 case 0x0f51: /* sqrtps */ 7632 case 0x660f51: /* sqrtpd */ 7633 case 0xf20f51: /* sqrtsd */ 7634 case 0xf30f51: /* sqrtss */ 7635 case 0x0f52: /* rsqrtps */ 7636 case 0xf30f52: /* rsqrtss */ 7637 case 0x0f53: /* rcpps */ 7638 case 0xf30f53: /* rcpss */ 7639 case 0x0f54: /* andps */ 7640 case 0x660f54: /* andpd */ 7641 case 0x0f55: /* andnps */ 7642 case 0x660f55: /* andnpd */ 7643 case 0x0f56: /* orps */ 7644 case 0x660f56: /* orpd */ 7645 case 0x0f57: /* xorps */ 7646 case 0x660f57: /* xorpd */ 7647 case 0x0f58: /* addps */ 7648 case 0x660f58: /* addpd */ 7649 case 0xf20f58: /* addsd */ 7650 case 0xf30f58: /* addss */ 7651 case 0x0f59: /* mulps */ 7652 case 0x660f59: /* mulpd */ 7653 case 0xf20f59: /* mulsd */ 7654 case 0xf30f59: /* mulss */ 7655 case 0x0f5a: /* cvtps2pd */ 7656 case 0x660f5a: /* cvtpd2ps */ 7657 case 0xf20f5a: /* cvtsd2ss */ 7658 case 0xf30f5a: /* cvtss2sd */ 7659 case 0x0f5b: /* cvtdq2ps */ 7660 case 0x660f5b: /* cvtps2dq */ 7661 case 0xf30f5b: /* cvttps2dq */ 7662 case 0x0f5c: /* subps */ 7663 case 0x660f5c: /* subpd */ 7664 case 0xf20f5c: /* subsd */ 7665 case 0xf30f5c: /* subss */ 7666 case 0x0f5d: /* minps */ 7667 case 0x660f5d: /* minpd */ 7668 case 0xf20f5d: /* minsd */ 7669 case 0xf30f5d: /* minss */ 7670 case 0x0f5e: /* divps */ 7671 case 0x660f5e: /* divpd */ 7672 case 0xf20f5e: /* divsd */ 7673 case 0xf30f5e: /* divss */ 7674 case 0x0f5f: /* maxps */ 7675 case 0x660f5f: /* maxpd */ 7676 case 0xf20f5f: /* maxsd */ 7677 case 0xf30f5f: /* maxss */ 7678 case 0x660f60: /* punpcklbw */ 7679 case 0x660f61: /* punpcklwd */ 7680 case 0x660f62: /* punpckldq */ 7681 case 0x660f63: /* packsswb */ 7682 case 0x660f64: /* pcmpgtb */ 7683 case 0x660f65: /* pcmpgtw */ 7684 case 0x660f66: /* pcmpgtd */ 7685 case 0x660f67: /* packuswb */ 7686 case 0x660f68: /* punpckhbw */ 7687 case 0x660f69: /* punpckhwd */ 7688 case 0x660f6a: /* punpckhdq */ 7689 case 0x660f6b: /* packssdw */ 7690 case 0x660f6c: /* punpcklqdq */ 7691 case 0x660f6d: /* punpckhqdq */ 7692 case 0x660f6e: /* movd */ 7693 case 0x660f6f: /* movdqa */ 7694 case 0xf30f6f: /* movdqu */ 7695 case 0x660f70: /* pshufd */ 7696 case 0xf20f70: /* pshuflw */ 7697 case 0xf30f70: /* pshufhw */ 7698 case 0x660f74: /* pcmpeqb */ 7699 case 0x660f75: /* pcmpeqw */ 7700 case 0x660f76: /* pcmpeqd */ 7701 case 0x660f7c: /* haddpd */ 7702 case 0xf20f7c: /* haddps */ 7703 case 0x660f7d: /* hsubpd */ 7704 case 0xf20f7d: /* hsubps */ 7705 case 0xf30f7e: /* movq */ 7706 case 0x0fc2: /* cmpps */ 7707 case 0x660fc2: /* cmppd */ 7708 case 0xf20fc2: /* cmpsd */ 7709 case 0xf30fc2: /* cmpss */ 7710 case 0x660fc4: /* pinsrw */ 7711 case 0x0fc6: /* shufps */ 7712 case 0x660fc6: /* shufpd */ 7713 case 0x660fd0: /* addsubpd */ 7714 case 0xf20fd0: /* addsubps */ 7715 case 0x660fd1: /* psrlw */ 7716 case 0x660fd2: /* psrld */ 7717 case 0x660fd3: /* psrlq */ 7718 case 0x660fd4: /* paddq */ 7719 case 0x660fd5: /* pmullw */ 7720 case 0xf30fd6: /* movq2dq */ 7721 case 0x660fd8: /* psubusb */ 7722 case 0x660fd9: /* psubusw */ 7723 case 0x660fda: /* pminub */ 7724 case 0x660fdb: /* pand */ 7725 case 0x660fdc: /* paddusb */ 7726 case 0x660fdd: /* paddusw */ 7727 case 0x660fde: /* pmaxub */ 7728 case 0x660fdf: /* pandn */ 7729 case 0x660fe0: /* pavgb */ 7730 case 0x660fe1: /* psraw */ 7731 case 0x660fe2: /* psrad */ 7732 case 0x660fe3: /* pavgw */ 7733 case 0x660fe4: /* pmulhuw */ 7734 case 0x660fe5: /* pmulhw */ 7735 case 0x660fe6: /* cvttpd2dq */ 7736 case 0xf20fe6: /* cvtpd2dq */ 7737 case 0xf30fe6: /* cvtdq2pd */ 7738 case 0x660fe8: /* psubsb */ 7739 case 0x660fe9: /* psubsw */ 7740 case 0x660fea: /* pminsw */ 7741 case 0x660feb: /* por */ 7742 case 0x660fec: /* paddsb */ 7743 case 0x660fed: /* paddsw */ 7744 case 0x660fee: /* pmaxsw */ 7745 case 0x660fef: /* pxor */ 7746 case 0xf20ff0: /* lddqu */ 7747 case 0x660ff1: /* psllw */ 7748 case 0x660ff2: /* pslld */ 7749 case 0x660ff3: /* psllq */ 7750 case 0x660ff4: /* pmuludq */ 7751 case 0x660ff5: /* pmaddwd */ 7752 case 0x660ff6: /* psadbw */ 7753 case 0x660ff8: /* psubb */ 7754 case 0x660ff9: /* psubw */ 7755 case 0x660ffa: /* psubd */ 7756 case 0x660ffb: /* psubq */ 7757 case 0x660ffc: /* paddb */ 7758 case 0x660ffd: /* paddw */ 7759 case 0x660ffe: /* paddd */ 7760 if (i386_record_modrm (&ir)) 7761 return -1; 7762 ir.reg |= rex_r; 7763 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) 7764 goto no_support; 7765 record_full_arch_list_add_reg (ir.regcache, 7766 I387_XMM0_REGNUM (tdep) + ir.reg); 7767 if ((opcode & 0xfffffffc) == 0x660f3a60) 7768 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7769 break; 7770 7771 case 0x0f11: /* movups */ 7772 case 0x660f11: /* movupd */ 7773 case 0xf30f11: /* movss */ 7774 case 0xf20f11: /* movsd */ 7775 case 0x0f13: /* movlps */ 7776 case 0x660f13: /* movlpd */ 7777 case 0x0f17: /* movhps */ 7778 case 0x660f17: /* movhpd */ 7779 case 0x0f29: /* movaps */ 7780 case 0x660f29: /* movapd */ 7781 case 0x660f3a14: /* pextrb */ 7782 case 0x660f3a15: /* pextrw */ 7783 case 0x660f3a16: /* pextrd pextrq */ 7784 case 0x660f3a17: /* extractps */ 7785 case 0x660f7f: /* movdqa */ 7786 case 0xf30f7f: /* movdqu */ 7787 if (i386_record_modrm (&ir)) 7788 return -1; 7789 if (ir.mod == 3) 7790 { 7791 if (opcode == 0x0f13 || opcode == 0x660f13 7792 || opcode == 0x0f17 || opcode == 0x660f17) 7793 goto no_support; 7794 ir.rm |= ir.rex_b; 7795 if (!i386_xmm_regnum_p (gdbarch, 7796 I387_XMM0_REGNUM (tdep) + ir.rm)) 7797 goto no_support; 7798 record_full_arch_list_add_reg (ir.regcache, 7799 I387_XMM0_REGNUM (tdep) + ir.rm); 7800 } 7801 else 7802 { 7803 switch (opcode) 7804 { 7805 case 0x660f3a14: 7806 ir.ot = OT_BYTE; 7807 break; 7808 case 0x660f3a15: 7809 ir.ot = OT_WORD; 7810 break; 7811 case 0x660f3a16: 7812 ir.ot = OT_LONG; 7813 break; 7814 case 0x660f3a17: 7815 ir.ot = OT_QUAD; 7816 break; 7817 default: 7818 ir.ot = OT_DQUAD; 7819 break; 7820 } 7821 if (i386_record_lea_modrm (&ir)) 7822 return -1; 7823 } 7824 break; 7825 7826 case 0x0f2b: /* movntps */ 7827 case 0x660f2b: /* movntpd */ 7828 case 0x0fe7: /* movntq */ 7829 case 0x660fe7: /* movntdq */ 7830 if (ir.mod == 3) 7831 goto no_support; 7832 if (opcode == 0x0fe7) 7833 ir.ot = OT_QUAD; 7834 else 7835 ir.ot = OT_DQUAD; 7836 if (i386_record_lea_modrm (&ir)) 7837 return -1; 7838 break; 7839 7840 case 0xf30f2c: /* cvttss2si */ 7841 case 0xf20f2c: /* cvttsd2si */ 7842 case 0xf30f2d: /* cvtss2si */ 7843 case 0xf20f2d: /* cvtsd2si */ 7844 case 0xf20f38f0: /* crc32 */ 7845 case 0xf20f38f1: /* crc32 */ 7846 case 0x0f50: /* movmskps */ 7847 case 0x660f50: /* movmskpd */ 7848 case 0x0fc5: /* pextrw */ 7849 case 0x660fc5: /* pextrw */ 7850 case 0x0fd7: /* pmovmskb */ 7851 case 0x660fd7: /* pmovmskb */ 7852 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); 7853 break; 7854 7855 case 0x0f3800: /* pshufb */ 7856 case 0x0f3801: /* phaddw */ 7857 case 0x0f3802: /* phaddd */ 7858 case 0x0f3803: /* phaddsw */ 7859 case 0x0f3804: /* pmaddubsw */ 7860 case 0x0f3805: /* phsubw */ 7861 case 0x0f3806: /* phsubd */ 7862 case 0x0f3807: /* phsubsw */ 7863 case 0x0f3808: /* psignb */ 7864 case 0x0f3809: /* psignw */ 7865 case 0x0f380a: /* psignd */ 7866 case 0x0f380b: /* pmulhrsw */ 7867 case 0x0f381c: /* pabsb */ 7868 case 0x0f381d: /* pabsw */ 7869 case 0x0f381e: /* pabsd */ 7870 case 0x0f382b: /* packusdw */ 7871 case 0x0f3830: /* pmovzxbw */ 7872 case 0x0f3831: /* pmovzxbd */ 7873 case 0x0f3832: /* pmovzxbq */ 7874 case 0x0f3833: /* pmovzxwd */ 7875 case 0x0f3834: /* pmovzxwq */ 7876 case 0x0f3835: /* pmovzxdq */ 7877 case 0x0f3837: /* pcmpgtq */ 7878 case 0x0f3838: /* pminsb */ 7879 case 0x0f3839: /* pminsd */ 7880 case 0x0f383a: /* pminuw */ 7881 case 0x0f383b: /* pminud */ 7882 case 0x0f383c: /* pmaxsb */ 7883 case 0x0f383d: /* pmaxsd */ 7884 case 0x0f383e: /* pmaxuw */ 7885 case 0x0f383f: /* pmaxud */ 7886 case 0x0f3840: /* pmulld */ 7887 case 0x0f3841: /* phminposuw */ 7888 case 0x0f3a0f: /* palignr */ 7889 case 0x0f60: /* punpcklbw */ 7890 case 0x0f61: /* punpcklwd */ 7891 case 0x0f62: /* punpckldq */ 7892 case 0x0f63: /* packsswb */ 7893 case 0x0f64: /* pcmpgtb */ 7894 case 0x0f65: /* pcmpgtw */ 7895 case 0x0f66: /* pcmpgtd */ 7896 case 0x0f67: /* packuswb */ 7897 case 0x0f68: /* punpckhbw */ 7898 case 0x0f69: /* punpckhwd */ 7899 case 0x0f6a: /* punpckhdq */ 7900 case 0x0f6b: /* packssdw */ 7901 case 0x0f6e: /* movd */ 7902 case 0x0f6f: /* movq */ 7903 case 0x0f70: /* pshufw */ 7904 case 0x0f74: /* pcmpeqb */ 7905 case 0x0f75: /* pcmpeqw */ 7906 case 0x0f76: /* pcmpeqd */ 7907 case 0x0fc4: /* pinsrw */ 7908 case 0x0fd1: /* psrlw */ 7909 case 0x0fd2: /* psrld */ 7910 case 0x0fd3: /* psrlq */ 7911 case 0x0fd4: /* paddq */ 7912 case 0x0fd5: /* pmullw */ 7913 case 0xf20fd6: /* movdq2q */ 7914 case 0x0fd8: /* psubusb */ 7915 case 0x0fd9: /* psubusw */ 7916 case 0x0fda: /* pminub */ 7917 case 0x0fdb: /* pand */ 7918 case 0x0fdc: /* paddusb */ 7919 case 0x0fdd: /* paddusw */ 7920 case 0x0fde: /* pmaxub */ 7921 case 0x0fdf: /* pandn */ 7922 case 0x0fe0: /* pavgb */ 7923 case 0x0fe1: /* psraw */ 7924 case 0x0fe2: /* psrad */ 7925 case 0x0fe3: /* pavgw */ 7926 case 0x0fe4: /* pmulhuw */ 7927 case 0x0fe5: /* pmulhw */ 7928 case 0x0fe8: /* psubsb */ 7929 case 0x0fe9: /* psubsw */ 7930 case 0x0fea: /* pminsw */ 7931 case 0x0feb: /* por */ 7932 case 0x0fec: /* paddsb */ 7933 case 0x0fed: /* paddsw */ 7934 case 0x0fee: /* pmaxsw */ 7935 case 0x0fef: /* pxor */ 7936 case 0x0ff1: /* psllw */ 7937 case 0x0ff2: /* pslld */ 7938 case 0x0ff3: /* psllq */ 7939 case 0x0ff4: /* pmuludq */ 7940 case 0x0ff5: /* pmaddwd */ 7941 case 0x0ff6: /* psadbw */ 7942 case 0x0ff8: /* psubb */ 7943 case 0x0ff9: /* psubw */ 7944 case 0x0ffa: /* psubd */ 7945 case 0x0ffb: /* psubq */ 7946 case 0x0ffc: /* paddb */ 7947 case 0x0ffd: /* paddw */ 7948 case 0x0ffe: /* paddd */ 7949 if (i386_record_modrm (&ir)) 7950 return -1; 7951 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) 7952 goto no_support; 7953 record_full_arch_list_add_reg (ir.regcache, 7954 I387_MM0_REGNUM (tdep) + ir.reg); 7955 break; 7956 7957 case 0x0f71: /* psllw */ 7958 case 0x0f72: /* pslld */ 7959 case 0x0f73: /* psllq */ 7960 if (i386_record_modrm (&ir)) 7961 return -1; 7962 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) 7963 goto no_support; 7964 record_full_arch_list_add_reg (ir.regcache, 7965 I387_MM0_REGNUM (tdep) + ir.rm); 7966 break; 7967 7968 case 0x660f71: /* psllw */ 7969 case 0x660f72: /* pslld */ 7970 case 0x660f73: /* psllq */ 7971 if (i386_record_modrm (&ir)) 7972 return -1; 7973 ir.rm |= ir.rex_b; 7974 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) 7975 goto no_support; 7976 record_full_arch_list_add_reg (ir.regcache, 7977 I387_XMM0_REGNUM (tdep) + ir.rm); 7978 break; 7979 7980 case 0x0f7e: /* movd */ 7981 case 0x660f7e: /* movd */ 7982 if (i386_record_modrm (&ir)) 7983 return -1; 7984 if (ir.mod == 3) 7985 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 7986 else 7987 { 7988 if (ir.dflag == 2) 7989 ir.ot = OT_QUAD; 7990 else 7991 ir.ot = OT_LONG; 7992 if (i386_record_lea_modrm (&ir)) 7993 return -1; 7994 } 7995 break; 7996 7997 case 0x0f7f: /* movq */ 7998 if (i386_record_modrm (&ir)) 7999 return -1; 8000 if (ir.mod == 3) 8001 { 8002 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) 8003 goto no_support; 8004 record_full_arch_list_add_reg (ir.regcache, 8005 I387_MM0_REGNUM (tdep) + ir.rm); 8006 } 8007 else 8008 { 8009 ir.ot = OT_QUAD; 8010 if (i386_record_lea_modrm (&ir)) 8011 return -1; 8012 } 8013 break; 8014 8015 case 0xf30fb8: /* popcnt */ 8016 if (i386_record_modrm (&ir)) 8017 return -1; 8018 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 8019 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 8020 break; 8021 8022 case 0x660fd6: /* movq */ 8023 if (i386_record_modrm (&ir)) 8024 return -1; 8025 if (ir.mod == 3) 8026 { 8027 ir.rm |= ir.rex_b; 8028 if (!i386_xmm_regnum_p (gdbarch, 8029 I387_XMM0_REGNUM (tdep) + ir.rm)) 8030 goto no_support; 8031 record_full_arch_list_add_reg (ir.regcache, 8032 I387_XMM0_REGNUM (tdep) + ir.rm); 8033 } 8034 else 8035 { 8036 ir.ot = OT_QUAD; 8037 if (i386_record_lea_modrm (&ir)) 8038 return -1; 8039 } 8040 break; 8041 8042 case 0x660f3817: /* ptest */ 8043 case 0x0f2e: /* ucomiss */ 8044 case 0x660f2e: /* ucomisd */ 8045 case 0x0f2f: /* comiss */ 8046 case 0x660f2f: /* comisd */ 8047 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 8048 break; 8049 8050 case 0x0ff7: /* maskmovq */ 8051 regcache_raw_read_unsigned (ir.regcache, 8052 ir.regmap[X86_RECORD_REDI_REGNUM], 8053 &addr); 8054 if (record_full_arch_list_add_mem (addr, 64)) 8055 return -1; 8056 break; 8057 8058 case 0x660ff7: /* maskmovdqu */ 8059 regcache_raw_read_unsigned (ir.regcache, 8060 ir.regmap[X86_RECORD_REDI_REGNUM], 8061 &addr); 8062 if (record_full_arch_list_add_mem (addr, 128)) 8063 return -1; 8064 break; 8065 8066 default: 8067 goto no_support; 8068 break; 8069 } 8070 break; 8071 8072 default: 8073 goto no_support; 8074 break; 8075 } 8076 8077 /* In the future, maybe still need to deal with need_dasm. */ 8078 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); 8079 if (record_full_arch_list_add_end ()) 8080 return -1; 8081 8082 return 0; 8083 8084 no_support: 8085 printf_unfiltered (_("Process record does not support instruction 0x%02x " 8086 "at address %s.\n"), 8087 (unsigned int) (opcode), 8088 paddress (gdbarch, ir.orig_addr)); 8089 return -1; 8090 } 8091 8092 static const int i386_record_regmap[] = 8093 { 8094 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, 8095 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, 8096 0, 0, 0, 0, 0, 0, 0, 0, 8097 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, 8098 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM 8099 }; 8100 8101 /* Check that the given address appears suitable for a fast 8102 tracepoint, which on x86-64 means that we need an instruction of at 8103 least 5 bytes, so that we can overwrite it with a 4-byte-offset 8104 jump and not have to worry about program jumps to an address in the 8105 middle of the tracepoint jump. On x86, it may be possible to use 8106 4-byte jumps with a 2-byte offset to a trampoline located in the 8107 bottom 64 KiB of memory. Returns 1 if OK, and writes a size 8108 of instruction to replace, and 0 if not, plus an explanatory 8109 string. */ 8110 8111 static int 8112 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr, 8113 char **msg) 8114 { 8115 int len, jumplen; 8116 static struct ui_file *gdb_null = NULL; 8117 8118 /* Ask the target for the minimum instruction length supported. */ 8119 jumplen = target_get_min_fast_tracepoint_insn_len (); 8120 8121 if (jumplen < 0) 8122 { 8123 /* If the target does not support the get_min_fast_tracepoint_insn_len 8124 operation, assume that fast tracepoints will always be implemented 8125 using 4-byte relative jumps on both x86 and x86-64. */ 8126 jumplen = 5; 8127 } 8128 else if (jumplen == 0) 8129 { 8130 /* If the target does support get_min_fast_tracepoint_insn_len but 8131 returns zero, then the IPA has not loaded yet. In this case, 8132 we optimistically assume that truncated 2-byte relative jumps 8133 will be available on x86, and compensate later if this assumption 8134 turns out to be incorrect. On x86-64 architectures, 4-byte relative 8135 jumps will always be used. */ 8136 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; 8137 } 8138 8139 /* Dummy file descriptor for the disassembler. */ 8140 if (!gdb_null) 8141 gdb_null = ui_file_new (); 8142 8143 /* Check for fit. */ 8144 len = gdb_print_insn (gdbarch, addr, gdb_null, NULL); 8145 8146 if (len < jumplen) 8147 { 8148 /* Return a bit of target-specific detail to add to the caller's 8149 generic failure message. */ 8150 if (msg) 8151 *msg = xstrprintf (_("; instruction is only %d bytes long, " 8152 "need at least %d bytes for the jump"), 8153 len, jumplen); 8154 return 0; 8155 } 8156 else 8157 { 8158 if (msg) 8159 *msg = NULL; 8160 return 1; 8161 } 8162 } 8163 8164 static int 8165 i386_validate_tdesc_p (struct gdbarch_tdep *tdep, 8166 struct tdesc_arch_data *tdesc_data) 8167 { 8168 const struct target_desc *tdesc = tdep->tdesc; 8169 const struct tdesc_feature *feature_core; 8170 8171 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx, 8172 *feature_avx512; 8173 int i, num_regs, valid_p; 8174 8175 if (! tdesc_has_registers (tdesc)) 8176 return 0; 8177 8178 /* Get core registers. */ 8179 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); 8180 if (feature_core == NULL) 8181 return 0; 8182 8183 /* Get SSE registers. */ 8184 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); 8185 8186 /* Try AVX registers. */ 8187 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); 8188 8189 /* Try MPX registers. */ 8190 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx"); 8191 8192 /* Try AVX512 registers. */ 8193 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512"); 8194 8195 valid_p = 1; 8196 8197 /* The XCR0 bits. */ 8198 if (feature_avx512) 8199 { 8200 /* AVX512 register description requires AVX register description. */ 8201 if (!feature_avx) 8202 return 0; 8203 8204 tdep->xcr0 = X86_XSTATE_MPX_AVX512_MASK; 8205 8206 /* It may have been set by OSABI initialization function. */ 8207 if (tdep->k0_regnum < 0) 8208 { 8209 tdep->k_register_names = i386_k_names; 8210 tdep->k0_regnum = I386_K0_REGNUM; 8211 } 8212 8213 for (i = 0; i < I387_NUM_K_REGS; i++) 8214 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, 8215 tdep->k0_regnum + i, 8216 i386_k_names[i]); 8217 8218 if (tdep->num_zmm_regs == 0) 8219 { 8220 tdep->zmmh_register_names = i386_zmmh_names; 8221 tdep->num_zmm_regs = 8; 8222 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM; 8223 } 8224 8225 for (i = 0; i < tdep->num_zmm_regs; i++) 8226 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, 8227 tdep->zmm0h_regnum + i, 8228 tdep->zmmh_register_names[i]); 8229 8230 for (i = 0; i < tdep->num_xmm_avx512_regs; i++) 8231 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, 8232 tdep->xmm16_regnum + i, 8233 tdep->xmm_avx512_register_names[i]); 8234 8235 for (i = 0; i < tdep->num_ymm_avx512_regs; i++) 8236 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, 8237 tdep->ymm16h_regnum + i, 8238 tdep->ymm16h_register_names[i]); 8239 } 8240 if (feature_avx) 8241 { 8242 /* AVX register description requires SSE register description. */ 8243 if (!feature_sse) 8244 return 0; 8245 8246 if (!feature_avx512) 8247 tdep->xcr0 = X86_XSTATE_AVX_MASK; 8248 8249 /* It may have been set by OSABI initialization function. */ 8250 if (tdep->num_ymm_regs == 0) 8251 { 8252 tdep->ymmh_register_names = i386_ymmh_names; 8253 tdep->num_ymm_regs = 8; 8254 tdep->ymm0h_regnum = I386_YMM0H_REGNUM; 8255 } 8256 8257 for (i = 0; i < tdep->num_ymm_regs; i++) 8258 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, 8259 tdep->ymm0h_regnum + i, 8260 tdep->ymmh_register_names[i]); 8261 } 8262 else if (feature_sse) 8263 tdep->xcr0 = X86_XSTATE_SSE_MASK; 8264 else 8265 { 8266 tdep->xcr0 = X86_XSTATE_X87_MASK; 8267 tdep->num_xmm_regs = 0; 8268 } 8269 8270 num_regs = tdep->num_core_regs; 8271 for (i = 0; i < num_regs; i++) 8272 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, 8273 tdep->register_names[i]); 8274 8275 if (feature_sse) 8276 { 8277 /* Need to include %mxcsr, so add one. */ 8278 num_regs += tdep->num_xmm_regs + 1; 8279 for (; i < num_regs; i++) 8280 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, 8281 tdep->register_names[i]); 8282 } 8283 8284 if (feature_mpx) 8285 { 8286 tdep->xcr0 |= X86_XSTATE_MPX_MASK; 8287 8288 if (tdep->bnd0r_regnum < 0) 8289 { 8290 tdep->mpx_register_names = i386_mpx_names; 8291 tdep->bnd0r_regnum = I386_BND0R_REGNUM; 8292 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM; 8293 } 8294 8295 for (i = 0; i < I387_NUM_MPX_REGS; i++) 8296 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data, 8297 I387_BND0R_REGNUM (tdep) + i, 8298 tdep->mpx_register_names[i]); 8299 } 8300 8301 return valid_p; 8302 } 8303 8304 8305 static struct gdbarch * 8306 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 8307 { 8308 struct gdbarch_tdep *tdep; 8309 struct gdbarch *gdbarch; 8310 struct tdesc_arch_data *tdesc_data; 8311 const struct target_desc *tdesc; 8312 int mm0_regnum; 8313 int ymm0_regnum; 8314 int bnd0_regnum; 8315 int num_bnd_cooked; 8316 8317 /* If there is already a candidate, use it. */ 8318 arches = gdbarch_list_lookup_by_info (arches, &info); 8319 if (arches != NULL) 8320 return arches->gdbarch; 8321 8322 /* Allocate space for the new architecture. */ 8323 tdep = XCNEW (struct gdbarch_tdep); 8324 gdbarch = gdbarch_alloc (&info, tdep); 8325 8326 /* General-purpose registers. */ 8327 tdep->gregset_reg_offset = NULL; 8328 tdep->gregset_num_regs = I386_NUM_GREGS; 8329 tdep->sizeof_gregset = 0; 8330 8331 /* Floating-point registers. */ 8332 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; 8333 tdep->fpregset = &i386_fpregset; 8334 8335 /* The default settings include the FPU registers, the MMX registers 8336 and the SSE registers. This can be overridden for a specific ABI 8337 by adjusting the members `st0_regnum', `mm0_regnum' and 8338 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers 8339 will show up in the output of "info all-registers". */ 8340 8341 tdep->st0_regnum = I386_ST0_REGNUM; 8342 8343 /* I386_NUM_XREGS includes %mxcsr, so substract one. */ 8344 tdep->num_xmm_regs = I386_NUM_XREGS - 1; 8345 8346 tdep->jb_pc_offset = -1; 8347 tdep->struct_return = pcc_struct_return; 8348 tdep->sigtramp_start = 0; 8349 tdep->sigtramp_end = 0; 8350 tdep->sigtramp_p = i386_sigtramp_p; 8351 tdep->sigcontext_addr = NULL; 8352 tdep->sc_reg_offset = NULL; 8353 tdep->sc_pc_offset = -1; 8354 tdep->sc_sp_offset = -1; 8355 8356 tdep->xsave_xcr0_offset = -1; 8357 8358 tdep->record_regmap = i386_record_regmap; 8359 8360 set_gdbarch_long_long_align_bit (gdbarch, 32); 8361 8362 /* The format used for `long double' on almost all i386 targets is 8363 the i387 extended floating-point format. In fact, of all targets 8364 in the GCC 2.95 tree, only OSF/1 does it different, and insists 8365 on having a `long double' that's not `long' at all. */ 8366 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); 8367 8368 /* Although the i387 extended floating-point has only 80 significant 8369 bits, a `long double' actually takes up 96, probably to enforce 8370 alignment. */ 8371 set_gdbarch_long_double_bit (gdbarch, 96); 8372 8373 /* Register numbers of various important registers. */ 8374 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ 8375 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ 8376 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ 8377 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ 8378 8379 /* NOTE: kettenis/20040418: GCC does have two possible register 8380 numbering schemes on the i386: dbx and SVR4. These schemes 8381 differ in how they number %ebp, %esp, %eflags, and the 8382 floating-point registers, and are implemented by the arrays 8383 dbx_register_map[] and svr4_dbx_register_map in 8384 gcc/config/i386.c. GCC also defines a third numbering scheme in 8385 gcc/config/i386.c, which it designates as the "default" register 8386 map used in 64bit mode. This last register numbering scheme is 8387 implemented in dbx64_register_map, and is used for AMD64; see 8388 amd64-tdep.c. 8389 8390 Currently, each GCC i386 target always uses the same register 8391 numbering scheme across all its supported debugging formats 8392 i.e. SDB (COFF), stabs and DWARF 2. This is because 8393 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the 8394 DBX_REGISTER_NUMBER macro which is defined by each target's 8395 respective config header in a manner independent of the requested 8396 output debugging format. 8397 8398 This does not match the arrangement below, which presumes that 8399 the SDB and stabs numbering schemes differ from the DWARF and 8400 DWARF 2 ones. The reason for this arrangement is that it is 8401 likely to get the numbering scheme for the target's 8402 default/native debug format right. For targets where GCC is the 8403 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for 8404 targets where the native toolchain uses a different numbering 8405 scheme for a particular debug format (stabs-in-ELF on Solaris) 8406 the defaults below will have to be overridden, like 8407 i386_elf_init_abi() does. */ 8408 8409 /* Use the dbx register numbering scheme for stabs and COFF. */ 8410 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); 8411 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); 8412 8413 /* Use the SVR4 register numbering scheme for DWARF 2. */ 8414 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum); 8415 8416 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to 8417 be in use on any of the supported i386 targets. */ 8418 8419 set_gdbarch_print_float_info (gdbarch, i387_print_float_info); 8420 8421 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); 8422 8423 /* Call dummy code. */ 8424 set_gdbarch_call_dummy_location (gdbarch, ON_STACK); 8425 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code); 8426 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); 8427 set_gdbarch_frame_align (gdbarch, i386_frame_align); 8428 8429 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); 8430 set_gdbarch_register_to_value (gdbarch, i386_register_to_value); 8431 set_gdbarch_value_to_register (gdbarch, i386_value_to_register); 8432 8433 set_gdbarch_return_value (gdbarch, i386_return_value); 8434 8435 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); 8436 8437 /* Stack grows downward. */ 8438 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 8439 8440 set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); 8441 set_gdbarch_decr_pc_after_break (gdbarch, 1); 8442 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); 8443 8444 set_gdbarch_frame_args_skip (gdbarch, 8); 8445 8446 set_gdbarch_print_insn (gdbarch, i386_print_insn); 8447 8448 set_gdbarch_dummy_id (gdbarch, i386_dummy_id); 8449 8450 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); 8451 8452 /* Add the i386 register groups. */ 8453 i386_add_reggroups (gdbarch); 8454 tdep->register_reggroup_p = i386_register_reggroup_p; 8455 8456 /* Helper for function argument information. */ 8457 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); 8458 8459 /* Hook the function epilogue frame unwinder. This unwinder is 8460 appended to the list first, so that it supercedes the DWARF 8461 unwinder in function epilogues (where the DWARF unwinder 8462 currently fails). */ 8463 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); 8464 8465 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended 8466 to the list before the prologue-based unwinders, so that DWARF 8467 CFI info will be used if it is available. */ 8468 dwarf2_append_unwinders (gdbarch); 8469 8470 frame_base_set_default (gdbarch, &i386_frame_base); 8471 8472 /* Pseudo registers may be changed by amd64_init_abi. */ 8473 set_gdbarch_pseudo_register_read_value (gdbarch, 8474 i386_pseudo_register_read_value); 8475 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); 8476 set_gdbarch_ax_pseudo_register_collect (gdbarch, 8477 i386_ax_pseudo_register_collect); 8478 8479 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); 8480 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); 8481 8482 /* Override the normal target description method to make the AVX 8483 upper halves anonymous. */ 8484 set_gdbarch_register_name (gdbarch, i386_register_name); 8485 8486 /* Even though the default ABI only includes general-purpose registers, 8487 floating-point registers and the SSE registers, we have to leave a 8488 gap for the upper AVX, MPX and AVX512 registers. */ 8489 set_gdbarch_num_regs (gdbarch, I386_AVX512_NUM_REGS); 8490 8491 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); 8492 8493 /* Get the x86 target description from INFO. */ 8494 tdesc = info.target_desc; 8495 if (! tdesc_has_registers (tdesc)) 8496 tdesc = tdesc_i386; 8497 tdep->tdesc = tdesc; 8498 8499 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; 8500 tdep->register_names = i386_register_names; 8501 8502 /* No upper YMM registers. */ 8503 tdep->ymmh_register_names = NULL; 8504 tdep->ymm0h_regnum = -1; 8505 8506 /* No upper ZMM registers. */ 8507 tdep->zmmh_register_names = NULL; 8508 tdep->zmm0h_regnum = -1; 8509 8510 /* No high XMM registers. */ 8511 tdep->xmm_avx512_register_names = NULL; 8512 tdep->xmm16_regnum = -1; 8513 8514 /* No upper YMM16-31 registers. */ 8515 tdep->ymm16h_register_names = NULL; 8516 tdep->ymm16h_regnum = -1; 8517 8518 tdep->num_byte_regs = 8; 8519 tdep->num_word_regs = 8; 8520 tdep->num_dword_regs = 0; 8521 tdep->num_mmx_regs = 8; 8522 tdep->num_ymm_regs = 0; 8523 8524 /* No MPX registers. */ 8525 tdep->bnd0r_regnum = -1; 8526 tdep->bndcfgu_regnum = -1; 8527 8528 /* No AVX512 registers. */ 8529 tdep->k0_regnum = -1; 8530 tdep->num_zmm_regs = 0; 8531 tdep->num_ymm_avx512_regs = 0; 8532 tdep->num_xmm_avx512_regs = 0; 8533 8534 tdesc_data = tdesc_data_alloc (); 8535 8536 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); 8537 8538 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); 8539 8540 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call); 8541 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret); 8542 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump); 8543 8544 /* Hook in ABI-specific overrides, if they have been registered. */ 8545 info.tdep_info = tdesc_data; 8546 gdbarch_init_osabi (info, gdbarch); 8547 8548 if (!i386_validate_tdesc_p (tdep, tdesc_data)) 8549 { 8550 tdesc_data_cleanup (tdesc_data); 8551 xfree (tdep); 8552 gdbarch_free (gdbarch); 8553 return NULL; 8554 } 8555 8556 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); 8557 8558 /* Wire in pseudo registers. Number of pseudo registers may be 8559 changed. */ 8560 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs 8561 + tdep->num_word_regs 8562 + tdep->num_dword_regs 8563 + tdep->num_mmx_regs 8564 + tdep->num_ymm_regs 8565 + num_bnd_cooked 8566 + tdep->num_ymm_avx512_regs 8567 + tdep->num_zmm_regs)); 8568 8569 /* Target description may be changed. */ 8570 tdesc = tdep->tdesc; 8571 8572 tdesc_use_registers (gdbarch, tdesc, tdesc_data); 8573 8574 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ 8575 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); 8576 8577 /* Make %al the first pseudo-register. */ 8578 tdep->al_regnum = gdbarch_num_regs (gdbarch); 8579 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; 8580 8581 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; 8582 if (tdep->num_dword_regs) 8583 { 8584 /* Support dword pseudo-register if it hasn't been disabled. */ 8585 tdep->eax_regnum = ymm0_regnum; 8586 ymm0_regnum += tdep->num_dword_regs; 8587 } 8588 else 8589 tdep->eax_regnum = -1; 8590 8591 mm0_regnum = ymm0_regnum; 8592 if (tdep->num_ymm_regs) 8593 { 8594 /* Support YMM pseudo-register if it is available. */ 8595 tdep->ymm0_regnum = ymm0_regnum; 8596 mm0_regnum += tdep->num_ymm_regs; 8597 } 8598 else 8599 tdep->ymm0_regnum = -1; 8600 8601 if (tdep->num_ymm_avx512_regs) 8602 { 8603 /* Support YMM16-31 pseudo registers if available. */ 8604 tdep->ymm16_regnum = mm0_regnum; 8605 mm0_regnum += tdep->num_ymm_avx512_regs; 8606 } 8607 else 8608 tdep->ymm16_regnum = -1; 8609 8610 if (tdep->num_zmm_regs) 8611 { 8612 /* Support ZMM pseudo-register if it is available. */ 8613 tdep->zmm0_regnum = mm0_regnum; 8614 mm0_regnum += tdep->num_zmm_regs; 8615 } 8616 else 8617 tdep->zmm0_regnum = -1; 8618 8619 bnd0_regnum = mm0_regnum; 8620 if (tdep->num_mmx_regs != 0) 8621 { 8622 /* Support MMX pseudo-register if MMX hasn't been disabled. */ 8623 tdep->mm0_regnum = mm0_regnum; 8624 bnd0_regnum += tdep->num_mmx_regs; 8625 } 8626 else 8627 tdep->mm0_regnum = -1; 8628 8629 if (tdep->bnd0r_regnum > 0) 8630 tdep->bnd0_regnum = bnd0_regnum; 8631 else 8632 tdep-> bnd0_regnum = -1; 8633 8634 /* Hook in the legacy prologue-based unwinders last (fallback). */ 8635 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); 8636 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); 8637 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); 8638 8639 /* If we have a register mapping, enable the generic core file 8640 support, unless it has already been enabled. */ 8641 if (tdep->gregset_reg_offset 8642 && !gdbarch_iterate_over_regset_sections_p (gdbarch)) 8643 set_gdbarch_iterate_over_regset_sections 8644 (gdbarch, i386_iterate_over_regset_sections); 8645 8646 set_gdbarch_fast_tracepoint_valid_at (gdbarch, 8647 i386_fast_tracepoint_valid_at); 8648 8649 return gdbarch; 8650 } 8651 8652 static enum gdb_osabi 8653 i386_coff_osabi_sniffer (bfd *abfd) 8654 { 8655 if (strcmp (bfd_get_target (abfd), "coff-go32-exe") == 0 8656 || strcmp (bfd_get_target (abfd), "coff-go32") == 0) 8657 return GDB_OSABI_GO32; 8658 8659 return GDB_OSABI_UNKNOWN; 8660 } 8661 8662 8663 /* Return the target description for a specified XSAVE feature mask. */ 8664 8665 const struct target_desc * 8666 i386_target_description (uint64_t xcr0) 8667 { 8668 switch (xcr0 & X86_XSTATE_ALL_MASK) 8669 { 8670 case X86_XSTATE_MPX_AVX512_MASK: 8671 case X86_XSTATE_AVX512_MASK: 8672 return tdesc_i386_avx512; 8673 case X86_XSTATE_AVX_MPX_MASK: 8674 return tdesc_i386_avx_mpx; 8675 case X86_XSTATE_MPX_MASK: 8676 return tdesc_i386_mpx; 8677 case X86_XSTATE_AVX_MASK: 8678 return tdesc_i386_avx; 8679 default: 8680 return tdesc_i386; 8681 } 8682 } 8683 8684 #define MPX_BASE_MASK (~(ULONGEST) 0xfff) 8685 8686 /* Find the bound directory base address. */ 8687 8688 static unsigned long 8689 i386_mpx_bd_base (void) 8690 { 8691 struct regcache *rcache; 8692 struct gdbarch_tdep *tdep; 8693 ULONGEST ret; 8694 enum register_status regstatus; 8695 8696 rcache = get_current_regcache (); 8697 tdep = gdbarch_tdep (get_regcache_arch (rcache)); 8698 8699 regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret); 8700 8701 if (regstatus != REG_VALID) 8702 error (_("BNDCFGU register invalid, read status %d."), regstatus); 8703 8704 return ret & MPX_BASE_MASK; 8705 } 8706 8707 int 8708 i386_mpx_enabled (void) 8709 { 8710 const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ()); 8711 const struct target_desc *tdesc = tdep->tdesc; 8712 8713 return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL); 8714 } 8715 8716 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */ 8717 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */ 8718 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */ 8719 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */ 8720 8721 /* Find the bound table entry given the pointer location and the base 8722 address of the table. */ 8723 8724 static CORE_ADDR 8725 i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base) 8726 { 8727 CORE_ADDR offset1; 8728 CORE_ADDR offset2; 8729 CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift; 8730 CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift; 8731 CORE_ADDR bd_entry_addr; 8732 CORE_ADDR bt_addr; 8733 CORE_ADDR bd_entry; 8734 struct gdbarch *gdbarch = get_current_arch (); 8735 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; 8736 8737 8738 if (gdbarch_ptr_bit (gdbarch) == 64) 8739 { 8740 mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK; 8741 bd_ptr_r_shift = 20; 8742 bd_ptr_l_shift = 3; 8743 bt_select_r_shift = 3; 8744 bt_select_l_shift = 5; 8745 bt_mask = (CORE_ADDR) MPX_BT_MASK; 8746 8747 if ( sizeof (CORE_ADDR) == 4) 8748 error (_("bound table examination not supported\ 8749 for 64-bit process with 32-bit GDB")); 8750 } 8751 else 8752 { 8753 mpx_bd_mask = MPX_BD_MASK_32; 8754 bd_ptr_r_shift = 12; 8755 bd_ptr_l_shift = 2; 8756 bt_select_r_shift = 2; 8757 bt_select_l_shift = 4; 8758 bt_mask = MPX_BT_MASK_32; 8759 } 8760 8761 offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift; 8762 bd_entry_addr = bd_base + offset1; 8763 bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type); 8764 8765 if ((bd_entry & 0x1) == 0) 8766 error (_("Invalid bounds directory entry at %s."), 8767 paddress (get_current_arch (), bd_entry_addr)); 8768 8769 /* Clearing status bit. */ 8770 bd_entry--; 8771 bt_addr = bd_entry & ~bt_select_r_shift; 8772 offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift; 8773 8774 return bt_addr + offset2; 8775 } 8776 8777 /* Print routine for the mpx bounds. */ 8778 8779 static void 8780 i386_mpx_print_bounds (const CORE_ADDR bt_entry[4]) 8781 { 8782 struct ui_out *uiout = current_uiout; 8783 LONGEST size; 8784 struct gdbarch *gdbarch = get_current_arch (); 8785 CORE_ADDR onecompl = ~((CORE_ADDR) 0); 8786 int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0); 8787 8788 if (bounds_in_map == 1) 8789 { 8790 ui_out_text (uiout, "Null bounds on map:"); 8791 ui_out_text (uiout, " pointer value = "); 8792 ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]); 8793 ui_out_text (uiout, "."); 8794 ui_out_text (uiout, "\n"); 8795 } 8796 else 8797 { 8798 ui_out_text (uiout, "{lbound = "); 8799 ui_out_field_core_addr (uiout, "lower-bound", gdbarch, bt_entry[0]); 8800 ui_out_text (uiout, ", ubound = "); 8801 8802 /* The upper bound is stored in 1's complement. */ 8803 ui_out_field_core_addr (uiout, "upper-bound", gdbarch, ~bt_entry[1]); 8804 ui_out_text (uiout, "}: pointer value = "); 8805 ui_out_field_core_addr (uiout, "pointer-value", gdbarch, bt_entry[2]); 8806 8807 if (gdbarch_ptr_bit (gdbarch) == 64) 8808 size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]); 8809 else 8810 size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]); 8811 8812 /* In case the bounds are 0x0 and 0xffff... the difference will be -1. 8813 -1 represents in this sense full memory access, and there is no need 8814 one to the size. */ 8815 8816 size = (size > -1 ? size + 1 : size); 8817 ui_out_text (uiout, ", size = "); 8818 ui_out_field_fmt (uiout, "size", "%s", plongest (size)); 8819 8820 ui_out_text (uiout, ", metadata = "); 8821 ui_out_field_core_addr (uiout, "metadata", gdbarch, bt_entry[3]); 8822 ui_out_text (uiout, "\n"); 8823 } 8824 } 8825 8826 /* Implement the command "show mpx bound". */ 8827 8828 static void 8829 i386_mpx_info_bounds (char *args, int from_tty) 8830 { 8831 CORE_ADDR bd_base = 0; 8832 CORE_ADDR addr; 8833 CORE_ADDR bt_entry_addr = 0; 8834 CORE_ADDR bt_entry[4]; 8835 int i; 8836 struct gdbarch *gdbarch = get_current_arch (); 8837 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; 8838 8839 if (!i386_mpx_enabled ()) 8840 { 8841 printf_unfiltered (_("Intel Memory Protection Extensions not " 8842 "supported on this target.\n")); 8843 return; 8844 } 8845 8846 if (args == NULL) 8847 { 8848 printf_unfiltered (_("Address of pointer variable expected.\n")); 8849 return; 8850 } 8851 8852 addr = parse_and_eval_address (args); 8853 8854 bd_base = i386_mpx_bd_base (); 8855 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); 8856 8857 memset (bt_entry, 0, sizeof (bt_entry)); 8858 8859 for (i = 0; i < 4; i++) 8860 bt_entry[i] = read_memory_typed_address (bt_entry_addr 8861 + i * TYPE_LENGTH (data_ptr_type), 8862 data_ptr_type); 8863 8864 i386_mpx_print_bounds (bt_entry); 8865 } 8866 8867 /* Implement the command "set mpx bound". */ 8868 8869 static void 8870 i386_mpx_set_bounds (char *args, int from_tty) 8871 { 8872 CORE_ADDR bd_base = 0; 8873 CORE_ADDR addr, lower, upper; 8874 CORE_ADDR bt_entry_addr = 0; 8875 CORE_ADDR bt_entry[2]; 8876 const char *input = args; 8877 int i; 8878 struct gdbarch *gdbarch = get_current_arch (); 8879 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 8880 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; 8881 8882 if (!i386_mpx_enabled ()) 8883 error (_("Intel Memory Protection Extensions not supported\ 8884 on this target.")); 8885 8886 if (args == NULL) 8887 error (_("Pointer value expected.")); 8888 8889 addr = value_as_address (parse_to_comma_and_eval (&input)); 8890 8891 if (input[0] == ',') 8892 ++input; 8893 if (input[0] == '\0') 8894 error (_("wrong number of arguments: missing lower and upper bound.")); 8895 lower = value_as_address (parse_to_comma_and_eval (&input)); 8896 8897 if (input[0] == ',') 8898 ++input; 8899 if (input[0] == '\0') 8900 error (_("Wrong number of arguments; Missing upper bound.")); 8901 upper = value_as_address (parse_to_comma_and_eval (&input)); 8902 8903 bd_base = i386_mpx_bd_base (); 8904 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); 8905 for (i = 0; i < 2; i++) 8906 bt_entry[i] = read_memory_typed_address (bt_entry_addr 8907 + i * TYPE_LENGTH (data_ptr_type), 8908 data_ptr_type); 8909 bt_entry[0] = (uint64_t) lower; 8910 bt_entry[1] = ~(uint64_t) upper; 8911 8912 for (i = 0; i < 2; i++) 8913 write_memory_unsigned_integer (bt_entry_addr 8914 + i * TYPE_LENGTH (data_ptr_type), 8915 TYPE_LENGTH (data_ptr_type), byte_order, 8916 bt_entry[i]); 8917 } 8918 8919 static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist; 8920 8921 /* Helper function for the CLI commands. */ 8922 8923 static void 8924 set_mpx_cmd (char *args, int from_tty) 8925 { 8926 help_list (mpx_set_cmdlist, "set mpx ", all_commands, gdb_stdout); 8927 } 8928 8929 /* Helper function for the CLI commands. */ 8930 8931 static void 8932 show_mpx_cmd (char *args, int from_tty) 8933 { 8934 cmd_show_list (mpx_show_cmdlist, from_tty, ""); 8935 } 8936 8937 /* Provide a prototype to silence -Wmissing-prototypes. */ 8938 void _initialize_i386_tdep (void); 8939 8940 void 8941 _initialize_i386_tdep (void) 8942 { 8943 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); 8944 8945 /* Add the variable that controls the disassembly flavor. */ 8946 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, 8947 &disassembly_flavor, _("\ 8948 Set the disassembly flavor."), _("\ 8949 Show the disassembly flavor."), _("\ 8950 The valid values are \"att\" and \"intel\", and the default value is \"att\"."), 8951 NULL, 8952 NULL, /* FIXME: i18n: */ 8953 &setlist, &showlist); 8954 8955 /* Add the variable that controls the convention for returning 8956 structs. */ 8957 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, 8958 &struct_convention, _("\ 8959 Set the convention for returning small structs."), _("\ 8960 Show the convention for returning small structs."), _("\ 8961 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ 8962 is \"default\"."), 8963 NULL, 8964 NULL, /* FIXME: i18n: */ 8965 &setlist, &showlist); 8966 8967 /* Add "mpx" prefix for the set commands. */ 8968 8969 add_prefix_cmd ("mpx", class_support, set_mpx_cmd, _("\ 8970 Set Intel Memory Protection Extensions specific variables."), 8971 &mpx_set_cmdlist, "set mpx ", 8972 0 /* allow-unknown */, &setlist); 8973 8974 /* Add "mpx" prefix for the show commands. */ 8975 8976 add_prefix_cmd ("mpx", class_support, show_mpx_cmd, _("\ 8977 Show Intel Memory Protection Extensions specific variables."), 8978 &mpx_show_cmdlist, "show mpx ", 8979 0 /* allow-unknown */, &showlist); 8980 8981 /* Add "bound" command for the show mpx commands list. */ 8982 8983 add_cmd ("bound", no_class, i386_mpx_info_bounds, 8984 "Show the memory bounds for a given array/pointer storage\ 8985 in the bound table.", 8986 &mpx_show_cmdlist); 8987 8988 /* Add "bound" command for the set mpx commands list. */ 8989 8990 add_cmd ("bound", no_class, i386_mpx_set_bounds, 8991 "Set the memory bounds for a given array/pointer storage\ 8992 in the bound table.", 8993 &mpx_set_cmdlist); 8994 8995 gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_coff_flavour, 8996 i386_coff_osabi_sniffer); 8997 8998 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, 8999 i386_svr4_init_abi); 9000 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_GO32, 9001 i386_go32_init_abi); 9002 9003 /* Initialize the i386-specific register groups. */ 9004 i386_init_reggroups (); 9005 9006 /* Initialize the standard target descriptions. */ 9007 initialize_tdesc_i386 (); 9008 initialize_tdesc_i386_mmx (); 9009 initialize_tdesc_i386_avx (); 9010 initialize_tdesc_i386_mpx (); 9011 initialize_tdesc_i386_avx_mpx (); 9012 initialize_tdesc_i386_avx512 (); 9013 9014 /* Tell remote stub that we support XML target description. */ 9015 register_remote_support_xml ("i386"); 9016 } 9017