1 /* Intel 386 target-dependent stuff. 2 3 Copyright (C) 1988-2020 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "opcode/i386.h" 22 #include "arch-utils.h" 23 #include "command.h" 24 #include "dummy-frame.h" 25 #include "dwarf2/frame.h" 26 #include "frame.h" 27 #include "frame-base.h" 28 #include "frame-unwind.h" 29 #include "inferior.h" 30 #include "infrun.h" 31 #include "gdbcmd.h" 32 #include "gdbcore.h" 33 #include "gdbtypes.h" 34 #include "objfiles.h" 35 #include "osabi.h" 36 #include "regcache.h" 37 #include "reggroups.h" 38 #include "regset.h" 39 #include "symfile.h" 40 #include "symtab.h" 41 #include "target.h" 42 #include "target-float.h" 43 #include "value.h" 44 #include "dis-asm.h" 45 #include "disasm.h" 46 #include "remote.h" 47 #include "i386-tdep.h" 48 #include "i387-tdep.h" 49 #include "gdbsupport/x86-xstate.h" 50 #include "x86-tdep.h" 51 52 #include "record.h" 53 #include "record-full.h" 54 #include "target-descriptions.h" 55 #include "arch/i386.h" 56 57 #include "ax.h" 58 #include "ax-gdb.h" 59 60 #include "stap-probe.h" 61 #include "user-regs.h" 62 #include "cli/cli-utils.h" 63 #include "expression.h" 64 #include "parser-defs.h" 65 #include <ctype.h> 66 #include <algorithm> 67 #include <unordered_set> 68 #include "producer.h" 69 70 /* Register names. */ 71 72 static const char *i386_register_names[] = 73 { 74 "eax", "ecx", "edx", "ebx", 75 "esp", "ebp", "esi", "edi", 76 "eip", "eflags", "cs", "ss", 77 "ds", "es", "fs", "gs", 78 "st0", "st1", "st2", "st3", 79 "st4", "st5", "st6", "st7", 80 "fctrl", "fstat", "ftag", "fiseg", 81 "fioff", "foseg", "fooff", "fop", 82 "xmm0", "xmm1", "xmm2", "xmm3", 83 "xmm4", "xmm5", "xmm6", "xmm7", 84 "mxcsr" 85 }; 86 87 static const char *i386_zmm_names[] = 88 { 89 "zmm0", "zmm1", "zmm2", "zmm3", 90 "zmm4", "zmm5", "zmm6", "zmm7" 91 }; 92 93 static const char *i386_zmmh_names[] = 94 { 95 "zmm0h", "zmm1h", "zmm2h", "zmm3h", 96 "zmm4h", "zmm5h", "zmm6h", "zmm7h" 97 }; 98 99 static const char *i386_k_names[] = 100 { 101 "k0", "k1", "k2", "k3", 102 "k4", "k5", "k6", "k7" 103 }; 104 105 static const char *i386_ymm_names[] = 106 { 107 "ymm0", "ymm1", "ymm2", "ymm3", 108 "ymm4", "ymm5", "ymm6", "ymm7", 109 }; 110 111 static const char *i386_ymmh_names[] = 112 { 113 "ymm0h", "ymm1h", "ymm2h", "ymm3h", 114 "ymm4h", "ymm5h", "ymm6h", "ymm7h", 115 }; 116 117 static const char *i386_mpx_names[] = 118 { 119 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" 120 }; 121 122 static const char* i386_pkeys_names[] = 123 { 124 "pkru" 125 }; 126 127 /* Register names for MPX pseudo-registers. */ 128 129 static const char *i386_bnd_names[] = 130 { 131 "bnd0", "bnd1", "bnd2", "bnd3" 132 }; 133 134 /* Register names for MMX pseudo-registers. */ 135 136 static const char *i386_mmx_names[] = 137 { 138 "mm0", "mm1", "mm2", "mm3", 139 "mm4", "mm5", "mm6", "mm7" 140 }; 141 142 /* Register names for byte pseudo-registers. */ 143 144 static const char *i386_byte_names[] = 145 { 146 "al", "cl", "dl", "bl", 147 "ah", "ch", "dh", "bh" 148 }; 149 150 /* Register names for word pseudo-registers. */ 151 152 static const char *i386_word_names[] = 153 { 154 "ax", "cx", "dx", "bx", 155 "", "bp", "si", "di" 156 }; 157 158 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have 159 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition, 160 we have 16 upper ZMM regs that have to be handled differently. */ 161 162 const int num_lower_zmm_regs = 16; 163 164 /* MMX register? */ 165 166 static int 167 i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) 168 { 169 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 170 int mm0_regnum = tdep->mm0_regnum; 171 172 if (mm0_regnum < 0) 173 return 0; 174 175 regnum -= mm0_regnum; 176 return regnum >= 0 && regnum < tdep->num_mmx_regs; 177 } 178 179 /* Byte register? */ 180 181 int 182 i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) 183 { 184 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 185 186 regnum -= tdep->al_regnum; 187 return regnum >= 0 && regnum < tdep->num_byte_regs; 188 } 189 190 /* Word register? */ 191 192 int 193 i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) 194 { 195 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 196 197 regnum -= tdep->ax_regnum; 198 return regnum >= 0 && regnum < tdep->num_word_regs; 199 } 200 201 /* Dword register? */ 202 203 int 204 i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) 205 { 206 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 207 int eax_regnum = tdep->eax_regnum; 208 209 if (eax_regnum < 0) 210 return 0; 211 212 regnum -= eax_regnum; 213 return regnum >= 0 && regnum < tdep->num_dword_regs; 214 } 215 216 /* AVX512 register? */ 217 218 int 219 i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum) 220 { 221 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 222 int zmm0h_regnum = tdep->zmm0h_regnum; 223 224 if (zmm0h_regnum < 0) 225 return 0; 226 227 regnum -= zmm0h_regnum; 228 return regnum >= 0 && regnum < tdep->num_zmm_regs; 229 } 230 231 int 232 i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum) 233 { 234 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 235 int zmm0_regnum = tdep->zmm0_regnum; 236 237 if (zmm0_regnum < 0) 238 return 0; 239 240 regnum -= zmm0_regnum; 241 return regnum >= 0 && regnum < tdep->num_zmm_regs; 242 } 243 244 int 245 i386_k_regnum_p (struct gdbarch *gdbarch, int regnum) 246 { 247 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 248 int k0_regnum = tdep->k0_regnum; 249 250 if (k0_regnum < 0) 251 return 0; 252 253 regnum -= k0_regnum; 254 return regnum >= 0 && regnum < I387_NUM_K_REGS; 255 } 256 257 static int 258 i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) 259 { 260 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 261 int ymm0h_regnum = tdep->ymm0h_regnum; 262 263 if (ymm0h_regnum < 0) 264 return 0; 265 266 regnum -= ymm0h_regnum; 267 return regnum >= 0 && regnum < tdep->num_ymm_regs; 268 } 269 270 /* AVX register? */ 271 272 int 273 i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) 274 { 275 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 276 int ymm0_regnum = tdep->ymm0_regnum; 277 278 if (ymm0_regnum < 0) 279 return 0; 280 281 regnum -= ymm0_regnum; 282 return regnum >= 0 && regnum < tdep->num_ymm_regs; 283 } 284 285 static int 286 i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) 287 { 288 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 289 int ymm16h_regnum = tdep->ymm16h_regnum; 290 291 if (ymm16h_regnum < 0) 292 return 0; 293 294 regnum -= ymm16h_regnum; 295 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; 296 } 297 298 int 299 i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) 300 { 301 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 302 int ymm16_regnum = tdep->ymm16_regnum; 303 304 if (ymm16_regnum < 0) 305 return 0; 306 307 regnum -= ymm16_regnum; 308 return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; 309 } 310 311 /* BND register? */ 312 313 int 314 i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum) 315 { 316 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 317 int bnd0_regnum = tdep->bnd0_regnum; 318 319 if (bnd0_regnum < 0) 320 return 0; 321 322 regnum -= bnd0_regnum; 323 return regnum >= 0 && regnum < I387_NUM_BND_REGS; 324 } 325 326 /* SSE register? */ 327 328 int 329 i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) 330 { 331 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 332 int num_xmm_regs = I387_NUM_XMM_REGS (tdep); 333 334 if (num_xmm_regs == 0) 335 return 0; 336 337 regnum -= I387_XMM0_REGNUM (tdep); 338 return regnum >= 0 && regnum < num_xmm_regs; 339 } 340 341 /* XMM_512 register? */ 342 343 int 344 i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) 345 { 346 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 347 int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep); 348 349 if (num_xmm_avx512_regs == 0) 350 return 0; 351 352 regnum -= I387_XMM16_REGNUM (tdep); 353 return regnum >= 0 && regnum < num_xmm_avx512_regs; 354 } 355 356 static int 357 i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) 358 { 359 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 360 361 if (I387_NUM_XMM_REGS (tdep) == 0) 362 return 0; 363 364 return (regnum == I387_MXCSR_REGNUM (tdep)); 365 } 366 367 /* FP register? */ 368 369 int 370 i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) 371 { 372 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 373 374 if (I387_ST0_REGNUM (tdep) < 0) 375 return 0; 376 377 return (I387_ST0_REGNUM (tdep) <= regnum 378 && regnum < I387_FCTRL_REGNUM (tdep)); 379 } 380 381 int 382 i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) 383 { 384 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 385 386 if (I387_ST0_REGNUM (tdep) < 0) 387 return 0; 388 389 return (I387_FCTRL_REGNUM (tdep) <= regnum 390 && regnum < I387_XMM0_REGNUM (tdep)); 391 } 392 393 /* BNDr (raw) register? */ 394 395 static int 396 i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum) 397 { 398 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 399 400 if (I387_BND0R_REGNUM (tdep) < 0) 401 return 0; 402 403 regnum -= tdep->bnd0r_regnum; 404 return regnum >= 0 && regnum < I387_NUM_BND_REGS; 405 } 406 407 /* BND control register? */ 408 409 static int 410 i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum) 411 { 412 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 413 414 if (I387_BNDCFGU_REGNUM (tdep) < 0) 415 return 0; 416 417 regnum -= I387_BNDCFGU_REGNUM (tdep); 418 return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS; 419 } 420 421 /* PKRU register? */ 422 423 bool 424 i386_pkru_regnum_p (struct gdbarch *gdbarch, int regnum) 425 { 426 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 427 int pkru_regnum = tdep->pkru_regnum; 428 429 if (pkru_regnum < 0) 430 return false; 431 432 regnum -= pkru_regnum; 433 return regnum >= 0 && regnum < I387_NUM_PKEYS_REGS; 434 } 435 436 /* Return the name of register REGNUM, or the empty string if it is 437 an anonymous register. */ 438 439 static const char * 440 i386_register_name (struct gdbarch *gdbarch, int regnum) 441 { 442 /* Hide the upper YMM registers. */ 443 if (i386_ymmh_regnum_p (gdbarch, regnum)) 444 return ""; 445 446 /* Hide the upper YMM16-31 registers. */ 447 if (i386_ymmh_avx512_regnum_p (gdbarch, regnum)) 448 return ""; 449 450 /* Hide the upper ZMM registers. */ 451 if (i386_zmmh_regnum_p (gdbarch, regnum)) 452 return ""; 453 454 return tdesc_register_name (gdbarch, regnum); 455 } 456 457 /* Return the name of register REGNUM. */ 458 459 const char * 460 i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) 461 { 462 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 463 if (i386_bnd_regnum_p (gdbarch, regnum)) 464 return i386_bnd_names[regnum - tdep->bnd0_regnum]; 465 if (i386_mmx_regnum_p (gdbarch, regnum)) 466 return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; 467 else if (i386_ymm_regnum_p (gdbarch, regnum)) 468 return i386_ymm_names[regnum - tdep->ymm0_regnum]; 469 else if (i386_zmm_regnum_p (gdbarch, regnum)) 470 return i386_zmm_names[regnum - tdep->zmm0_regnum]; 471 else if (i386_byte_regnum_p (gdbarch, regnum)) 472 return i386_byte_names[regnum - tdep->al_regnum]; 473 else if (i386_word_regnum_p (gdbarch, regnum)) 474 return i386_word_names[regnum - tdep->ax_regnum]; 475 476 internal_error (__FILE__, __LINE__, _("invalid regnum")); 477 } 478 479 /* Convert a dbx register number REG to the appropriate register 480 number used by GDB. */ 481 482 static int 483 i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) 484 { 485 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 486 487 /* This implements what GCC calls the "default" register map 488 (dbx_register_map[]). */ 489 490 if (reg >= 0 && reg <= 7) 491 { 492 /* General-purpose registers. The debug info calls %ebp 493 register 4, and %esp register 5. */ 494 if (reg == 4) 495 return 5; 496 else if (reg == 5) 497 return 4; 498 else return reg; 499 } 500 else if (reg >= 12 && reg <= 19) 501 { 502 /* Floating-point registers. */ 503 return reg - 12 + I387_ST0_REGNUM (tdep); 504 } 505 else if (reg >= 21 && reg <= 28) 506 { 507 /* SSE registers. */ 508 int ymm0_regnum = tdep->ymm0_regnum; 509 510 if (ymm0_regnum >= 0 511 && i386_xmm_regnum_p (gdbarch, reg)) 512 return reg - 21 + ymm0_regnum; 513 else 514 return reg - 21 + I387_XMM0_REGNUM (tdep); 515 } 516 else if (reg >= 29 && reg <= 36) 517 { 518 /* MMX registers. */ 519 return reg - 29 + I387_MM0_REGNUM (tdep); 520 } 521 522 /* This will hopefully provoke a warning. */ 523 return gdbarch_num_cooked_regs (gdbarch); 524 } 525 526 /* Convert SVR4 DWARF register number REG to the appropriate register number 527 used by GDB. */ 528 529 static int 530 i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) 531 { 532 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 533 534 /* This implements the GCC register map that tries to be compatible 535 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ 536 537 /* The SVR4 register numbering includes %eip and %eflags, and 538 numbers the floating point registers differently. */ 539 if (reg >= 0 && reg <= 9) 540 { 541 /* General-purpose registers. */ 542 return reg; 543 } 544 else if (reg >= 11 && reg <= 18) 545 { 546 /* Floating-point registers. */ 547 return reg - 11 + I387_ST0_REGNUM (tdep); 548 } 549 else if (reg >= 21 && reg <= 36) 550 { 551 /* The SSE and MMX registers have the same numbers as with dbx. */ 552 return i386_dbx_reg_to_regnum (gdbarch, reg); 553 } 554 555 switch (reg) 556 { 557 case 37: return I387_FCTRL_REGNUM (tdep); 558 case 38: return I387_FSTAT_REGNUM (tdep); 559 case 39: return I387_MXCSR_REGNUM (tdep); 560 case 40: return I386_ES_REGNUM; 561 case 41: return I386_CS_REGNUM; 562 case 42: return I386_SS_REGNUM; 563 case 43: return I386_DS_REGNUM; 564 case 44: return I386_FS_REGNUM; 565 case 45: return I386_GS_REGNUM; 566 } 567 568 return -1; 569 } 570 571 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return 572 num_regs + num_pseudo_regs for other debug formats. */ 573 574 int 575 i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) 576 { 577 int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg); 578 579 if (regnum == -1) 580 return gdbarch_num_cooked_regs (gdbarch); 581 return regnum; 582 } 583 584 585 586 /* This is the variable that is set with "set disassembly-flavor", and 587 its legitimate values. */ 588 static const char att_flavor[] = "att"; 589 static const char intel_flavor[] = "intel"; 590 static const char *const valid_flavors[] = 591 { 592 att_flavor, 593 intel_flavor, 594 NULL 595 }; 596 static const char *disassembly_flavor = att_flavor; 597 598 599 /* Use the program counter to determine the contents and size of a 600 breakpoint instruction. Return a pointer to a string of bytes that 601 encode a breakpoint instruction, store the length of the string in 602 *LEN and optionally adjust *PC to point to the correct memory 603 location for inserting the breakpoint. 604 605 On the i386 we have a single breakpoint that fits in a single byte 606 and can be inserted anywhere. 607 608 This function is 64-bit safe. */ 609 610 constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */ 611 612 typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint; 613 614 615 /* Displaced instruction handling. */ 616 617 /* Skip the legacy instruction prefixes in INSN. 618 Not all prefixes are valid for any particular insn 619 but we needn't care, the insn will fault if it's invalid. 620 The result is a pointer to the first opcode byte, 621 or NULL if we run off the end of the buffer. */ 622 623 static gdb_byte * 624 i386_skip_prefixes (gdb_byte *insn, size_t max_len) 625 { 626 gdb_byte *end = insn + max_len; 627 628 while (insn < end) 629 { 630 switch (*insn) 631 { 632 case DATA_PREFIX_OPCODE: 633 case ADDR_PREFIX_OPCODE: 634 case CS_PREFIX_OPCODE: 635 case DS_PREFIX_OPCODE: 636 case ES_PREFIX_OPCODE: 637 case FS_PREFIX_OPCODE: 638 case GS_PREFIX_OPCODE: 639 case SS_PREFIX_OPCODE: 640 case LOCK_PREFIX_OPCODE: 641 case REPE_PREFIX_OPCODE: 642 case REPNE_PREFIX_OPCODE: 643 ++insn; 644 continue; 645 default: 646 return insn; 647 } 648 } 649 650 return NULL; 651 } 652 653 static int 654 i386_absolute_jmp_p (const gdb_byte *insn) 655 { 656 /* jmp far (absolute address in operand). */ 657 if (insn[0] == 0xea) 658 return 1; 659 660 if (insn[0] == 0xff) 661 { 662 /* jump near, absolute indirect (/4). */ 663 if ((insn[1] & 0x38) == 0x20) 664 return 1; 665 666 /* jump far, absolute indirect (/5). */ 667 if ((insn[1] & 0x38) == 0x28) 668 return 1; 669 } 670 671 return 0; 672 } 673 674 /* Return non-zero if INSN is a jump, zero otherwise. */ 675 676 static int 677 i386_jmp_p (const gdb_byte *insn) 678 { 679 /* jump short, relative. */ 680 if (insn[0] == 0xeb) 681 return 1; 682 683 /* jump near, relative. */ 684 if (insn[0] == 0xe9) 685 return 1; 686 687 return i386_absolute_jmp_p (insn); 688 } 689 690 static int 691 i386_absolute_call_p (const gdb_byte *insn) 692 { 693 /* call far, absolute. */ 694 if (insn[0] == 0x9a) 695 return 1; 696 697 if (insn[0] == 0xff) 698 { 699 /* Call near, absolute indirect (/2). */ 700 if ((insn[1] & 0x38) == 0x10) 701 return 1; 702 703 /* Call far, absolute indirect (/3). */ 704 if ((insn[1] & 0x38) == 0x18) 705 return 1; 706 } 707 708 return 0; 709 } 710 711 static int 712 i386_ret_p (const gdb_byte *insn) 713 { 714 switch (insn[0]) 715 { 716 case 0xc2: /* ret near, pop N bytes. */ 717 case 0xc3: /* ret near */ 718 case 0xca: /* ret far, pop N bytes. */ 719 case 0xcb: /* ret far */ 720 case 0xcf: /* iret */ 721 return 1; 722 723 default: 724 return 0; 725 } 726 } 727 728 static int 729 i386_call_p (const gdb_byte *insn) 730 { 731 if (i386_absolute_call_p (insn)) 732 return 1; 733 734 /* call near, relative. */ 735 if (insn[0] == 0xe8) 736 return 1; 737 738 return 0; 739 } 740 741 /* Return non-zero if INSN is a system call, and set *LENGTHP to its 742 length in bytes. Otherwise, return zero. */ 743 744 static int 745 i386_syscall_p (const gdb_byte *insn, int *lengthp) 746 { 747 /* Is it 'int $0x80'? */ 748 if ((insn[0] == 0xcd && insn[1] == 0x80) 749 /* Or is it 'sysenter'? */ 750 || (insn[0] == 0x0f && insn[1] == 0x34) 751 /* Or is it 'syscall'? */ 752 || (insn[0] == 0x0f && insn[1] == 0x05)) 753 { 754 *lengthp = 2; 755 return 1; 756 } 757 758 return 0; 759 } 760 761 /* The gdbarch insn_is_call method. */ 762 763 static int 764 i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) 765 { 766 gdb_byte buf[I386_MAX_INSN_LEN], *insn; 767 768 read_code (addr, buf, I386_MAX_INSN_LEN); 769 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); 770 771 return i386_call_p (insn); 772 } 773 774 /* The gdbarch insn_is_ret method. */ 775 776 static int 777 i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) 778 { 779 gdb_byte buf[I386_MAX_INSN_LEN], *insn; 780 781 read_code (addr, buf, I386_MAX_INSN_LEN); 782 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); 783 784 return i386_ret_p (insn); 785 } 786 787 /* The gdbarch insn_is_jump method. */ 788 789 static int 790 i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) 791 { 792 gdb_byte buf[I386_MAX_INSN_LEN], *insn; 793 794 read_code (addr, buf, I386_MAX_INSN_LEN); 795 insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); 796 797 return i386_jmp_p (insn); 798 } 799 800 /* Some kernels may run one past a syscall insn, so we have to cope. */ 801 802 displaced_step_closure_up 803 i386_displaced_step_copy_insn (struct gdbarch *gdbarch, 804 CORE_ADDR from, CORE_ADDR to, 805 struct regcache *regs) 806 { 807 size_t len = gdbarch_max_insn_length (gdbarch); 808 std::unique_ptr<i386_displaced_step_closure> closure 809 (new i386_displaced_step_closure (len)); 810 gdb_byte *buf = closure->buf.data (); 811 812 read_memory (from, buf, len); 813 814 /* GDB may get control back after the insn after the syscall. 815 Presumably this is a kernel bug. 816 If this is a syscall, make sure there's a nop afterwards. */ 817 { 818 int syscall_length; 819 gdb_byte *insn; 820 821 insn = i386_skip_prefixes (buf, len); 822 if (insn != NULL && i386_syscall_p (insn, &syscall_length)) 823 insn[syscall_length] = NOP_OPCODE; 824 } 825 826 write_memory (to, buf, len); 827 828 if (debug_displaced) 829 { 830 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", 831 paddress (gdbarch, from), paddress (gdbarch, to)); 832 displaced_step_dump_bytes (gdb_stdlog, buf, len); 833 } 834 835 /* This is a work around for a problem with g++ 4.8. */ 836 return displaced_step_closure_up (closure.release ()); 837 } 838 839 /* Fix up the state of registers and memory after having single-stepped 840 a displaced instruction. */ 841 842 void 843 i386_displaced_step_fixup (struct gdbarch *gdbarch, 844 struct displaced_step_closure *closure_, 845 CORE_ADDR from, CORE_ADDR to, 846 struct regcache *regs) 847 { 848 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 849 850 /* The offset we applied to the instruction's address. 851 This could well be negative (when viewed as a signed 32-bit 852 value), but ULONGEST won't reflect that, so take care when 853 applying it. */ 854 ULONGEST insn_offset = to - from; 855 856 i386_displaced_step_closure *closure 857 = (i386_displaced_step_closure *) closure_; 858 gdb_byte *insn = closure->buf.data (); 859 /* The start of the insn, needed in case we see some prefixes. */ 860 gdb_byte *insn_start = insn; 861 862 if (debug_displaced) 863 fprintf_unfiltered (gdb_stdlog, 864 "displaced: fixup (%s, %s), " 865 "insn = 0x%02x 0x%02x ...\n", 866 paddress (gdbarch, from), paddress (gdbarch, to), 867 insn[0], insn[1]); 868 869 /* The list of issues to contend with here is taken from 870 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. 871 Yay for Free Software! */ 872 873 /* Relocate the %eip, if necessary. */ 874 875 /* The instruction recognizers we use assume any leading prefixes 876 have been skipped. */ 877 { 878 /* This is the size of the buffer in closure. */ 879 size_t max_insn_len = gdbarch_max_insn_length (gdbarch); 880 gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); 881 /* If there are too many prefixes, just ignore the insn. 882 It will fault when run. */ 883 if (opcode != NULL) 884 insn = opcode; 885 } 886 887 /* Except in the case of absolute or indirect jump or call 888 instructions, or a return instruction, the new eip is relative to 889 the displaced instruction; make it relative. Well, signal 890 handler returns don't need relocation either, but we use the 891 value of %eip to recognize those; see below. */ 892 if (! i386_absolute_jmp_p (insn) 893 && ! i386_absolute_call_p (insn) 894 && ! i386_ret_p (insn)) 895 { 896 ULONGEST orig_eip; 897 int insn_len; 898 899 regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); 900 901 /* A signal trampoline system call changes the %eip, resuming 902 execution of the main program after the signal handler has 903 returned. That makes them like 'return' instructions; we 904 shouldn't relocate %eip. 905 906 But most system calls don't, and we do need to relocate %eip. 907 908 Our heuristic for distinguishing these cases: if stepping 909 over the system call instruction left control directly after 910 the instruction, the we relocate --- control almost certainly 911 doesn't belong in the displaced copy. Otherwise, we assume 912 the instruction has put control where it belongs, and leave 913 it unrelocated. Goodness help us if there are PC-relative 914 system calls. */ 915 if (i386_syscall_p (insn, &insn_len) 916 && orig_eip != to + (insn - insn_start) + insn_len 917 /* GDB can get control back after the insn after the syscall. 918 Presumably this is a kernel bug. 919 i386_displaced_step_copy_insn ensures its a nop, 920 we add one to the length for it. */ 921 && orig_eip != to + (insn - insn_start) + insn_len + 1) 922 { 923 if (debug_displaced) 924 fprintf_unfiltered (gdb_stdlog, 925 "displaced: syscall changed %%eip; " 926 "not relocating\n"); 927 } 928 else 929 { 930 ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; 931 932 /* If we just stepped over a breakpoint insn, we don't backup 933 the pc on purpose; this is to match behaviour without 934 stepping. */ 935 936 regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); 937 938 if (debug_displaced) 939 fprintf_unfiltered (gdb_stdlog, 940 "displaced: " 941 "relocated %%eip from %s to %s\n", 942 paddress (gdbarch, orig_eip), 943 paddress (gdbarch, eip)); 944 } 945 } 946 947 /* If the instruction was PUSHFL, then the TF bit will be set in the 948 pushed value, and should be cleared. We'll leave this for later, 949 since GDB already messes up the TF flag when stepping over a 950 pushfl. */ 951 952 /* If the instruction was a call, the return address now atop the 953 stack is the address following the copied instruction. We need 954 to make it the address following the original instruction. */ 955 if (i386_call_p (insn)) 956 { 957 ULONGEST esp; 958 ULONGEST retaddr; 959 const ULONGEST retaddr_len = 4; 960 961 regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); 962 retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); 963 retaddr = (retaddr - insn_offset) & 0xffffffffUL; 964 write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); 965 966 if (debug_displaced) 967 fprintf_unfiltered (gdb_stdlog, 968 "displaced: relocated return addr at %s to %s\n", 969 paddress (gdbarch, esp), 970 paddress (gdbarch, retaddr)); 971 } 972 } 973 974 static void 975 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) 976 { 977 target_write_memory (*to, buf, len); 978 *to += len; 979 } 980 981 static void 982 i386_relocate_instruction (struct gdbarch *gdbarch, 983 CORE_ADDR *to, CORE_ADDR oldloc) 984 { 985 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 986 gdb_byte buf[I386_MAX_INSN_LEN]; 987 int offset = 0, rel32, newrel; 988 int insn_length; 989 gdb_byte *insn = buf; 990 991 read_memory (oldloc, buf, I386_MAX_INSN_LEN); 992 993 insn_length = gdb_buffered_insn_length (gdbarch, insn, 994 I386_MAX_INSN_LEN, oldloc); 995 996 /* Get past the prefixes. */ 997 insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); 998 999 /* Adjust calls with 32-bit relative addresses as push/jump, with 1000 the address pushed being the location where the original call in 1001 the user program would return to. */ 1002 if (insn[0] == 0xe8) 1003 { 1004 gdb_byte push_buf[16]; 1005 unsigned int ret_addr; 1006 1007 /* Where "ret" in the original code will return to. */ 1008 ret_addr = oldloc + insn_length; 1009 push_buf[0] = 0x68; /* pushq $... */ 1010 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); 1011 /* Push the push. */ 1012 append_insns (to, 5, push_buf); 1013 1014 /* Convert the relative call to a relative jump. */ 1015 insn[0] = 0xe9; 1016 1017 /* Adjust the destination offset. */ 1018 rel32 = extract_signed_integer (insn + 1, 4, byte_order); 1019 newrel = (oldloc - *to) + rel32; 1020 store_signed_integer (insn + 1, 4, byte_order, newrel); 1021 1022 if (debug_displaced) 1023 fprintf_unfiltered (gdb_stdlog, 1024 "Adjusted insn rel32=%s at %s to" 1025 " rel32=%s at %s\n", 1026 hex_string (rel32), paddress (gdbarch, oldloc), 1027 hex_string (newrel), paddress (gdbarch, *to)); 1028 1029 /* Write the adjusted jump into its displaced location. */ 1030 append_insns (to, 5, insn); 1031 return; 1032 } 1033 1034 /* Adjust jumps with 32-bit relative addresses. Calls are already 1035 handled above. */ 1036 if (insn[0] == 0xe9) 1037 offset = 1; 1038 /* Adjust conditional jumps. */ 1039 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) 1040 offset = 2; 1041 1042 if (offset) 1043 { 1044 rel32 = extract_signed_integer (insn + offset, 4, byte_order); 1045 newrel = (oldloc - *to) + rel32; 1046 store_signed_integer (insn + offset, 4, byte_order, newrel); 1047 if (debug_displaced) 1048 fprintf_unfiltered (gdb_stdlog, 1049 "Adjusted insn rel32=%s at %s to" 1050 " rel32=%s at %s\n", 1051 hex_string (rel32), paddress (gdbarch, oldloc), 1052 hex_string (newrel), paddress (gdbarch, *to)); 1053 } 1054 1055 /* Write the adjusted instructions into their displaced 1056 location. */ 1057 append_insns (to, insn_length, buf); 1058 } 1059 1060 1061 #ifdef I386_REGNO_TO_SYMMETRY 1062 #error "The Sequent Symmetry is no longer supported." 1063 #endif 1064 1065 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi 1066 and %esp "belong" to the calling function. Therefore these 1067 registers should be saved if they're going to be modified. */ 1068 1069 /* The maximum number of saved registers. This should include all 1070 registers mentioned above, and %eip. */ 1071 #define I386_NUM_SAVED_REGS I386_NUM_GREGS 1072 1073 struct i386_frame_cache 1074 { 1075 /* Base address. */ 1076 CORE_ADDR base; 1077 int base_p; 1078 LONGEST sp_offset; 1079 CORE_ADDR pc; 1080 1081 /* Saved registers. */ 1082 CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; 1083 CORE_ADDR saved_sp; 1084 int saved_sp_reg; 1085 int pc_in_eax; 1086 1087 /* Stack space reserved for local variables. */ 1088 long locals; 1089 }; 1090 1091 /* Allocate and initialize a frame cache. */ 1092 1093 static struct i386_frame_cache * 1094 i386_alloc_frame_cache (void) 1095 { 1096 struct i386_frame_cache *cache; 1097 int i; 1098 1099 cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); 1100 1101 /* Base address. */ 1102 cache->base_p = 0; 1103 cache->base = 0; 1104 cache->sp_offset = -4; 1105 cache->pc = 0; 1106 1107 /* Saved registers. We initialize these to -1 since zero is a valid 1108 offset (that's where %ebp is supposed to be stored). */ 1109 for (i = 0; i < I386_NUM_SAVED_REGS; i++) 1110 cache->saved_regs[i] = -1; 1111 cache->saved_sp = 0; 1112 cache->saved_sp_reg = -1; 1113 cache->pc_in_eax = 0; 1114 1115 /* Frameless until proven otherwise. */ 1116 cache->locals = -1; 1117 1118 return cache; 1119 } 1120 1121 /* If the instruction at PC is a jump, return the address of its 1122 target. Otherwise, return PC. */ 1123 1124 static CORE_ADDR 1125 i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) 1126 { 1127 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1128 gdb_byte op; 1129 long delta = 0; 1130 int data16 = 0; 1131 1132 if (target_read_code (pc, &op, 1)) 1133 return pc; 1134 1135 if (op == 0x66) 1136 { 1137 data16 = 1; 1138 1139 op = read_code_unsigned_integer (pc + 1, 1, byte_order); 1140 } 1141 1142 switch (op) 1143 { 1144 case 0xe9: 1145 /* Relative jump: if data16 == 0, disp32, else disp16. */ 1146 if (data16) 1147 { 1148 delta = read_memory_integer (pc + 2, 2, byte_order); 1149 1150 /* Include the size of the jmp instruction (including the 1151 0x66 prefix). */ 1152 delta += 4; 1153 } 1154 else 1155 { 1156 delta = read_memory_integer (pc + 1, 4, byte_order); 1157 1158 /* Include the size of the jmp instruction. */ 1159 delta += 5; 1160 } 1161 break; 1162 case 0xeb: 1163 /* Relative jump, disp8 (ignore data16). */ 1164 delta = read_memory_integer (pc + data16 + 1, 1, byte_order); 1165 1166 delta += data16 + 2; 1167 break; 1168 } 1169 1170 return pc + delta; 1171 } 1172 1173 /* Check whether PC points at a prologue for a function returning a 1174 structure or union. If so, it updates CACHE and returns the 1175 address of the first instruction after the code sequence that 1176 removes the "hidden" argument from the stack or CURRENT_PC, 1177 whichever is smaller. Otherwise, return PC. */ 1178 1179 static CORE_ADDR 1180 i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, 1181 struct i386_frame_cache *cache) 1182 { 1183 /* Functions that return a structure or union start with: 1184 1185 popl %eax 0x58 1186 xchgl %eax, (%esp) 0x87 0x04 0x24 1187 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 1188 1189 (the System V compiler puts out the second `xchg' instruction, 1190 and the assembler doesn't try to optimize it, so the 'sib' form 1191 gets generated). This sequence is used to get the address of the 1192 return buffer for a function that returns a structure. */ 1193 static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; 1194 static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; 1195 gdb_byte buf[4]; 1196 gdb_byte op; 1197 1198 if (current_pc <= pc) 1199 return pc; 1200 1201 if (target_read_code (pc, &op, 1)) 1202 return pc; 1203 1204 if (op != 0x58) /* popl %eax */ 1205 return pc; 1206 1207 if (target_read_code (pc + 1, buf, 4)) 1208 return pc; 1209 1210 if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) 1211 return pc; 1212 1213 if (current_pc == pc) 1214 { 1215 cache->sp_offset += 4; 1216 return current_pc; 1217 } 1218 1219 if (current_pc == pc + 1) 1220 { 1221 cache->pc_in_eax = 1; 1222 return current_pc; 1223 } 1224 1225 if (buf[1] == proto1[1]) 1226 return pc + 4; 1227 else 1228 return pc + 5; 1229 } 1230 1231 static CORE_ADDR 1232 i386_skip_probe (CORE_ADDR pc) 1233 { 1234 /* A function may start with 1235 1236 pushl constant 1237 call _probe 1238 addl $4, %esp 1239 1240 followed by 1241 1242 pushl %ebp 1243 1244 etc. */ 1245 gdb_byte buf[8]; 1246 gdb_byte op; 1247 1248 if (target_read_code (pc, &op, 1)) 1249 return pc; 1250 1251 if (op == 0x68 || op == 0x6a) 1252 { 1253 int delta; 1254 1255 /* Skip past the `pushl' instruction; it has either a one-byte or a 1256 four-byte operand, depending on the opcode. */ 1257 if (op == 0x68) 1258 delta = 5; 1259 else 1260 delta = 2; 1261 1262 /* Read the following 8 bytes, which should be `call _probe' (6 1263 bytes) followed by `addl $4,%esp' (2 bytes). */ 1264 read_memory (pc + delta, buf, sizeof (buf)); 1265 if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) 1266 pc += delta + sizeof (buf); 1267 } 1268 1269 return pc; 1270 } 1271 1272 /* GCC 4.1 and later, can put code in the prologue to realign the 1273 stack pointer. Check whether PC points to such code, and update 1274 CACHE accordingly. Return the first instruction after the code 1275 sequence or CURRENT_PC, whichever is smaller. If we don't 1276 recognize the code, return PC. */ 1277 1278 static CORE_ADDR 1279 i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, 1280 struct i386_frame_cache *cache) 1281 { 1282 /* There are 2 code sequences to re-align stack before the frame 1283 gets set up: 1284 1285 1. Use a caller-saved saved register: 1286 1287 leal 4(%esp), %reg 1288 andl $-XXX, %esp 1289 pushl -4(%reg) 1290 1291 2. Use a callee-saved saved register: 1292 1293 pushl %reg 1294 leal 8(%esp), %reg 1295 andl $-XXX, %esp 1296 pushl -4(%reg) 1297 1298 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: 1299 1300 0x83 0xe4 0xf0 andl $-16, %esp 1301 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp 1302 */ 1303 1304 gdb_byte buf[14]; 1305 int reg; 1306 int offset, offset_and; 1307 static int regnums[8] = { 1308 I386_EAX_REGNUM, /* %eax */ 1309 I386_ECX_REGNUM, /* %ecx */ 1310 I386_EDX_REGNUM, /* %edx */ 1311 I386_EBX_REGNUM, /* %ebx */ 1312 I386_ESP_REGNUM, /* %esp */ 1313 I386_EBP_REGNUM, /* %ebp */ 1314 I386_ESI_REGNUM, /* %esi */ 1315 I386_EDI_REGNUM /* %edi */ 1316 }; 1317 1318 if (target_read_code (pc, buf, sizeof buf)) 1319 return pc; 1320 1321 /* Check caller-saved saved register. The first instruction has 1322 to be "leal 4(%esp), %reg". */ 1323 if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) 1324 { 1325 /* MOD must be binary 10 and R/M must be binary 100. */ 1326 if ((buf[1] & 0xc7) != 0x44) 1327 return pc; 1328 1329 /* REG has register number. */ 1330 reg = (buf[1] >> 3) & 7; 1331 offset = 4; 1332 } 1333 else 1334 { 1335 /* Check callee-saved saved register. The first instruction 1336 has to be "pushl %reg". */ 1337 if ((buf[0] & 0xf8) != 0x50) 1338 return pc; 1339 1340 /* Get register. */ 1341 reg = buf[0] & 0x7; 1342 1343 /* The next instruction has to be "leal 8(%esp), %reg". */ 1344 if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) 1345 return pc; 1346 1347 /* MOD must be binary 10 and R/M must be binary 100. */ 1348 if ((buf[2] & 0xc7) != 0x44) 1349 return pc; 1350 1351 /* REG has register number. Registers in pushl and leal have to 1352 be the same. */ 1353 if (reg != ((buf[2] >> 3) & 7)) 1354 return pc; 1355 1356 offset = 5; 1357 } 1358 1359 /* Rigister can't be %esp nor %ebp. */ 1360 if (reg == 4 || reg == 5) 1361 return pc; 1362 1363 /* The next instruction has to be "andl $-XXX, %esp". */ 1364 if (buf[offset + 1] != 0xe4 1365 || (buf[offset] != 0x81 && buf[offset] != 0x83)) 1366 return pc; 1367 1368 offset_and = offset; 1369 offset += buf[offset] == 0x81 ? 6 : 3; 1370 1371 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is 1372 0xfc. REG must be binary 110 and MOD must be binary 01. */ 1373 if (buf[offset] != 0xff 1374 || buf[offset + 2] != 0xfc 1375 || (buf[offset + 1] & 0xf8) != 0x70) 1376 return pc; 1377 1378 /* R/M has register. Registers in leal and pushl have to be the 1379 same. */ 1380 if (reg != (buf[offset + 1] & 7)) 1381 return pc; 1382 1383 if (current_pc > pc + offset_and) 1384 cache->saved_sp_reg = regnums[reg]; 1385 1386 return std::min (pc + offset + 3, current_pc); 1387 } 1388 1389 /* Maximum instruction length we need to handle. */ 1390 #define I386_MAX_MATCHED_INSN_LEN 6 1391 1392 /* Instruction description. */ 1393 struct i386_insn 1394 { 1395 size_t len; 1396 gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; 1397 gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; 1398 }; 1399 1400 /* Return whether instruction at PC matches PATTERN. */ 1401 1402 static int 1403 i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) 1404 { 1405 gdb_byte op; 1406 1407 if (target_read_code (pc, &op, 1)) 1408 return 0; 1409 1410 if ((op & pattern.mask[0]) == pattern.insn[0]) 1411 { 1412 gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; 1413 int insn_matched = 1; 1414 size_t i; 1415 1416 gdb_assert (pattern.len > 1); 1417 gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); 1418 1419 if (target_read_code (pc + 1, buf, pattern.len - 1)) 1420 return 0; 1421 1422 for (i = 1; i < pattern.len; i++) 1423 { 1424 if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) 1425 insn_matched = 0; 1426 } 1427 return insn_matched; 1428 } 1429 return 0; 1430 } 1431 1432 /* Search for the instruction at PC in the list INSN_PATTERNS. Return 1433 the first instruction description that matches. Otherwise, return 1434 NULL. */ 1435 1436 static struct i386_insn * 1437 i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) 1438 { 1439 struct i386_insn *pattern; 1440 1441 for (pattern = insn_patterns; pattern->len > 0; pattern++) 1442 { 1443 if (i386_match_pattern (pc, *pattern)) 1444 return pattern; 1445 } 1446 1447 return NULL; 1448 } 1449 1450 /* Return whether PC points inside a sequence of instructions that 1451 matches INSN_PATTERNS. */ 1452 1453 static int 1454 i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) 1455 { 1456 CORE_ADDR current_pc; 1457 int ix, i; 1458 struct i386_insn *insn; 1459 1460 insn = i386_match_insn (pc, insn_patterns); 1461 if (insn == NULL) 1462 return 0; 1463 1464 current_pc = pc; 1465 ix = insn - insn_patterns; 1466 for (i = ix - 1; i >= 0; i--) 1467 { 1468 current_pc -= insn_patterns[i].len; 1469 1470 if (!i386_match_pattern (current_pc, insn_patterns[i])) 1471 return 0; 1472 } 1473 1474 current_pc = pc + insn->len; 1475 for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) 1476 { 1477 if (!i386_match_pattern (current_pc, *insn)) 1478 return 0; 1479 1480 current_pc += insn->len; 1481 } 1482 1483 return 1; 1484 } 1485 1486 /* Some special instructions that might be migrated by GCC into the 1487 part of the prologue that sets up the new stack frame. Because the 1488 stack frame hasn't been setup yet, no registers have been saved 1489 yet, and only the scratch registers %eax, %ecx and %edx can be 1490 touched. */ 1491 1492 struct i386_insn i386_frame_setup_skip_insns[] = 1493 { 1494 /* Check for `movb imm8, r' and `movl imm32, r'. 1495 1496 ??? Should we handle 16-bit operand-sizes here? */ 1497 1498 /* `movb imm8, %al' and `movb imm8, %ah' */ 1499 /* `movb imm8, %cl' and `movb imm8, %ch' */ 1500 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, 1501 /* `movb imm8, %dl' and `movb imm8, %dh' */ 1502 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, 1503 /* `movl imm32, %eax' and `movl imm32, %ecx' */ 1504 { 5, { 0xb8 }, { 0xfe } }, 1505 /* `movl imm32, %edx' */ 1506 { 5, { 0xba }, { 0xff } }, 1507 1508 /* Check for `mov imm32, r32'. Note that there is an alternative 1509 encoding for `mov m32, %eax'. 1510 1511 ??? Should we handle SIB addressing here? 1512 ??? Should we handle 16-bit operand-sizes here? */ 1513 1514 /* `movl m32, %eax' */ 1515 { 5, { 0xa1 }, { 0xff } }, 1516 /* `movl m32, %eax' and `mov; m32, %ecx' */ 1517 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, 1518 /* `movl m32, %edx' */ 1519 { 6, { 0x89, 0x15 }, {0xff, 0xff } }, 1520 1521 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. 1522 Because of the symmetry, there are actually two ways to encode 1523 these instructions; opcode bytes 0x29 and 0x2b for `subl' and 1524 opcode bytes 0x31 and 0x33 for `xorl'. */ 1525 1526 /* `subl %eax, %eax' */ 1527 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, 1528 /* `subl %ecx, %ecx' */ 1529 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, 1530 /* `subl %edx, %edx' */ 1531 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, 1532 /* `xorl %eax, %eax' */ 1533 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, 1534 /* `xorl %ecx, %ecx' */ 1535 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, 1536 /* `xorl %edx, %edx' */ 1537 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, 1538 { 0 } 1539 }; 1540 1541 1542 /* Check whether PC points to a no-op instruction. */ 1543 static CORE_ADDR 1544 i386_skip_noop (CORE_ADDR pc) 1545 { 1546 gdb_byte op; 1547 int check = 1; 1548 1549 if (target_read_code (pc, &op, 1)) 1550 return pc; 1551 1552 while (check) 1553 { 1554 check = 0; 1555 /* Ignore `nop' instruction. */ 1556 if (op == 0x90) 1557 { 1558 pc += 1; 1559 if (target_read_code (pc, &op, 1)) 1560 return pc; 1561 check = 1; 1562 } 1563 /* Ignore no-op instruction `mov %edi, %edi'. 1564 Microsoft system dlls often start with 1565 a `mov %edi,%edi' instruction. 1566 The 5 bytes before the function start are 1567 filled with `nop' instructions. 1568 This pattern can be used for hot-patching: 1569 The `mov %edi, %edi' instruction can be replaced by a 1570 near jump to the location of the 5 `nop' instructions 1571 which can be replaced by a 32-bit jump to anywhere 1572 in the 32-bit address space. */ 1573 1574 else if (op == 0x8b) 1575 { 1576 if (target_read_code (pc + 1, &op, 1)) 1577 return pc; 1578 1579 if (op == 0xff) 1580 { 1581 pc += 2; 1582 if (target_read_code (pc, &op, 1)) 1583 return pc; 1584 1585 check = 1; 1586 } 1587 } 1588 } 1589 return pc; 1590 } 1591 1592 /* Check whether PC points at a code that sets up a new stack frame. 1593 If so, it updates CACHE and returns the address of the first 1594 instruction after the sequence that sets up the frame or LIMIT, 1595 whichever is smaller. If we don't recognize the code, return PC. */ 1596 1597 static CORE_ADDR 1598 i386_analyze_frame_setup (struct gdbarch *gdbarch, 1599 CORE_ADDR pc, CORE_ADDR limit, 1600 struct i386_frame_cache *cache) 1601 { 1602 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1603 struct i386_insn *insn; 1604 gdb_byte op; 1605 int skip = 0; 1606 1607 if (limit <= pc) 1608 return limit; 1609 1610 if (target_read_code (pc, &op, 1)) 1611 return pc; 1612 1613 if (op == 0x55) /* pushl %ebp */ 1614 { 1615 /* Take into account that we've executed the `pushl %ebp' that 1616 starts this instruction sequence. */ 1617 cache->saved_regs[I386_EBP_REGNUM] = 0; 1618 cache->sp_offset += 4; 1619 pc++; 1620 1621 /* If that's all, return now. */ 1622 if (limit <= pc) 1623 return limit; 1624 1625 /* Check for some special instructions that might be migrated by 1626 GCC into the prologue and skip them. At this point in the 1627 prologue, code should only touch the scratch registers %eax, 1628 %ecx and %edx, so while the number of possibilities is sheer, 1629 it is limited. 1630 1631 Make sure we only skip these instructions if we later see the 1632 `movl %esp, %ebp' that actually sets up the frame. */ 1633 while (pc + skip < limit) 1634 { 1635 insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); 1636 if (insn == NULL) 1637 break; 1638 1639 skip += insn->len; 1640 } 1641 1642 /* If that's all, return now. */ 1643 if (limit <= pc + skip) 1644 return limit; 1645 1646 if (target_read_code (pc + skip, &op, 1)) 1647 return pc + skip; 1648 1649 /* The i386 prologue looks like 1650 1651 push %ebp 1652 mov %esp,%ebp 1653 sub $0x10,%esp 1654 1655 and a different prologue can be generated for atom. 1656 1657 push %ebp 1658 lea (%esp),%ebp 1659 lea -0x10(%esp),%esp 1660 1661 We handle both of them here. */ 1662 1663 switch (op) 1664 { 1665 /* Check for `movl %esp, %ebp' -- can be written in two ways. */ 1666 case 0x8b: 1667 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) 1668 != 0xec) 1669 return pc; 1670 pc += (skip + 2); 1671 break; 1672 case 0x89: 1673 if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) 1674 != 0xe5) 1675 return pc; 1676 pc += (skip + 2); 1677 break; 1678 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */ 1679 if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order) 1680 != 0x242c) 1681 return pc; 1682 pc += (skip + 3); 1683 break; 1684 default: 1685 return pc; 1686 } 1687 1688 /* OK, we actually have a frame. We just don't know how large 1689 it is yet. Set its size to zero. We'll adjust it if 1690 necessary. We also now commit to skipping the special 1691 instructions mentioned before. */ 1692 cache->locals = 0; 1693 1694 /* If that's all, return now. */ 1695 if (limit <= pc) 1696 return limit; 1697 1698 /* Check for stack adjustment 1699 1700 subl $XXX, %esp 1701 or 1702 lea -XXX(%esp),%esp 1703 1704 NOTE: You can't subtract a 16-bit immediate from a 32-bit 1705 reg, so we don't have to worry about a data16 prefix. */ 1706 if (target_read_code (pc, &op, 1)) 1707 return pc; 1708 if (op == 0x83) 1709 { 1710 /* `subl' with 8-bit immediate. */ 1711 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) 1712 /* Some instruction starting with 0x83 other than `subl'. */ 1713 return pc; 1714 1715 /* `subl' with signed 8-bit immediate (though it wouldn't 1716 make sense to be negative). */ 1717 cache->locals = read_code_integer (pc + 2, 1, byte_order); 1718 return pc + 3; 1719 } 1720 else if (op == 0x81) 1721 { 1722 /* Maybe it is `subl' with a 32-bit immediate. */ 1723 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) 1724 /* Some instruction starting with 0x81 other than `subl'. */ 1725 return pc; 1726 1727 /* It is `subl' with a 32-bit immediate. */ 1728 cache->locals = read_code_integer (pc + 2, 4, byte_order); 1729 return pc + 6; 1730 } 1731 else if (op == 0x8d) 1732 { 1733 /* The ModR/M byte is 0x64. */ 1734 if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64) 1735 return pc; 1736 /* 'lea' with 8-bit displacement. */ 1737 cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order); 1738 return pc + 4; 1739 } 1740 else 1741 { 1742 /* Some instruction other than `subl' nor 'lea'. */ 1743 return pc; 1744 } 1745 } 1746 else if (op == 0xc8) /* enter */ 1747 { 1748 cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order); 1749 return pc + 4; 1750 } 1751 1752 return pc; 1753 } 1754 1755 /* Check whether PC points at code that saves registers on the stack. 1756 If so, it updates CACHE and returns the address of the first 1757 instruction after the register saves or CURRENT_PC, whichever is 1758 smaller. Otherwise, return PC. */ 1759 1760 static CORE_ADDR 1761 i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, 1762 struct i386_frame_cache *cache) 1763 { 1764 CORE_ADDR offset = 0; 1765 gdb_byte op; 1766 int i; 1767 1768 if (cache->locals > 0) 1769 offset -= cache->locals; 1770 for (i = 0; i < 8 && pc < current_pc; i++) 1771 { 1772 if (target_read_code (pc, &op, 1)) 1773 return pc; 1774 if (op < 0x50 || op > 0x57) 1775 break; 1776 1777 offset -= 4; 1778 cache->saved_regs[op - 0x50] = offset; 1779 cache->sp_offset += 4; 1780 pc++; 1781 } 1782 1783 return pc; 1784 } 1785 1786 /* Do a full analysis of the prologue at PC and update CACHE 1787 accordingly. Bail out early if CURRENT_PC is reached. Return the 1788 address where the analysis stopped. 1789 1790 We handle these cases: 1791 1792 The startup sequence can be at the start of the function, or the 1793 function can start with a branch to startup code at the end. 1794 1795 %ebp can be set up with either the 'enter' instruction, or "pushl 1796 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was 1797 once used in the System V compiler). 1798 1799 Local space is allocated just below the saved %ebp by either the 1800 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a 1801 16-bit unsigned argument for space to allocate, and the 'addl' 1802 instruction could have either a signed byte, or 32-bit immediate. 1803 1804 Next, the registers used by this function are pushed. With the 1805 System V compiler they will always be in the order: %edi, %esi, 1806 %ebx (and sometimes a harmless bug causes it to also save but not 1807 restore %eax); however, the code below is willing to see the pushes 1808 in any order, and will handle up to 8 of them. 1809 1810 If the setup sequence is at the end of the function, then the next 1811 instruction will be a branch back to the start. */ 1812 1813 static CORE_ADDR 1814 i386_analyze_prologue (struct gdbarch *gdbarch, 1815 CORE_ADDR pc, CORE_ADDR current_pc, 1816 struct i386_frame_cache *cache) 1817 { 1818 pc = i386_skip_noop (pc); 1819 pc = i386_follow_jump (gdbarch, pc); 1820 pc = i386_analyze_struct_return (pc, current_pc, cache); 1821 pc = i386_skip_probe (pc); 1822 pc = i386_analyze_stack_align (pc, current_pc, cache); 1823 pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); 1824 return i386_analyze_register_saves (pc, current_pc, cache); 1825 } 1826 1827 /* Return PC of first real instruction. */ 1828 1829 static CORE_ADDR 1830 i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 1831 { 1832 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1833 1834 static gdb_byte pic_pat[6] = 1835 { 1836 0xe8, 0, 0, 0, 0, /* call 0x0 */ 1837 0x5b, /* popl %ebx */ 1838 }; 1839 struct i386_frame_cache cache; 1840 CORE_ADDR pc; 1841 gdb_byte op; 1842 int i; 1843 CORE_ADDR func_addr; 1844 1845 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) 1846 { 1847 CORE_ADDR post_prologue_pc 1848 = skip_prologue_using_sal (gdbarch, func_addr); 1849 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); 1850 1851 /* LLVM backend (Clang/Flang) always emits a line note before the 1852 prologue and another one after. We trust clang to emit usable 1853 line notes. */ 1854 if (post_prologue_pc 1855 && (cust != NULL 1856 && COMPUNIT_PRODUCER (cust) != NULL 1857 && producer_is_llvm (COMPUNIT_PRODUCER (cust)))) 1858 return std::max (start_pc, post_prologue_pc); 1859 } 1860 1861 cache.locals = -1; 1862 pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); 1863 if (cache.locals < 0) 1864 return start_pc; 1865 1866 /* Found valid frame setup. */ 1867 1868 /* The native cc on SVR4 in -K PIC mode inserts the following code 1869 to get the address of the global offset table (GOT) into register 1870 %ebx: 1871 1872 call 0x0 1873 popl %ebx 1874 movl %ebx,x(%ebp) (optional) 1875 addl y,%ebx 1876 1877 This code is with the rest of the prologue (at the end of the 1878 function), so we have to skip it to get to the first real 1879 instruction at the start of the function. */ 1880 1881 for (i = 0; i < 6; i++) 1882 { 1883 if (target_read_code (pc + i, &op, 1)) 1884 return pc; 1885 1886 if (pic_pat[i] != op) 1887 break; 1888 } 1889 if (i == 6) 1890 { 1891 int delta = 6; 1892 1893 if (target_read_code (pc + delta, &op, 1)) 1894 return pc; 1895 1896 if (op == 0x89) /* movl %ebx, x(%ebp) */ 1897 { 1898 op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order); 1899 1900 if (op == 0x5d) /* One byte offset from %ebp. */ 1901 delta += 3; 1902 else if (op == 0x9d) /* Four byte offset from %ebp. */ 1903 delta += 6; 1904 else /* Unexpected instruction. */ 1905 delta = 0; 1906 1907 if (target_read_code (pc + delta, &op, 1)) 1908 return pc; 1909 } 1910 1911 /* addl y,%ebx */ 1912 if (delta > 0 && op == 0x81 1913 && read_code_unsigned_integer (pc + delta + 1, 1, byte_order) 1914 == 0xc3) 1915 { 1916 pc += delta + 6; 1917 } 1918 } 1919 1920 /* If the function starts with a branch (to startup code at the end) 1921 the last instruction should bring us back to the first 1922 instruction of the real code. */ 1923 if (i386_follow_jump (gdbarch, start_pc) != start_pc) 1924 pc = i386_follow_jump (gdbarch, pc); 1925 1926 return pc; 1927 } 1928 1929 /* Check that the code pointed to by PC corresponds to a call to 1930 __main, skip it if so. Return PC otherwise. */ 1931 1932 CORE_ADDR 1933 i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 1934 { 1935 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1936 gdb_byte op; 1937 1938 if (target_read_code (pc, &op, 1)) 1939 return pc; 1940 if (op == 0xe8) 1941 { 1942 gdb_byte buf[4]; 1943 1944 if (target_read_code (pc + 1, buf, sizeof buf) == 0) 1945 { 1946 /* Make sure address is computed correctly as a 32bit 1947 integer even if CORE_ADDR is 64 bit wide. */ 1948 struct bound_minimal_symbol s; 1949 CORE_ADDR call_dest; 1950 1951 call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); 1952 call_dest = call_dest & 0xffffffffU; 1953 s = lookup_minimal_symbol_by_pc (call_dest); 1954 if (s.minsym != NULL 1955 && s.minsym->linkage_name () != NULL 1956 && strcmp (s.minsym->linkage_name (), "__main") == 0) 1957 pc += 5; 1958 } 1959 } 1960 1961 return pc; 1962 } 1963 1964 /* This function is 64-bit safe. */ 1965 1966 static CORE_ADDR 1967 i386_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1968 { 1969 gdb_byte buf[8]; 1970 1971 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); 1972 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); 1973 } 1974 1975 1976 /* Normal frames. */ 1977 1978 static void 1979 i386_frame_cache_1 (struct frame_info *this_frame, 1980 struct i386_frame_cache *cache) 1981 { 1982 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1983 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1984 gdb_byte buf[4]; 1985 int i; 1986 1987 cache->pc = get_frame_func (this_frame); 1988 1989 /* In principle, for normal frames, %ebp holds the frame pointer, 1990 which holds the base address for the current stack frame. 1991 However, for functions that don't need it, the frame pointer is 1992 optional. For these "frameless" functions the frame pointer is 1993 actually the frame pointer of the calling frame. Signal 1994 trampolines are just a special case of a "frameless" function. 1995 They (usually) share their frame pointer with the frame that was 1996 in progress when the signal occurred. */ 1997 1998 get_frame_register (this_frame, I386_EBP_REGNUM, buf); 1999 cache->base = extract_unsigned_integer (buf, 4, byte_order); 2000 if (cache->base == 0) 2001 { 2002 cache->base_p = 1; 2003 return; 2004 } 2005 2006 /* For normal frames, %eip is stored at 4(%ebp). */ 2007 cache->saved_regs[I386_EIP_REGNUM] = 4; 2008 2009 if (cache->pc != 0) 2010 i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), 2011 cache); 2012 2013 if (cache->locals < 0) 2014 { 2015 /* We didn't find a valid frame, which means that CACHE->base 2016 currently holds the frame pointer for our calling frame. If 2017 we're at the start of a function, or somewhere half-way its 2018 prologue, the function's frame probably hasn't been fully 2019 setup yet. Try to reconstruct the base address for the stack 2020 frame by looking at the stack pointer. For truly "frameless" 2021 functions this might work too. */ 2022 2023 if (cache->saved_sp_reg != -1) 2024 { 2025 /* Saved stack pointer has been saved. */ 2026 get_frame_register (this_frame, cache->saved_sp_reg, buf); 2027 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); 2028 2029 /* We're halfway aligning the stack. */ 2030 cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; 2031 cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; 2032 2033 /* This will be added back below. */ 2034 cache->saved_regs[I386_EIP_REGNUM] -= cache->base; 2035 } 2036 else if (cache->pc != 0 2037 || target_read_code (get_frame_pc (this_frame), buf, 1)) 2038 { 2039 /* We're in a known function, but did not find a frame 2040 setup. Assume that the function does not use %ebp. 2041 Alternatively, we may have jumped to an invalid 2042 address; in that case there is definitely no new 2043 frame in %ebp. */ 2044 get_frame_register (this_frame, I386_ESP_REGNUM, buf); 2045 cache->base = extract_unsigned_integer (buf, 4, byte_order) 2046 + cache->sp_offset; 2047 } 2048 else 2049 /* We're in an unknown function. We could not find the start 2050 of the function to analyze the prologue; our best option is 2051 to assume a typical frame layout with the caller's %ebp 2052 saved. */ 2053 cache->saved_regs[I386_EBP_REGNUM] = 0; 2054 } 2055 2056 if (cache->saved_sp_reg != -1) 2057 { 2058 /* Saved stack pointer has been saved (but the SAVED_SP_REG 2059 register may be unavailable). */ 2060 if (cache->saved_sp == 0 2061 && deprecated_frame_register_read (this_frame, 2062 cache->saved_sp_reg, buf)) 2063 cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); 2064 } 2065 /* Now that we have the base address for the stack frame we can 2066 calculate the value of %esp in the calling frame. */ 2067 else if (cache->saved_sp == 0) 2068 cache->saved_sp = cache->base + 8; 2069 2070 /* Adjust all the saved registers such that they contain addresses 2071 instead of offsets. */ 2072 for (i = 0; i < I386_NUM_SAVED_REGS; i++) 2073 if (cache->saved_regs[i] != -1) 2074 cache->saved_regs[i] += cache->base; 2075 2076 cache->base_p = 1; 2077 } 2078 2079 static struct i386_frame_cache * 2080 i386_frame_cache (struct frame_info *this_frame, void **this_cache) 2081 { 2082 struct i386_frame_cache *cache; 2083 2084 if (*this_cache) 2085 return (struct i386_frame_cache *) *this_cache; 2086 2087 cache = i386_alloc_frame_cache (); 2088 *this_cache = cache; 2089 2090 try 2091 { 2092 i386_frame_cache_1 (this_frame, cache); 2093 } 2094 catch (const gdb_exception_error &ex) 2095 { 2096 if (ex.error != NOT_AVAILABLE_ERROR) 2097 throw; 2098 } 2099 2100 return cache; 2101 } 2102 2103 static void 2104 i386_frame_this_id (struct frame_info *this_frame, void **this_cache, 2105 struct frame_id *this_id) 2106 { 2107 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); 2108 2109 if (!cache->base_p) 2110 (*this_id) = frame_id_build_unavailable_stack (cache->pc); 2111 else if (cache->base == 0) 2112 { 2113 /* This marks the outermost frame. */ 2114 } 2115 else 2116 { 2117 /* See the end of i386_push_dummy_call. */ 2118 (*this_id) = frame_id_build (cache->base + 8, cache->pc); 2119 } 2120 } 2121 2122 static enum unwind_stop_reason 2123 i386_frame_unwind_stop_reason (struct frame_info *this_frame, 2124 void **this_cache) 2125 { 2126 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); 2127 2128 if (!cache->base_p) 2129 return UNWIND_UNAVAILABLE; 2130 2131 /* This marks the outermost frame. */ 2132 if (cache->base == 0) 2133 return UNWIND_OUTERMOST; 2134 2135 return UNWIND_NO_REASON; 2136 } 2137 2138 static struct value * 2139 i386_frame_prev_register (struct frame_info *this_frame, void **this_cache, 2140 int regnum) 2141 { 2142 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); 2143 2144 gdb_assert (regnum >= 0); 2145 2146 /* The System V ABI says that: 2147 2148 "The flags register contains the system flags, such as the 2149 direction flag and the carry flag. The direction flag must be 2150 set to the forward (that is, zero) direction before entry and 2151 upon exit from a function. Other user flags have no specified 2152 role in the standard calling sequence and are not preserved." 2153 2154 To guarantee the "upon exit" part of that statement we fake a 2155 saved flags register that has its direction flag cleared. 2156 2157 Note that GCC doesn't seem to rely on the fact that the direction 2158 flag is cleared after a function return; it always explicitly 2159 clears the flag before operations where it matters. 2160 2161 FIXME: kettenis/20030316: I'm not quite sure whether this is the 2162 right thing to do. The way we fake the flags register here makes 2163 it impossible to change it. */ 2164 2165 if (regnum == I386_EFLAGS_REGNUM) 2166 { 2167 ULONGEST val; 2168 2169 val = get_frame_register_unsigned (this_frame, regnum); 2170 val &= ~(1 << 10); 2171 return frame_unwind_got_constant (this_frame, regnum, val); 2172 } 2173 2174 if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) 2175 return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); 2176 2177 if (regnum == I386_ESP_REGNUM 2178 && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) 2179 { 2180 /* If the SP has been saved, but we don't know where, then this 2181 means that SAVED_SP_REG register was found unavailable back 2182 when we built the cache. */ 2183 if (cache->saved_sp == 0) 2184 return frame_unwind_got_register (this_frame, regnum, 2185 cache->saved_sp_reg); 2186 else 2187 return frame_unwind_got_constant (this_frame, regnum, 2188 cache->saved_sp); 2189 } 2190 2191 if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) 2192 return frame_unwind_got_memory (this_frame, regnum, 2193 cache->saved_regs[regnum]); 2194 2195 return frame_unwind_got_register (this_frame, regnum, regnum); 2196 } 2197 2198 static const struct frame_unwind i386_frame_unwind = 2199 { 2200 NORMAL_FRAME, 2201 i386_frame_unwind_stop_reason, 2202 i386_frame_this_id, 2203 i386_frame_prev_register, 2204 NULL, 2205 default_frame_sniffer 2206 }; 2207 2208 /* Normal frames, but in a function epilogue. */ 2209 2210 /* Implement the stack_frame_destroyed_p gdbarch method. 2211 2212 The epilogue is defined here as the 'ret' instruction, which will 2213 follow any instruction such as 'leave' or 'pop %ebp' that destroys 2214 the function's stack frame. */ 2215 2216 static int 2217 i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 2218 { 2219 gdb_byte insn; 2220 struct compunit_symtab *cust; 2221 2222 cust = find_pc_compunit_symtab (pc); 2223 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust)) 2224 return 0; 2225 2226 if (target_read_memory (pc, &insn, 1)) 2227 return 0; /* Can't read memory at pc. */ 2228 2229 if (insn != 0xc3) /* 'ret' instruction. */ 2230 return 0; 2231 2232 return 1; 2233 } 2234 2235 static int 2236 i386_epilogue_frame_sniffer (const struct frame_unwind *self, 2237 struct frame_info *this_frame, 2238 void **this_prologue_cache) 2239 { 2240 if (frame_relative_level (this_frame) == 0) 2241 return i386_stack_frame_destroyed_p (get_frame_arch (this_frame), 2242 get_frame_pc (this_frame)); 2243 else 2244 return 0; 2245 } 2246 2247 static struct i386_frame_cache * 2248 i386_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) 2249 { 2250 struct i386_frame_cache *cache; 2251 CORE_ADDR sp; 2252 2253 if (*this_cache) 2254 return (struct i386_frame_cache *) *this_cache; 2255 2256 cache = i386_alloc_frame_cache (); 2257 *this_cache = cache; 2258 2259 try 2260 { 2261 cache->pc = get_frame_func (this_frame); 2262 2263 /* At this point the stack looks as if we just entered the 2264 function, with the return address at the top of the 2265 stack. */ 2266 sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); 2267 cache->base = sp + cache->sp_offset; 2268 cache->saved_sp = cache->base + 8; 2269 cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; 2270 2271 cache->base_p = 1; 2272 } 2273 catch (const gdb_exception_error &ex) 2274 { 2275 if (ex.error != NOT_AVAILABLE_ERROR) 2276 throw; 2277 } 2278 2279 return cache; 2280 } 2281 2282 static enum unwind_stop_reason 2283 i386_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, 2284 void **this_cache) 2285 { 2286 struct i386_frame_cache *cache = 2287 i386_epilogue_frame_cache (this_frame, this_cache); 2288 2289 if (!cache->base_p) 2290 return UNWIND_UNAVAILABLE; 2291 2292 return UNWIND_NO_REASON; 2293 } 2294 2295 static void 2296 i386_epilogue_frame_this_id (struct frame_info *this_frame, 2297 void **this_cache, 2298 struct frame_id *this_id) 2299 { 2300 struct i386_frame_cache *cache = 2301 i386_epilogue_frame_cache (this_frame, this_cache); 2302 2303 if (!cache->base_p) 2304 (*this_id) = frame_id_build_unavailable_stack (cache->pc); 2305 else 2306 (*this_id) = frame_id_build (cache->base + 8, cache->pc); 2307 } 2308 2309 static struct value * 2310 i386_epilogue_frame_prev_register (struct frame_info *this_frame, 2311 void **this_cache, int regnum) 2312 { 2313 /* Make sure we've initialized the cache. */ 2314 i386_epilogue_frame_cache (this_frame, this_cache); 2315 2316 return i386_frame_prev_register (this_frame, this_cache, regnum); 2317 } 2318 2319 static const struct frame_unwind i386_epilogue_frame_unwind = 2320 { 2321 NORMAL_FRAME, 2322 i386_epilogue_frame_unwind_stop_reason, 2323 i386_epilogue_frame_this_id, 2324 i386_epilogue_frame_prev_register, 2325 NULL, 2326 i386_epilogue_frame_sniffer 2327 }; 2328 2329 2330 /* Stack-based trampolines. */ 2331 2332 /* These trampolines are used on cross x86 targets, when taking the 2333 address of a nested function. When executing these trampolines, 2334 no stack frame is set up, so we are in a similar situation as in 2335 epilogues and i386_epilogue_frame_this_id can be re-used. */ 2336 2337 /* Static chain passed in register. */ 2338 2339 struct i386_insn i386_tramp_chain_in_reg_insns[] = 2340 { 2341 /* `movl imm32, %eax' and `movl imm32, %ecx' */ 2342 { 5, { 0xb8 }, { 0xfe } }, 2343 2344 /* `jmp imm32' */ 2345 { 5, { 0xe9 }, { 0xff } }, 2346 2347 {0} 2348 }; 2349 2350 /* Static chain passed on stack (when regparm=3). */ 2351 2352 struct i386_insn i386_tramp_chain_on_stack_insns[] = 2353 { 2354 /* `push imm32' */ 2355 { 5, { 0x68 }, { 0xff } }, 2356 2357 /* `jmp imm32' */ 2358 { 5, { 0xe9 }, { 0xff } }, 2359 2360 {0} 2361 }; 2362 2363 /* Return whether PC points inside a stack trampoline. */ 2364 2365 static int 2366 i386_in_stack_tramp_p (CORE_ADDR pc) 2367 { 2368 gdb_byte insn; 2369 const char *name; 2370 2371 /* A stack trampoline is detected if no name is associated 2372 to the current pc and if it points inside a trampoline 2373 sequence. */ 2374 2375 find_pc_partial_function (pc, &name, NULL, NULL); 2376 if (name) 2377 return 0; 2378 2379 if (target_read_memory (pc, &insn, 1)) 2380 return 0; 2381 2382 if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) 2383 && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) 2384 return 0; 2385 2386 return 1; 2387 } 2388 2389 static int 2390 i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, 2391 struct frame_info *this_frame, 2392 void **this_cache) 2393 { 2394 if (frame_relative_level (this_frame) == 0) 2395 return i386_in_stack_tramp_p (get_frame_pc (this_frame)); 2396 else 2397 return 0; 2398 } 2399 2400 static const struct frame_unwind i386_stack_tramp_frame_unwind = 2401 { 2402 NORMAL_FRAME, 2403 i386_epilogue_frame_unwind_stop_reason, 2404 i386_epilogue_frame_this_id, 2405 i386_epilogue_frame_prev_register, 2406 NULL, 2407 i386_stack_tramp_frame_sniffer 2408 }; 2409 2410 /* Generate a bytecode expression to get the value of the saved PC. */ 2411 2412 static void 2413 i386_gen_return_address (struct gdbarch *gdbarch, 2414 struct agent_expr *ax, struct axs_value *value, 2415 CORE_ADDR scope) 2416 { 2417 /* The following sequence assumes the traditional use of the base 2418 register. */ 2419 ax_reg (ax, I386_EBP_REGNUM); 2420 ax_const_l (ax, 4); 2421 ax_simple (ax, aop_add); 2422 value->type = register_type (gdbarch, I386_EIP_REGNUM); 2423 value->kind = axs_lvalue_memory; 2424 } 2425 2426 2427 /* Signal trampolines. */ 2428 2429 static struct i386_frame_cache * 2430 i386_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) 2431 { 2432 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2433 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2434 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2435 struct i386_frame_cache *cache; 2436 CORE_ADDR addr; 2437 gdb_byte buf[4]; 2438 2439 if (*this_cache) 2440 return (struct i386_frame_cache *) *this_cache; 2441 2442 cache = i386_alloc_frame_cache (); 2443 2444 try 2445 { 2446 get_frame_register (this_frame, I386_ESP_REGNUM, buf); 2447 cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; 2448 2449 addr = tdep->sigcontext_addr (this_frame); 2450 if (tdep->sc_reg_offset) 2451 { 2452 int i; 2453 2454 gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); 2455 2456 for (i = 0; i < tdep->sc_num_regs; i++) 2457 if (tdep->sc_reg_offset[i] != -1) 2458 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; 2459 } 2460 else 2461 { 2462 cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; 2463 cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; 2464 } 2465 2466 cache->base_p = 1; 2467 } 2468 catch (const gdb_exception_error &ex) 2469 { 2470 if (ex.error != NOT_AVAILABLE_ERROR) 2471 throw; 2472 } 2473 2474 *this_cache = cache; 2475 return cache; 2476 } 2477 2478 static enum unwind_stop_reason 2479 i386_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, 2480 void **this_cache) 2481 { 2482 struct i386_frame_cache *cache = 2483 i386_sigtramp_frame_cache (this_frame, this_cache); 2484 2485 if (!cache->base_p) 2486 return UNWIND_UNAVAILABLE; 2487 2488 return UNWIND_NO_REASON; 2489 } 2490 2491 static void 2492 i386_sigtramp_frame_this_id (struct frame_info *this_frame, void **this_cache, 2493 struct frame_id *this_id) 2494 { 2495 struct i386_frame_cache *cache = 2496 i386_sigtramp_frame_cache (this_frame, this_cache); 2497 2498 if (!cache->base_p) 2499 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); 2500 else 2501 { 2502 /* See the end of i386_push_dummy_call. */ 2503 (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); 2504 } 2505 } 2506 2507 static struct value * 2508 i386_sigtramp_frame_prev_register (struct frame_info *this_frame, 2509 void **this_cache, int regnum) 2510 { 2511 /* Make sure we've initialized the cache. */ 2512 i386_sigtramp_frame_cache (this_frame, this_cache); 2513 2514 return i386_frame_prev_register (this_frame, this_cache, regnum); 2515 } 2516 2517 static int 2518 i386_sigtramp_frame_sniffer (const struct frame_unwind *self, 2519 struct frame_info *this_frame, 2520 void **this_prologue_cache) 2521 { 2522 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); 2523 2524 /* We shouldn't even bother if we don't have a sigcontext_addr 2525 handler. */ 2526 if (tdep->sigcontext_addr == NULL) 2527 return 0; 2528 2529 if (tdep->sigtramp_p != NULL) 2530 { 2531 if (tdep->sigtramp_p (this_frame)) 2532 return 1; 2533 } 2534 2535 if (tdep->sigtramp_start != 0) 2536 { 2537 CORE_ADDR pc = get_frame_pc (this_frame); 2538 2539 gdb_assert (tdep->sigtramp_end != 0); 2540 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) 2541 return 1; 2542 } 2543 2544 return 0; 2545 } 2546 2547 static const struct frame_unwind i386_sigtramp_frame_unwind = 2548 { 2549 SIGTRAMP_FRAME, 2550 i386_sigtramp_frame_unwind_stop_reason, 2551 i386_sigtramp_frame_this_id, 2552 i386_sigtramp_frame_prev_register, 2553 NULL, 2554 i386_sigtramp_frame_sniffer 2555 }; 2556 2557 2558 static CORE_ADDR 2559 i386_frame_base_address (struct frame_info *this_frame, void **this_cache) 2560 { 2561 struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); 2562 2563 return cache->base; 2564 } 2565 2566 static const struct frame_base i386_frame_base = 2567 { 2568 &i386_frame_unwind, 2569 i386_frame_base_address, 2570 i386_frame_base_address, 2571 i386_frame_base_address 2572 }; 2573 2574 static struct frame_id 2575 i386_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 2576 { 2577 CORE_ADDR fp; 2578 2579 fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); 2580 2581 /* See the end of i386_push_dummy_call. */ 2582 return frame_id_build (fp + 8, get_frame_pc (this_frame)); 2583 } 2584 2585 /* _Decimal128 function return values need 16-byte alignment on the 2586 stack. */ 2587 2588 static CORE_ADDR 2589 i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 2590 { 2591 return sp & -(CORE_ADDR)16; 2592 } 2593 2594 2595 /* Figure out where the longjmp will land. Slurp the args out of the 2596 stack. We expect the first arg to be a pointer to the jmp_buf 2597 structure from which we extract the address that we will land at. 2598 This address is copied into PC. This routine returns non-zero on 2599 success. */ 2600 2601 static int 2602 i386_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 2603 { 2604 gdb_byte buf[4]; 2605 CORE_ADDR sp, jb_addr; 2606 struct gdbarch *gdbarch = get_frame_arch (frame); 2607 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2608 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; 2609 2610 /* If JB_PC_OFFSET is -1, we have no way to find out where the 2611 longjmp will land. */ 2612 if (jb_pc_offset == -1) 2613 return 0; 2614 2615 get_frame_register (frame, I386_ESP_REGNUM, buf); 2616 sp = extract_unsigned_integer (buf, 4, byte_order); 2617 if (target_read_memory (sp + 4, buf, 4)) 2618 return 0; 2619 2620 jb_addr = extract_unsigned_integer (buf, 4, byte_order); 2621 if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) 2622 return 0; 2623 2624 *pc = extract_unsigned_integer (buf, 4, byte_order); 2625 return 1; 2626 } 2627 2628 2629 /* Check whether TYPE must be 16-byte-aligned when passed as a 2630 function argument. 16-byte vectors, _Decimal128 and structures or 2631 unions containing such types must be 16-byte-aligned; other 2632 arguments are 4-byte-aligned. */ 2633 2634 static int 2635 i386_16_byte_align_p (struct type *type) 2636 { 2637 type = check_typedef (type); 2638 if ((type->code () == TYPE_CODE_DECFLOAT 2639 || (type->code () == TYPE_CODE_ARRAY && TYPE_VECTOR (type))) 2640 && TYPE_LENGTH (type) == 16) 2641 return 1; 2642 if (type->code () == TYPE_CODE_ARRAY) 2643 return i386_16_byte_align_p (TYPE_TARGET_TYPE (type)); 2644 if (type->code () == TYPE_CODE_STRUCT 2645 || type->code () == TYPE_CODE_UNION) 2646 { 2647 int i; 2648 for (i = 0; i < type->num_fields (); i++) 2649 { 2650 if (i386_16_byte_align_p (type->field (i).type ())) 2651 return 1; 2652 } 2653 } 2654 return 0; 2655 } 2656 2657 /* Implementation for set_gdbarch_push_dummy_code. */ 2658 2659 static CORE_ADDR 2660 i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, 2661 struct value **args, int nargs, struct type *value_type, 2662 CORE_ADDR *real_pc, CORE_ADDR *bp_addr, 2663 struct regcache *regcache) 2664 { 2665 /* Use 0xcc breakpoint - 1 byte. */ 2666 *bp_addr = sp - 1; 2667 *real_pc = funaddr; 2668 2669 /* Keep the stack aligned. */ 2670 return sp - 16; 2671 } 2672 2673 /* The "push_dummy_call" gdbarch method, optionally with the thiscall 2674 calling convention. */ 2675 2676 CORE_ADDR 2677 i386_thiscall_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 2678 struct regcache *regcache, CORE_ADDR bp_addr, 2679 int nargs, struct value **args, CORE_ADDR sp, 2680 function_call_return_method return_method, 2681 CORE_ADDR struct_addr, bool thiscall) 2682 { 2683 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2684 gdb_byte buf[4]; 2685 int i; 2686 int write_pass; 2687 int args_space = 0; 2688 2689 /* BND registers can be in arbitrary values at the moment of the 2690 inferior call. This can cause boundary violations that are not 2691 due to a real bug or even desired by the user. The best to be done 2692 is set the BND registers to allow access to the whole memory, INIT 2693 state, before pushing the inferior call. */ 2694 i387_reset_bnd_regs (gdbarch, regcache); 2695 2696 /* Determine the total space required for arguments and struct 2697 return address in a first pass (allowing for 16-byte-aligned 2698 arguments), then push arguments in a second pass. */ 2699 2700 for (write_pass = 0; write_pass < 2; write_pass++) 2701 { 2702 int args_space_used = 0; 2703 2704 if (return_method == return_method_struct) 2705 { 2706 if (write_pass) 2707 { 2708 /* Push value address. */ 2709 store_unsigned_integer (buf, 4, byte_order, struct_addr); 2710 write_memory (sp, buf, 4); 2711 args_space_used += 4; 2712 } 2713 else 2714 args_space += 4; 2715 } 2716 2717 for (i = thiscall ? 1 : 0; i < nargs; i++) 2718 { 2719 int len = TYPE_LENGTH (value_enclosing_type (args[i])); 2720 2721 if (write_pass) 2722 { 2723 if (i386_16_byte_align_p (value_enclosing_type (args[i]))) 2724 args_space_used = align_up (args_space_used, 16); 2725 2726 write_memory (sp + args_space_used, 2727 value_contents_all (args[i]), len); 2728 /* The System V ABI says that: 2729 2730 "An argument's size is increased, if necessary, to make it a 2731 multiple of [32-bit] words. This may require tail padding, 2732 depending on the size of the argument." 2733 2734 This makes sure the stack stays word-aligned. */ 2735 args_space_used += align_up (len, 4); 2736 } 2737 else 2738 { 2739 if (i386_16_byte_align_p (value_enclosing_type (args[i]))) 2740 args_space = align_up (args_space, 16); 2741 args_space += align_up (len, 4); 2742 } 2743 } 2744 2745 if (!write_pass) 2746 { 2747 sp -= args_space; 2748 2749 /* The original System V ABI only requires word alignment, 2750 but modern incarnations need 16-byte alignment in order 2751 to support SSE. Since wasting a few bytes here isn't 2752 harmful we unconditionally enforce 16-byte alignment. */ 2753 sp &= ~0xf; 2754 } 2755 } 2756 2757 /* Store return address. */ 2758 sp -= 4; 2759 store_unsigned_integer (buf, 4, byte_order, bp_addr); 2760 write_memory (sp, buf, 4); 2761 2762 /* Finally, update the stack pointer... */ 2763 store_unsigned_integer (buf, 4, byte_order, sp); 2764 regcache->cooked_write (I386_ESP_REGNUM, buf); 2765 2766 /* ...and fake a frame pointer. */ 2767 regcache->cooked_write (I386_EBP_REGNUM, buf); 2768 2769 /* The 'this' pointer needs to be in ECX. */ 2770 if (thiscall) 2771 regcache->cooked_write (I386_ECX_REGNUM, value_contents_all (args[0])); 2772 2773 /* MarkK wrote: This "+ 8" is all over the place: 2774 (i386_frame_this_id, i386_sigtramp_frame_this_id, 2775 i386_dummy_id). It's there, since all frame unwinders for 2776 a given target have to agree (within a certain margin) on the 2777 definition of the stack address of a frame. Otherwise frame id 2778 comparison might not work correctly. Since DWARF2/GCC uses the 2779 stack address *before* the function call as a frame's CFA. On 2780 the i386, when %ebp is used as a frame pointer, the offset 2781 between the contents %ebp and the CFA as defined by GCC. */ 2782 return sp + 8; 2783 } 2784 2785 /* Implement the "push_dummy_call" gdbarch method. */ 2786 2787 static CORE_ADDR 2788 i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 2789 struct regcache *regcache, CORE_ADDR bp_addr, int nargs, 2790 struct value **args, CORE_ADDR sp, 2791 function_call_return_method return_method, 2792 CORE_ADDR struct_addr) 2793 { 2794 return i386_thiscall_push_dummy_call (gdbarch, function, regcache, bp_addr, 2795 nargs, args, sp, return_method, 2796 struct_addr, false); 2797 } 2798 2799 /* These registers are used for returning integers (and on some 2800 targets also for returning `struct' and `union' values when their 2801 size and alignment match an integer type). */ 2802 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ 2803 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ 2804 2805 /* Read, for architecture GDBARCH, a function return value of TYPE 2806 from REGCACHE, and copy that into VALBUF. */ 2807 2808 static void 2809 i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, 2810 struct regcache *regcache, gdb_byte *valbuf) 2811 { 2812 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2813 int len = TYPE_LENGTH (type); 2814 gdb_byte buf[I386_MAX_REGISTER_SIZE]; 2815 2816 if (type->code () == TYPE_CODE_FLT) 2817 { 2818 if (tdep->st0_regnum < 0) 2819 { 2820 warning (_("Cannot find floating-point return value.")); 2821 memset (valbuf, 0, len); 2822 return; 2823 } 2824 2825 /* Floating-point return values can be found in %st(0). Convert 2826 its contents to the desired type. This is probably not 2827 exactly how it would happen on the target itself, but it is 2828 the best we can do. */ 2829 regcache->raw_read (I386_ST0_REGNUM, buf); 2830 target_float_convert (buf, i387_ext_type (gdbarch), valbuf, type); 2831 } 2832 else 2833 { 2834 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); 2835 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); 2836 2837 if (len <= low_size) 2838 { 2839 regcache->raw_read (LOW_RETURN_REGNUM, buf); 2840 memcpy (valbuf, buf, len); 2841 } 2842 else if (len <= (low_size + high_size)) 2843 { 2844 regcache->raw_read (LOW_RETURN_REGNUM, buf); 2845 memcpy (valbuf, buf, low_size); 2846 regcache->raw_read (HIGH_RETURN_REGNUM, buf); 2847 memcpy (valbuf + low_size, buf, len - low_size); 2848 } 2849 else 2850 internal_error (__FILE__, __LINE__, 2851 _("Cannot extract return value of %d bytes long."), 2852 len); 2853 } 2854 } 2855 2856 /* Write, for architecture GDBARCH, a function return value of TYPE 2857 from VALBUF into REGCACHE. */ 2858 2859 static void 2860 i386_store_return_value (struct gdbarch *gdbarch, struct type *type, 2861 struct regcache *regcache, const gdb_byte *valbuf) 2862 { 2863 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2864 int len = TYPE_LENGTH (type); 2865 2866 if (type->code () == TYPE_CODE_FLT) 2867 { 2868 ULONGEST fstat; 2869 gdb_byte buf[I386_MAX_REGISTER_SIZE]; 2870 2871 if (tdep->st0_regnum < 0) 2872 { 2873 warning (_("Cannot set floating-point return value.")); 2874 return; 2875 } 2876 2877 /* Returning floating-point values is a bit tricky. Apart from 2878 storing the return value in %st(0), we have to simulate the 2879 state of the FPU at function return point. */ 2880 2881 /* Convert the value found in VALBUF to the extended 2882 floating-point format used by the FPU. This is probably 2883 not exactly how it would happen on the target itself, but 2884 it is the best we can do. */ 2885 target_float_convert (valbuf, type, buf, i387_ext_type (gdbarch)); 2886 regcache->raw_write (I386_ST0_REGNUM, buf); 2887 2888 /* Set the top of the floating-point register stack to 7. The 2889 actual value doesn't really matter, but 7 is what a normal 2890 function return would end up with if the program started out 2891 with a freshly initialized FPU. */ 2892 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); 2893 fstat |= (7 << 11); 2894 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); 2895 2896 /* Mark %st(1) through %st(7) as empty. Since we set the top of 2897 the floating-point register stack to 7, the appropriate value 2898 for the tag word is 0x3fff. */ 2899 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); 2900 } 2901 else 2902 { 2903 int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); 2904 int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); 2905 2906 if (len <= low_size) 2907 regcache->raw_write_part (LOW_RETURN_REGNUM, 0, len, valbuf); 2908 else if (len <= (low_size + high_size)) 2909 { 2910 regcache->raw_write (LOW_RETURN_REGNUM, valbuf); 2911 regcache->raw_write_part (HIGH_RETURN_REGNUM, 0, len - low_size, 2912 valbuf + low_size); 2913 } 2914 else 2915 internal_error (__FILE__, __LINE__, 2916 _("Cannot store return value of %d bytes long."), len); 2917 } 2918 } 2919 2920 2921 /* This is the variable that is set with "set struct-convention", and 2922 its legitimate values. */ 2923 static const char default_struct_convention[] = "default"; 2924 static const char pcc_struct_convention[] = "pcc"; 2925 static const char reg_struct_convention[] = "reg"; 2926 static const char *const valid_conventions[] = 2927 { 2928 default_struct_convention, 2929 pcc_struct_convention, 2930 reg_struct_convention, 2931 NULL 2932 }; 2933 static const char *struct_convention = default_struct_convention; 2934 2935 /* Return non-zero if TYPE, which is assumed to be a structure, 2936 a union type, or an array type, should be returned in registers 2937 for architecture GDBARCH. */ 2938 2939 static int 2940 i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) 2941 { 2942 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2943 enum type_code code = type->code (); 2944 int len = TYPE_LENGTH (type); 2945 2946 gdb_assert (code == TYPE_CODE_STRUCT 2947 || code == TYPE_CODE_UNION 2948 || code == TYPE_CODE_ARRAY); 2949 2950 if (struct_convention == pcc_struct_convention 2951 || (struct_convention == default_struct_convention 2952 && tdep->struct_return == pcc_struct_return)) 2953 return 0; 2954 2955 /* Structures consisting of a single `float', `double' or 'long 2956 double' member are returned in %st(0). */ 2957 if (code == TYPE_CODE_STRUCT && type->num_fields () == 1) 2958 { 2959 type = check_typedef (type->field (0).type ()); 2960 if (type->code () == TYPE_CODE_FLT) 2961 return (len == 4 || len == 8 || len == 12); 2962 } 2963 2964 return (len == 1 || len == 2 || len == 4 || len == 8); 2965 } 2966 2967 /* Determine, for architecture GDBARCH, how a return value of TYPE 2968 should be returned. If it is supposed to be returned in registers, 2969 and READBUF is non-zero, read the appropriate value from REGCACHE, 2970 and copy it into READBUF. If WRITEBUF is non-zero, write the value 2971 from WRITEBUF into REGCACHE. */ 2972 2973 static enum return_value_convention 2974 i386_return_value (struct gdbarch *gdbarch, struct value *function, 2975 struct type *type, struct regcache *regcache, 2976 gdb_byte *readbuf, const gdb_byte *writebuf) 2977 { 2978 enum type_code code = type->code (); 2979 2980 if (((code == TYPE_CODE_STRUCT 2981 || code == TYPE_CODE_UNION 2982 || code == TYPE_CODE_ARRAY) 2983 && !i386_reg_struct_return_p (gdbarch, type)) 2984 /* Complex double and long double uses the struct return convention. */ 2985 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 16) 2986 || (code == TYPE_CODE_COMPLEX && TYPE_LENGTH (type) == 24) 2987 /* 128-bit decimal float uses the struct return convention. */ 2988 || (code == TYPE_CODE_DECFLOAT && TYPE_LENGTH (type) == 16)) 2989 { 2990 /* The System V ABI says that: 2991 2992 "A function that returns a structure or union also sets %eax 2993 to the value of the original address of the caller's area 2994 before it returns. Thus when the caller receives control 2995 again, the address of the returned object resides in register 2996 %eax and can be used to access the object." 2997 2998 So the ABI guarantees that we can always find the return 2999 value just after the function has returned. */ 3000 3001 /* Note that the ABI doesn't mention functions returning arrays, 3002 which is something possible in certain languages such as Ada. 3003 In this case, the value is returned as if it was wrapped in 3004 a record, so the convention applied to records also applies 3005 to arrays. */ 3006 3007 if (readbuf) 3008 { 3009 ULONGEST addr; 3010 3011 regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); 3012 read_memory (addr, readbuf, TYPE_LENGTH (type)); 3013 } 3014 3015 return RETURN_VALUE_ABI_RETURNS_ADDRESS; 3016 } 3017 3018 /* This special case is for structures consisting of a single 3019 `float', `double' or 'long double' member. These structures are 3020 returned in %st(0). For these structures, we call ourselves 3021 recursively, changing TYPE into the type of the first member of 3022 the structure. Since that should work for all structures that 3023 have only one member, we don't bother to check the member's type 3024 here. */ 3025 if (code == TYPE_CODE_STRUCT && type->num_fields () == 1) 3026 { 3027 type = check_typedef (type->field (0).type ()); 3028 return i386_return_value (gdbarch, function, type, regcache, 3029 readbuf, writebuf); 3030 } 3031 3032 if (readbuf) 3033 i386_extract_return_value (gdbarch, type, regcache, readbuf); 3034 if (writebuf) 3035 i386_store_return_value (gdbarch, type, regcache, writebuf); 3036 3037 return RETURN_VALUE_REGISTER_CONVENTION; 3038 } 3039 3040 3041 struct type * 3042 i387_ext_type (struct gdbarch *gdbarch) 3043 { 3044 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3045 3046 if (!tdep->i387_ext_type) 3047 { 3048 tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); 3049 gdb_assert (tdep->i387_ext_type != NULL); 3050 } 3051 3052 return tdep->i387_ext_type; 3053 } 3054 3055 /* Construct type for pseudo BND registers. We can't use 3056 tdesc_find_type since a complement of one value has to be used 3057 to describe the upper bound. */ 3058 3059 static struct type * 3060 i386_bnd_type (struct gdbarch *gdbarch) 3061 { 3062 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3063 3064 3065 if (!tdep->i386_bnd_type) 3066 { 3067 struct type *t; 3068 const struct builtin_type *bt = builtin_type (gdbarch); 3069 3070 /* The type we're building is described bellow: */ 3071 #if 0 3072 struct __bound128 3073 { 3074 void *lbound; 3075 void *ubound; /* One complement of raw ubound field. */ 3076 }; 3077 #endif 3078 3079 t = arch_composite_type (gdbarch, 3080 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT); 3081 3082 append_composite_type_field (t, "lbound", bt->builtin_data_ptr); 3083 append_composite_type_field (t, "ubound", bt->builtin_data_ptr); 3084 3085 t->set_name ("builtin_type_bound128"); 3086 tdep->i386_bnd_type = t; 3087 } 3088 3089 return tdep->i386_bnd_type; 3090 } 3091 3092 /* Construct vector type for pseudo ZMM registers. We can't use 3093 tdesc_find_type since ZMM isn't described in target description. */ 3094 3095 static struct type * 3096 i386_zmm_type (struct gdbarch *gdbarch) 3097 { 3098 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3099 3100 if (!tdep->i386_zmm_type) 3101 { 3102 const struct builtin_type *bt = builtin_type (gdbarch); 3103 3104 /* The type we're building is this: */ 3105 #if 0 3106 union __gdb_builtin_type_vec512i 3107 { 3108 int128_t v4_int128[4]; 3109 int64_t v8_int64[8]; 3110 int32_t v16_int32[16]; 3111 int16_t v32_int16[32]; 3112 int8_t v64_int8[64]; 3113 double v8_double[8]; 3114 float v16_float[16]; 3115 bfloat16_t v32_bfloat16[32]; 3116 }; 3117 #endif 3118 3119 struct type *t; 3120 3121 t = arch_composite_type (gdbarch, 3122 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION); 3123 append_composite_type_field (t, "v32_bfloat16", 3124 init_vector_type (bt->builtin_bfloat16, 32)); 3125 append_composite_type_field (t, "v16_float", 3126 init_vector_type (bt->builtin_float, 16)); 3127 append_composite_type_field (t, "v8_double", 3128 init_vector_type (bt->builtin_double, 8)); 3129 append_composite_type_field (t, "v64_int8", 3130 init_vector_type (bt->builtin_int8, 64)); 3131 append_composite_type_field (t, "v32_int16", 3132 init_vector_type (bt->builtin_int16, 32)); 3133 append_composite_type_field (t, "v16_int32", 3134 init_vector_type (bt->builtin_int32, 16)); 3135 append_composite_type_field (t, "v8_int64", 3136 init_vector_type (bt->builtin_int64, 8)); 3137 append_composite_type_field (t, "v4_int128", 3138 init_vector_type (bt->builtin_int128, 4)); 3139 3140 TYPE_VECTOR (t) = 1; 3141 t->set_name ("builtin_type_vec512i"); 3142 tdep->i386_zmm_type = t; 3143 } 3144 3145 return tdep->i386_zmm_type; 3146 } 3147 3148 /* Construct vector type for pseudo YMM registers. We can't use 3149 tdesc_find_type since YMM isn't described in target description. */ 3150 3151 static struct type * 3152 i386_ymm_type (struct gdbarch *gdbarch) 3153 { 3154 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3155 3156 if (!tdep->i386_ymm_type) 3157 { 3158 const struct builtin_type *bt = builtin_type (gdbarch); 3159 3160 /* The type we're building is this: */ 3161 #if 0 3162 union __gdb_builtin_type_vec256i 3163 { 3164 int128_t v2_int128[2]; 3165 int64_t v4_int64[4]; 3166 int32_t v8_int32[8]; 3167 int16_t v16_int16[16]; 3168 int8_t v32_int8[32]; 3169 double v4_double[4]; 3170 float v8_float[8]; 3171 bfloat16_t v16_bfloat16[16]; 3172 }; 3173 #endif 3174 3175 struct type *t; 3176 3177 t = arch_composite_type (gdbarch, 3178 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); 3179 append_composite_type_field (t, "v16_bfloat16", 3180 init_vector_type (bt->builtin_bfloat16, 16)); 3181 append_composite_type_field (t, "v8_float", 3182 init_vector_type (bt->builtin_float, 8)); 3183 append_composite_type_field (t, "v4_double", 3184 init_vector_type (bt->builtin_double, 4)); 3185 append_composite_type_field (t, "v32_int8", 3186 init_vector_type (bt->builtin_int8, 32)); 3187 append_composite_type_field (t, "v16_int16", 3188 init_vector_type (bt->builtin_int16, 16)); 3189 append_composite_type_field (t, "v8_int32", 3190 init_vector_type (bt->builtin_int32, 8)); 3191 append_composite_type_field (t, "v4_int64", 3192 init_vector_type (bt->builtin_int64, 4)); 3193 append_composite_type_field (t, "v2_int128", 3194 init_vector_type (bt->builtin_int128, 2)); 3195 3196 TYPE_VECTOR (t) = 1; 3197 t->set_name ("builtin_type_vec256i"); 3198 tdep->i386_ymm_type = t; 3199 } 3200 3201 return tdep->i386_ymm_type; 3202 } 3203 3204 /* Construct vector type for MMX registers. */ 3205 static struct type * 3206 i386_mmx_type (struct gdbarch *gdbarch) 3207 { 3208 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3209 3210 if (!tdep->i386_mmx_type) 3211 { 3212 const struct builtin_type *bt = builtin_type (gdbarch); 3213 3214 /* The type we're building is this: */ 3215 #if 0 3216 union __gdb_builtin_type_vec64i 3217 { 3218 int64_t uint64; 3219 int32_t v2_int32[2]; 3220 int16_t v4_int16[4]; 3221 int8_t v8_int8[8]; 3222 }; 3223 #endif 3224 3225 struct type *t; 3226 3227 t = arch_composite_type (gdbarch, 3228 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); 3229 3230 append_composite_type_field (t, "uint64", bt->builtin_int64); 3231 append_composite_type_field (t, "v2_int32", 3232 init_vector_type (bt->builtin_int32, 2)); 3233 append_composite_type_field (t, "v4_int16", 3234 init_vector_type (bt->builtin_int16, 4)); 3235 append_composite_type_field (t, "v8_int8", 3236 init_vector_type (bt->builtin_int8, 8)); 3237 3238 TYPE_VECTOR (t) = 1; 3239 t->set_name ("builtin_type_vec64i"); 3240 tdep->i386_mmx_type = t; 3241 } 3242 3243 return tdep->i386_mmx_type; 3244 } 3245 3246 /* Return the GDB type object for the "standard" data type of data in 3247 register REGNUM. */ 3248 3249 struct type * 3250 i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) 3251 { 3252 if (i386_bnd_regnum_p (gdbarch, regnum)) 3253 return i386_bnd_type (gdbarch); 3254 if (i386_mmx_regnum_p (gdbarch, regnum)) 3255 return i386_mmx_type (gdbarch); 3256 else if (i386_ymm_regnum_p (gdbarch, regnum)) 3257 return i386_ymm_type (gdbarch); 3258 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) 3259 return i386_ymm_type (gdbarch); 3260 else if (i386_zmm_regnum_p (gdbarch, regnum)) 3261 return i386_zmm_type (gdbarch); 3262 else 3263 { 3264 const struct builtin_type *bt = builtin_type (gdbarch); 3265 if (i386_byte_regnum_p (gdbarch, regnum)) 3266 return bt->builtin_int8; 3267 else if (i386_word_regnum_p (gdbarch, regnum)) 3268 return bt->builtin_int16; 3269 else if (i386_dword_regnum_p (gdbarch, regnum)) 3270 return bt->builtin_int32; 3271 else if (i386_k_regnum_p (gdbarch, regnum)) 3272 return bt->builtin_int64; 3273 } 3274 3275 internal_error (__FILE__, __LINE__, _("invalid regnum")); 3276 } 3277 3278 /* Map a cooked register onto a raw register or memory. For the i386, 3279 the MMX registers need to be mapped onto floating point registers. */ 3280 3281 static int 3282 i386_mmx_regnum_to_fp_regnum (readable_regcache *regcache, int regnum) 3283 { 3284 struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); 3285 int mmxreg, fpreg; 3286 ULONGEST fstat; 3287 int tos; 3288 3289 mmxreg = regnum - tdep->mm0_regnum; 3290 regcache->raw_read (I387_FSTAT_REGNUM (tdep), &fstat); 3291 tos = (fstat >> 11) & 0x7; 3292 fpreg = (mmxreg + tos) % 8; 3293 3294 return (I387_ST0_REGNUM (tdep) + fpreg); 3295 } 3296 3297 /* A helper function for us by i386_pseudo_register_read_value and 3298 amd64_pseudo_register_read_value. It does all the work but reads 3299 the data into an already-allocated value. */ 3300 3301 void 3302 i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, 3303 readable_regcache *regcache, 3304 int regnum, 3305 struct value *result_value) 3306 { 3307 gdb_byte raw_buf[I386_MAX_REGISTER_SIZE]; 3308 enum register_status status; 3309 gdb_byte *buf = value_contents_raw (result_value); 3310 3311 if (i386_mmx_regnum_p (gdbarch, regnum)) 3312 { 3313 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); 3314 3315 /* Extract (always little endian). */ 3316 status = regcache->raw_read (fpnum, raw_buf); 3317 if (status != REG_VALID) 3318 mark_value_bytes_unavailable (result_value, 0, 3319 TYPE_LENGTH (value_type (result_value))); 3320 else 3321 memcpy (buf, raw_buf, register_size (gdbarch, regnum)); 3322 } 3323 else 3324 { 3325 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3326 if (i386_bnd_regnum_p (gdbarch, regnum)) 3327 { 3328 regnum -= tdep->bnd0_regnum; 3329 3330 /* Extract (always little endian). Read lower 128bits. */ 3331 status = regcache->raw_read (I387_BND0R_REGNUM (tdep) + regnum, 3332 raw_buf); 3333 if (status != REG_VALID) 3334 mark_value_bytes_unavailable (result_value, 0, 16); 3335 else 3336 { 3337 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); 3338 LONGEST upper, lower; 3339 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); 3340 3341 lower = extract_unsigned_integer (raw_buf, 8, byte_order); 3342 upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order); 3343 upper = ~upper; 3344 3345 memcpy (buf, &lower, size); 3346 memcpy (buf + size, &upper, size); 3347 } 3348 } 3349 else if (i386_k_regnum_p (gdbarch, regnum)) 3350 { 3351 regnum -= tdep->k0_regnum; 3352 3353 /* Extract (always little endian). */ 3354 status = regcache->raw_read (tdep->k0_regnum + regnum, raw_buf); 3355 if (status != REG_VALID) 3356 mark_value_bytes_unavailable (result_value, 0, 8); 3357 else 3358 memcpy (buf, raw_buf, 8); 3359 } 3360 else if (i386_zmm_regnum_p (gdbarch, regnum)) 3361 { 3362 regnum -= tdep->zmm0_regnum; 3363 3364 if (regnum < num_lower_zmm_regs) 3365 { 3366 /* Extract (always little endian). Read lower 128bits. */ 3367 status = regcache->raw_read (I387_XMM0_REGNUM (tdep) + regnum, 3368 raw_buf); 3369 if (status != REG_VALID) 3370 mark_value_bytes_unavailable (result_value, 0, 16); 3371 else 3372 memcpy (buf, raw_buf, 16); 3373 3374 /* Extract (always little endian). Read upper 128bits. */ 3375 status = regcache->raw_read (tdep->ymm0h_regnum + regnum, 3376 raw_buf); 3377 if (status != REG_VALID) 3378 mark_value_bytes_unavailable (result_value, 16, 16); 3379 else 3380 memcpy (buf + 16, raw_buf, 16); 3381 } 3382 else 3383 { 3384 /* Extract (always little endian). Read lower 128bits. */ 3385 status = regcache->raw_read (I387_XMM16_REGNUM (tdep) + regnum 3386 - num_lower_zmm_regs, 3387 raw_buf); 3388 if (status != REG_VALID) 3389 mark_value_bytes_unavailable (result_value, 0, 16); 3390 else 3391 memcpy (buf, raw_buf, 16); 3392 3393 /* Extract (always little endian). Read upper 128bits. */ 3394 status = regcache->raw_read (I387_YMM16H_REGNUM (tdep) + regnum 3395 - num_lower_zmm_regs, 3396 raw_buf); 3397 if (status != REG_VALID) 3398 mark_value_bytes_unavailable (result_value, 16, 16); 3399 else 3400 memcpy (buf + 16, raw_buf, 16); 3401 } 3402 3403 /* Read upper 256bits. */ 3404 status = regcache->raw_read (tdep->zmm0h_regnum + regnum, 3405 raw_buf); 3406 if (status != REG_VALID) 3407 mark_value_bytes_unavailable (result_value, 32, 32); 3408 else 3409 memcpy (buf + 32, raw_buf, 32); 3410 } 3411 else if (i386_ymm_regnum_p (gdbarch, regnum)) 3412 { 3413 regnum -= tdep->ymm0_regnum; 3414 3415 /* Extract (always little endian). Read lower 128bits. */ 3416 status = regcache->raw_read (I387_XMM0_REGNUM (tdep) + regnum, 3417 raw_buf); 3418 if (status != REG_VALID) 3419 mark_value_bytes_unavailable (result_value, 0, 16); 3420 else 3421 memcpy (buf, raw_buf, 16); 3422 /* Read upper 128bits. */ 3423 status = regcache->raw_read (tdep->ymm0h_regnum + regnum, 3424 raw_buf); 3425 if (status != REG_VALID) 3426 mark_value_bytes_unavailable (result_value, 16, 32); 3427 else 3428 memcpy (buf + 16, raw_buf, 16); 3429 } 3430 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) 3431 { 3432 regnum -= tdep->ymm16_regnum; 3433 /* Extract (always little endian). Read lower 128bits. */ 3434 status = regcache->raw_read (I387_XMM16_REGNUM (tdep) + regnum, 3435 raw_buf); 3436 if (status != REG_VALID) 3437 mark_value_bytes_unavailable (result_value, 0, 16); 3438 else 3439 memcpy (buf, raw_buf, 16); 3440 /* Read upper 128bits. */ 3441 status = regcache->raw_read (tdep->ymm16h_regnum + regnum, 3442 raw_buf); 3443 if (status != REG_VALID) 3444 mark_value_bytes_unavailable (result_value, 16, 16); 3445 else 3446 memcpy (buf + 16, raw_buf, 16); 3447 } 3448 else if (i386_word_regnum_p (gdbarch, regnum)) 3449 { 3450 int gpnum = regnum - tdep->ax_regnum; 3451 3452 /* Extract (always little endian). */ 3453 status = regcache->raw_read (gpnum, raw_buf); 3454 if (status != REG_VALID) 3455 mark_value_bytes_unavailable (result_value, 0, 3456 TYPE_LENGTH (value_type (result_value))); 3457 else 3458 memcpy (buf, raw_buf, 2); 3459 } 3460 else if (i386_byte_regnum_p (gdbarch, regnum)) 3461 { 3462 int gpnum = regnum - tdep->al_regnum; 3463 3464 /* Extract (always little endian). We read both lower and 3465 upper registers. */ 3466 status = regcache->raw_read (gpnum % 4, raw_buf); 3467 if (status != REG_VALID) 3468 mark_value_bytes_unavailable (result_value, 0, 3469 TYPE_LENGTH (value_type (result_value))); 3470 else if (gpnum >= 4) 3471 memcpy (buf, raw_buf + 1, 1); 3472 else 3473 memcpy (buf, raw_buf, 1); 3474 } 3475 else 3476 internal_error (__FILE__, __LINE__, _("invalid regnum")); 3477 } 3478 } 3479 3480 static struct value * 3481 i386_pseudo_register_read_value (struct gdbarch *gdbarch, 3482 readable_regcache *regcache, 3483 int regnum) 3484 { 3485 struct value *result; 3486 3487 result = allocate_value (register_type (gdbarch, regnum)); 3488 VALUE_LVAL (result) = lval_register; 3489 VALUE_REGNUM (result) = regnum; 3490 3491 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); 3492 3493 return result; 3494 } 3495 3496 void 3497 i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 3498 int regnum, const gdb_byte *buf) 3499 { 3500 gdb_byte raw_buf[I386_MAX_REGISTER_SIZE]; 3501 3502 if (i386_mmx_regnum_p (gdbarch, regnum)) 3503 { 3504 int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); 3505 3506 /* Read ... */ 3507 regcache->raw_read (fpnum, raw_buf); 3508 /* ... Modify ... (always little endian). */ 3509 memcpy (raw_buf, buf, register_size (gdbarch, regnum)); 3510 /* ... Write. */ 3511 regcache->raw_write (fpnum, raw_buf); 3512 } 3513 else 3514 { 3515 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3516 3517 if (i386_bnd_regnum_p (gdbarch, regnum)) 3518 { 3519 ULONGEST upper, lower; 3520 int size = TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr); 3521 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); 3522 3523 /* New values from input value. */ 3524 regnum -= tdep->bnd0_regnum; 3525 lower = extract_unsigned_integer (buf, size, byte_order); 3526 upper = extract_unsigned_integer (buf + size, size, byte_order); 3527 3528 /* Fetching register buffer. */ 3529 regcache->raw_read (I387_BND0R_REGNUM (tdep) + regnum, 3530 raw_buf); 3531 3532 upper = ~upper; 3533 3534 /* Set register bits. */ 3535 memcpy (raw_buf, &lower, 8); 3536 memcpy (raw_buf + 8, &upper, 8); 3537 3538 regcache->raw_write (I387_BND0R_REGNUM (tdep) + regnum, raw_buf); 3539 } 3540 else if (i386_k_regnum_p (gdbarch, regnum)) 3541 { 3542 regnum -= tdep->k0_regnum; 3543 3544 regcache->raw_write (tdep->k0_regnum + regnum, buf); 3545 } 3546 else if (i386_zmm_regnum_p (gdbarch, regnum)) 3547 { 3548 regnum -= tdep->zmm0_regnum; 3549 3550 if (regnum < num_lower_zmm_regs) 3551 { 3552 /* Write lower 128bits. */ 3553 regcache->raw_write (I387_XMM0_REGNUM (tdep) + regnum, buf); 3554 /* Write upper 128bits. */ 3555 regcache->raw_write (I387_YMM0_REGNUM (tdep) + regnum, buf + 16); 3556 } 3557 else 3558 { 3559 /* Write lower 128bits. */ 3560 regcache->raw_write (I387_XMM16_REGNUM (tdep) + regnum 3561 - num_lower_zmm_regs, buf); 3562 /* Write upper 128bits. */ 3563 regcache->raw_write (I387_YMM16H_REGNUM (tdep) + regnum 3564 - num_lower_zmm_regs, buf + 16); 3565 } 3566 /* Write upper 256bits. */ 3567 regcache->raw_write (tdep->zmm0h_regnum + regnum, buf + 32); 3568 } 3569 else if (i386_ymm_regnum_p (gdbarch, regnum)) 3570 { 3571 regnum -= tdep->ymm0_regnum; 3572 3573 /* ... Write lower 128bits. */ 3574 regcache->raw_write (I387_XMM0_REGNUM (tdep) + regnum, buf); 3575 /* ... Write upper 128bits. */ 3576 regcache->raw_write (tdep->ymm0h_regnum + regnum, buf + 16); 3577 } 3578 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) 3579 { 3580 regnum -= tdep->ymm16_regnum; 3581 3582 /* ... Write lower 128bits. */ 3583 regcache->raw_write (I387_XMM16_REGNUM (tdep) + regnum, buf); 3584 /* ... Write upper 128bits. */ 3585 regcache->raw_write (tdep->ymm16h_regnum + regnum, buf + 16); 3586 } 3587 else if (i386_word_regnum_p (gdbarch, regnum)) 3588 { 3589 int gpnum = regnum - tdep->ax_regnum; 3590 3591 /* Read ... */ 3592 regcache->raw_read (gpnum, raw_buf); 3593 /* ... Modify ... (always little endian). */ 3594 memcpy (raw_buf, buf, 2); 3595 /* ... Write. */ 3596 regcache->raw_write (gpnum, raw_buf); 3597 } 3598 else if (i386_byte_regnum_p (gdbarch, regnum)) 3599 { 3600 int gpnum = regnum - tdep->al_regnum; 3601 3602 /* Read ... We read both lower and upper registers. */ 3603 regcache->raw_read (gpnum % 4, raw_buf); 3604 /* ... Modify ... (always little endian). */ 3605 if (gpnum >= 4) 3606 memcpy (raw_buf + 1, buf, 1); 3607 else 3608 memcpy (raw_buf, buf, 1); 3609 /* ... Write. */ 3610 regcache->raw_write (gpnum % 4, raw_buf); 3611 } 3612 else 3613 internal_error (__FILE__, __LINE__, _("invalid regnum")); 3614 } 3615 } 3616 3617 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */ 3618 3619 int 3620 i386_ax_pseudo_register_collect (struct gdbarch *gdbarch, 3621 struct agent_expr *ax, int regnum) 3622 { 3623 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3624 3625 if (i386_mmx_regnum_p (gdbarch, regnum)) 3626 { 3627 /* MMX to FPU register mapping depends on current TOS. Let's just 3628 not care and collect everything... */ 3629 int i; 3630 3631 ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep)); 3632 for (i = 0; i < 8; i++) 3633 ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i); 3634 return 0; 3635 } 3636 else if (i386_bnd_regnum_p (gdbarch, regnum)) 3637 { 3638 regnum -= tdep->bnd0_regnum; 3639 ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum); 3640 return 0; 3641 } 3642 else if (i386_k_regnum_p (gdbarch, regnum)) 3643 { 3644 regnum -= tdep->k0_regnum; 3645 ax_reg_mask (ax, tdep->k0_regnum + regnum); 3646 return 0; 3647 } 3648 else if (i386_zmm_regnum_p (gdbarch, regnum)) 3649 { 3650 regnum -= tdep->zmm0_regnum; 3651 if (regnum < num_lower_zmm_regs) 3652 { 3653 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); 3654 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); 3655 } 3656 else 3657 { 3658 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum 3659 - num_lower_zmm_regs); 3660 ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum 3661 - num_lower_zmm_regs); 3662 } 3663 ax_reg_mask (ax, tdep->zmm0h_regnum + regnum); 3664 return 0; 3665 } 3666 else if (i386_ymm_regnum_p (gdbarch, regnum)) 3667 { 3668 regnum -= tdep->ymm0_regnum; 3669 ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); 3670 ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); 3671 return 0; 3672 } 3673 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) 3674 { 3675 regnum -= tdep->ymm16_regnum; 3676 ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum); 3677 ax_reg_mask (ax, tdep->ymm16h_regnum + regnum); 3678 return 0; 3679 } 3680 else if (i386_word_regnum_p (gdbarch, regnum)) 3681 { 3682 int gpnum = regnum - tdep->ax_regnum; 3683 3684 ax_reg_mask (ax, gpnum); 3685 return 0; 3686 } 3687 else if (i386_byte_regnum_p (gdbarch, regnum)) 3688 { 3689 int gpnum = regnum - tdep->al_regnum; 3690 3691 ax_reg_mask (ax, gpnum % 4); 3692 return 0; 3693 } 3694 else 3695 internal_error (__FILE__, __LINE__, _("invalid regnum")); 3696 return 1; 3697 } 3698 3699 3700 /* Return the register number of the register allocated by GCC after 3701 REGNUM, or -1 if there is no such register. */ 3702 3703 static int 3704 i386_next_regnum (int regnum) 3705 { 3706 /* GCC allocates the registers in the order: 3707 3708 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... 3709 3710 Since storing a variable in %esp doesn't make any sense we return 3711 -1 for %ebp and for %esp itself. */ 3712 static int next_regnum[] = 3713 { 3714 I386_EDX_REGNUM, /* Slot for %eax. */ 3715 I386_EBX_REGNUM, /* Slot for %ecx. */ 3716 I386_ECX_REGNUM, /* Slot for %edx. */ 3717 I386_ESI_REGNUM, /* Slot for %ebx. */ 3718 -1, -1, /* Slots for %esp and %ebp. */ 3719 I386_EDI_REGNUM, /* Slot for %esi. */ 3720 I386_EBP_REGNUM /* Slot for %edi. */ 3721 }; 3722 3723 if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) 3724 return next_regnum[regnum]; 3725 3726 return -1; 3727 } 3728 3729 /* Return nonzero if a value of type TYPE stored in register REGNUM 3730 needs any special handling. */ 3731 3732 static int 3733 i386_convert_register_p (struct gdbarch *gdbarch, 3734 int regnum, struct type *type) 3735 { 3736 int len = TYPE_LENGTH (type); 3737 3738 /* Values may be spread across multiple registers. Most debugging 3739 formats aren't expressive enough to specify the locations, so 3740 some heuristics is involved. Right now we only handle types that 3741 have a length that is a multiple of the word size, since GCC 3742 doesn't seem to put any other types into registers. */ 3743 if (len > 4 && len % 4 == 0) 3744 { 3745 int last_regnum = regnum; 3746 3747 while (len > 4) 3748 { 3749 last_regnum = i386_next_regnum (last_regnum); 3750 len -= 4; 3751 } 3752 3753 if (last_regnum != -1) 3754 return 1; 3755 } 3756 3757 return i387_convert_register_p (gdbarch, regnum, type); 3758 } 3759 3760 /* Read a value of type TYPE from register REGNUM in frame FRAME, and 3761 return its contents in TO. */ 3762 3763 static int 3764 i386_register_to_value (struct frame_info *frame, int regnum, 3765 struct type *type, gdb_byte *to, 3766 int *optimizedp, int *unavailablep) 3767 { 3768 struct gdbarch *gdbarch = get_frame_arch (frame); 3769 int len = TYPE_LENGTH (type); 3770 3771 if (i386_fp_regnum_p (gdbarch, regnum)) 3772 return i387_register_to_value (frame, regnum, type, to, 3773 optimizedp, unavailablep); 3774 3775 /* Read a value spread across multiple registers. */ 3776 3777 gdb_assert (len > 4 && len % 4 == 0); 3778 3779 while (len > 0) 3780 { 3781 gdb_assert (regnum != -1); 3782 gdb_assert (register_size (gdbarch, regnum) == 4); 3783 3784 if (!get_frame_register_bytes (frame, regnum, 0, 3785 register_size (gdbarch, regnum), 3786 to, optimizedp, unavailablep)) 3787 return 0; 3788 3789 regnum = i386_next_regnum (regnum); 3790 len -= 4; 3791 to += 4; 3792 } 3793 3794 *optimizedp = *unavailablep = 0; 3795 return 1; 3796 } 3797 3798 /* Write the contents FROM of a value of type TYPE into register 3799 REGNUM in frame FRAME. */ 3800 3801 static void 3802 i386_value_to_register (struct frame_info *frame, int regnum, 3803 struct type *type, const gdb_byte *from) 3804 { 3805 int len = TYPE_LENGTH (type); 3806 3807 if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) 3808 { 3809 i387_value_to_register (frame, regnum, type, from); 3810 return; 3811 } 3812 3813 /* Write a value spread across multiple registers. */ 3814 3815 gdb_assert (len > 4 && len % 4 == 0); 3816 3817 while (len > 0) 3818 { 3819 gdb_assert (regnum != -1); 3820 gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); 3821 3822 put_frame_register (frame, regnum, from); 3823 regnum = i386_next_regnum (regnum); 3824 len -= 4; 3825 from += 4; 3826 } 3827 } 3828 3829 /* Supply register REGNUM from the buffer specified by GREGS and LEN 3830 in the general-purpose register set REGSET to register cache 3831 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 3832 3833 void 3834 i386_supply_gregset (const struct regset *regset, struct regcache *regcache, 3835 int regnum, const void *gregs, size_t len) 3836 { 3837 struct gdbarch *gdbarch = regcache->arch (); 3838 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3839 const gdb_byte *regs = (const gdb_byte *) gregs; 3840 int i; 3841 3842 gdb_assert (len >= tdep->sizeof_gregset); 3843 3844 for (i = 0; i < tdep->gregset_num_regs; i++) 3845 { 3846 if ((regnum == i || regnum == -1) 3847 && tdep->gregset_reg_offset[i] != -1) 3848 regcache->raw_supply (i, regs + tdep->gregset_reg_offset[i]); 3849 } 3850 } 3851 3852 /* Collect register REGNUM from the register cache REGCACHE and store 3853 it in the buffer specified by GREGS and LEN as described by the 3854 general-purpose register set REGSET. If REGNUM is -1, do this for 3855 all registers in REGSET. */ 3856 3857 static void 3858 i386_collect_gregset (const struct regset *regset, 3859 const struct regcache *regcache, 3860 int regnum, void *gregs, size_t len) 3861 { 3862 struct gdbarch *gdbarch = regcache->arch (); 3863 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3864 gdb_byte *regs = (gdb_byte *) gregs; 3865 int i; 3866 3867 gdb_assert (len >= tdep->sizeof_gregset); 3868 3869 for (i = 0; i < tdep->gregset_num_regs; i++) 3870 { 3871 if ((regnum == i || regnum == -1) 3872 && tdep->gregset_reg_offset[i] != -1) 3873 regcache->raw_collect (i, regs + tdep->gregset_reg_offset[i]); 3874 } 3875 } 3876 3877 /* Supply register REGNUM from the buffer specified by FPREGS and LEN 3878 in the floating-point register set REGSET to register cache 3879 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 3880 3881 static void 3882 i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, 3883 int regnum, const void *fpregs, size_t len) 3884 { 3885 struct gdbarch *gdbarch = regcache->arch (); 3886 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3887 3888 if (len == I387_SIZEOF_FXSAVE) 3889 { 3890 i387_supply_fxsave (regcache, regnum, fpregs); 3891 return; 3892 } 3893 3894 gdb_assert (len >= tdep->sizeof_fpregset); 3895 i387_supply_fsave (regcache, regnum, fpregs); 3896 } 3897 3898 /* Collect register REGNUM from the register cache REGCACHE and store 3899 it in the buffer specified by FPREGS and LEN as described by the 3900 floating-point register set REGSET. If REGNUM is -1, do this for 3901 all registers in REGSET. */ 3902 3903 static void 3904 i386_collect_fpregset (const struct regset *regset, 3905 const struct regcache *regcache, 3906 int regnum, void *fpregs, size_t len) 3907 { 3908 struct gdbarch *gdbarch = regcache->arch (); 3909 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3910 3911 if (len == I387_SIZEOF_FXSAVE) 3912 { 3913 i387_collect_fxsave (regcache, regnum, fpregs); 3914 return; 3915 } 3916 3917 gdb_assert (len >= tdep->sizeof_fpregset); 3918 i387_collect_fsave (regcache, regnum, fpregs); 3919 } 3920 3921 /* Register set definitions. */ 3922 3923 const struct regset i386_gregset = 3924 { 3925 NULL, i386_supply_gregset, i386_collect_gregset 3926 }; 3927 3928 const struct regset i386_fpregset = 3929 { 3930 NULL, i386_supply_fpregset, i386_collect_fpregset 3931 }; 3932 3933 /* Default iterator over core file register note sections. */ 3934 3935 void 3936 i386_iterate_over_regset_sections (struct gdbarch *gdbarch, 3937 iterate_over_regset_sections_cb *cb, 3938 void *cb_data, 3939 const struct regcache *regcache) 3940 { 3941 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3942 3943 cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, &i386_gregset, NULL, 3944 cb_data); 3945 if (tdep->sizeof_fpregset) 3946 cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, 3947 NULL, cb_data); 3948 } 3949 3950 3951 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ 3952 3953 CORE_ADDR 3954 i386_pe_skip_trampoline_code (struct frame_info *frame, 3955 CORE_ADDR pc, char *name) 3956 { 3957 struct gdbarch *gdbarch = get_frame_arch (frame); 3958 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 3959 3960 /* jmp *(dest) */ 3961 if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) 3962 { 3963 unsigned long indirect = 3964 read_memory_unsigned_integer (pc + 2, 4, byte_order); 3965 struct minimal_symbol *indsym = 3966 indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0; 3967 const char *symname = indsym ? indsym->linkage_name () : 0; 3968 3969 if (symname) 3970 { 3971 if (startswith (symname, "__imp_") 3972 || startswith (symname, "_imp_")) 3973 return name ? 1 : 3974 read_memory_unsigned_integer (indirect, 4, byte_order); 3975 } 3976 } 3977 return 0; /* Not a trampoline. */ 3978 } 3979 3980 3981 /* Return whether the THIS_FRAME corresponds to a sigtramp 3982 routine. */ 3983 3984 int 3985 i386_sigtramp_p (struct frame_info *this_frame) 3986 { 3987 CORE_ADDR pc = get_frame_pc (this_frame); 3988 const char *name; 3989 3990 find_pc_partial_function (pc, &name, NULL, NULL); 3991 return (name && strcmp ("_sigtramp", name) == 0); 3992 } 3993 3994 3995 /* We have two flavours of disassembly. The machinery on this page 3996 deals with switching between those. */ 3997 3998 static int 3999 i386_print_insn (bfd_vma pc, struct disassemble_info *info) 4000 { 4001 gdb_assert (disassembly_flavor == att_flavor 4002 || disassembly_flavor == intel_flavor); 4003 4004 info->disassembler_options = disassembly_flavor; 4005 4006 return default_print_insn (pc, info); 4007 } 4008 4009 4010 /* There are a few i386 architecture variants that differ only 4011 slightly from the generic i386 target. For now, we don't give them 4012 their own source file, but include them here. As a consequence, 4013 they'll always be included. */ 4014 4015 /* System V Release 4 (SVR4). */ 4016 4017 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp 4018 routine. */ 4019 4020 static int 4021 i386_svr4_sigtramp_p (struct frame_info *this_frame) 4022 { 4023 CORE_ADDR pc = get_frame_pc (this_frame); 4024 const char *name; 4025 4026 /* The origin of these symbols is currently unknown. */ 4027 find_pc_partial_function (pc, &name, NULL, NULL); 4028 return (name && (strcmp ("_sigreturn", name) == 0 4029 || strcmp ("sigvechandler", name) == 0)); 4030 } 4031 4032 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the 4033 address of the associated sigcontext (ucontext) structure. */ 4034 4035 static CORE_ADDR 4036 i386_svr4_sigcontext_addr (struct frame_info *this_frame) 4037 { 4038 struct gdbarch *gdbarch = get_frame_arch (this_frame); 4039 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 4040 gdb_byte buf[4]; 4041 CORE_ADDR sp; 4042 4043 get_frame_register (this_frame, I386_ESP_REGNUM, buf); 4044 sp = extract_unsigned_integer (buf, 4, byte_order); 4045 4046 return read_memory_unsigned_integer (sp + 8, 4, byte_order); 4047 } 4048 4049 4050 4051 /* Implementation of `gdbarch_stap_is_single_operand', as defined in 4052 gdbarch.h. */ 4053 4054 int 4055 i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) 4056 { 4057 return (*s == '$' /* Literal number. */ 4058 || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ 4059 || (*s == '(' && s[1] == '%') /* Register indirection. */ 4060 || (*s == '%' && isalpha (s[1]))); /* Register access. */ 4061 } 4062 4063 /* Helper function for i386_stap_parse_special_token. 4064 4065 This function parses operands of the form `-8+3+1(%rbp)', which 4066 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'. 4067 4068 Return true if the operand was parsed successfully, false 4069 otherwise. */ 4070 4071 static bool 4072 i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch, 4073 struct stap_parse_info *p) 4074 { 4075 const char *s = p->arg; 4076 4077 if (isdigit (*s) || *s == '-' || *s == '+') 4078 { 4079 bool got_minus[3]; 4080 int i; 4081 long displacements[3]; 4082 const char *start; 4083 char *regname; 4084 int len; 4085 struct stoken str; 4086 char *endp; 4087 4088 got_minus[0] = false; 4089 if (*s == '+') 4090 ++s; 4091 else if (*s == '-') 4092 { 4093 ++s; 4094 got_minus[0] = true; 4095 } 4096 4097 if (!isdigit ((unsigned char) *s)) 4098 return false; 4099 4100 displacements[0] = strtol (s, &endp, 10); 4101 s = endp; 4102 4103 if (*s != '+' && *s != '-') 4104 { 4105 /* We are not dealing with a triplet. */ 4106 return false; 4107 } 4108 4109 got_minus[1] = false; 4110 if (*s == '+') 4111 ++s; 4112 else 4113 { 4114 ++s; 4115 got_minus[1] = true; 4116 } 4117 4118 if (!isdigit ((unsigned char) *s)) 4119 return false; 4120 4121 displacements[1] = strtol (s, &endp, 10); 4122 s = endp; 4123 4124 if (*s != '+' && *s != '-') 4125 { 4126 /* We are not dealing with a triplet. */ 4127 return false; 4128 } 4129 4130 got_minus[2] = false; 4131 if (*s == '+') 4132 ++s; 4133 else 4134 { 4135 ++s; 4136 got_minus[2] = true; 4137 } 4138 4139 if (!isdigit ((unsigned char) *s)) 4140 return false; 4141 4142 displacements[2] = strtol (s, &endp, 10); 4143 s = endp; 4144 4145 if (*s != '(' || s[1] != '%') 4146 return false; 4147 4148 s += 2; 4149 start = s; 4150 4151 while (isalnum (*s)) 4152 ++s; 4153 4154 if (*s++ != ')') 4155 return false; 4156 4157 len = s - start - 1; 4158 regname = (char *) alloca (len + 1); 4159 4160 strncpy (regname, start, len); 4161 regname[len] = '\0'; 4162 4163 if (user_reg_map_name_to_regnum (gdbarch, regname, len) == -1) 4164 error (_("Invalid register name `%s' on expression `%s'."), 4165 regname, p->saved_arg); 4166 4167 for (i = 0; i < 3; i++) 4168 { 4169 write_exp_elt_opcode (&p->pstate, OP_LONG); 4170 write_exp_elt_type 4171 (&p->pstate, builtin_type (gdbarch)->builtin_long); 4172 write_exp_elt_longcst (&p->pstate, displacements[i]); 4173 write_exp_elt_opcode (&p->pstate, OP_LONG); 4174 if (got_minus[i]) 4175 write_exp_elt_opcode (&p->pstate, UNOP_NEG); 4176 } 4177 4178 write_exp_elt_opcode (&p->pstate, OP_REGISTER); 4179 str.ptr = regname; 4180 str.length = len; 4181 write_exp_string (&p->pstate, str); 4182 write_exp_elt_opcode (&p->pstate, OP_REGISTER); 4183 4184 write_exp_elt_opcode (&p->pstate, UNOP_CAST); 4185 write_exp_elt_type (&p->pstate, 4186 builtin_type (gdbarch)->builtin_data_ptr); 4187 write_exp_elt_opcode (&p->pstate, UNOP_CAST); 4188 4189 write_exp_elt_opcode (&p->pstate, BINOP_ADD); 4190 write_exp_elt_opcode (&p->pstate, BINOP_ADD); 4191 write_exp_elt_opcode (&p->pstate, BINOP_ADD); 4192 4193 write_exp_elt_opcode (&p->pstate, UNOP_CAST); 4194 write_exp_elt_type (&p->pstate, 4195 lookup_pointer_type (p->arg_type)); 4196 write_exp_elt_opcode (&p->pstate, UNOP_CAST); 4197 4198 write_exp_elt_opcode (&p->pstate, UNOP_IND); 4199 4200 p->arg = s; 4201 4202 return true; 4203 } 4204 4205 return false; 4206 } 4207 4208 /* Helper function for i386_stap_parse_special_token. 4209 4210 This function parses operands of the form `register base + 4211 (register index * size) + offset', as represented in 4212 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. 4213 4214 Return true if the operand was parsed successfully, false 4215 otherwise. */ 4216 4217 static bool 4218 i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch, 4219 struct stap_parse_info *p) 4220 { 4221 const char *s = p->arg; 4222 4223 if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') 4224 { 4225 bool offset_minus = false; 4226 long offset = 0; 4227 bool size_minus = false; 4228 long size = 0; 4229 const char *start; 4230 char *base; 4231 int len_base; 4232 char *index; 4233 int len_index; 4234 struct stoken base_token, index_token; 4235 4236 if (*s == '+') 4237 ++s; 4238 else if (*s == '-') 4239 { 4240 ++s; 4241 offset_minus = true; 4242 } 4243 4244 if (offset_minus && !isdigit (*s)) 4245 return false; 4246 4247 if (isdigit (*s)) 4248 { 4249 char *endp; 4250 4251 offset = strtol (s, &endp, 10); 4252 s = endp; 4253 } 4254 4255 if (*s != '(' || s[1] != '%') 4256 return false; 4257 4258 s += 2; 4259 start = s; 4260 4261 while (isalnum (*s)) 4262 ++s; 4263 4264 if (*s != ',' || s[1] != '%') 4265 return false; 4266 4267 len_base = s - start; 4268 base = (char *) alloca (len_base + 1); 4269 strncpy (base, start, len_base); 4270 base[len_base] = '\0'; 4271 4272 if (user_reg_map_name_to_regnum (gdbarch, base, len_base) == -1) 4273 error (_("Invalid register name `%s' on expression `%s'."), 4274 base, p->saved_arg); 4275 4276 s += 2; 4277 start = s; 4278 4279 while (isalnum (*s)) 4280 ++s; 4281 4282 len_index = s - start; 4283 index = (char *) alloca (len_index + 1); 4284 strncpy (index, start, len_index); 4285 index[len_index] = '\0'; 4286 4287 if (user_reg_map_name_to_regnum (gdbarch, index, len_index) == -1) 4288 error (_("Invalid register name `%s' on expression `%s'."), 4289 index, p->saved_arg); 4290 4291 if (*s != ',' && *s != ')') 4292 return false; 4293 4294 if (*s == ',') 4295 { 4296 char *endp; 4297 4298 ++s; 4299 if (*s == '+') 4300 ++s; 4301 else if (*s == '-') 4302 { 4303 ++s; 4304 size_minus = true; 4305 } 4306 4307 size = strtol (s, &endp, 10); 4308 s = endp; 4309 4310 if (*s != ')') 4311 return false; 4312 } 4313 4314 ++s; 4315 4316 if (offset) 4317 { 4318 write_exp_elt_opcode (&p->pstate, OP_LONG); 4319 write_exp_elt_type (&p->pstate, 4320 builtin_type (gdbarch)->builtin_long); 4321 write_exp_elt_longcst (&p->pstate, offset); 4322 write_exp_elt_opcode (&p->pstate, OP_LONG); 4323 if (offset_minus) 4324 write_exp_elt_opcode (&p->pstate, UNOP_NEG); 4325 } 4326 4327 write_exp_elt_opcode (&p->pstate, OP_REGISTER); 4328 base_token.ptr = base; 4329 base_token.length = len_base; 4330 write_exp_string (&p->pstate, base_token); 4331 write_exp_elt_opcode (&p->pstate, OP_REGISTER); 4332 4333 if (offset) 4334 write_exp_elt_opcode (&p->pstate, BINOP_ADD); 4335 4336 write_exp_elt_opcode (&p->pstate, OP_REGISTER); 4337 index_token.ptr = index; 4338 index_token.length = len_index; 4339 write_exp_string (&p->pstate, index_token); 4340 write_exp_elt_opcode (&p->pstate, OP_REGISTER); 4341 4342 if (size) 4343 { 4344 write_exp_elt_opcode (&p->pstate, OP_LONG); 4345 write_exp_elt_type (&p->pstate, 4346 builtin_type (gdbarch)->builtin_long); 4347 write_exp_elt_longcst (&p->pstate, size); 4348 write_exp_elt_opcode (&p->pstate, OP_LONG); 4349 if (size_minus) 4350 write_exp_elt_opcode (&p->pstate, UNOP_NEG); 4351 write_exp_elt_opcode (&p->pstate, BINOP_MUL); 4352 } 4353 4354 write_exp_elt_opcode (&p->pstate, BINOP_ADD); 4355 4356 write_exp_elt_opcode (&p->pstate, UNOP_CAST); 4357 write_exp_elt_type (&p->pstate, 4358 lookup_pointer_type (p->arg_type)); 4359 write_exp_elt_opcode (&p->pstate, UNOP_CAST); 4360 4361 write_exp_elt_opcode (&p->pstate, UNOP_IND); 4362 4363 p->arg = s; 4364 4365 return true; 4366 } 4367 4368 return false; 4369 } 4370 4371 /* Implementation of `gdbarch_stap_parse_special_token', as defined in 4372 gdbarch.h. */ 4373 4374 int 4375 i386_stap_parse_special_token (struct gdbarch *gdbarch, 4376 struct stap_parse_info *p) 4377 { 4378 /* In order to parse special tokens, we use a state-machine that go 4379 through every known token and try to get a match. */ 4380 enum 4381 { 4382 TRIPLET, 4383 THREE_ARG_DISPLACEMENT, 4384 DONE 4385 }; 4386 int current_state; 4387 4388 current_state = TRIPLET; 4389 4390 /* The special tokens to be parsed here are: 4391 4392 - `register base + (register index * size) + offset', as represented 4393 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. 4394 4395 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as 4396 `*(-8 + 3 - 1 + (void *) $eax)'. */ 4397 4398 while (current_state != DONE) 4399 { 4400 switch (current_state) 4401 { 4402 case TRIPLET: 4403 if (i386_stap_parse_special_token_triplet (gdbarch, p)) 4404 return 1; 4405 break; 4406 4407 case THREE_ARG_DISPLACEMENT: 4408 if (i386_stap_parse_special_token_three_arg_disp (gdbarch, p)) 4409 return 1; 4410 break; 4411 } 4412 4413 /* Advancing to the next state. */ 4414 ++current_state; 4415 } 4416 4417 return 0; 4418 } 4419 4420 /* Implementation of 'gdbarch_stap_adjust_register', as defined in 4421 gdbarch.h. */ 4422 4423 static std::string 4424 i386_stap_adjust_register (struct gdbarch *gdbarch, struct stap_parse_info *p, 4425 const std::string ®name, int regnum) 4426 { 4427 static const std::unordered_set<std::string> reg_assoc 4428 = { "ax", "bx", "cx", "dx", 4429 "si", "di", "bp", "sp" }; 4430 4431 /* If we are dealing with a register whose size is less than the size 4432 specified by the "[-]N@" prefix, and it is one of the registers that 4433 we know has an extended variant available, then use the extended 4434 version of the register instead. */ 4435 if (register_size (gdbarch, regnum) < TYPE_LENGTH (p->arg_type) 4436 && reg_assoc.find (regname) != reg_assoc.end ()) 4437 return "e" + regname; 4438 4439 /* Otherwise, just use the requested register. */ 4440 return regname; 4441 } 4442 4443 4444 4445 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always 4446 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */ 4447 4448 static const char * 4449 i386_gnu_triplet_regexp (struct gdbarch *gdbarch) 4450 { 4451 return "(x86_64|i.86)"; 4452 } 4453 4454 4455 4456 /* Implement the "in_indirect_branch_thunk" gdbarch function. */ 4457 4458 static bool 4459 i386_in_indirect_branch_thunk (struct gdbarch *gdbarch, CORE_ADDR pc) 4460 { 4461 return x86_in_indirect_branch_thunk (pc, i386_register_names, 4462 I386_EAX_REGNUM, I386_EIP_REGNUM); 4463 } 4464 4465 /* Generic ELF. */ 4466 4467 void 4468 i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 4469 { 4470 static const char *const stap_integer_prefixes[] = { "$", NULL }; 4471 static const char *const stap_register_prefixes[] = { "%", NULL }; 4472 static const char *const stap_register_indirection_prefixes[] = { "(", 4473 NULL }; 4474 static const char *const stap_register_indirection_suffixes[] = { ")", 4475 NULL }; 4476 4477 /* We typically use stabs-in-ELF with the SVR4 register numbering. */ 4478 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); 4479 4480 /* Registering SystemTap handlers. */ 4481 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); 4482 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); 4483 set_gdbarch_stap_register_indirection_prefixes (gdbarch, 4484 stap_register_indirection_prefixes); 4485 set_gdbarch_stap_register_indirection_suffixes (gdbarch, 4486 stap_register_indirection_suffixes); 4487 set_gdbarch_stap_is_single_operand (gdbarch, 4488 i386_stap_is_single_operand); 4489 set_gdbarch_stap_parse_special_token (gdbarch, 4490 i386_stap_parse_special_token); 4491 set_gdbarch_stap_adjust_register (gdbarch, 4492 i386_stap_adjust_register); 4493 4494 set_gdbarch_in_indirect_branch_thunk (gdbarch, 4495 i386_in_indirect_branch_thunk); 4496 } 4497 4498 /* System V Release 4 (SVR4). */ 4499 4500 void 4501 i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 4502 { 4503 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 4504 4505 /* System V Release 4 uses ELF. */ 4506 i386_elf_init_abi (info, gdbarch); 4507 4508 /* System V Release 4 has shared libraries. */ 4509 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); 4510 4511 tdep->sigtramp_p = i386_svr4_sigtramp_p; 4512 tdep->sigcontext_addr = i386_svr4_sigcontext_addr; 4513 tdep->sc_pc_offset = 36 + 14 * 4; 4514 tdep->sc_sp_offset = 36 + 17 * 4; 4515 4516 tdep->jb_pc_offset = 20; 4517 } 4518 4519 4520 4521 /* i386 register groups. In addition to the normal groups, add "mmx" 4522 and "sse". */ 4523 4524 static struct reggroup *i386_sse_reggroup; 4525 static struct reggroup *i386_mmx_reggroup; 4526 4527 static void 4528 i386_init_reggroups (void) 4529 { 4530 i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); 4531 i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); 4532 } 4533 4534 static void 4535 i386_add_reggroups (struct gdbarch *gdbarch) 4536 { 4537 reggroup_add (gdbarch, i386_sse_reggroup); 4538 reggroup_add (gdbarch, i386_mmx_reggroup); 4539 reggroup_add (gdbarch, general_reggroup); 4540 reggroup_add (gdbarch, float_reggroup); 4541 reggroup_add (gdbarch, all_reggroup); 4542 reggroup_add (gdbarch, save_reggroup); 4543 reggroup_add (gdbarch, restore_reggroup); 4544 reggroup_add (gdbarch, vector_reggroup); 4545 reggroup_add (gdbarch, system_reggroup); 4546 } 4547 4548 int 4549 i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 4550 struct reggroup *group) 4551 { 4552 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 4553 int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, 4554 ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p, 4555 bndr_regnum_p, bnd_regnum_p, zmm_regnum_p, zmmh_regnum_p, 4556 mpx_ctrl_regnum_p, xmm_avx512_regnum_p, 4557 avx512_p, avx_p, sse_p, pkru_regnum_p; 4558 4559 /* Don't include pseudo registers, except for MMX, in any register 4560 groups. */ 4561 if (i386_byte_regnum_p (gdbarch, regnum)) 4562 return 0; 4563 4564 if (i386_word_regnum_p (gdbarch, regnum)) 4565 return 0; 4566 4567 if (i386_dword_regnum_p (gdbarch, regnum)) 4568 return 0; 4569 4570 mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); 4571 if (group == i386_mmx_reggroup) 4572 return mmx_regnum_p; 4573 4574 pkru_regnum_p = i386_pkru_regnum_p(gdbarch, regnum); 4575 xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); 4576 xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum); 4577 mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); 4578 if (group == i386_sse_reggroup) 4579 return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p; 4580 4581 ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); 4582 ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum); 4583 zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum); 4584 4585 avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) 4586 == X86_XSTATE_AVX_AVX512_MASK); 4587 avx_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) 4588 == X86_XSTATE_AVX_MASK) && !avx512_p; 4589 sse_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) 4590 == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p; 4591 4592 if (group == vector_reggroup) 4593 return (mmx_regnum_p 4594 || (zmm_regnum_p && avx512_p) 4595 || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p) 4596 || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p) 4597 || mxcsr_regnum_p); 4598 4599 fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) 4600 || i386_fpc_regnum_p (gdbarch, regnum)); 4601 if (group == float_reggroup) 4602 return fp_regnum_p; 4603 4604 /* For "info reg all", don't include upper YMM registers nor XMM 4605 registers when AVX is supported. */ 4606 ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); 4607 ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum); 4608 zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum); 4609 if (group == all_reggroup 4610 && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p) 4611 || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p) 4612 || ymmh_regnum_p 4613 || ymmh_avx512_regnum_p 4614 || zmmh_regnum_p)) 4615 return 0; 4616 4617 bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum); 4618 if (group == all_reggroup 4619 && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) 4620 return bnd_regnum_p; 4621 4622 bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum); 4623 if (group == all_reggroup 4624 && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) 4625 return 0; 4626 4627 mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum); 4628 if (group == all_reggroup 4629 && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) 4630 return mpx_ctrl_regnum_p; 4631 4632 if (group == general_reggroup) 4633 return (!fp_regnum_p 4634 && !mmx_regnum_p 4635 && !mxcsr_regnum_p 4636 && !xmm_regnum_p 4637 && !xmm_avx512_regnum_p 4638 && !ymm_regnum_p 4639 && !ymmh_regnum_p 4640 && !ymm_avx512_regnum_p 4641 && !ymmh_avx512_regnum_p 4642 && !bndr_regnum_p 4643 && !bnd_regnum_p 4644 && !mpx_ctrl_regnum_p 4645 && !zmm_regnum_p 4646 && !zmmh_regnum_p 4647 && !pkru_regnum_p); 4648 4649 return default_register_reggroup_p (gdbarch, regnum, group); 4650 } 4651 4652 4653 /* Get the ARGIth function argument for the current function. */ 4654 4655 static CORE_ADDR 4656 i386_fetch_pointer_argument (struct frame_info *frame, int argi, 4657 struct type *type) 4658 { 4659 struct gdbarch *gdbarch = get_frame_arch (frame); 4660 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 4661 CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); 4662 return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); 4663 } 4664 4665 #define PREFIX_REPZ 0x01 4666 #define PREFIX_REPNZ 0x02 4667 #define PREFIX_LOCK 0x04 4668 #define PREFIX_DATA 0x08 4669 #define PREFIX_ADDR 0x10 4670 4671 /* operand size */ 4672 enum 4673 { 4674 OT_BYTE = 0, 4675 OT_WORD, 4676 OT_LONG, 4677 OT_QUAD, 4678 OT_DQUAD, 4679 }; 4680 4681 /* i386 arith/logic operations */ 4682 enum 4683 { 4684 OP_ADDL, 4685 OP_ORL, 4686 OP_ADCL, 4687 OP_SBBL, 4688 OP_ANDL, 4689 OP_SUBL, 4690 OP_XORL, 4691 OP_CMPL, 4692 }; 4693 4694 struct i386_record_s 4695 { 4696 struct gdbarch *gdbarch; 4697 struct regcache *regcache; 4698 CORE_ADDR orig_addr; 4699 CORE_ADDR addr; 4700 int aflag; 4701 int dflag; 4702 int override; 4703 uint8_t modrm; 4704 uint8_t mod, reg, rm; 4705 int ot; 4706 uint8_t rex_x; 4707 uint8_t rex_b; 4708 int rip_offset; 4709 int popl_esp_hack; 4710 const int *regmap; 4711 }; 4712 4713 /* Parse the "modrm" part of the memory address irp->addr points at. 4714 Returns -1 if something goes wrong, 0 otherwise. */ 4715 4716 static int 4717 i386_record_modrm (struct i386_record_s *irp) 4718 { 4719 struct gdbarch *gdbarch = irp->gdbarch; 4720 4721 if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1)) 4722 return -1; 4723 4724 irp->addr++; 4725 irp->mod = (irp->modrm >> 6) & 3; 4726 irp->reg = (irp->modrm >> 3) & 7; 4727 irp->rm = irp->modrm & 7; 4728 4729 return 0; 4730 } 4731 4732 /* Extract the memory address that the current instruction writes to, 4733 and return it in *ADDR. Return -1 if something goes wrong. */ 4734 4735 static int 4736 i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) 4737 { 4738 struct gdbarch *gdbarch = irp->gdbarch; 4739 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 4740 gdb_byte buf[4]; 4741 ULONGEST offset64; 4742 4743 *addr = 0; 4744 if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM]) 4745 { 4746 /* 32/64 bits */ 4747 int havesib = 0; 4748 uint8_t scale = 0; 4749 uint8_t byte; 4750 uint8_t index = 0; 4751 uint8_t base = irp->rm; 4752 4753 if (base == 4) 4754 { 4755 havesib = 1; 4756 if (record_read_memory (gdbarch, irp->addr, &byte, 1)) 4757 return -1; 4758 irp->addr++; 4759 scale = (byte >> 6) & 3; 4760 index = ((byte >> 3) & 7) | irp->rex_x; 4761 base = (byte & 7); 4762 } 4763 base |= irp->rex_b; 4764 4765 switch (irp->mod) 4766 { 4767 case 0: 4768 if ((base & 7) == 5) 4769 { 4770 base = 0xff; 4771 if (record_read_memory (gdbarch, irp->addr, buf, 4)) 4772 return -1; 4773 irp->addr += 4; 4774 *addr = extract_signed_integer (buf, 4, byte_order); 4775 if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) 4776 *addr += irp->addr + irp->rip_offset; 4777 } 4778 break; 4779 case 1: 4780 if (record_read_memory (gdbarch, irp->addr, buf, 1)) 4781 return -1; 4782 irp->addr++; 4783 *addr = (int8_t) buf[0]; 4784 break; 4785 case 2: 4786 if (record_read_memory (gdbarch, irp->addr, buf, 4)) 4787 return -1; 4788 *addr = extract_signed_integer (buf, 4, byte_order); 4789 irp->addr += 4; 4790 break; 4791 } 4792 4793 offset64 = 0; 4794 if (base != 0xff) 4795 { 4796 if (base == 4 && irp->popl_esp_hack) 4797 *addr += irp->popl_esp_hack; 4798 regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], 4799 &offset64); 4800 } 4801 if (irp->aflag == 2) 4802 { 4803 *addr += offset64; 4804 } 4805 else 4806 *addr = (uint32_t) (offset64 + *addr); 4807 4808 if (havesib && (index != 4 || scale != 0)) 4809 { 4810 regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], 4811 &offset64); 4812 if (irp->aflag == 2) 4813 *addr += offset64 << scale; 4814 else 4815 *addr = (uint32_t) (*addr + (offset64 << scale)); 4816 } 4817 4818 if (!irp->aflag) 4819 { 4820 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend 4821 address from 32-bit to 64-bit. */ 4822 *addr = (uint32_t) *addr; 4823 } 4824 } 4825 else 4826 { 4827 /* 16 bits */ 4828 switch (irp->mod) 4829 { 4830 case 0: 4831 if (irp->rm == 6) 4832 { 4833 if (record_read_memory (gdbarch, irp->addr, buf, 2)) 4834 return -1; 4835 irp->addr += 2; 4836 *addr = extract_signed_integer (buf, 2, byte_order); 4837 irp->rm = 0; 4838 goto no_rm; 4839 } 4840 break; 4841 case 1: 4842 if (record_read_memory (gdbarch, irp->addr, buf, 1)) 4843 return -1; 4844 irp->addr++; 4845 *addr = (int8_t) buf[0]; 4846 break; 4847 case 2: 4848 if (record_read_memory (gdbarch, irp->addr, buf, 2)) 4849 return -1; 4850 irp->addr += 2; 4851 *addr = extract_signed_integer (buf, 2, byte_order); 4852 break; 4853 } 4854 4855 switch (irp->rm) 4856 { 4857 case 0: 4858 regcache_raw_read_unsigned (irp->regcache, 4859 irp->regmap[X86_RECORD_REBX_REGNUM], 4860 &offset64); 4861 *addr = (uint32_t) (*addr + offset64); 4862 regcache_raw_read_unsigned (irp->regcache, 4863 irp->regmap[X86_RECORD_RESI_REGNUM], 4864 &offset64); 4865 *addr = (uint32_t) (*addr + offset64); 4866 break; 4867 case 1: 4868 regcache_raw_read_unsigned (irp->regcache, 4869 irp->regmap[X86_RECORD_REBX_REGNUM], 4870 &offset64); 4871 *addr = (uint32_t) (*addr + offset64); 4872 regcache_raw_read_unsigned (irp->regcache, 4873 irp->regmap[X86_RECORD_REDI_REGNUM], 4874 &offset64); 4875 *addr = (uint32_t) (*addr + offset64); 4876 break; 4877 case 2: 4878 regcache_raw_read_unsigned (irp->regcache, 4879 irp->regmap[X86_RECORD_REBP_REGNUM], 4880 &offset64); 4881 *addr = (uint32_t) (*addr + offset64); 4882 regcache_raw_read_unsigned (irp->regcache, 4883 irp->regmap[X86_RECORD_RESI_REGNUM], 4884 &offset64); 4885 *addr = (uint32_t) (*addr + offset64); 4886 break; 4887 case 3: 4888 regcache_raw_read_unsigned (irp->regcache, 4889 irp->regmap[X86_RECORD_REBP_REGNUM], 4890 &offset64); 4891 *addr = (uint32_t) (*addr + offset64); 4892 regcache_raw_read_unsigned (irp->regcache, 4893 irp->regmap[X86_RECORD_REDI_REGNUM], 4894 &offset64); 4895 *addr = (uint32_t) (*addr + offset64); 4896 break; 4897 case 4: 4898 regcache_raw_read_unsigned (irp->regcache, 4899 irp->regmap[X86_RECORD_RESI_REGNUM], 4900 &offset64); 4901 *addr = (uint32_t) (*addr + offset64); 4902 break; 4903 case 5: 4904 regcache_raw_read_unsigned (irp->regcache, 4905 irp->regmap[X86_RECORD_REDI_REGNUM], 4906 &offset64); 4907 *addr = (uint32_t) (*addr + offset64); 4908 break; 4909 case 6: 4910 regcache_raw_read_unsigned (irp->regcache, 4911 irp->regmap[X86_RECORD_REBP_REGNUM], 4912 &offset64); 4913 *addr = (uint32_t) (*addr + offset64); 4914 break; 4915 case 7: 4916 regcache_raw_read_unsigned (irp->regcache, 4917 irp->regmap[X86_RECORD_REBX_REGNUM], 4918 &offset64); 4919 *addr = (uint32_t) (*addr + offset64); 4920 break; 4921 } 4922 *addr &= 0xffff; 4923 } 4924 4925 no_rm: 4926 return 0; 4927 } 4928 4929 /* Record the address and contents of the memory that will be changed 4930 by the current instruction. Return -1 if something goes wrong, 0 4931 otherwise. */ 4932 4933 static int 4934 i386_record_lea_modrm (struct i386_record_s *irp) 4935 { 4936 struct gdbarch *gdbarch = irp->gdbarch; 4937 uint64_t addr; 4938 4939 if (irp->override >= 0) 4940 { 4941 if (record_full_memory_query) 4942 { 4943 if (yquery (_("\ 4944 Process record ignores the memory change of instruction at address %s\n\ 4945 because it can't get the value of the segment register.\n\ 4946 Do you want to stop the program?"), 4947 paddress (gdbarch, irp->orig_addr))) 4948 return -1; 4949 } 4950 4951 return 0; 4952 } 4953 4954 if (i386_record_lea_modrm_addr (irp, &addr)) 4955 return -1; 4956 4957 if (record_full_arch_list_add_mem (addr, 1 << irp->ot)) 4958 return -1; 4959 4960 return 0; 4961 } 4962 4963 /* Record the effects of a push operation. Return -1 if something 4964 goes wrong, 0 otherwise. */ 4965 4966 static int 4967 i386_record_push (struct i386_record_s *irp, int size) 4968 { 4969 ULONGEST addr; 4970 4971 if (record_full_arch_list_add_reg (irp->regcache, 4972 irp->regmap[X86_RECORD_RESP_REGNUM])) 4973 return -1; 4974 regcache_raw_read_unsigned (irp->regcache, 4975 irp->regmap[X86_RECORD_RESP_REGNUM], 4976 &addr); 4977 if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size)) 4978 return -1; 4979 4980 return 0; 4981 } 4982 4983 4984 /* Defines contents to record. */ 4985 #define I386_SAVE_FPU_REGS 0xfffd 4986 #define I386_SAVE_FPU_ENV 0xfffe 4987 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff 4988 4989 /* Record the values of the floating point registers which will be 4990 changed by the current instruction. Returns -1 if something is 4991 wrong, 0 otherwise. */ 4992 4993 static int i386_record_floats (struct gdbarch *gdbarch, 4994 struct i386_record_s *ir, 4995 uint32_t iregnum) 4996 { 4997 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 4998 int i; 4999 5000 /* Oza: Because of floating point insn push/pop of fpu stack is going to 5001 happen. Currently we store st0-st7 registers, but we need not store all 5002 registers all the time, in future we use ftag register and record only 5003 those who are not marked as an empty. */ 5004 5005 if (I386_SAVE_FPU_REGS == iregnum) 5006 { 5007 for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) 5008 { 5009 if (record_full_arch_list_add_reg (ir->regcache, i)) 5010 return -1; 5011 } 5012 } 5013 else if (I386_SAVE_FPU_ENV == iregnum) 5014 { 5015 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) 5016 { 5017 if (record_full_arch_list_add_reg (ir->regcache, i)) 5018 return -1; 5019 } 5020 } 5021 else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) 5022 { 5023 for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) 5024 { 5025 if (record_full_arch_list_add_reg (ir->regcache, i)) 5026 return -1; 5027 } 5028 } 5029 else if ((iregnum >= I387_ST0_REGNUM (tdep)) && 5030 (iregnum <= I387_FOP_REGNUM (tdep))) 5031 { 5032 if (record_full_arch_list_add_reg (ir->regcache,iregnum)) 5033 return -1; 5034 } 5035 else 5036 { 5037 /* Parameter error. */ 5038 return -1; 5039 } 5040 if(I386_SAVE_FPU_ENV != iregnum) 5041 { 5042 for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) 5043 { 5044 if (record_full_arch_list_add_reg (ir->regcache, i)) 5045 return -1; 5046 } 5047 } 5048 return 0; 5049 } 5050 5051 /* Parse the current instruction, and record the values of the 5052 registers and memory that will be changed by the current 5053 instruction. Returns -1 if something goes wrong, 0 otherwise. */ 5054 5055 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \ 5056 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) 5057 5058 int 5059 i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, 5060 CORE_ADDR input_addr) 5061 { 5062 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 5063 int prefixes = 0; 5064 int regnum = 0; 5065 uint32_t opcode; 5066 uint8_t opcode8; 5067 ULONGEST addr; 5068 gdb_byte buf[I386_MAX_REGISTER_SIZE]; 5069 struct i386_record_s ir; 5070 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 5071 uint8_t rex_w = -1; 5072 uint8_t rex_r = 0; 5073 5074 memset (&ir, 0, sizeof (struct i386_record_s)); 5075 ir.regcache = regcache; 5076 ir.addr = input_addr; 5077 ir.orig_addr = input_addr; 5078 ir.aflag = 1; 5079 ir.dflag = 1; 5080 ir.override = -1; 5081 ir.popl_esp_hack = 0; 5082 ir.regmap = tdep->record_regmap; 5083 ir.gdbarch = gdbarch; 5084 5085 if (record_debug > 1) 5086 fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " 5087 "addr = %s\n", 5088 paddress (gdbarch, ir.addr)); 5089 5090 /* prefixes */ 5091 while (1) 5092 { 5093 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) 5094 return -1; 5095 ir.addr++; 5096 switch (opcode8) /* Instruction prefixes */ 5097 { 5098 case REPE_PREFIX_OPCODE: 5099 prefixes |= PREFIX_REPZ; 5100 break; 5101 case REPNE_PREFIX_OPCODE: 5102 prefixes |= PREFIX_REPNZ; 5103 break; 5104 case LOCK_PREFIX_OPCODE: 5105 prefixes |= PREFIX_LOCK; 5106 break; 5107 case CS_PREFIX_OPCODE: 5108 ir.override = X86_RECORD_CS_REGNUM; 5109 break; 5110 case SS_PREFIX_OPCODE: 5111 ir.override = X86_RECORD_SS_REGNUM; 5112 break; 5113 case DS_PREFIX_OPCODE: 5114 ir.override = X86_RECORD_DS_REGNUM; 5115 break; 5116 case ES_PREFIX_OPCODE: 5117 ir.override = X86_RECORD_ES_REGNUM; 5118 break; 5119 case FS_PREFIX_OPCODE: 5120 ir.override = X86_RECORD_FS_REGNUM; 5121 break; 5122 case GS_PREFIX_OPCODE: 5123 ir.override = X86_RECORD_GS_REGNUM; 5124 break; 5125 case DATA_PREFIX_OPCODE: 5126 prefixes |= PREFIX_DATA; 5127 break; 5128 case ADDR_PREFIX_OPCODE: 5129 prefixes |= PREFIX_ADDR; 5130 break; 5131 case 0x40: /* i386 inc %eax */ 5132 case 0x41: /* i386 inc %ecx */ 5133 case 0x42: /* i386 inc %edx */ 5134 case 0x43: /* i386 inc %ebx */ 5135 case 0x44: /* i386 inc %esp */ 5136 case 0x45: /* i386 inc %ebp */ 5137 case 0x46: /* i386 inc %esi */ 5138 case 0x47: /* i386 inc %edi */ 5139 case 0x48: /* i386 dec %eax */ 5140 case 0x49: /* i386 dec %ecx */ 5141 case 0x4a: /* i386 dec %edx */ 5142 case 0x4b: /* i386 dec %ebx */ 5143 case 0x4c: /* i386 dec %esp */ 5144 case 0x4d: /* i386 dec %ebp */ 5145 case 0x4e: /* i386 dec %esi */ 5146 case 0x4f: /* i386 dec %edi */ 5147 if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ 5148 { 5149 /* REX */ 5150 rex_w = (opcode8 >> 3) & 1; 5151 rex_r = (opcode8 & 0x4) << 1; 5152 ir.rex_x = (opcode8 & 0x2) << 2; 5153 ir.rex_b = (opcode8 & 0x1) << 3; 5154 } 5155 else /* 32 bit target */ 5156 goto out_prefixes; 5157 break; 5158 default: 5159 goto out_prefixes; 5160 break; 5161 } 5162 } 5163 out_prefixes: 5164 if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) 5165 { 5166 ir.dflag = 2; 5167 } 5168 else 5169 { 5170 if (prefixes & PREFIX_DATA) 5171 ir.dflag ^= 1; 5172 } 5173 if (prefixes & PREFIX_ADDR) 5174 ir.aflag ^= 1; 5175 else if (ir.regmap[X86_RECORD_R8_REGNUM]) 5176 ir.aflag = 2; 5177 5178 /* Now check op code. */ 5179 opcode = (uint32_t) opcode8; 5180 reswitch: 5181 switch (opcode) 5182 { 5183 case 0x0f: 5184 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) 5185 return -1; 5186 ir.addr++; 5187 opcode = (uint32_t) opcode8 | 0x0f00; 5188 goto reswitch; 5189 break; 5190 5191 case 0x00: /* arith & logic */ 5192 case 0x01: 5193 case 0x02: 5194 case 0x03: 5195 case 0x04: 5196 case 0x05: 5197 case 0x08: 5198 case 0x09: 5199 case 0x0a: 5200 case 0x0b: 5201 case 0x0c: 5202 case 0x0d: 5203 case 0x10: 5204 case 0x11: 5205 case 0x12: 5206 case 0x13: 5207 case 0x14: 5208 case 0x15: 5209 case 0x18: 5210 case 0x19: 5211 case 0x1a: 5212 case 0x1b: 5213 case 0x1c: 5214 case 0x1d: 5215 case 0x20: 5216 case 0x21: 5217 case 0x22: 5218 case 0x23: 5219 case 0x24: 5220 case 0x25: 5221 case 0x28: 5222 case 0x29: 5223 case 0x2a: 5224 case 0x2b: 5225 case 0x2c: 5226 case 0x2d: 5227 case 0x30: 5228 case 0x31: 5229 case 0x32: 5230 case 0x33: 5231 case 0x34: 5232 case 0x35: 5233 case 0x38: 5234 case 0x39: 5235 case 0x3a: 5236 case 0x3b: 5237 case 0x3c: 5238 case 0x3d: 5239 if (((opcode >> 3) & 7) != OP_CMPL) 5240 { 5241 if ((opcode & 1) == 0) 5242 ir.ot = OT_BYTE; 5243 else 5244 ir.ot = ir.dflag + OT_WORD; 5245 5246 switch ((opcode >> 1) & 3) 5247 { 5248 case 0: /* OP Ev, Gv */ 5249 if (i386_record_modrm (&ir)) 5250 return -1; 5251 if (ir.mod != 3) 5252 { 5253 if (i386_record_lea_modrm (&ir)) 5254 return -1; 5255 } 5256 else 5257 { 5258 ir.rm |= ir.rex_b; 5259 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5260 ir.rm &= 0x3; 5261 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 5262 } 5263 break; 5264 case 1: /* OP Gv, Ev */ 5265 if (i386_record_modrm (&ir)) 5266 return -1; 5267 ir.reg |= rex_r; 5268 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5269 ir.reg &= 0x3; 5270 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5271 break; 5272 case 2: /* OP A, Iv */ 5273 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5274 break; 5275 } 5276 } 5277 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5278 break; 5279 5280 case 0x80: /* GRP1 */ 5281 case 0x81: 5282 case 0x82: 5283 case 0x83: 5284 if (i386_record_modrm (&ir)) 5285 return -1; 5286 5287 if (ir.reg != OP_CMPL) 5288 { 5289 if ((opcode & 1) == 0) 5290 ir.ot = OT_BYTE; 5291 else 5292 ir.ot = ir.dflag + OT_WORD; 5293 5294 if (ir.mod != 3) 5295 { 5296 if (opcode == 0x83) 5297 ir.rip_offset = 1; 5298 else 5299 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 5300 if (i386_record_lea_modrm (&ir)) 5301 return -1; 5302 } 5303 else 5304 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 5305 } 5306 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5307 break; 5308 5309 case 0x40: /* inc */ 5310 case 0x41: 5311 case 0x42: 5312 case 0x43: 5313 case 0x44: 5314 case 0x45: 5315 case 0x46: 5316 case 0x47: 5317 5318 case 0x48: /* dec */ 5319 case 0x49: 5320 case 0x4a: 5321 case 0x4b: 5322 case 0x4c: 5323 case 0x4d: 5324 case 0x4e: 5325 case 0x4f: 5326 5327 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7); 5328 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5329 break; 5330 5331 case 0xf6: /* GRP3 */ 5332 case 0xf7: 5333 if ((opcode & 1) == 0) 5334 ir.ot = OT_BYTE; 5335 else 5336 ir.ot = ir.dflag + OT_WORD; 5337 if (i386_record_modrm (&ir)) 5338 return -1; 5339 5340 if (ir.mod != 3 && ir.reg == 0) 5341 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 5342 5343 switch (ir.reg) 5344 { 5345 case 0: /* test */ 5346 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5347 break; 5348 case 2: /* not */ 5349 case 3: /* neg */ 5350 if (ir.mod != 3) 5351 { 5352 if (i386_record_lea_modrm (&ir)) 5353 return -1; 5354 } 5355 else 5356 { 5357 ir.rm |= ir.rex_b; 5358 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5359 ir.rm &= 0x3; 5360 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 5361 } 5362 if (ir.reg == 3) /* neg */ 5363 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5364 break; 5365 case 4: /* mul */ 5366 case 5: /* imul */ 5367 case 6: /* div */ 5368 case 7: /* idiv */ 5369 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5370 if (ir.ot != OT_BYTE) 5371 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 5372 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5373 break; 5374 default: 5375 ir.addr -= 2; 5376 opcode = opcode << 8 | ir.modrm; 5377 goto no_support; 5378 break; 5379 } 5380 break; 5381 5382 case 0xfe: /* GRP4 */ 5383 case 0xff: /* GRP5 */ 5384 if (i386_record_modrm (&ir)) 5385 return -1; 5386 if (ir.reg >= 2 && opcode == 0xfe) 5387 { 5388 ir.addr -= 2; 5389 opcode = opcode << 8 | ir.modrm; 5390 goto no_support; 5391 } 5392 switch (ir.reg) 5393 { 5394 case 0: /* inc */ 5395 case 1: /* dec */ 5396 if ((opcode & 1) == 0) 5397 ir.ot = OT_BYTE; 5398 else 5399 ir.ot = ir.dflag + OT_WORD; 5400 if (ir.mod != 3) 5401 { 5402 if (i386_record_lea_modrm (&ir)) 5403 return -1; 5404 } 5405 else 5406 { 5407 ir.rm |= ir.rex_b; 5408 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5409 ir.rm &= 0x3; 5410 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 5411 } 5412 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5413 break; 5414 case 2: /* call */ 5415 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 5416 ir.dflag = 2; 5417 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5418 return -1; 5419 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5420 break; 5421 case 3: /* lcall */ 5422 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); 5423 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5424 return -1; 5425 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5426 break; 5427 case 4: /* jmp */ 5428 case 5: /* ljmp */ 5429 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5430 break; 5431 case 6: /* push */ 5432 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 5433 ir.dflag = 2; 5434 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5435 return -1; 5436 break; 5437 default: 5438 ir.addr -= 2; 5439 opcode = opcode << 8 | ir.modrm; 5440 goto no_support; 5441 break; 5442 } 5443 break; 5444 5445 case 0x84: /* test */ 5446 case 0x85: 5447 case 0xa8: 5448 case 0xa9: 5449 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5450 break; 5451 5452 case 0x98: /* CWDE/CBW */ 5453 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5454 break; 5455 5456 case 0x99: /* CDQ/CWD */ 5457 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5458 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 5459 break; 5460 5461 case 0x0faf: /* imul */ 5462 case 0x69: 5463 case 0x6b: 5464 ir.ot = ir.dflag + OT_WORD; 5465 if (i386_record_modrm (&ir)) 5466 return -1; 5467 if (opcode == 0x69) 5468 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 5469 else if (opcode == 0x6b) 5470 ir.rip_offset = 1; 5471 ir.reg |= rex_r; 5472 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5473 ir.reg &= 0x3; 5474 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5475 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5476 break; 5477 5478 case 0x0fc0: /* xadd */ 5479 case 0x0fc1: 5480 if ((opcode & 1) == 0) 5481 ir.ot = OT_BYTE; 5482 else 5483 ir.ot = ir.dflag + OT_WORD; 5484 if (i386_record_modrm (&ir)) 5485 return -1; 5486 ir.reg |= rex_r; 5487 if (ir.mod == 3) 5488 { 5489 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5490 ir.reg &= 0x3; 5491 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5492 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5493 ir.rm &= 0x3; 5494 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 5495 } 5496 else 5497 { 5498 if (i386_record_lea_modrm (&ir)) 5499 return -1; 5500 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5501 ir.reg &= 0x3; 5502 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5503 } 5504 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5505 break; 5506 5507 case 0x0fb0: /* cmpxchg */ 5508 case 0x0fb1: 5509 if ((opcode & 1) == 0) 5510 ir.ot = OT_BYTE; 5511 else 5512 ir.ot = ir.dflag + OT_WORD; 5513 if (i386_record_modrm (&ir)) 5514 return -1; 5515 if (ir.mod == 3) 5516 { 5517 ir.reg |= rex_r; 5518 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5519 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5520 ir.reg &= 0x3; 5521 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5522 } 5523 else 5524 { 5525 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5526 if (i386_record_lea_modrm (&ir)) 5527 return -1; 5528 } 5529 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5530 break; 5531 5532 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */ 5533 if (i386_record_modrm (&ir)) 5534 return -1; 5535 if (ir.mod == 3) 5536 { 5537 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as 5538 an extended opcode. rdrand has bits 110 (/6) and rdseed 5539 has bits 111 (/7). */ 5540 if (ir.reg == 6 || ir.reg == 7) 5541 { 5542 /* The storage register is described by the 3 R/M bits, but the 5543 REX.B prefix may be used to give access to registers 5544 R8~R15. In this case ir.rex_b + R/M will give us the register 5545 in the range R8~R15. 5546 5547 REX.W may also be used to access 64-bit registers, but we 5548 already record entire registers and not just partial bits 5549 of them. */ 5550 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm); 5551 /* These instructions also set conditional bits. */ 5552 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5553 break; 5554 } 5555 else 5556 { 5557 /* We don't handle this particular instruction yet. */ 5558 ir.addr -= 2; 5559 opcode = opcode << 8 | ir.modrm; 5560 goto no_support; 5561 } 5562 } 5563 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5564 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 5565 if (i386_record_lea_modrm (&ir)) 5566 return -1; 5567 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5568 break; 5569 5570 case 0x50: /* push */ 5571 case 0x51: 5572 case 0x52: 5573 case 0x53: 5574 case 0x54: 5575 case 0x55: 5576 case 0x56: 5577 case 0x57: 5578 case 0x68: 5579 case 0x6a: 5580 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 5581 ir.dflag = 2; 5582 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5583 return -1; 5584 break; 5585 5586 case 0x06: /* push es */ 5587 case 0x0e: /* push cs */ 5588 case 0x16: /* push ss */ 5589 case 0x1e: /* push ds */ 5590 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5591 { 5592 ir.addr -= 1; 5593 goto no_support; 5594 } 5595 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5596 return -1; 5597 break; 5598 5599 case 0x0fa0: /* push fs */ 5600 case 0x0fa8: /* push gs */ 5601 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5602 { 5603 ir.addr -= 2; 5604 goto no_support; 5605 } 5606 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5607 return -1; 5608 break; 5609 5610 case 0x60: /* pusha */ 5611 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5612 { 5613 ir.addr -= 1; 5614 goto no_support; 5615 } 5616 if (i386_record_push (&ir, 1 << (ir.dflag + 4))) 5617 return -1; 5618 break; 5619 5620 case 0x58: /* pop */ 5621 case 0x59: 5622 case 0x5a: 5623 case 0x5b: 5624 case 0x5c: 5625 case 0x5d: 5626 case 0x5e: 5627 case 0x5f: 5628 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5629 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); 5630 break; 5631 5632 case 0x61: /* popa */ 5633 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5634 { 5635 ir.addr -= 1; 5636 goto no_support; 5637 } 5638 for (regnum = X86_RECORD_REAX_REGNUM; 5639 regnum <= X86_RECORD_REDI_REGNUM; 5640 regnum++) 5641 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); 5642 break; 5643 5644 case 0x8f: /* pop */ 5645 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5646 ir.ot = ir.dflag ? OT_QUAD : OT_WORD; 5647 else 5648 ir.ot = ir.dflag + OT_WORD; 5649 if (i386_record_modrm (&ir)) 5650 return -1; 5651 if (ir.mod == 3) 5652 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 5653 else 5654 { 5655 ir.popl_esp_hack = 1 << ir.ot; 5656 if (i386_record_lea_modrm (&ir)) 5657 return -1; 5658 } 5659 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5660 break; 5661 5662 case 0xc8: /* enter */ 5663 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); 5664 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 5665 ir.dflag = 2; 5666 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 5667 return -1; 5668 break; 5669 5670 case 0xc9: /* leave */ 5671 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5672 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); 5673 break; 5674 5675 case 0x07: /* pop es */ 5676 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5677 { 5678 ir.addr -= 1; 5679 goto no_support; 5680 } 5681 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5682 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); 5683 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5684 break; 5685 5686 case 0x17: /* pop ss */ 5687 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5688 { 5689 ir.addr -= 1; 5690 goto no_support; 5691 } 5692 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5693 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); 5694 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5695 break; 5696 5697 case 0x1f: /* pop ds */ 5698 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5699 { 5700 ir.addr -= 1; 5701 goto no_support; 5702 } 5703 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5704 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); 5705 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5706 break; 5707 5708 case 0x0fa1: /* pop fs */ 5709 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5710 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); 5711 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5712 break; 5713 5714 case 0x0fa9: /* pop gs */ 5715 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 5716 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); 5717 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5718 break; 5719 5720 case 0x88: /* mov */ 5721 case 0x89: 5722 case 0xc6: 5723 case 0xc7: 5724 if ((opcode & 1) == 0) 5725 ir.ot = OT_BYTE; 5726 else 5727 ir.ot = ir.dflag + OT_WORD; 5728 5729 if (i386_record_modrm (&ir)) 5730 return -1; 5731 5732 if (ir.mod != 3) 5733 { 5734 if (opcode == 0xc6 || opcode == 0xc7) 5735 ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); 5736 if (i386_record_lea_modrm (&ir)) 5737 return -1; 5738 } 5739 else 5740 { 5741 if (opcode == 0xc6 || opcode == 0xc7) 5742 ir.rm |= ir.rex_b; 5743 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5744 ir.rm &= 0x3; 5745 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 5746 } 5747 break; 5748 5749 case 0x8a: /* mov */ 5750 case 0x8b: 5751 if ((opcode & 1) == 0) 5752 ir.ot = OT_BYTE; 5753 else 5754 ir.ot = ir.dflag + OT_WORD; 5755 if (i386_record_modrm (&ir)) 5756 return -1; 5757 ir.reg |= rex_r; 5758 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5759 ir.reg &= 0x3; 5760 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5761 break; 5762 5763 case 0x8c: /* mov seg */ 5764 if (i386_record_modrm (&ir)) 5765 return -1; 5766 if (ir.reg > 5) 5767 { 5768 ir.addr -= 2; 5769 opcode = opcode << 8 | ir.modrm; 5770 goto no_support; 5771 } 5772 5773 if (ir.mod == 3) 5774 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 5775 else 5776 { 5777 ir.ot = OT_WORD; 5778 if (i386_record_lea_modrm (&ir)) 5779 return -1; 5780 } 5781 break; 5782 5783 case 0x8e: /* mov seg */ 5784 if (i386_record_modrm (&ir)) 5785 return -1; 5786 switch (ir.reg) 5787 { 5788 case 0: 5789 regnum = X86_RECORD_ES_REGNUM; 5790 break; 5791 case 2: 5792 regnum = X86_RECORD_SS_REGNUM; 5793 break; 5794 case 3: 5795 regnum = X86_RECORD_DS_REGNUM; 5796 break; 5797 case 4: 5798 regnum = X86_RECORD_FS_REGNUM; 5799 break; 5800 case 5: 5801 regnum = X86_RECORD_GS_REGNUM; 5802 break; 5803 default: 5804 ir.addr -= 2; 5805 opcode = opcode << 8 | ir.modrm; 5806 goto no_support; 5807 break; 5808 } 5809 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); 5810 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5811 break; 5812 5813 case 0x0fb6: /* movzbS */ 5814 case 0x0fb7: /* movzwS */ 5815 case 0x0fbe: /* movsbS */ 5816 case 0x0fbf: /* movswS */ 5817 if (i386_record_modrm (&ir)) 5818 return -1; 5819 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); 5820 break; 5821 5822 case 0x8d: /* lea */ 5823 if (i386_record_modrm (&ir)) 5824 return -1; 5825 if (ir.mod == 3) 5826 { 5827 ir.addr -= 2; 5828 opcode = opcode << 8 | ir.modrm; 5829 goto no_support; 5830 } 5831 ir.ot = ir.dflag; 5832 ir.reg |= rex_r; 5833 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5834 ir.reg &= 0x3; 5835 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5836 break; 5837 5838 case 0xa0: /* mov EAX */ 5839 case 0xa1: 5840 5841 case 0xd7: /* xlat */ 5842 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5843 break; 5844 5845 case 0xa2: /* mov EAX */ 5846 case 0xa3: 5847 if (ir.override >= 0) 5848 { 5849 if (record_full_memory_query) 5850 { 5851 if (yquery (_("\ 5852 Process record ignores the memory change of instruction at address %s\n\ 5853 because it can't get the value of the segment register.\n\ 5854 Do you want to stop the program?"), 5855 paddress (gdbarch, ir.orig_addr))) 5856 return -1; 5857 } 5858 } 5859 else 5860 { 5861 if ((opcode & 1) == 0) 5862 ir.ot = OT_BYTE; 5863 else 5864 ir.ot = ir.dflag + OT_WORD; 5865 if (ir.aflag == 2) 5866 { 5867 if (record_read_memory (gdbarch, ir.addr, buf, 8)) 5868 return -1; 5869 ir.addr += 8; 5870 addr = extract_unsigned_integer (buf, 8, byte_order); 5871 } 5872 else if (ir.aflag) 5873 { 5874 if (record_read_memory (gdbarch, ir.addr, buf, 4)) 5875 return -1; 5876 ir.addr += 4; 5877 addr = extract_unsigned_integer (buf, 4, byte_order); 5878 } 5879 else 5880 { 5881 if (record_read_memory (gdbarch, ir.addr, buf, 2)) 5882 return -1; 5883 ir.addr += 2; 5884 addr = extract_unsigned_integer (buf, 2, byte_order); 5885 } 5886 if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) 5887 return -1; 5888 } 5889 break; 5890 5891 case 0xb0: /* mov R, Ib */ 5892 case 0xb1: 5893 case 0xb2: 5894 case 0xb3: 5895 case 0xb4: 5896 case 0xb5: 5897 case 0xb6: 5898 case 0xb7: 5899 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) 5900 ? ((opcode & 0x7) | ir.rex_b) 5901 : ((opcode & 0x7) & 0x3)); 5902 break; 5903 5904 case 0xb8: /* mov R, Iv */ 5905 case 0xb9: 5906 case 0xba: 5907 case 0xbb: 5908 case 0xbc: 5909 case 0xbd: 5910 case 0xbe: 5911 case 0xbf: 5912 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); 5913 break; 5914 5915 case 0x91: /* xchg R, EAX */ 5916 case 0x92: 5917 case 0x93: 5918 case 0x94: 5919 case 0x95: 5920 case 0x96: 5921 case 0x97: 5922 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 5923 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7); 5924 break; 5925 5926 case 0x86: /* xchg Ev, Gv */ 5927 case 0x87: 5928 if ((opcode & 1) == 0) 5929 ir.ot = OT_BYTE; 5930 else 5931 ir.ot = ir.dflag + OT_WORD; 5932 if (i386_record_modrm (&ir)) 5933 return -1; 5934 if (ir.mod == 3) 5935 { 5936 ir.rm |= ir.rex_b; 5937 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5938 ir.rm &= 0x3; 5939 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 5940 } 5941 else 5942 { 5943 if (i386_record_lea_modrm (&ir)) 5944 return -1; 5945 } 5946 ir.reg |= rex_r; 5947 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 5948 ir.reg &= 0x3; 5949 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 5950 break; 5951 5952 case 0xc4: /* les Gv */ 5953 case 0xc5: /* lds Gv */ 5954 if (ir.regmap[X86_RECORD_R8_REGNUM]) 5955 { 5956 ir.addr -= 1; 5957 goto no_support; 5958 } 5959 /* FALLTHROUGH */ 5960 case 0x0fb2: /* lss Gv */ 5961 case 0x0fb4: /* lfs Gv */ 5962 case 0x0fb5: /* lgs Gv */ 5963 if (i386_record_modrm (&ir)) 5964 return -1; 5965 if (ir.mod == 3) 5966 { 5967 if (opcode > 0xff) 5968 ir.addr -= 3; 5969 else 5970 ir.addr -= 2; 5971 opcode = opcode << 8 | ir.modrm; 5972 goto no_support; 5973 } 5974 switch (opcode) 5975 { 5976 case 0xc4: /* les Gv */ 5977 regnum = X86_RECORD_ES_REGNUM; 5978 break; 5979 case 0xc5: /* lds Gv */ 5980 regnum = X86_RECORD_DS_REGNUM; 5981 break; 5982 case 0x0fb2: /* lss Gv */ 5983 regnum = X86_RECORD_SS_REGNUM; 5984 break; 5985 case 0x0fb4: /* lfs Gv */ 5986 regnum = X86_RECORD_FS_REGNUM; 5987 break; 5988 case 0x0fb5: /* lgs Gv */ 5989 regnum = X86_RECORD_GS_REGNUM; 5990 break; 5991 } 5992 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); 5993 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); 5994 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 5995 break; 5996 5997 case 0xc0: /* shifts */ 5998 case 0xc1: 5999 case 0xd0: 6000 case 0xd1: 6001 case 0xd2: 6002 case 0xd3: 6003 if ((opcode & 1) == 0) 6004 ir.ot = OT_BYTE; 6005 else 6006 ir.ot = ir.dflag + OT_WORD; 6007 if (i386_record_modrm (&ir)) 6008 return -1; 6009 if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) 6010 { 6011 if (i386_record_lea_modrm (&ir)) 6012 return -1; 6013 } 6014 else 6015 { 6016 ir.rm |= ir.rex_b; 6017 if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) 6018 ir.rm &= 0x3; 6019 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); 6020 } 6021 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6022 break; 6023 6024 case 0x0fa4: 6025 case 0x0fa5: 6026 case 0x0fac: 6027 case 0x0fad: 6028 if (i386_record_modrm (&ir)) 6029 return -1; 6030 if (ir.mod == 3) 6031 { 6032 if (record_full_arch_list_add_reg (ir.regcache, ir.rm)) 6033 return -1; 6034 } 6035 else 6036 { 6037 if (i386_record_lea_modrm (&ir)) 6038 return -1; 6039 } 6040 break; 6041 6042 case 0xd8: /* Floats. */ 6043 case 0xd9: 6044 case 0xda: 6045 case 0xdb: 6046 case 0xdc: 6047 case 0xdd: 6048 case 0xde: 6049 case 0xdf: 6050 if (i386_record_modrm (&ir)) 6051 return -1; 6052 ir.reg |= ((opcode & 7) << 3); 6053 if (ir.mod != 3) 6054 { 6055 /* Memory. */ 6056 uint64_t addr64; 6057 6058 if (i386_record_lea_modrm_addr (&ir, &addr64)) 6059 return -1; 6060 switch (ir.reg) 6061 { 6062 case 0x02: 6063 case 0x12: 6064 case 0x22: 6065 case 0x32: 6066 /* For fcom, ficom nothing to do. */ 6067 break; 6068 case 0x03: 6069 case 0x13: 6070 case 0x23: 6071 case 0x33: 6072 /* For fcomp, ficomp pop FPU stack, store all. */ 6073 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 6074 return -1; 6075 break; 6076 case 0x00: 6077 case 0x01: 6078 case 0x04: 6079 case 0x05: 6080 case 0x06: 6081 case 0x07: 6082 case 0x10: 6083 case 0x11: 6084 case 0x14: 6085 case 0x15: 6086 case 0x16: 6087 case 0x17: 6088 case 0x20: 6089 case 0x21: 6090 case 0x24: 6091 case 0x25: 6092 case 0x26: 6093 case 0x27: 6094 case 0x30: 6095 case 0x31: 6096 case 0x34: 6097 case 0x35: 6098 case 0x36: 6099 case 0x37: 6100 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, 6101 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension 6102 of code, always affects st(0) register. */ 6103 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) 6104 return -1; 6105 break; 6106 case 0x08: 6107 case 0x0a: 6108 case 0x0b: 6109 case 0x18: 6110 case 0x19: 6111 case 0x1a: 6112 case 0x1b: 6113 case 0x1d: 6114 case 0x28: 6115 case 0x29: 6116 case 0x2a: 6117 case 0x2b: 6118 case 0x38: 6119 case 0x39: 6120 case 0x3a: 6121 case 0x3b: 6122 case 0x3c: 6123 case 0x3d: 6124 switch (ir.reg & 7) 6125 { 6126 case 0: 6127 /* Handling fld, fild. */ 6128 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 6129 return -1; 6130 break; 6131 case 1: 6132 switch (ir.reg >> 4) 6133 { 6134 case 0: 6135 if (record_full_arch_list_add_mem (addr64, 4)) 6136 return -1; 6137 break; 6138 case 2: 6139 if (record_full_arch_list_add_mem (addr64, 8)) 6140 return -1; 6141 break; 6142 case 3: 6143 break; 6144 default: 6145 if (record_full_arch_list_add_mem (addr64, 2)) 6146 return -1; 6147 break; 6148 } 6149 break; 6150 default: 6151 switch (ir.reg >> 4) 6152 { 6153 case 0: 6154 if (record_full_arch_list_add_mem (addr64, 4)) 6155 return -1; 6156 if (3 == (ir.reg & 7)) 6157 { 6158 /* For fstp m32fp. */ 6159 if (i386_record_floats (gdbarch, &ir, 6160 I386_SAVE_FPU_REGS)) 6161 return -1; 6162 } 6163 break; 6164 case 1: 6165 if (record_full_arch_list_add_mem (addr64, 4)) 6166 return -1; 6167 if ((3 == (ir.reg & 7)) 6168 || (5 == (ir.reg & 7)) 6169 || (7 == (ir.reg & 7))) 6170 { 6171 /* For fstp insn. */ 6172 if (i386_record_floats (gdbarch, &ir, 6173 I386_SAVE_FPU_REGS)) 6174 return -1; 6175 } 6176 break; 6177 case 2: 6178 if (record_full_arch_list_add_mem (addr64, 8)) 6179 return -1; 6180 if (3 == (ir.reg & 7)) 6181 { 6182 /* For fstp m64fp. */ 6183 if (i386_record_floats (gdbarch, &ir, 6184 I386_SAVE_FPU_REGS)) 6185 return -1; 6186 } 6187 break; 6188 case 3: 6189 if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) 6190 { 6191 /* For fistp, fbld, fild, fbstp. */ 6192 if (i386_record_floats (gdbarch, &ir, 6193 I386_SAVE_FPU_REGS)) 6194 return -1; 6195 } 6196 /* Fall through */ 6197 default: 6198 if (record_full_arch_list_add_mem (addr64, 2)) 6199 return -1; 6200 break; 6201 } 6202 break; 6203 } 6204 break; 6205 case 0x0c: 6206 /* Insn fldenv. */ 6207 if (i386_record_floats (gdbarch, &ir, 6208 I386_SAVE_FPU_ENV_REG_STACK)) 6209 return -1; 6210 break; 6211 case 0x0d: 6212 /* Insn fldcw. */ 6213 if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) 6214 return -1; 6215 break; 6216 case 0x2c: 6217 /* Insn frstor. */ 6218 if (i386_record_floats (gdbarch, &ir, 6219 I386_SAVE_FPU_ENV_REG_STACK)) 6220 return -1; 6221 break; 6222 case 0x0e: 6223 if (ir.dflag) 6224 { 6225 if (record_full_arch_list_add_mem (addr64, 28)) 6226 return -1; 6227 } 6228 else 6229 { 6230 if (record_full_arch_list_add_mem (addr64, 14)) 6231 return -1; 6232 } 6233 break; 6234 case 0x0f: 6235 case 0x2f: 6236 if (record_full_arch_list_add_mem (addr64, 2)) 6237 return -1; 6238 /* Insn fstp, fbstp. */ 6239 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 6240 return -1; 6241 break; 6242 case 0x1f: 6243 case 0x3e: 6244 if (record_full_arch_list_add_mem (addr64, 10)) 6245 return -1; 6246 break; 6247 case 0x2e: 6248 if (ir.dflag) 6249 { 6250 if (record_full_arch_list_add_mem (addr64, 28)) 6251 return -1; 6252 addr64 += 28; 6253 } 6254 else 6255 { 6256 if (record_full_arch_list_add_mem (addr64, 14)) 6257 return -1; 6258 addr64 += 14; 6259 } 6260 if (record_full_arch_list_add_mem (addr64, 80)) 6261 return -1; 6262 /* Insn fsave. */ 6263 if (i386_record_floats (gdbarch, &ir, 6264 I386_SAVE_FPU_ENV_REG_STACK)) 6265 return -1; 6266 break; 6267 case 0x3f: 6268 if (record_full_arch_list_add_mem (addr64, 8)) 6269 return -1; 6270 /* Insn fistp. */ 6271 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 6272 return -1; 6273 break; 6274 default: 6275 ir.addr -= 2; 6276 opcode = opcode << 8 | ir.modrm; 6277 goto no_support; 6278 break; 6279 } 6280 } 6281 /* Opcode is an extension of modR/M byte. */ 6282 else 6283 { 6284 switch (opcode) 6285 { 6286 case 0xd8: 6287 if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) 6288 return -1; 6289 break; 6290 case 0xd9: 6291 if (0x0c == (ir.modrm >> 4)) 6292 { 6293 if ((ir.modrm & 0x0f) <= 7) 6294 { 6295 if (i386_record_floats (gdbarch, &ir, 6296 I386_SAVE_FPU_REGS)) 6297 return -1; 6298 } 6299 else 6300 { 6301 if (i386_record_floats (gdbarch, &ir, 6302 I387_ST0_REGNUM (tdep))) 6303 return -1; 6304 /* If only st(0) is changing, then we have already 6305 recorded. */ 6306 if ((ir.modrm & 0x0f) - 0x08) 6307 { 6308 if (i386_record_floats (gdbarch, &ir, 6309 I387_ST0_REGNUM (tdep) + 6310 ((ir.modrm & 0x0f) - 0x08))) 6311 return -1; 6312 } 6313 } 6314 } 6315 else 6316 { 6317 switch (ir.modrm) 6318 { 6319 case 0xe0: 6320 case 0xe1: 6321 case 0xf0: 6322 case 0xf5: 6323 case 0xf8: 6324 case 0xfa: 6325 case 0xfc: 6326 case 0xfe: 6327 case 0xff: 6328 if (i386_record_floats (gdbarch, &ir, 6329 I387_ST0_REGNUM (tdep))) 6330 return -1; 6331 break; 6332 case 0xf1: 6333 case 0xf2: 6334 case 0xf3: 6335 case 0xf4: 6336 case 0xf6: 6337 case 0xf7: 6338 case 0xe8: 6339 case 0xe9: 6340 case 0xea: 6341 case 0xeb: 6342 case 0xec: 6343 case 0xed: 6344 case 0xee: 6345 case 0xf9: 6346 case 0xfb: 6347 if (i386_record_floats (gdbarch, &ir, 6348 I386_SAVE_FPU_REGS)) 6349 return -1; 6350 break; 6351 case 0xfd: 6352 if (i386_record_floats (gdbarch, &ir, 6353 I387_ST0_REGNUM (tdep))) 6354 return -1; 6355 if (i386_record_floats (gdbarch, &ir, 6356 I387_ST0_REGNUM (tdep) + 1)) 6357 return -1; 6358 break; 6359 } 6360 } 6361 break; 6362 case 0xda: 6363 if (0xe9 == ir.modrm) 6364 { 6365 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 6366 return -1; 6367 } 6368 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) 6369 { 6370 if (i386_record_floats (gdbarch, &ir, 6371 I387_ST0_REGNUM (tdep))) 6372 return -1; 6373 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) 6374 { 6375 if (i386_record_floats (gdbarch, &ir, 6376 I387_ST0_REGNUM (tdep) + 6377 (ir.modrm & 0x0f))) 6378 return -1; 6379 } 6380 else if ((ir.modrm & 0x0f) - 0x08) 6381 { 6382 if (i386_record_floats (gdbarch, &ir, 6383 I387_ST0_REGNUM (tdep) + 6384 ((ir.modrm & 0x0f) - 0x08))) 6385 return -1; 6386 } 6387 } 6388 break; 6389 case 0xdb: 6390 if (0xe3 == ir.modrm) 6391 { 6392 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) 6393 return -1; 6394 } 6395 else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) 6396 { 6397 if (i386_record_floats (gdbarch, &ir, 6398 I387_ST0_REGNUM (tdep))) 6399 return -1; 6400 if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) 6401 { 6402 if (i386_record_floats (gdbarch, &ir, 6403 I387_ST0_REGNUM (tdep) + 6404 (ir.modrm & 0x0f))) 6405 return -1; 6406 } 6407 else if ((ir.modrm & 0x0f) - 0x08) 6408 { 6409 if (i386_record_floats (gdbarch, &ir, 6410 I387_ST0_REGNUM (tdep) + 6411 ((ir.modrm & 0x0f) - 0x08))) 6412 return -1; 6413 } 6414 } 6415 break; 6416 case 0xdc: 6417 if ((0x0c == ir.modrm >> 4) 6418 || (0x0d == ir.modrm >> 4) 6419 || (0x0f == ir.modrm >> 4)) 6420 { 6421 if ((ir.modrm & 0x0f) <= 7) 6422 { 6423 if (i386_record_floats (gdbarch, &ir, 6424 I387_ST0_REGNUM (tdep) + 6425 (ir.modrm & 0x0f))) 6426 return -1; 6427 } 6428 else 6429 { 6430 if (i386_record_floats (gdbarch, &ir, 6431 I387_ST0_REGNUM (tdep) + 6432 ((ir.modrm & 0x0f) - 0x08))) 6433 return -1; 6434 } 6435 } 6436 break; 6437 case 0xdd: 6438 if (0x0c == ir.modrm >> 4) 6439 { 6440 if (i386_record_floats (gdbarch, &ir, 6441 I387_FTAG_REGNUM (tdep))) 6442 return -1; 6443 } 6444 else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) 6445 { 6446 if ((ir.modrm & 0x0f) <= 7) 6447 { 6448 if (i386_record_floats (gdbarch, &ir, 6449 I387_ST0_REGNUM (tdep) + 6450 (ir.modrm & 0x0f))) 6451 return -1; 6452 } 6453 else 6454 { 6455 if (i386_record_floats (gdbarch, &ir, 6456 I386_SAVE_FPU_REGS)) 6457 return -1; 6458 } 6459 } 6460 break; 6461 case 0xde: 6462 if ((0x0c == ir.modrm >> 4) 6463 || (0x0e == ir.modrm >> 4) 6464 || (0x0f == ir.modrm >> 4) 6465 || (0xd9 == ir.modrm)) 6466 { 6467 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 6468 return -1; 6469 } 6470 break; 6471 case 0xdf: 6472 if (0xe0 == ir.modrm) 6473 { 6474 if (record_full_arch_list_add_reg (ir.regcache, 6475 I386_EAX_REGNUM)) 6476 return -1; 6477 } 6478 else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) 6479 { 6480 if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) 6481 return -1; 6482 } 6483 break; 6484 } 6485 } 6486 break; 6487 /* string ops */ 6488 case 0xa4: /* movsS */ 6489 case 0xa5: 6490 case 0xaa: /* stosS */ 6491 case 0xab: 6492 case 0x6c: /* insS */ 6493 case 0x6d: 6494 regcache_raw_read_unsigned (ir.regcache, 6495 ir.regmap[X86_RECORD_RECX_REGNUM], 6496 &addr); 6497 if (addr) 6498 { 6499 ULONGEST es, ds; 6500 6501 if ((opcode & 1) == 0) 6502 ir.ot = OT_BYTE; 6503 else 6504 ir.ot = ir.dflag + OT_WORD; 6505 regcache_raw_read_unsigned (ir.regcache, 6506 ir.regmap[X86_RECORD_REDI_REGNUM], 6507 &addr); 6508 6509 regcache_raw_read_unsigned (ir.regcache, 6510 ir.regmap[X86_RECORD_ES_REGNUM], 6511 &es); 6512 regcache_raw_read_unsigned (ir.regcache, 6513 ir.regmap[X86_RECORD_DS_REGNUM], 6514 &ds); 6515 if (ir.aflag && (es != ds)) 6516 { 6517 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ 6518 if (record_full_memory_query) 6519 { 6520 if (yquery (_("\ 6521 Process record ignores the memory change of instruction at address %s\n\ 6522 because it can't get the value of the segment register.\n\ 6523 Do you want to stop the program?"), 6524 paddress (gdbarch, ir.orig_addr))) 6525 return -1; 6526 } 6527 } 6528 else 6529 { 6530 if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) 6531 return -1; 6532 } 6533 6534 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 6535 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 6536 if (opcode == 0xa4 || opcode == 0xa5) 6537 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 6538 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 6539 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6540 } 6541 break; 6542 6543 case 0xa6: /* cmpsS */ 6544 case 0xa7: 6545 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 6546 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 6547 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 6548 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 6549 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6550 break; 6551 6552 case 0xac: /* lodsS */ 6553 case 0xad: 6554 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 6555 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 6556 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 6557 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 6558 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6559 break; 6560 6561 case 0xae: /* scasS */ 6562 case 0xaf: 6563 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 6564 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 6565 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 6566 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6567 break; 6568 6569 case 0x6e: /* outsS */ 6570 case 0x6f: 6571 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 6572 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) 6573 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 6574 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6575 break; 6576 6577 case 0xe4: /* port I/O */ 6578 case 0xe5: 6579 case 0xec: 6580 case 0xed: 6581 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6582 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 6583 break; 6584 6585 case 0xe6: 6586 case 0xe7: 6587 case 0xee: 6588 case 0xef: 6589 break; 6590 6591 /* control */ 6592 case 0xc2: /* ret im */ 6593 case 0xc3: /* ret */ 6594 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 6595 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6596 break; 6597 6598 case 0xca: /* lret im */ 6599 case 0xcb: /* lret */ 6600 case 0xcf: /* iret */ 6601 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); 6602 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 6603 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6604 break; 6605 6606 case 0xe8: /* call im */ 6607 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 6608 ir.dflag = 2; 6609 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 6610 return -1; 6611 break; 6612 6613 case 0x9a: /* lcall im */ 6614 if (ir.regmap[X86_RECORD_R8_REGNUM]) 6615 { 6616 ir.addr -= 1; 6617 goto no_support; 6618 } 6619 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); 6620 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 6621 return -1; 6622 break; 6623 6624 case 0xe9: /* jmp im */ 6625 case 0xea: /* ljmp im */ 6626 case 0xeb: /* jmp Jb */ 6627 case 0x70: /* jcc Jb */ 6628 case 0x71: 6629 case 0x72: 6630 case 0x73: 6631 case 0x74: 6632 case 0x75: 6633 case 0x76: 6634 case 0x77: 6635 case 0x78: 6636 case 0x79: 6637 case 0x7a: 6638 case 0x7b: 6639 case 0x7c: 6640 case 0x7d: 6641 case 0x7e: 6642 case 0x7f: 6643 case 0x0f80: /* jcc Jv */ 6644 case 0x0f81: 6645 case 0x0f82: 6646 case 0x0f83: 6647 case 0x0f84: 6648 case 0x0f85: 6649 case 0x0f86: 6650 case 0x0f87: 6651 case 0x0f88: 6652 case 0x0f89: 6653 case 0x0f8a: 6654 case 0x0f8b: 6655 case 0x0f8c: 6656 case 0x0f8d: 6657 case 0x0f8e: 6658 case 0x0f8f: 6659 break; 6660 6661 case 0x0f90: /* setcc Gv */ 6662 case 0x0f91: 6663 case 0x0f92: 6664 case 0x0f93: 6665 case 0x0f94: 6666 case 0x0f95: 6667 case 0x0f96: 6668 case 0x0f97: 6669 case 0x0f98: 6670 case 0x0f99: 6671 case 0x0f9a: 6672 case 0x0f9b: 6673 case 0x0f9c: 6674 case 0x0f9d: 6675 case 0x0f9e: 6676 case 0x0f9f: 6677 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6678 ir.ot = OT_BYTE; 6679 if (i386_record_modrm (&ir)) 6680 return -1; 6681 if (ir.mod == 3) 6682 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) 6683 : (ir.rm & 0x3)); 6684 else 6685 { 6686 if (i386_record_lea_modrm (&ir)) 6687 return -1; 6688 } 6689 break; 6690 6691 case 0x0f40: /* cmov Gv, Ev */ 6692 case 0x0f41: 6693 case 0x0f42: 6694 case 0x0f43: 6695 case 0x0f44: 6696 case 0x0f45: 6697 case 0x0f46: 6698 case 0x0f47: 6699 case 0x0f48: 6700 case 0x0f49: 6701 case 0x0f4a: 6702 case 0x0f4b: 6703 case 0x0f4c: 6704 case 0x0f4d: 6705 case 0x0f4e: 6706 case 0x0f4f: 6707 if (i386_record_modrm (&ir)) 6708 return -1; 6709 ir.reg |= rex_r; 6710 if (ir.dflag == OT_BYTE) 6711 ir.reg &= 0x3; 6712 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 6713 break; 6714 6715 /* flags */ 6716 case 0x9c: /* pushf */ 6717 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6718 if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) 6719 ir.dflag = 2; 6720 if (i386_record_push (&ir, 1 << (ir.dflag + 1))) 6721 return -1; 6722 break; 6723 6724 case 0x9d: /* popf */ 6725 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 6726 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6727 break; 6728 6729 case 0x9e: /* sahf */ 6730 if (ir.regmap[X86_RECORD_R8_REGNUM]) 6731 { 6732 ir.addr -= 1; 6733 goto no_support; 6734 } 6735 /* FALLTHROUGH */ 6736 case 0xf5: /* cmc */ 6737 case 0xf8: /* clc */ 6738 case 0xf9: /* stc */ 6739 case 0xfc: /* cld */ 6740 case 0xfd: /* std */ 6741 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6742 break; 6743 6744 case 0x9f: /* lahf */ 6745 if (ir.regmap[X86_RECORD_R8_REGNUM]) 6746 { 6747 ir.addr -= 1; 6748 goto no_support; 6749 } 6750 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6751 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 6752 break; 6753 6754 /* bit operations */ 6755 case 0x0fba: /* bt/bts/btr/btc Gv, im */ 6756 ir.ot = ir.dflag + OT_WORD; 6757 if (i386_record_modrm (&ir)) 6758 return -1; 6759 if (ir.reg < 4) 6760 { 6761 ir.addr -= 2; 6762 opcode = opcode << 8 | ir.modrm; 6763 goto no_support; 6764 } 6765 if (ir.reg != 4) 6766 { 6767 if (ir.mod == 3) 6768 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 6769 else 6770 { 6771 if (i386_record_lea_modrm (&ir)) 6772 return -1; 6773 } 6774 } 6775 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6776 break; 6777 6778 case 0x0fa3: /* bt Gv, Ev */ 6779 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6780 break; 6781 6782 case 0x0fab: /* bts */ 6783 case 0x0fb3: /* btr */ 6784 case 0x0fbb: /* btc */ 6785 ir.ot = ir.dflag + OT_WORD; 6786 if (i386_record_modrm (&ir)) 6787 return -1; 6788 if (ir.mod == 3) 6789 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 6790 else 6791 { 6792 uint64_t addr64; 6793 if (i386_record_lea_modrm_addr (&ir, &addr64)) 6794 return -1; 6795 regcache_raw_read_unsigned (ir.regcache, 6796 ir.regmap[ir.reg | rex_r], 6797 &addr); 6798 switch (ir.dflag) 6799 { 6800 case 0: 6801 addr64 += ((int16_t) addr >> 4) << 4; 6802 break; 6803 case 1: 6804 addr64 += ((int32_t) addr >> 5) << 5; 6805 break; 6806 case 2: 6807 addr64 += ((int64_t) addr >> 6) << 6; 6808 break; 6809 } 6810 if (record_full_arch_list_add_mem (addr64, 1 << ir.ot)) 6811 return -1; 6812 if (i386_record_lea_modrm (&ir)) 6813 return -1; 6814 } 6815 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6816 break; 6817 6818 case 0x0fbc: /* bsf */ 6819 case 0x0fbd: /* bsr */ 6820 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); 6821 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6822 break; 6823 6824 /* bcd */ 6825 case 0x27: /* daa */ 6826 case 0x2f: /* das */ 6827 case 0x37: /* aaa */ 6828 case 0x3f: /* aas */ 6829 case 0xd4: /* aam */ 6830 case 0xd5: /* aad */ 6831 if (ir.regmap[X86_RECORD_R8_REGNUM]) 6832 { 6833 ir.addr -= 1; 6834 goto no_support; 6835 } 6836 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 6837 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6838 break; 6839 6840 /* misc */ 6841 case 0x90: /* nop */ 6842 if (prefixes & PREFIX_LOCK) 6843 { 6844 ir.addr -= 1; 6845 goto no_support; 6846 } 6847 break; 6848 6849 case 0x9b: /* fwait */ 6850 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) 6851 return -1; 6852 opcode = (uint32_t) opcode8; 6853 ir.addr++; 6854 goto reswitch; 6855 break; 6856 6857 /* XXX */ 6858 case 0xcc: /* int3 */ 6859 printf_unfiltered (_("Process record does not support instruction " 6860 "int3.\n")); 6861 ir.addr -= 1; 6862 goto no_support; 6863 break; 6864 6865 /* XXX */ 6866 case 0xcd: /* int */ 6867 { 6868 int ret; 6869 uint8_t interrupt; 6870 if (record_read_memory (gdbarch, ir.addr, &interrupt, 1)) 6871 return -1; 6872 ir.addr++; 6873 if (interrupt != 0x80 6874 || tdep->i386_intx80_record == NULL) 6875 { 6876 printf_unfiltered (_("Process record does not support " 6877 "instruction int 0x%02x.\n"), 6878 interrupt); 6879 ir.addr -= 2; 6880 goto no_support; 6881 } 6882 ret = tdep->i386_intx80_record (ir.regcache); 6883 if (ret) 6884 return ret; 6885 } 6886 break; 6887 6888 /* XXX */ 6889 case 0xce: /* into */ 6890 printf_unfiltered (_("Process record does not support " 6891 "instruction into.\n")); 6892 ir.addr -= 1; 6893 goto no_support; 6894 break; 6895 6896 case 0xfa: /* cli */ 6897 case 0xfb: /* sti */ 6898 break; 6899 6900 case 0x62: /* bound */ 6901 printf_unfiltered (_("Process record does not support " 6902 "instruction bound.\n")); 6903 ir.addr -= 1; 6904 goto no_support; 6905 break; 6906 6907 case 0x0fc8: /* bswap reg */ 6908 case 0x0fc9: 6909 case 0x0fca: 6910 case 0x0fcb: 6911 case 0x0fcc: 6912 case 0x0fcd: 6913 case 0x0fce: 6914 case 0x0fcf: 6915 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); 6916 break; 6917 6918 case 0xd6: /* salc */ 6919 if (ir.regmap[X86_RECORD_R8_REGNUM]) 6920 { 6921 ir.addr -= 1; 6922 goto no_support; 6923 } 6924 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 6925 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6926 break; 6927 6928 case 0xe0: /* loopnz */ 6929 case 0xe1: /* loopz */ 6930 case 0xe2: /* loop */ 6931 case 0xe3: /* jecxz */ 6932 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 6933 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 6934 break; 6935 6936 case 0x0f30: /* wrmsr */ 6937 printf_unfiltered (_("Process record does not support " 6938 "instruction wrmsr.\n")); 6939 ir.addr -= 2; 6940 goto no_support; 6941 break; 6942 6943 case 0x0f32: /* rdmsr */ 6944 printf_unfiltered (_("Process record does not support " 6945 "instruction rdmsr.\n")); 6946 ir.addr -= 2; 6947 goto no_support; 6948 break; 6949 6950 case 0x0f31: /* rdtsc */ 6951 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 6952 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 6953 break; 6954 6955 case 0x0f34: /* sysenter */ 6956 { 6957 int ret; 6958 if (ir.regmap[X86_RECORD_R8_REGNUM]) 6959 { 6960 ir.addr -= 2; 6961 goto no_support; 6962 } 6963 if (tdep->i386_sysenter_record == NULL) 6964 { 6965 printf_unfiltered (_("Process record does not support " 6966 "instruction sysenter.\n")); 6967 ir.addr -= 2; 6968 goto no_support; 6969 } 6970 ret = tdep->i386_sysenter_record (ir.regcache); 6971 if (ret) 6972 return ret; 6973 } 6974 break; 6975 6976 case 0x0f35: /* sysexit */ 6977 printf_unfiltered (_("Process record does not support " 6978 "instruction sysexit.\n")); 6979 ir.addr -= 2; 6980 goto no_support; 6981 break; 6982 6983 case 0x0f05: /* syscall */ 6984 { 6985 int ret; 6986 if (tdep->i386_syscall_record == NULL) 6987 { 6988 printf_unfiltered (_("Process record does not support " 6989 "instruction syscall.\n")); 6990 ir.addr -= 2; 6991 goto no_support; 6992 } 6993 ret = tdep->i386_syscall_record (ir.regcache); 6994 if (ret) 6995 return ret; 6996 } 6997 break; 6998 6999 case 0x0f07: /* sysret */ 7000 printf_unfiltered (_("Process record does not support " 7001 "instruction sysret.\n")); 7002 ir.addr -= 2; 7003 goto no_support; 7004 break; 7005 7006 case 0x0fa2: /* cpuid */ 7007 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 7008 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 7009 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 7010 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); 7011 break; 7012 7013 case 0xf4: /* hlt */ 7014 printf_unfiltered (_("Process record does not support " 7015 "instruction hlt.\n")); 7016 ir.addr -= 1; 7017 goto no_support; 7018 break; 7019 7020 case 0x0f00: 7021 if (i386_record_modrm (&ir)) 7022 return -1; 7023 switch (ir.reg) 7024 { 7025 case 0: /* sldt */ 7026 case 1: /* str */ 7027 if (ir.mod == 3) 7028 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 7029 else 7030 { 7031 ir.ot = OT_WORD; 7032 if (i386_record_lea_modrm (&ir)) 7033 return -1; 7034 } 7035 break; 7036 case 2: /* lldt */ 7037 case 3: /* ltr */ 7038 break; 7039 case 4: /* verr */ 7040 case 5: /* verw */ 7041 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7042 break; 7043 default: 7044 ir.addr -= 3; 7045 opcode = opcode << 8 | ir.modrm; 7046 goto no_support; 7047 break; 7048 } 7049 break; 7050 7051 case 0x0f01: 7052 if (i386_record_modrm (&ir)) 7053 return -1; 7054 switch (ir.reg) 7055 { 7056 case 0: /* sgdt */ 7057 { 7058 uint64_t addr64; 7059 7060 if (ir.mod == 3) 7061 { 7062 ir.addr -= 3; 7063 opcode = opcode << 8 | ir.modrm; 7064 goto no_support; 7065 } 7066 if (ir.override >= 0) 7067 { 7068 if (record_full_memory_query) 7069 { 7070 if (yquery (_("\ 7071 Process record ignores the memory change of instruction at address %s\n\ 7072 because it can't get the value of the segment register.\n\ 7073 Do you want to stop the program?"), 7074 paddress (gdbarch, ir.orig_addr))) 7075 return -1; 7076 } 7077 } 7078 else 7079 { 7080 if (i386_record_lea_modrm_addr (&ir, &addr64)) 7081 return -1; 7082 if (record_full_arch_list_add_mem (addr64, 2)) 7083 return -1; 7084 addr64 += 2; 7085 if (ir.regmap[X86_RECORD_R8_REGNUM]) 7086 { 7087 if (record_full_arch_list_add_mem (addr64, 8)) 7088 return -1; 7089 } 7090 else 7091 { 7092 if (record_full_arch_list_add_mem (addr64, 4)) 7093 return -1; 7094 } 7095 } 7096 } 7097 break; 7098 case 1: 7099 if (ir.mod == 3) 7100 { 7101 switch (ir.rm) 7102 { 7103 case 0: /* monitor */ 7104 break; 7105 case 1: /* mwait */ 7106 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7107 break; 7108 default: 7109 ir.addr -= 3; 7110 opcode = opcode << 8 | ir.modrm; 7111 goto no_support; 7112 break; 7113 } 7114 } 7115 else 7116 { 7117 /* sidt */ 7118 if (ir.override >= 0) 7119 { 7120 if (record_full_memory_query) 7121 { 7122 if (yquery (_("\ 7123 Process record ignores the memory change of instruction at address %s\n\ 7124 because it can't get the value of the segment register.\n\ 7125 Do you want to stop the program?"), 7126 paddress (gdbarch, ir.orig_addr))) 7127 return -1; 7128 } 7129 } 7130 else 7131 { 7132 uint64_t addr64; 7133 7134 if (i386_record_lea_modrm_addr (&ir, &addr64)) 7135 return -1; 7136 if (record_full_arch_list_add_mem (addr64, 2)) 7137 return -1; 7138 addr64 += 2; 7139 if (ir.regmap[X86_RECORD_R8_REGNUM]) 7140 { 7141 if (record_full_arch_list_add_mem (addr64, 8)) 7142 return -1; 7143 } 7144 else 7145 { 7146 if (record_full_arch_list_add_mem (addr64, 4)) 7147 return -1; 7148 } 7149 } 7150 } 7151 break; 7152 case 2: /* lgdt */ 7153 if (ir.mod == 3) 7154 { 7155 /* xgetbv */ 7156 if (ir.rm == 0) 7157 { 7158 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 7159 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 7160 break; 7161 } 7162 /* xsetbv */ 7163 else if (ir.rm == 1) 7164 break; 7165 } 7166 /* Fall through. */ 7167 case 3: /* lidt */ 7168 if (ir.mod == 3) 7169 { 7170 ir.addr -= 3; 7171 opcode = opcode << 8 | ir.modrm; 7172 goto no_support; 7173 } 7174 break; 7175 case 4: /* smsw */ 7176 if (ir.mod == 3) 7177 { 7178 if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) 7179 return -1; 7180 } 7181 else 7182 { 7183 ir.ot = OT_WORD; 7184 if (i386_record_lea_modrm (&ir)) 7185 return -1; 7186 } 7187 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7188 break; 7189 case 6: /* lmsw */ 7190 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7191 break; 7192 case 7: /* invlpg */ 7193 if (ir.mod == 3) 7194 { 7195 if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) 7196 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); 7197 else 7198 { 7199 ir.addr -= 3; 7200 opcode = opcode << 8 | ir.modrm; 7201 goto no_support; 7202 } 7203 } 7204 else 7205 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7206 break; 7207 default: 7208 ir.addr -= 3; 7209 opcode = opcode << 8 | ir.modrm; 7210 goto no_support; 7211 break; 7212 } 7213 break; 7214 7215 case 0x0f08: /* invd */ 7216 case 0x0f09: /* wbinvd */ 7217 break; 7218 7219 case 0x63: /* arpl */ 7220 if (i386_record_modrm (&ir)) 7221 return -1; 7222 if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) 7223 { 7224 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] 7225 ? (ir.reg | rex_r) : ir.rm); 7226 } 7227 else 7228 { 7229 ir.ot = ir.dflag ? OT_LONG : OT_WORD; 7230 if (i386_record_lea_modrm (&ir)) 7231 return -1; 7232 } 7233 if (!ir.regmap[X86_RECORD_R8_REGNUM]) 7234 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7235 break; 7236 7237 case 0x0f02: /* lar */ 7238 case 0x0f03: /* lsl */ 7239 if (i386_record_modrm (&ir)) 7240 return -1; 7241 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); 7242 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7243 break; 7244 7245 case 0x0f18: 7246 if (i386_record_modrm (&ir)) 7247 return -1; 7248 if (ir.mod == 3 && ir.reg == 3) 7249 { 7250 ir.addr -= 3; 7251 opcode = opcode << 8 | ir.modrm; 7252 goto no_support; 7253 } 7254 break; 7255 7256 case 0x0f19: 7257 case 0x0f1a: 7258 case 0x0f1b: 7259 case 0x0f1c: 7260 case 0x0f1d: 7261 case 0x0f1e: 7262 case 0x0f1f: 7263 /* nop (multi byte) */ 7264 break; 7265 7266 case 0x0f20: /* mov reg, crN */ 7267 case 0x0f22: /* mov crN, reg */ 7268 if (i386_record_modrm (&ir)) 7269 return -1; 7270 if ((ir.modrm & 0xc0) != 0xc0) 7271 { 7272 ir.addr -= 3; 7273 opcode = opcode << 8 | ir.modrm; 7274 goto no_support; 7275 } 7276 switch (ir.reg) 7277 { 7278 case 0: 7279 case 2: 7280 case 3: 7281 case 4: 7282 case 8: 7283 if (opcode & 2) 7284 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7285 else 7286 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 7287 break; 7288 default: 7289 ir.addr -= 3; 7290 opcode = opcode << 8 | ir.modrm; 7291 goto no_support; 7292 break; 7293 } 7294 break; 7295 7296 case 0x0f21: /* mov reg, drN */ 7297 case 0x0f23: /* mov drN, reg */ 7298 if (i386_record_modrm (&ir)) 7299 return -1; 7300 if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 7301 || ir.reg == 5 || ir.reg >= 8) 7302 { 7303 ir.addr -= 3; 7304 opcode = opcode << 8 | ir.modrm; 7305 goto no_support; 7306 } 7307 if (opcode & 2) 7308 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7309 else 7310 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 7311 break; 7312 7313 case 0x0f06: /* clts */ 7314 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7315 break; 7316 7317 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ 7318 7319 case 0x0f0d: /* 3DNow! prefetch */ 7320 break; 7321 7322 case 0x0f0e: /* 3DNow! femms */ 7323 case 0x0f77: /* emms */ 7324 if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) 7325 goto no_support; 7326 record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); 7327 break; 7328 7329 case 0x0f0f: /* 3DNow! data */ 7330 if (i386_record_modrm (&ir)) 7331 return -1; 7332 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) 7333 return -1; 7334 ir.addr++; 7335 switch (opcode8) 7336 { 7337 case 0x0c: /* 3DNow! pi2fw */ 7338 case 0x0d: /* 3DNow! pi2fd */ 7339 case 0x1c: /* 3DNow! pf2iw */ 7340 case 0x1d: /* 3DNow! pf2id */ 7341 case 0x8a: /* 3DNow! pfnacc */ 7342 case 0x8e: /* 3DNow! pfpnacc */ 7343 case 0x90: /* 3DNow! pfcmpge */ 7344 case 0x94: /* 3DNow! pfmin */ 7345 case 0x96: /* 3DNow! pfrcp */ 7346 case 0x97: /* 3DNow! pfrsqrt */ 7347 case 0x9a: /* 3DNow! pfsub */ 7348 case 0x9e: /* 3DNow! pfadd */ 7349 case 0xa0: /* 3DNow! pfcmpgt */ 7350 case 0xa4: /* 3DNow! pfmax */ 7351 case 0xa6: /* 3DNow! pfrcpit1 */ 7352 case 0xa7: /* 3DNow! pfrsqit1 */ 7353 case 0xaa: /* 3DNow! pfsubr */ 7354 case 0xae: /* 3DNow! pfacc */ 7355 case 0xb0: /* 3DNow! pfcmpeq */ 7356 case 0xb4: /* 3DNow! pfmul */ 7357 case 0xb6: /* 3DNow! pfrcpit2 */ 7358 case 0xb7: /* 3DNow! pmulhrw */ 7359 case 0xbb: /* 3DNow! pswapd */ 7360 case 0xbf: /* 3DNow! pavgusb */ 7361 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) 7362 goto no_support_3dnow_data; 7363 record_full_arch_list_add_reg (ir.regcache, ir.reg); 7364 break; 7365 7366 default: 7367 no_support_3dnow_data: 7368 opcode = (opcode << 8) | opcode8; 7369 goto no_support; 7370 break; 7371 } 7372 break; 7373 7374 case 0x0faa: /* rsm */ 7375 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7376 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); 7377 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); 7378 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); 7379 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); 7380 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); 7381 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); 7382 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); 7383 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); 7384 break; 7385 7386 case 0x0fae: 7387 if (i386_record_modrm (&ir)) 7388 return -1; 7389 switch(ir.reg) 7390 { 7391 case 0: /* fxsave */ 7392 { 7393 uint64_t tmpu64; 7394 7395 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7396 if (i386_record_lea_modrm_addr (&ir, &tmpu64)) 7397 return -1; 7398 if (record_full_arch_list_add_mem (tmpu64, 512)) 7399 return -1; 7400 } 7401 break; 7402 7403 case 1: /* fxrstor */ 7404 { 7405 int i; 7406 7407 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7408 7409 for (i = I387_MM0_REGNUM (tdep); 7410 i386_mmx_regnum_p (gdbarch, i); i++) 7411 record_full_arch_list_add_reg (ir.regcache, i); 7412 7413 for (i = I387_XMM0_REGNUM (tdep); 7414 i386_xmm_regnum_p (gdbarch, i); i++) 7415 record_full_arch_list_add_reg (ir.regcache, i); 7416 7417 if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) 7418 record_full_arch_list_add_reg (ir.regcache, 7419 I387_MXCSR_REGNUM(tdep)); 7420 7421 for (i = I387_ST0_REGNUM (tdep); 7422 i386_fp_regnum_p (gdbarch, i); i++) 7423 record_full_arch_list_add_reg (ir.regcache, i); 7424 7425 for (i = I387_FCTRL_REGNUM (tdep); 7426 i386_fpc_regnum_p (gdbarch, i); i++) 7427 record_full_arch_list_add_reg (ir.regcache, i); 7428 } 7429 break; 7430 7431 case 2: /* ldmxcsr */ 7432 if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) 7433 goto no_support; 7434 record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); 7435 break; 7436 7437 case 3: /* stmxcsr */ 7438 ir.ot = OT_LONG; 7439 if (i386_record_lea_modrm (&ir)) 7440 return -1; 7441 break; 7442 7443 case 5: /* lfence */ 7444 case 6: /* mfence */ 7445 case 7: /* sfence clflush */ 7446 break; 7447 7448 default: 7449 opcode = (opcode << 8) | ir.modrm; 7450 goto no_support; 7451 break; 7452 } 7453 break; 7454 7455 case 0x0fc3: /* movnti */ 7456 ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; 7457 if (i386_record_modrm (&ir)) 7458 return -1; 7459 if (ir.mod == 3) 7460 goto no_support; 7461 ir.reg |= rex_r; 7462 if (i386_record_lea_modrm (&ir)) 7463 return -1; 7464 break; 7465 7466 /* Add prefix to opcode. */ 7467 case 0x0f10: 7468 case 0x0f11: 7469 case 0x0f12: 7470 case 0x0f13: 7471 case 0x0f14: 7472 case 0x0f15: 7473 case 0x0f16: 7474 case 0x0f17: 7475 case 0x0f28: 7476 case 0x0f29: 7477 case 0x0f2a: 7478 case 0x0f2b: 7479 case 0x0f2c: 7480 case 0x0f2d: 7481 case 0x0f2e: 7482 case 0x0f2f: 7483 case 0x0f38: 7484 case 0x0f39: 7485 case 0x0f3a: 7486 case 0x0f50: 7487 case 0x0f51: 7488 case 0x0f52: 7489 case 0x0f53: 7490 case 0x0f54: 7491 case 0x0f55: 7492 case 0x0f56: 7493 case 0x0f57: 7494 case 0x0f58: 7495 case 0x0f59: 7496 case 0x0f5a: 7497 case 0x0f5b: 7498 case 0x0f5c: 7499 case 0x0f5d: 7500 case 0x0f5e: 7501 case 0x0f5f: 7502 case 0x0f60: 7503 case 0x0f61: 7504 case 0x0f62: 7505 case 0x0f63: 7506 case 0x0f64: 7507 case 0x0f65: 7508 case 0x0f66: 7509 case 0x0f67: 7510 case 0x0f68: 7511 case 0x0f69: 7512 case 0x0f6a: 7513 case 0x0f6b: 7514 case 0x0f6c: 7515 case 0x0f6d: 7516 case 0x0f6e: 7517 case 0x0f6f: 7518 case 0x0f70: 7519 case 0x0f71: 7520 case 0x0f72: 7521 case 0x0f73: 7522 case 0x0f74: 7523 case 0x0f75: 7524 case 0x0f76: 7525 case 0x0f7c: 7526 case 0x0f7d: 7527 case 0x0f7e: 7528 case 0x0f7f: 7529 case 0x0fb8: 7530 case 0x0fc2: 7531 case 0x0fc4: 7532 case 0x0fc5: 7533 case 0x0fc6: 7534 case 0x0fd0: 7535 case 0x0fd1: 7536 case 0x0fd2: 7537 case 0x0fd3: 7538 case 0x0fd4: 7539 case 0x0fd5: 7540 case 0x0fd6: 7541 case 0x0fd7: 7542 case 0x0fd8: 7543 case 0x0fd9: 7544 case 0x0fda: 7545 case 0x0fdb: 7546 case 0x0fdc: 7547 case 0x0fdd: 7548 case 0x0fde: 7549 case 0x0fdf: 7550 case 0x0fe0: 7551 case 0x0fe1: 7552 case 0x0fe2: 7553 case 0x0fe3: 7554 case 0x0fe4: 7555 case 0x0fe5: 7556 case 0x0fe6: 7557 case 0x0fe7: 7558 case 0x0fe8: 7559 case 0x0fe9: 7560 case 0x0fea: 7561 case 0x0feb: 7562 case 0x0fec: 7563 case 0x0fed: 7564 case 0x0fee: 7565 case 0x0fef: 7566 case 0x0ff0: 7567 case 0x0ff1: 7568 case 0x0ff2: 7569 case 0x0ff3: 7570 case 0x0ff4: 7571 case 0x0ff5: 7572 case 0x0ff6: 7573 case 0x0ff7: 7574 case 0x0ff8: 7575 case 0x0ff9: 7576 case 0x0ffa: 7577 case 0x0ffb: 7578 case 0x0ffc: 7579 case 0x0ffd: 7580 case 0x0ffe: 7581 /* Mask out PREFIX_ADDR. */ 7582 switch ((prefixes & ~PREFIX_ADDR)) 7583 { 7584 case PREFIX_REPNZ: 7585 opcode |= 0xf20000; 7586 break; 7587 case PREFIX_DATA: 7588 opcode |= 0x660000; 7589 break; 7590 case PREFIX_REPZ: 7591 opcode |= 0xf30000; 7592 break; 7593 } 7594 reswitch_prefix_add: 7595 switch (opcode) 7596 { 7597 case 0x0f38: 7598 case 0x660f38: 7599 case 0xf20f38: 7600 case 0x0f3a: 7601 case 0x660f3a: 7602 if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) 7603 return -1; 7604 ir.addr++; 7605 opcode = (uint32_t) opcode8 | opcode << 8; 7606 goto reswitch_prefix_add; 7607 break; 7608 7609 case 0x0f10: /* movups */ 7610 case 0x660f10: /* movupd */ 7611 case 0xf30f10: /* movss */ 7612 case 0xf20f10: /* movsd */ 7613 case 0x0f12: /* movlps */ 7614 case 0x660f12: /* movlpd */ 7615 case 0xf30f12: /* movsldup */ 7616 case 0xf20f12: /* movddup */ 7617 case 0x0f14: /* unpcklps */ 7618 case 0x660f14: /* unpcklpd */ 7619 case 0x0f15: /* unpckhps */ 7620 case 0x660f15: /* unpckhpd */ 7621 case 0x0f16: /* movhps */ 7622 case 0x660f16: /* movhpd */ 7623 case 0xf30f16: /* movshdup */ 7624 case 0x0f28: /* movaps */ 7625 case 0x660f28: /* movapd */ 7626 case 0x0f2a: /* cvtpi2ps */ 7627 case 0x660f2a: /* cvtpi2pd */ 7628 case 0xf30f2a: /* cvtsi2ss */ 7629 case 0xf20f2a: /* cvtsi2sd */ 7630 case 0x0f2c: /* cvttps2pi */ 7631 case 0x660f2c: /* cvttpd2pi */ 7632 case 0x0f2d: /* cvtps2pi */ 7633 case 0x660f2d: /* cvtpd2pi */ 7634 case 0x660f3800: /* pshufb */ 7635 case 0x660f3801: /* phaddw */ 7636 case 0x660f3802: /* phaddd */ 7637 case 0x660f3803: /* phaddsw */ 7638 case 0x660f3804: /* pmaddubsw */ 7639 case 0x660f3805: /* phsubw */ 7640 case 0x660f3806: /* phsubd */ 7641 case 0x660f3807: /* phsubsw */ 7642 case 0x660f3808: /* psignb */ 7643 case 0x660f3809: /* psignw */ 7644 case 0x660f380a: /* psignd */ 7645 case 0x660f380b: /* pmulhrsw */ 7646 case 0x660f3810: /* pblendvb */ 7647 case 0x660f3814: /* blendvps */ 7648 case 0x660f3815: /* blendvpd */ 7649 case 0x660f381c: /* pabsb */ 7650 case 0x660f381d: /* pabsw */ 7651 case 0x660f381e: /* pabsd */ 7652 case 0x660f3820: /* pmovsxbw */ 7653 case 0x660f3821: /* pmovsxbd */ 7654 case 0x660f3822: /* pmovsxbq */ 7655 case 0x660f3823: /* pmovsxwd */ 7656 case 0x660f3824: /* pmovsxwq */ 7657 case 0x660f3825: /* pmovsxdq */ 7658 case 0x660f3828: /* pmuldq */ 7659 case 0x660f3829: /* pcmpeqq */ 7660 case 0x660f382a: /* movntdqa */ 7661 case 0x660f3a08: /* roundps */ 7662 case 0x660f3a09: /* roundpd */ 7663 case 0x660f3a0a: /* roundss */ 7664 case 0x660f3a0b: /* roundsd */ 7665 case 0x660f3a0c: /* blendps */ 7666 case 0x660f3a0d: /* blendpd */ 7667 case 0x660f3a0e: /* pblendw */ 7668 case 0x660f3a0f: /* palignr */ 7669 case 0x660f3a20: /* pinsrb */ 7670 case 0x660f3a21: /* insertps */ 7671 case 0x660f3a22: /* pinsrd pinsrq */ 7672 case 0x660f3a40: /* dpps */ 7673 case 0x660f3a41: /* dppd */ 7674 case 0x660f3a42: /* mpsadbw */ 7675 case 0x660f3a60: /* pcmpestrm */ 7676 case 0x660f3a61: /* pcmpestri */ 7677 case 0x660f3a62: /* pcmpistrm */ 7678 case 0x660f3a63: /* pcmpistri */ 7679 case 0x0f51: /* sqrtps */ 7680 case 0x660f51: /* sqrtpd */ 7681 case 0xf20f51: /* sqrtsd */ 7682 case 0xf30f51: /* sqrtss */ 7683 case 0x0f52: /* rsqrtps */ 7684 case 0xf30f52: /* rsqrtss */ 7685 case 0x0f53: /* rcpps */ 7686 case 0xf30f53: /* rcpss */ 7687 case 0x0f54: /* andps */ 7688 case 0x660f54: /* andpd */ 7689 case 0x0f55: /* andnps */ 7690 case 0x660f55: /* andnpd */ 7691 case 0x0f56: /* orps */ 7692 case 0x660f56: /* orpd */ 7693 case 0x0f57: /* xorps */ 7694 case 0x660f57: /* xorpd */ 7695 case 0x0f58: /* addps */ 7696 case 0x660f58: /* addpd */ 7697 case 0xf20f58: /* addsd */ 7698 case 0xf30f58: /* addss */ 7699 case 0x0f59: /* mulps */ 7700 case 0x660f59: /* mulpd */ 7701 case 0xf20f59: /* mulsd */ 7702 case 0xf30f59: /* mulss */ 7703 case 0x0f5a: /* cvtps2pd */ 7704 case 0x660f5a: /* cvtpd2ps */ 7705 case 0xf20f5a: /* cvtsd2ss */ 7706 case 0xf30f5a: /* cvtss2sd */ 7707 case 0x0f5b: /* cvtdq2ps */ 7708 case 0x660f5b: /* cvtps2dq */ 7709 case 0xf30f5b: /* cvttps2dq */ 7710 case 0x0f5c: /* subps */ 7711 case 0x660f5c: /* subpd */ 7712 case 0xf20f5c: /* subsd */ 7713 case 0xf30f5c: /* subss */ 7714 case 0x0f5d: /* minps */ 7715 case 0x660f5d: /* minpd */ 7716 case 0xf20f5d: /* minsd */ 7717 case 0xf30f5d: /* minss */ 7718 case 0x0f5e: /* divps */ 7719 case 0x660f5e: /* divpd */ 7720 case 0xf20f5e: /* divsd */ 7721 case 0xf30f5e: /* divss */ 7722 case 0x0f5f: /* maxps */ 7723 case 0x660f5f: /* maxpd */ 7724 case 0xf20f5f: /* maxsd */ 7725 case 0xf30f5f: /* maxss */ 7726 case 0x660f60: /* punpcklbw */ 7727 case 0x660f61: /* punpcklwd */ 7728 case 0x660f62: /* punpckldq */ 7729 case 0x660f63: /* packsswb */ 7730 case 0x660f64: /* pcmpgtb */ 7731 case 0x660f65: /* pcmpgtw */ 7732 case 0x660f66: /* pcmpgtd */ 7733 case 0x660f67: /* packuswb */ 7734 case 0x660f68: /* punpckhbw */ 7735 case 0x660f69: /* punpckhwd */ 7736 case 0x660f6a: /* punpckhdq */ 7737 case 0x660f6b: /* packssdw */ 7738 case 0x660f6c: /* punpcklqdq */ 7739 case 0x660f6d: /* punpckhqdq */ 7740 case 0x660f6e: /* movd */ 7741 case 0x660f6f: /* movdqa */ 7742 case 0xf30f6f: /* movdqu */ 7743 case 0x660f70: /* pshufd */ 7744 case 0xf20f70: /* pshuflw */ 7745 case 0xf30f70: /* pshufhw */ 7746 case 0x660f74: /* pcmpeqb */ 7747 case 0x660f75: /* pcmpeqw */ 7748 case 0x660f76: /* pcmpeqd */ 7749 case 0x660f7c: /* haddpd */ 7750 case 0xf20f7c: /* haddps */ 7751 case 0x660f7d: /* hsubpd */ 7752 case 0xf20f7d: /* hsubps */ 7753 case 0xf30f7e: /* movq */ 7754 case 0x0fc2: /* cmpps */ 7755 case 0x660fc2: /* cmppd */ 7756 case 0xf20fc2: /* cmpsd */ 7757 case 0xf30fc2: /* cmpss */ 7758 case 0x660fc4: /* pinsrw */ 7759 case 0x0fc6: /* shufps */ 7760 case 0x660fc6: /* shufpd */ 7761 case 0x660fd0: /* addsubpd */ 7762 case 0xf20fd0: /* addsubps */ 7763 case 0x660fd1: /* psrlw */ 7764 case 0x660fd2: /* psrld */ 7765 case 0x660fd3: /* psrlq */ 7766 case 0x660fd4: /* paddq */ 7767 case 0x660fd5: /* pmullw */ 7768 case 0xf30fd6: /* movq2dq */ 7769 case 0x660fd8: /* psubusb */ 7770 case 0x660fd9: /* psubusw */ 7771 case 0x660fda: /* pminub */ 7772 case 0x660fdb: /* pand */ 7773 case 0x660fdc: /* paddusb */ 7774 case 0x660fdd: /* paddusw */ 7775 case 0x660fde: /* pmaxub */ 7776 case 0x660fdf: /* pandn */ 7777 case 0x660fe0: /* pavgb */ 7778 case 0x660fe1: /* psraw */ 7779 case 0x660fe2: /* psrad */ 7780 case 0x660fe3: /* pavgw */ 7781 case 0x660fe4: /* pmulhuw */ 7782 case 0x660fe5: /* pmulhw */ 7783 case 0x660fe6: /* cvttpd2dq */ 7784 case 0xf20fe6: /* cvtpd2dq */ 7785 case 0xf30fe6: /* cvtdq2pd */ 7786 case 0x660fe8: /* psubsb */ 7787 case 0x660fe9: /* psubsw */ 7788 case 0x660fea: /* pminsw */ 7789 case 0x660feb: /* por */ 7790 case 0x660fec: /* paddsb */ 7791 case 0x660fed: /* paddsw */ 7792 case 0x660fee: /* pmaxsw */ 7793 case 0x660fef: /* pxor */ 7794 case 0xf20ff0: /* lddqu */ 7795 case 0x660ff1: /* psllw */ 7796 case 0x660ff2: /* pslld */ 7797 case 0x660ff3: /* psllq */ 7798 case 0x660ff4: /* pmuludq */ 7799 case 0x660ff5: /* pmaddwd */ 7800 case 0x660ff6: /* psadbw */ 7801 case 0x660ff8: /* psubb */ 7802 case 0x660ff9: /* psubw */ 7803 case 0x660ffa: /* psubd */ 7804 case 0x660ffb: /* psubq */ 7805 case 0x660ffc: /* paddb */ 7806 case 0x660ffd: /* paddw */ 7807 case 0x660ffe: /* paddd */ 7808 if (i386_record_modrm (&ir)) 7809 return -1; 7810 ir.reg |= rex_r; 7811 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) 7812 goto no_support; 7813 record_full_arch_list_add_reg (ir.regcache, 7814 I387_XMM0_REGNUM (tdep) + ir.reg); 7815 if ((opcode & 0xfffffffc) == 0x660f3a60) 7816 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 7817 break; 7818 7819 case 0x0f11: /* movups */ 7820 case 0x660f11: /* movupd */ 7821 case 0xf30f11: /* movss */ 7822 case 0xf20f11: /* movsd */ 7823 case 0x0f13: /* movlps */ 7824 case 0x660f13: /* movlpd */ 7825 case 0x0f17: /* movhps */ 7826 case 0x660f17: /* movhpd */ 7827 case 0x0f29: /* movaps */ 7828 case 0x660f29: /* movapd */ 7829 case 0x660f3a14: /* pextrb */ 7830 case 0x660f3a15: /* pextrw */ 7831 case 0x660f3a16: /* pextrd pextrq */ 7832 case 0x660f3a17: /* extractps */ 7833 case 0x660f7f: /* movdqa */ 7834 case 0xf30f7f: /* movdqu */ 7835 if (i386_record_modrm (&ir)) 7836 return -1; 7837 if (ir.mod == 3) 7838 { 7839 if (opcode == 0x0f13 || opcode == 0x660f13 7840 || opcode == 0x0f17 || opcode == 0x660f17) 7841 goto no_support; 7842 ir.rm |= ir.rex_b; 7843 if (!i386_xmm_regnum_p (gdbarch, 7844 I387_XMM0_REGNUM (tdep) + ir.rm)) 7845 goto no_support; 7846 record_full_arch_list_add_reg (ir.regcache, 7847 I387_XMM0_REGNUM (tdep) + ir.rm); 7848 } 7849 else 7850 { 7851 switch (opcode) 7852 { 7853 case 0x660f3a14: 7854 ir.ot = OT_BYTE; 7855 break; 7856 case 0x660f3a15: 7857 ir.ot = OT_WORD; 7858 break; 7859 case 0x660f3a16: 7860 ir.ot = OT_LONG; 7861 break; 7862 case 0x660f3a17: 7863 ir.ot = OT_QUAD; 7864 break; 7865 default: 7866 ir.ot = OT_DQUAD; 7867 break; 7868 } 7869 if (i386_record_lea_modrm (&ir)) 7870 return -1; 7871 } 7872 break; 7873 7874 case 0x0f2b: /* movntps */ 7875 case 0x660f2b: /* movntpd */ 7876 case 0x0fe7: /* movntq */ 7877 case 0x660fe7: /* movntdq */ 7878 if (ir.mod == 3) 7879 goto no_support; 7880 if (opcode == 0x0fe7) 7881 ir.ot = OT_QUAD; 7882 else 7883 ir.ot = OT_DQUAD; 7884 if (i386_record_lea_modrm (&ir)) 7885 return -1; 7886 break; 7887 7888 case 0xf30f2c: /* cvttss2si */ 7889 case 0xf20f2c: /* cvttsd2si */ 7890 case 0xf30f2d: /* cvtss2si */ 7891 case 0xf20f2d: /* cvtsd2si */ 7892 case 0xf20f38f0: /* crc32 */ 7893 case 0xf20f38f1: /* crc32 */ 7894 case 0x0f50: /* movmskps */ 7895 case 0x660f50: /* movmskpd */ 7896 case 0x0fc5: /* pextrw */ 7897 case 0x660fc5: /* pextrw */ 7898 case 0x0fd7: /* pmovmskb */ 7899 case 0x660fd7: /* pmovmskb */ 7900 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); 7901 break; 7902 7903 case 0x0f3800: /* pshufb */ 7904 case 0x0f3801: /* phaddw */ 7905 case 0x0f3802: /* phaddd */ 7906 case 0x0f3803: /* phaddsw */ 7907 case 0x0f3804: /* pmaddubsw */ 7908 case 0x0f3805: /* phsubw */ 7909 case 0x0f3806: /* phsubd */ 7910 case 0x0f3807: /* phsubsw */ 7911 case 0x0f3808: /* psignb */ 7912 case 0x0f3809: /* psignw */ 7913 case 0x0f380a: /* psignd */ 7914 case 0x0f380b: /* pmulhrsw */ 7915 case 0x0f381c: /* pabsb */ 7916 case 0x0f381d: /* pabsw */ 7917 case 0x0f381e: /* pabsd */ 7918 case 0x0f382b: /* packusdw */ 7919 case 0x0f3830: /* pmovzxbw */ 7920 case 0x0f3831: /* pmovzxbd */ 7921 case 0x0f3832: /* pmovzxbq */ 7922 case 0x0f3833: /* pmovzxwd */ 7923 case 0x0f3834: /* pmovzxwq */ 7924 case 0x0f3835: /* pmovzxdq */ 7925 case 0x0f3837: /* pcmpgtq */ 7926 case 0x0f3838: /* pminsb */ 7927 case 0x0f3839: /* pminsd */ 7928 case 0x0f383a: /* pminuw */ 7929 case 0x0f383b: /* pminud */ 7930 case 0x0f383c: /* pmaxsb */ 7931 case 0x0f383d: /* pmaxsd */ 7932 case 0x0f383e: /* pmaxuw */ 7933 case 0x0f383f: /* pmaxud */ 7934 case 0x0f3840: /* pmulld */ 7935 case 0x0f3841: /* phminposuw */ 7936 case 0x0f3a0f: /* palignr */ 7937 case 0x0f60: /* punpcklbw */ 7938 case 0x0f61: /* punpcklwd */ 7939 case 0x0f62: /* punpckldq */ 7940 case 0x0f63: /* packsswb */ 7941 case 0x0f64: /* pcmpgtb */ 7942 case 0x0f65: /* pcmpgtw */ 7943 case 0x0f66: /* pcmpgtd */ 7944 case 0x0f67: /* packuswb */ 7945 case 0x0f68: /* punpckhbw */ 7946 case 0x0f69: /* punpckhwd */ 7947 case 0x0f6a: /* punpckhdq */ 7948 case 0x0f6b: /* packssdw */ 7949 case 0x0f6e: /* movd */ 7950 case 0x0f6f: /* movq */ 7951 case 0x0f70: /* pshufw */ 7952 case 0x0f74: /* pcmpeqb */ 7953 case 0x0f75: /* pcmpeqw */ 7954 case 0x0f76: /* pcmpeqd */ 7955 case 0x0fc4: /* pinsrw */ 7956 case 0x0fd1: /* psrlw */ 7957 case 0x0fd2: /* psrld */ 7958 case 0x0fd3: /* psrlq */ 7959 case 0x0fd4: /* paddq */ 7960 case 0x0fd5: /* pmullw */ 7961 case 0xf20fd6: /* movdq2q */ 7962 case 0x0fd8: /* psubusb */ 7963 case 0x0fd9: /* psubusw */ 7964 case 0x0fda: /* pminub */ 7965 case 0x0fdb: /* pand */ 7966 case 0x0fdc: /* paddusb */ 7967 case 0x0fdd: /* paddusw */ 7968 case 0x0fde: /* pmaxub */ 7969 case 0x0fdf: /* pandn */ 7970 case 0x0fe0: /* pavgb */ 7971 case 0x0fe1: /* psraw */ 7972 case 0x0fe2: /* psrad */ 7973 case 0x0fe3: /* pavgw */ 7974 case 0x0fe4: /* pmulhuw */ 7975 case 0x0fe5: /* pmulhw */ 7976 case 0x0fe8: /* psubsb */ 7977 case 0x0fe9: /* psubsw */ 7978 case 0x0fea: /* pminsw */ 7979 case 0x0feb: /* por */ 7980 case 0x0fec: /* paddsb */ 7981 case 0x0fed: /* paddsw */ 7982 case 0x0fee: /* pmaxsw */ 7983 case 0x0fef: /* pxor */ 7984 case 0x0ff1: /* psllw */ 7985 case 0x0ff2: /* pslld */ 7986 case 0x0ff3: /* psllq */ 7987 case 0x0ff4: /* pmuludq */ 7988 case 0x0ff5: /* pmaddwd */ 7989 case 0x0ff6: /* psadbw */ 7990 case 0x0ff8: /* psubb */ 7991 case 0x0ff9: /* psubw */ 7992 case 0x0ffa: /* psubd */ 7993 case 0x0ffb: /* psubq */ 7994 case 0x0ffc: /* paddb */ 7995 case 0x0ffd: /* paddw */ 7996 case 0x0ffe: /* paddd */ 7997 if (i386_record_modrm (&ir)) 7998 return -1; 7999 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) 8000 goto no_support; 8001 record_full_arch_list_add_reg (ir.regcache, 8002 I387_MM0_REGNUM (tdep) + ir.reg); 8003 break; 8004 8005 case 0x0f71: /* psllw */ 8006 case 0x0f72: /* pslld */ 8007 case 0x0f73: /* psllq */ 8008 if (i386_record_modrm (&ir)) 8009 return -1; 8010 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) 8011 goto no_support; 8012 record_full_arch_list_add_reg (ir.regcache, 8013 I387_MM0_REGNUM (tdep) + ir.rm); 8014 break; 8015 8016 case 0x660f71: /* psllw */ 8017 case 0x660f72: /* pslld */ 8018 case 0x660f73: /* psllq */ 8019 if (i386_record_modrm (&ir)) 8020 return -1; 8021 ir.rm |= ir.rex_b; 8022 if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) 8023 goto no_support; 8024 record_full_arch_list_add_reg (ir.regcache, 8025 I387_XMM0_REGNUM (tdep) + ir.rm); 8026 break; 8027 8028 case 0x0f7e: /* movd */ 8029 case 0x660f7e: /* movd */ 8030 if (i386_record_modrm (&ir)) 8031 return -1; 8032 if (ir.mod == 3) 8033 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); 8034 else 8035 { 8036 if (ir.dflag == 2) 8037 ir.ot = OT_QUAD; 8038 else 8039 ir.ot = OT_LONG; 8040 if (i386_record_lea_modrm (&ir)) 8041 return -1; 8042 } 8043 break; 8044 8045 case 0x0f7f: /* movq */ 8046 if (i386_record_modrm (&ir)) 8047 return -1; 8048 if (ir.mod == 3) 8049 { 8050 if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) 8051 goto no_support; 8052 record_full_arch_list_add_reg (ir.regcache, 8053 I387_MM0_REGNUM (tdep) + ir.rm); 8054 } 8055 else 8056 { 8057 ir.ot = OT_QUAD; 8058 if (i386_record_lea_modrm (&ir)) 8059 return -1; 8060 } 8061 break; 8062 8063 case 0xf30fb8: /* popcnt */ 8064 if (i386_record_modrm (&ir)) 8065 return -1; 8066 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); 8067 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 8068 break; 8069 8070 case 0x660fd6: /* movq */ 8071 if (i386_record_modrm (&ir)) 8072 return -1; 8073 if (ir.mod == 3) 8074 { 8075 ir.rm |= ir.rex_b; 8076 if (!i386_xmm_regnum_p (gdbarch, 8077 I387_XMM0_REGNUM (tdep) + ir.rm)) 8078 goto no_support; 8079 record_full_arch_list_add_reg (ir.regcache, 8080 I387_XMM0_REGNUM (tdep) + ir.rm); 8081 } 8082 else 8083 { 8084 ir.ot = OT_QUAD; 8085 if (i386_record_lea_modrm (&ir)) 8086 return -1; 8087 } 8088 break; 8089 8090 case 0x660f3817: /* ptest */ 8091 case 0x0f2e: /* ucomiss */ 8092 case 0x660f2e: /* ucomisd */ 8093 case 0x0f2f: /* comiss */ 8094 case 0x660f2f: /* comisd */ 8095 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); 8096 break; 8097 8098 case 0x0ff7: /* maskmovq */ 8099 regcache_raw_read_unsigned (ir.regcache, 8100 ir.regmap[X86_RECORD_REDI_REGNUM], 8101 &addr); 8102 if (record_full_arch_list_add_mem (addr, 64)) 8103 return -1; 8104 break; 8105 8106 case 0x660ff7: /* maskmovdqu */ 8107 regcache_raw_read_unsigned (ir.regcache, 8108 ir.regmap[X86_RECORD_REDI_REGNUM], 8109 &addr); 8110 if (record_full_arch_list_add_mem (addr, 128)) 8111 return -1; 8112 break; 8113 8114 default: 8115 goto no_support; 8116 break; 8117 } 8118 break; 8119 8120 default: 8121 goto no_support; 8122 break; 8123 } 8124 8125 /* In the future, maybe still need to deal with need_dasm. */ 8126 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); 8127 if (record_full_arch_list_add_end ()) 8128 return -1; 8129 8130 return 0; 8131 8132 no_support: 8133 printf_unfiltered (_("Process record does not support instruction 0x%02x " 8134 "at address %s.\n"), 8135 (unsigned int) (opcode), 8136 paddress (gdbarch, ir.orig_addr)); 8137 return -1; 8138 } 8139 8140 static const int i386_record_regmap[] = 8141 { 8142 I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, 8143 I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, 8144 0, 0, 0, 0, 0, 0, 0, 0, 8145 I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, 8146 I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM 8147 }; 8148 8149 /* Check that the given address appears suitable for a fast 8150 tracepoint, which on x86-64 means that we need an instruction of at 8151 least 5 bytes, so that we can overwrite it with a 4-byte-offset 8152 jump and not have to worry about program jumps to an address in the 8153 middle of the tracepoint jump. On x86, it may be possible to use 8154 4-byte jumps with a 2-byte offset to a trampoline located in the 8155 bottom 64 KiB of memory. Returns 1 if OK, and writes a size 8156 of instruction to replace, and 0 if not, plus an explanatory 8157 string. */ 8158 8159 static int 8160 i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr, 8161 std::string *msg) 8162 { 8163 int len, jumplen; 8164 8165 /* Ask the target for the minimum instruction length supported. */ 8166 jumplen = target_get_min_fast_tracepoint_insn_len (); 8167 8168 if (jumplen < 0) 8169 { 8170 /* If the target does not support the get_min_fast_tracepoint_insn_len 8171 operation, assume that fast tracepoints will always be implemented 8172 using 4-byte relative jumps on both x86 and x86-64. */ 8173 jumplen = 5; 8174 } 8175 else if (jumplen == 0) 8176 { 8177 /* If the target does support get_min_fast_tracepoint_insn_len but 8178 returns zero, then the IPA has not loaded yet. In this case, 8179 we optimistically assume that truncated 2-byte relative jumps 8180 will be available on x86, and compensate later if this assumption 8181 turns out to be incorrect. On x86-64 architectures, 4-byte relative 8182 jumps will always be used. */ 8183 jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; 8184 } 8185 8186 /* Check for fit. */ 8187 len = gdb_insn_length (gdbarch, addr); 8188 8189 if (len < jumplen) 8190 { 8191 /* Return a bit of target-specific detail to add to the caller's 8192 generic failure message. */ 8193 if (msg) 8194 *msg = string_printf (_("; instruction is only %d bytes long, " 8195 "need at least %d bytes for the jump"), 8196 len, jumplen); 8197 return 0; 8198 } 8199 else 8200 { 8201 if (msg) 8202 msg->clear (); 8203 return 1; 8204 } 8205 } 8206 8207 /* Return a floating-point format for a floating-point variable of 8208 length LEN in bits. If non-NULL, NAME is the name of its type. 8209 If no suitable type is found, return NULL. */ 8210 8211 static const struct floatformat ** 8212 i386_floatformat_for_type (struct gdbarch *gdbarch, 8213 const char *name, int len) 8214 { 8215 if (len == 128 && name) 8216 if (strcmp (name, "__float128") == 0 8217 || strcmp (name, "_Float128") == 0 8218 || strcmp (name, "complex _Float128") == 0 8219 || strcmp (name, "complex(kind=16)") == 0 8220 || strcmp (name, "quad complex") == 0 8221 || strcmp (name, "real(kind=16)") == 0 8222 || strcmp (name, "real*16") == 0) 8223 return floatformats_ia64_quad; 8224 8225 return default_floatformat_for_type (gdbarch, name, len); 8226 } 8227 8228 static int 8229 i386_validate_tdesc_p (struct gdbarch_tdep *tdep, 8230 struct tdesc_arch_data *tdesc_data) 8231 { 8232 const struct target_desc *tdesc = tdep->tdesc; 8233 const struct tdesc_feature *feature_core; 8234 8235 const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx, 8236 *feature_avx512, *feature_pkeys, *feature_segments; 8237 int i, num_regs, valid_p; 8238 8239 if (! tdesc_has_registers (tdesc)) 8240 return 0; 8241 8242 /* Get core registers. */ 8243 feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); 8244 if (feature_core == NULL) 8245 return 0; 8246 8247 /* Get SSE registers. */ 8248 feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); 8249 8250 /* Try AVX registers. */ 8251 feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); 8252 8253 /* Try MPX registers. */ 8254 feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx"); 8255 8256 /* Try AVX512 registers. */ 8257 feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512"); 8258 8259 /* Try segment base registers. */ 8260 feature_segments = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments"); 8261 8262 /* Try PKEYS */ 8263 feature_pkeys = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys"); 8264 8265 valid_p = 1; 8266 8267 /* The XCR0 bits. */ 8268 if (feature_avx512) 8269 { 8270 /* AVX512 register description requires AVX register description. */ 8271 if (!feature_avx) 8272 return 0; 8273 8274 tdep->xcr0 = X86_XSTATE_AVX_AVX512_MASK; 8275 8276 /* It may have been set by OSABI initialization function. */ 8277 if (tdep->k0_regnum < 0) 8278 { 8279 tdep->k_register_names = i386_k_names; 8280 tdep->k0_regnum = I386_K0_REGNUM; 8281 } 8282 8283 for (i = 0; i < I387_NUM_K_REGS; i++) 8284 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, 8285 tdep->k0_regnum + i, 8286 i386_k_names[i]); 8287 8288 if (tdep->num_zmm_regs == 0) 8289 { 8290 tdep->zmmh_register_names = i386_zmmh_names; 8291 tdep->num_zmm_regs = 8; 8292 tdep->zmm0h_regnum = I386_ZMM0H_REGNUM; 8293 } 8294 8295 for (i = 0; i < tdep->num_zmm_regs; i++) 8296 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, 8297 tdep->zmm0h_regnum + i, 8298 tdep->zmmh_register_names[i]); 8299 8300 for (i = 0; i < tdep->num_xmm_avx512_regs; i++) 8301 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, 8302 tdep->xmm16_regnum + i, 8303 tdep->xmm_avx512_register_names[i]); 8304 8305 for (i = 0; i < tdep->num_ymm_avx512_regs; i++) 8306 valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, 8307 tdep->ymm16h_regnum + i, 8308 tdep->ymm16h_register_names[i]); 8309 } 8310 if (feature_avx) 8311 { 8312 /* AVX register description requires SSE register description. */ 8313 if (!feature_sse) 8314 return 0; 8315 8316 if (!feature_avx512) 8317 tdep->xcr0 = X86_XSTATE_AVX_MASK; 8318 8319 /* It may have been set by OSABI initialization function. */ 8320 if (tdep->num_ymm_regs == 0) 8321 { 8322 tdep->ymmh_register_names = i386_ymmh_names; 8323 tdep->num_ymm_regs = 8; 8324 tdep->ymm0h_regnum = I386_YMM0H_REGNUM; 8325 } 8326 8327 for (i = 0; i < tdep->num_ymm_regs; i++) 8328 valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, 8329 tdep->ymm0h_regnum + i, 8330 tdep->ymmh_register_names[i]); 8331 } 8332 else if (feature_sse) 8333 tdep->xcr0 = X86_XSTATE_SSE_MASK; 8334 else 8335 { 8336 tdep->xcr0 = X86_XSTATE_X87_MASK; 8337 tdep->num_xmm_regs = 0; 8338 } 8339 8340 num_regs = tdep->num_core_regs; 8341 for (i = 0; i < num_regs; i++) 8342 valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, 8343 tdep->register_names[i]); 8344 8345 if (feature_sse) 8346 { 8347 /* Need to include %mxcsr, so add one. */ 8348 num_regs += tdep->num_xmm_regs + 1; 8349 for (; i < num_regs; i++) 8350 valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, 8351 tdep->register_names[i]); 8352 } 8353 8354 if (feature_mpx) 8355 { 8356 tdep->xcr0 |= X86_XSTATE_MPX_MASK; 8357 8358 if (tdep->bnd0r_regnum < 0) 8359 { 8360 tdep->mpx_register_names = i386_mpx_names; 8361 tdep->bnd0r_regnum = I386_BND0R_REGNUM; 8362 tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM; 8363 } 8364 8365 for (i = 0; i < I387_NUM_MPX_REGS; i++) 8366 valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data, 8367 I387_BND0R_REGNUM (tdep) + i, 8368 tdep->mpx_register_names[i]); 8369 } 8370 8371 if (feature_segments) 8372 { 8373 if (tdep->fsbase_regnum < 0) 8374 tdep->fsbase_regnum = I386_FSBASE_REGNUM; 8375 valid_p &= tdesc_numbered_register (feature_segments, tdesc_data, 8376 tdep->fsbase_regnum, "fs_base"); 8377 valid_p &= tdesc_numbered_register (feature_segments, tdesc_data, 8378 tdep->fsbase_regnum + 1, "gs_base"); 8379 } 8380 8381 if (feature_pkeys) 8382 { 8383 tdep->xcr0 |= X86_XSTATE_PKRU; 8384 if (tdep->pkru_regnum < 0) 8385 { 8386 tdep->pkeys_register_names = i386_pkeys_names; 8387 tdep->pkru_regnum = I386_PKRU_REGNUM; 8388 tdep->num_pkeys_regs = 1; 8389 } 8390 8391 for (i = 0; i < I387_NUM_PKEYS_REGS; i++) 8392 valid_p &= tdesc_numbered_register (feature_pkeys, tdesc_data, 8393 I387_PKRU_REGNUM (tdep) + i, 8394 tdep->pkeys_register_names[i]); 8395 } 8396 8397 return valid_p; 8398 } 8399 8400 8401 8402 /* Implement the type_align gdbarch function. */ 8403 8404 static ULONGEST 8405 i386_type_align (struct gdbarch *gdbarch, struct type *type) 8406 { 8407 type = check_typedef (type); 8408 8409 if (gdbarch_ptr_bit (gdbarch) == 32) 8410 { 8411 if ((type->code () == TYPE_CODE_INT 8412 || type->code () == TYPE_CODE_FLT) 8413 && TYPE_LENGTH (type) > 4) 8414 return 4; 8415 8416 /* Handle x86's funny long double. */ 8417 if (type->code () == TYPE_CODE_FLT 8418 && gdbarch_long_double_bit (gdbarch) == TYPE_LENGTH (type) * 8) 8419 return 4; 8420 } 8421 8422 return 0; 8423 } 8424 8425 8426 /* Note: This is called for both i386 and amd64. */ 8427 8428 static struct gdbarch * 8429 i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 8430 { 8431 struct gdbarch_tdep *tdep; 8432 struct gdbarch *gdbarch; 8433 struct tdesc_arch_data *tdesc_data; 8434 const struct target_desc *tdesc; 8435 int mm0_regnum; 8436 int ymm0_regnum; 8437 int bnd0_regnum; 8438 int num_bnd_cooked; 8439 8440 /* If there is already a candidate, use it. */ 8441 arches = gdbarch_list_lookup_by_info (arches, &info); 8442 if (arches != NULL) 8443 return arches->gdbarch; 8444 8445 /* Allocate space for the new architecture. Assume i386 for now. */ 8446 tdep = XCNEW (struct gdbarch_tdep); 8447 gdbarch = gdbarch_alloc (&info, tdep); 8448 8449 /* General-purpose registers. */ 8450 tdep->gregset_reg_offset = NULL; 8451 tdep->gregset_num_regs = I386_NUM_GREGS; 8452 tdep->sizeof_gregset = 0; 8453 8454 /* Floating-point registers. */ 8455 tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; 8456 tdep->fpregset = &i386_fpregset; 8457 8458 /* The default settings include the FPU registers, the MMX registers 8459 and the SSE registers. This can be overridden for a specific ABI 8460 by adjusting the members `st0_regnum', `mm0_regnum' and 8461 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers 8462 will show up in the output of "info all-registers". */ 8463 8464 tdep->st0_regnum = I386_ST0_REGNUM; 8465 8466 /* I386_NUM_XREGS includes %mxcsr, so substract one. */ 8467 tdep->num_xmm_regs = I386_NUM_XREGS - 1; 8468 8469 tdep->jb_pc_offset = -1; 8470 tdep->struct_return = pcc_struct_return; 8471 tdep->sigtramp_start = 0; 8472 tdep->sigtramp_end = 0; 8473 tdep->sigtramp_p = i386_sigtramp_p; 8474 tdep->sigcontext_addr = NULL; 8475 tdep->sc_reg_offset = NULL; 8476 tdep->sc_pc_offset = -1; 8477 tdep->sc_sp_offset = -1; 8478 8479 tdep->xsave_xcr0_offset = -1; 8480 8481 tdep->record_regmap = i386_record_regmap; 8482 8483 set_gdbarch_type_align (gdbarch, i386_type_align); 8484 8485 /* The format used for `long double' on almost all i386 targets is 8486 the i387 extended floating-point format. In fact, of all targets 8487 in the GCC 2.95 tree, only OSF/1 does it different, and insists 8488 on having a `long double' that's not `long' at all. */ 8489 set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); 8490 8491 /* Although the i387 extended floating-point has only 80 significant 8492 bits, a `long double' actually takes up 96, probably to enforce 8493 alignment. */ 8494 set_gdbarch_long_double_bit (gdbarch, 96); 8495 8496 /* Support of bfloat16 format. */ 8497 set_gdbarch_bfloat16_format (gdbarch, floatformats_bfloat16); 8498 8499 /* Support for floating-point data type variants. */ 8500 set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type); 8501 8502 /* Register numbers of various important registers. */ 8503 set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ 8504 set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ 8505 set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ 8506 set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ 8507 8508 /* NOTE: kettenis/20040418: GCC does have two possible register 8509 numbering schemes on the i386: dbx and SVR4. These schemes 8510 differ in how they number %ebp, %esp, %eflags, and the 8511 floating-point registers, and are implemented by the arrays 8512 dbx_register_map[] and svr4_dbx_register_map in 8513 gcc/config/i386.c. GCC also defines a third numbering scheme in 8514 gcc/config/i386.c, which it designates as the "default" register 8515 map used in 64bit mode. This last register numbering scheme is 8516 implemented in dbx64_register_map, and is used for AMD64; see 8517 amd64-tdep.c. 8518 8519 Currently, each GCC i386 target always uses the same register 8520 numbering scheme across all its supported debugging formats 8521 i.e. SDB (COFF), stabs and DWARF 2. This is because 8522 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the 8523 DBX_REGISTER_NUMBER macro which is defined by each target's 8524 respective config header in a manner independent of the requested 8525 output debugging format. 8526 8527 This does not match the arrangement below, which presumes that 8528 the SDB and stabs numbering schemes differ from the DWARF and 8529 DWARF 2 ones. The reason for this arrangement is that it is 8530 likely to get the numbering scheme for the target's 8531 default/native debug format right. For targets where GCC is the 8532 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for 8533 targets where the native toolchain uses a different numbering 8534 scheme for a particular debug format (stabs-in-ELF on Solaris) 8535 the defaults below will have to be overridden, like 8536 i386_elf_init_abi() does. */ 8537 8538 /* Use the dbx register numbering scheme for stabs and COFF. */ 8539 set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); 8540 set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); 8541 8542 /* Use the SVR4 register numbering scheme for DWARF 2. */ 8543 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum); 8544 8545 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to 8546 be in use on any of the supported i386 targets. */ 8547 8548 set_gdbarch_print_float_info (gdbarch, i387_print_float_info); 8549 8550 set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); 8551 8552 /* Call dummy code. */ 8553 set_gdbarch_call_dummy_location (gdbarch, ON_STACK); 8554 set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code); 8555 set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); 8556 set_gdbarch_frame_align (gdbarch, i386_frame_align); 8557 8558 set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); 8559 set_gdbarch_register_to_value (gdbarch, i386_register_to_value); 8560 set_gdbarch_value_to_register (gdbarch, i386_value_to_register); 8561 8562 set_gdbarch_return_value (gdbarch, i386_return_value); 8563 8564 set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); 8565 8566 /* Stack grows downward. */ 8567 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 8568 8569 set_gdbarch_breakpoint_kind_from_pc (gdbarch, i386_breakpoint::kind_from_pc); 8570 set_gdbarch_sw_breakpoint_from_kind (gdbarch, i386_breakpoint::bp_from_kind); 8571 8572 set_gdbarch_decr_pc_after_break (gdbarch, 1); 8573 set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); 8574 8575 set_gdbarch_frame_args_skip (gdbarch, 8); 8576 8577 set_gdbarch_print_insn (gdbarch, i386_print_insn); 8578 8579 set_gdbarch_dummy_id (gdbarch, i386_dummy_id); 8580 8581 set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); 8582 8583 /* Add the i386 register groups. */ 8584 i386_add_reggroups (gdbarch); 8585 tdep->register_reggroup_p = i386_register_reggroup_p; 8586 8587 /* Helper for function argument information. */ 8588 set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); 8589 8590 /* Hook the function epilogue frame unwinder. This unwinder is 8591 appended to the list first, so that it supercedes the DWARF 8592 unwinder in function epilogues (where the DWARF unwinder 8593 currently fails). */ 8594 frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); 8595 8596 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended 8597 to the list before the prologue-based unwinders, so that DWARF 8598 CFI info will be used if it is available. */ 8599 dwarf2_append_unwinders (gdbarch); 8600 8601 frame_base_set_default (gdbarch, &i386_frame_base); 8602 8603 /* Pseudo registers may be changed by amd64_init_abi. */ 8604 set_gdbarch_pseudo_register_read_value (gdbarch, 8605 i386_pseudo_register_read_value); 8606 set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); 8607 set_gdbarch_ax_pseudo_register_collect (gdbarch, 8608 i386_ax_pseudo_register_collect); 8609 8610 set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); 8611 set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); 8612 8613 /* Override the normal target description method to make the AVX 8614 upper halves anonymous. */ 8615 set_gdbarch_register_name (gdbarch, i386_register_name); 8616 8617 /* Even though the default ABI only includes general-purpose registers, 8618 floating-point registers and the SSE registers, we have to leave a 8619 gap for the upper AVX, MPX and AVX512 registers. */ 8620 set_gdbarch_num_regs (gdbarch, I386_NUM_REGS); 8621 8622 set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); 8623 8624 /* Get the x86 target description from INFO. */ 8625 tdesc = info.target_desc; 8626 if (! tdesc_has_registers (tdesc)) 8627 tdesc = i386_target_description (X86_XSTATE_SSE_MASK, false); 8628 tdep->tdesc = tdesc; 8629 8630 tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; 8631 tdep->register_names = i386_register_names; 8632 8633 /* No upper YMM registers. */ 8634 tdep->ymmh_register_names = NULL; 8635 tdep->ymm0h_regnum = -1; 8636 8637 /* No upper ZMM registers. */ 8638 tdep->zmmh_register_names = NULL; 8639 tdep->zmm0h_regnum = -1; 8640 8641 /* No high XMM registers. */ 8642 tdep->xmm_avx512_register_names = NULL; 8643 tdep->xmm16_regnum = -1; 8644 8645 /* No upper YMM16-31 registers. */ 8646 tdep->ymm16h_register_names = NULL; 8647 tdep->ymm16h_regnum = -1; 8648 8649 tdep->num_byte_regs = 8; 8650 tdep->num_word_regs = 8; 8651 tdep->num_dword_regs = 0; 8652 tdep->num_mmx_regs = 8; 8653 tdep->num_ymm_regs = 0; 8654 8655 /* No MPX registers. */ 8656 tdep->bnd0r_regnum = -1; 8657 tdep->bndcfgu_regnum = -1; 8658 8659 /* No AVX512 registers. */ 8660 tdep->k0_regnum = -1; 8661 tdep->num_zmm_regs = 0; 8662 tdep->num_ymm_avx512_regs = 0; 8663 tdep->num_xmm_avx512_regs = 0; 8664 8665 /* No PKEYS registers */ 8666 tdep->pkru_regnum = -1; 8667 tdep->num_pkeys_regs = 0; 8668 8669 /* No segment base registers. */ 8670 tdep->fsbase_regnum = -1; 8671 8672 tdesc_data = tdesc_data_alloc (); 8673 8674 set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); 8675 8676 set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); 8677 8678 set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call); 8679 set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret); 8680 set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump); 8681 8682 /* Hook in ABI-specific overrides, if they have been registered. 8683 Note: If INFO specifies a 64 bit arch, this is where we turn 8684 a 32-bit i386 into a 64-bit amd64. */ 8685 info.tdesc_data = tdesc_data; 8686 gdbarch_init_osabi (info, gdbarch); 8687 8688 if (!i386_validate_tdesc_p (tdep, tdesc_data)) 8689 { 8690 tdesc_data_cleanup (tdesc_data); 8691 xfree (tdep); 8692 gdbarch_free (gdbarch); 8693 return NULL; 8694 } 8695 8696 num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); 8697 8698 /* Wire in pseudo registers. Number of pseudo registers may be 8699 changed. */ 8700 set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs 8701 + tdep->num_word_regs 8702 + tdep->num_dword_regs 8703 + tdep->num_mmx_regs 8704 + tdep->num_ymm_regs 8705 + num_bnd_cooked 8706 + tdep->num_ymm_avx512_regs 8707 + tdep->num_zmm_regs)); 8708 8709 /* Target description may be changed. */ 8710 tdesc = tdep->tdesc; 8711 8712 tdesc_use_registers (gdbarch, tdesc, tdesc_data); 8713 8714 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ 8715 set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); 8716 8717 /* Make %al the first pseudo-register. */ 8718 tdep->al_regnum = gdbarch_num_regs (gdbarch); 8719 tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; 8720 8721 ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; 8722 if (tdep->num_dword_regs) 8723 { 8724 /* Support dword pseudo-register if it hasn't been disabled. */ 8725 tdep->eax_regnum = ymm0_regnum; 8726 ymm0_regnum += tdep->num_dword_regs; 8727 } 8728 else 8729 tdep->eax_regnum = -1; 8730 8731 mm0_regnum = ymm0_regnum; 8732 if (tdep->num_ymm_regs) 8733 { 8734 /* Support YMM pseudo-register if it is available. */ 8735 tdep->ymm0_regnum = ymm0_regnum; 8736 mm0_regnum += tdep->num_ymm_regs; 8737 } 8738 else 8739 tdep->ymm0_regnum = -1; 8740 8741 if (tdep->num_ymm_avx512_regs) 8742 { 8743 /* Support YMM16-31 pseudo registers if available. */ 8744 tdep->ymm16_regnum = mm0_regnum; 8745 mm0_regnum += tdep->num_ymm_avx512_regs; 8746 } 8747 else 8748 tdep->ymm16_regnum = -1; 8749 8750 if (tdep->num_zmm_regs) 8751 { 8752 /* Support ZMM pseudo-register if it is available. */ 8753 tdep->zmm0_regnum = mm0_regnum; 8754 mm0_regnum += tdep->num_zmm_regs; 8755 } 8756 else 8757 tdep->zmm0_regnum = -1; 8758 8759 bnd0_regnum = mm0_regnum; 8760 if (tdep->num_mmx_regs != 0) 8761 { 8762 /* Support MMX pseudo-register if MMX hasn't been disabled. */ 8763 tdep->mm0_regnum = mm0_regnum; 8764 bnd0_regnum += tdep->num_mmx_regs; 8765 } 8766 else 8767 tdep->mm0_regnum = -1; 8768 8769 if (tdep->bnd0r_regnum > 0) 8770 tdep->bnd0_regnum = bnd0_regnum; 8771 else 8772 tdep-> bnd0_regnum = -1; 8773 8774 /* Hook in the legacy prologue-based unwinders last (fallback). */ 8775 frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); 8776 frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); 8777 frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); 8778 8779 /* If we have a register mapping, enable the generic core file 8780 support, unless it has already been enabled. */ 8781 if (tdep->gregset_reg_offset 8782 && !gdbarch_iterate_over_regset_sections_p (gdbarch)) 8783 set_gdbarch_iterate_over_regset_sections 8784 (gdbarch, i386_iterate_over_regset_sections); 8785 8786 set_gdbarch_fast_tracepoint_valid_at (gdbarch, 8787 i386_fast_tracepoint_valid_at); 8788 8789 return gdbarch; 8790 } 8791 8792 8793 8794 /* Return the target description for a specified XSAVE feature mask. */ 8795 8796 const struct target_desc * 8797 i386_target_description (uint64_t xcr0, bool segments) 8798 { 8799 static target_desc *i386_tdescs \ 8800 [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {}; 8801 target_desc **tdesc; 8802 8803 tdesc = &i386_tdescs[(xcr0 & X86_XSTATE_SSE) ? 1 : 0] 8804 [(xcr0 & X86_XSTATE_AVX) ? 1 : 0] 8805 [(xcr0 & X86_XSTATE_MPX) ? 1 : 0] 8806 [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0] 8807 [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0] 8808 [segments ? 1 : 0]; 8809 8810 if (*tdesc == NULL) 8811 *tdesc = i386_create_target_description (xcr0, false, segments); 8812 8813 return *tdesc; 8814 } 8815 8816 #define MPX_BASE_MASK (~(ULONGEST) 0xfff) 8817 8818 /* Find the bound directory base address. */ 8819 8820 static unsigned long 8821 i386_mpx_bd_base (void) 8822 { 8823 struct regcache *rcache; 8824 struct gdbarch_tdep *tdep; 8825 ULONGEST ret; 8826 enum register_status regstatus; 8827 8828 rcache = get_current_regcache (); 8829 tdep = gdbarch_tdep (rcache->arch ()); 8830 8831 regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret); 8832 8833 if (regstatus != REG_VALID) 8834 error (_("BNDCFGU register invalid, read status %d."), regstatus); 8835 8836 return ret & MPX_BASE_MASK; 8837 } 8838 8839 int 8840 i386_mpx_enabled (void) 8841 { 8842 const struct gdbarch_tdep *tdep = gdbarch_tdep (get_current_arch ()); 8843 const struct target_desc *tdesc = tdep->tdesc; 8844 8845 return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL); 8846 } 8847 8848 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */ 8849 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */ 8850 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */ 8851 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */ 8852 8853 /* Find the bound table entry given the pointer location and the base 8854 address of the table. */ 8855 8856 static CORE_ADDR 8857 i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base) 8858 { 8859 CORE_ADDR offset1; 8860 CORE_ADDR offset2; 8861 CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift; 8862 CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift; 8863 CORE_ADDR bd_entry_addr; 8864 CORE_ADDR bt_addr; 8865 CORE_ADDR bd_entry; 8866 struct gdbarch *gdbarch = get_current_arch (); 8867 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; 8868 8869 8870 if (gdbarch_ptr_bit (gdbarch) == 64) 8871 { 8872 mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK; 8873 bd_ptr_r_shift = 20; 8874 bd_ptr_l_shift = 3; 8875 bt_select_r_shift = 3; 8876 bt_select_l_shift = 5; 8877 bt_mask = (CORE_ADDR) MPX_BT_MASK; 8878 8879 if ( sizeof (CORE_ADDR) == 4) 8880 error (_("bound table examination not supported\ 8881 for 64-bit process with 32-bit GDB")); 8882 } 8883 else 8884 { 8885 mpx_bd_mask = MPX_BD_MASK_32; 8886 bd_ptr_r_shift = 12; 8887 bd_ptr_l_shift = 2; 8888 bt_select_r_shift = 2; 8889 bt_select_l_shift = 4; 8890 bt_mask = MPX_BT_MASK_32; 8891 } 8892 8893 offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift; 8894 bd_entry_addr = bd_base + offset1; 8895 bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type); 8896 8897 if ((bd_entry & 0x1) == 0) 8898 error (_("Invalid bounds directory entry at %s."), 8899 paddress (get_current_arch (), bd_entry_addr)); 8900 8901 /* Clearing status bit. */ 8902 bd_entry--; 8903 bt_addr = bd_entry & ~bt_select_r_shift; 8904 offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift; 8905 8906 return bt_addr + offset2; 8907 } 8908 8909 /* Print routine for the mpx bounds. */ 8910 8911 static void 8912 i386_mpx_print_bounds (const CORE_ADDR bt_entry[4]) 8913 { 8914 struct ui_out *uiout = current_uiout; 8915 LONGEST size; 8916 struct gdbarch *gdbarch = get_current_arch (); 8917 CORE_ADDR onecompl = ~((CORE_ADDR) 0); 8918 int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0); 8919 8920 if (bounds_in_map == 1) 8921 { 8922 uiout->text ("Null bounds on map:"); 8923 uiout->text (" pointer value = "); 8924 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); 8925 uiout->text ("."); 8926 uiout->text ("\n"); 8927 } 8928 else 8929 { 8930 uiout->text ("{lbound = "); 8931 uiout->field_core_addr ("lower-bound", gdbarch, bt_entry[0]); 8932 uiout->text (", ubound = "); 8933 8934 /* The upper bound is stored in 1's complement. */ 8935 uiout->field_core_addr ("upper-bound", gdbarch, ~bt_entry[1]); 8936 uiout->text ("}: pointer value = "); 8937 uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); 8938 8939 if (gdbarch_ptr_bit (gdbarch) == 64) 8940 size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]); 8941 else 8942 size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]); 8943 8944 /* In case the bounds are 0x0 and 0xffff... the difference will be -1. 8945 -1 represents in this sense full memory access, and there is no need 8946 one to the size. */ 8947 8948 size = (size > -1 ? size + 1 : size); 8949 uiout->text (", size = "); 8950 uiout->field_string ("size", plongest (size)); 8951 8952 uiout->text (", metadata = "); 8953 uiout->field_core_addr ("metadata", gdbarch, bt_entry[3]); 8954 uiout->text ("\n"); 8955 } 8956 } 8957 8958 /* Implement the command "show mpx bound". */ 8959 8960 static void 8961 i386_mpx_info_bounds (const char *args, int from_tty) 8962 { 8963 CORE_ADDR bd_base = 0; 8964 CORE_ADDR addr; 8965 CORE_ADDR bt_entry_addr = 0; 8966 CORE_ADDR bt_entry[4]; 8967 int i; 8968 struct gdbarch *gdbarch = get_current_arch (); 8969 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; 8970 8971 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 8972 || !i386_mpx_enabled ()) 8973 { 8974 printf_unfiltered (_("Intel Memory Protection Extensions not " 8975 "supported on this target.\n")); 8976 return; 8977 } 8978 8979 if (args == NULL) 8980 { 8981 printf_unfiltered (_("Address of pointer variable expected.\n")); 8982 return; 8983 } 8984 8985 addr = parse_and_eval_address (args); 8986 8987 bd_base = i386_mpx_bd_base (); 8988 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); 8989 8990 memset (bt_entry, 0, sizeof (bt_entry)); 8991 8992 for (i = 0; i < 4; i++) 8993 bt_entry[i] = read_memory_typed_address (bt_entry_addr 8994 + i * TYPE_LENGTH (data_ptr_type), 8995 data_ptr_type); 8996 8997 i386_mpx_print_bounds (bt_entry); 8998 } 8999 9000 /* Implement the command "set mpx bound". */ 9001 9002 static void 9003 i386_mpx_set_bounds (const char *args, int from_tty) 9004 { 9005 CORE_ADDR bd_base = 0; 9006 CORE_ADDR addr, lower, upper; 9007 CORE_ADDR bt_entry_addr = 0; 9008 CORE_ADDR bt_entry[2]; 9009 const char *input = args; 9010 int i; 9011 struct gdbarch *gdbarch = get_current_arch (); 9012 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 9013 struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; 9014 9015 if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 9016 || !i386_mpx_enabled ()) 9017 error (_("Intel Memory Protection Extensions not supported\ 9018 on this target.")); 9019 9020 if (args == NULL) 9021 error (_("Pointer value expected.")); 9022 9023 addr = value_as_address (parse_to_comma_and_eval (&input)); 9024 9025 if (input[0] == ',') 9026 ++input; 9027 if (input[0] == '\0') 9028 error (_("wrong number of arguments: missing lower and upper bound.")); 9029 lower = value_as_address (parse_to_comma_and_eval (&input)); 9030 9031 if (input[0] == ',') 9032 ++input; 9033 if (input[0] == '\0') 9034 error (_("Wrong number of arguments; Missing upper bound.")); 9035 upper = value_as_address (parse_to_comma_and_eval (&input)); 9036 9037 bd_base = i386_mpx_bd_base (); 9038 bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); 9039 for (i = 0; i < 2; i++) 9040 bt_entry[i] = read_memory_typed_address (bt_entry_addr 9041 + i * TYPE_LENGTH (data_ptr_type), 9042 data_ptr_type); 9043 bt_entry[0] = (uint64_t) lower; 9044 bt_entry[1] = ~(uint64_t) upper; 9045 9046 for (i = 0; i < 2; i++) 9047 write_memory_unsigned_integer (bt_entry_addr 9048 + i * TYPE_LENGTH (data_ptr_type), 9049 TYPE_LENGTH (data_ptr_type), byte_order, 9050 bt_entry[i]); 9051 } 9052 9053 static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist; 9054 9055 void _initialize_i386_tdep (); 9056 void 9057 _initialize_i386_tdep () 9058 { 9059 register_gdbarch_init (bfd_arch_i386, i386_gdbarch_init); 9060 9061 /* Add the variable that controls the disassembly flavor. */ 9062 add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, 9063 &disassembly_flavor, _("\ 9064 Set the disassembly flavor."), _("\ 9065 Show the disassembly flavor."), _("\ 9066 The valid values are \"att\" and \"intel\", and the default value is \"att\"."), 9067 NULL, 9068 NULL, /* FIXME: i18n: */ 9069 &setlist, &showlist); 9070 9071 /* Add the variable that controls the convention for returning 9072 structs. */ 9073 add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, 9074 &struct_convention, _("\ 9075 Set the convention for returning small structs."), _("\ 9076 Show the convention for returning small structs."), _("\ 9077 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ 9078 is \"default\"."), 9079 NULL, 9080 NULL, /* FIXME: i18n: */ 9081 &setlist, &showlist); 9082 9083 /* Add "mpx" prefix for the set commands. */ 9084 9085 add_basic_prefix_cmd ("mpx", class_support, _("\ 9086 Set Intel Memory Protection Extensions specific variables."), 9087 &mpx_set_cmdlist, "set mpx ", 9088 0 /* allow-unknown */, &setlist); 9089 9090 /* Add "mpx" prefix for the show commands. */ 9091 9092 add_show_prefix_cmd ("mpx", class_support, _("\ 9093 Show Intel Memory Protection Extensions specific variables."), 9094 &mpx_show_cmdlist, "show mpx ", 9095 0 /* allow-unknown */, &showlist); 9096 9097 /* Add "bound" command for the show mpx commands list. */ 9098 9099 add_cmd ("bound", no_class, i386_mpx_info_bounds, 9100 "Show the memory bounds for a given array/pointer storage\ 9101 in the bound table.", 9102 &mpx_show_cmdlist); 9103 9104 /* Add "bound" command for the set mpx commands list. */ 9105 9106 add_cmd ("bound", no_class, i386_mpx_set_bounds, 9107 "Set the memory bounds for a given array/pointer storage\ 9108 in the bound table.", 9109 &mpx_set_cmdlist); 9110 9111 gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, 9112 i386_svr4_init_abi); 9113 9114 /* Initialize the i386-specific register groups. */ 9115 i386_init_reggroups (); 9116 9117 /* Tell remote stub that we support XML target description. */ 9118 register_remote_support_xml ("i386"); 9119 } 9120