1 /* Target-dependent code for AMD64. 2 3 Copyright (C) 2001-2016 Free Software Foundation, Inc. 4 5 Contributed by Jiri Smid, SuSE Labs. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22 #include "defs.h" 23 #include "opcode/i386.h" 24 #include "dis-asm.h" 25 #include "arch-utils.h" 26 #include "block.h" 27 #include "dummy-frame.h" 28 #include "frame.h" 29 #include "frame-base.h" 30 #include "frame-unwind.h" 31 #include "inferior.h" 32 #include "infrun.h" 33 #include "gdbcmd.h" 34 #include "gdbcore.h" 35 #include "objfiles.h" 36 #include "regcache.h" 37 #include "regset.h" 38 #include "symfile.h" 39 #include "disasm.h" 40 #include "amd64-tdep.h" 41 #include "i387-tdep.h" 42 #include "x86-xstate.h" 43 44 #include "features/i386/amd64.c" 45 #include "features/i386/amd64-avx.c" 46 #include "features/i386/amd64-mpx.c" 47 #include "features/i386/amd64-avx-mpx.c" 48 #include "features/i386/amd64-avx512.c" 49 50 #include "features/i386/x32.c" 51 #include "features/i386/x32-avx.c" 52 #include "features/i386/x32-avx512.c" 53 54 #include "ax.h" 55 #include "ax-gdb.h" 56 57 /* Note that the AMD64 architecture was previously known as x86-64. 58 The latter is (forever) engraved into the canonical system name as 59 returned by config.guess, and used as the name for the AMD64 port 60 of GNU/Linux. The BSD's have renamed their ports to amd64; they 61 don't like to shout. For GDB we prefer the amd64_-prefix over the 62 x86_64_-prefix since it's so much easier to type. */ 63 64 /* Register information. */ 65 66 static const char *amd64_register_names[] = 67 { 68 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", 69 70 /* %r8 is indeed register number 8. */ 71 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 72 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs", 73 74 /* %st0 is register number 24. */ 75 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", 76 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop", 77 78 /* %xmm0 is register number 40. */ 79 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 80 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 81 "mxcsr", 82 }; 83 84 static const char *amd64_ymm_names[] = 85 { 86 "ymm0", "ymm1", "ymm2", "ymm3", 87 "ymm4", "ymm5", "ymm6", "ymm7", 88 "ymm8", "ymm9", "ymm10", "ymm11", 89 "ymm12", "ymm13", "ymm14", "ymm15" 90 }; 91 92 static const char *amd64_ymm_avx512_names[] = 93 { 94 "ymm16", "ymm17", "ymm18", "ymm19", 95 "ymm20", "ymm21", "ymm22", "ymm23", 96 "ymm24", "ymm25", "ymm26", "ymm27", 97 "ymm28", "ymm29", "ymm30", "ymm31" 98 }; 99 100 static const char *amd64_ymmh_names[] = 101 { 102 "ymm0h", "ymm1h", "ymm2h", "ymm3h", 103 "ymm4h", "ymm5h", "ymm6h", "ymm7h", 104 "ymm8h", "ymm9h", "ymm10h", "ymm11h", 105 "ymm12h", "ymm13h", "ymm14h", "ymm15h" 106 }; 107 108 static const char *amd64_ymmh_avx512_names[] = 109 { 110 "ymm16h", "ymm17h", "ymm18h", "ymm19h", 111 "ymm20h", "ymm21h", "ymm22h", "ymm23h", 112 "ymm24h", "ymm25h", "ymm26h", "ymm27h", 113 "ymm28h", "ymm29h", "ymm30h", "ymm31h" 114 }; 115 116 static const char *amd64_mpx_names[] = 117 { 118 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" 119 }; 120 121 static const char *amd64_k_names[] = 122 { 123 "k0", "k1", "k2", "k3", 124 "k4", "k5", "k6", "k7" 125 }; 126 127 static const char *amd64_zmmh_names[] = 128 { 129 "zmm0h", "zmm1h", "zmm2h", "zmm3h", 130 "zmm4h", "zmm5h", "zmm6h", "zmm7h", 131 "zmm8h", "zmm9h", "zmm10h", "zmm11h", 132 "zmm12h", "zmm13h", "zmm14h", "zmm15h", 133 "zmm16h", "zmm17h", "zmm18h", "zmm19h", 134 "zmm20h", "zmm21h", "zmm22h", "zmm23h", 135 "zmm24h", "zmm25h", "zmm26h", "zmm27h", 136 "zmm28h", "zmm29h", "zmm30h", "zmm31h" 137 }; 138 139 static const char *amd64_zmm_names[] = 140 { 141 "zmm0", "zmm1", "zmm2", "zmm3", 142 "zmm4", "zmm5", "zmm6", "zmm7", 143 "zmm8", "zmm9", "zmm10", "zmm11", 144 "zmm12", "zmm13", "zmm14", "zmm15", 145 "zmm16", "zmm17", "zmm18", "zmm19", 146 "zmm20", "zmm21", "zmm22", "zmm23", 147 "zmm24", "zmm25", "zmm26", "zmm27", 148 "zmm28", "zmm29", "zmm30", "zmm31" 149 }; 150 151 static const char *amd64_xmm_avx512_names[] = { 152 "xmm16", "xmm17", "xmm18", "xmm19", 153 "xmm20", "xmm21", "xmm22", "xmm23", 154 "xmm24", "xmm25", "xmm26", "xmm27", 155 "xmm28", "xmm29", "xmm30", "xmm31" 156 }; 157 158 /* DWARF Register Number Mapping as defined in the System V psABI, 159 section 3.6. */ 160 161 static int amd64_dwarf_regmap[] = 162 { 163 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ 164 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, 165 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, 166 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, 167 168 /* Frame Pointer Register RBP. */ 169 AMD64_RBP_REGNUM, 170 171 /* Stack Pointer Register RSP. */ 172 AMD64_RSP_REGNUM, 173 174 /* Extended Integer Registers 8 - 15. */ 175 AMD64_R8_REGNUM, /* %r8 */ 176 AMD64_R9_REGNUM, /* %r9 */ 177 AMD64_R10_REGNUM, /* %r10 */ 178 AMD64_R11_REGNUM, /* %r11 */ 179 AMD64_R12_REGNUM, /* %r12 */ 180 AMD64_R13_REGNUM, /* %r13 */ 181 AMD64_R14_REGNUM, /* %r14 */ 182 AMD64_R15_REGNUM, /* %r15 */ 183 184 /* Return Address RA. Mapped to RIP. */ 185 AMD64_RIP_REGNUM, 186 187 /* SSE Registers 0 - 7. */ 188 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, 189 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, 190 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, 191 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, 192 193 /* Extended SSE Registers 8 - 15. */ 194 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, 195 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, 196 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, 197 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, 198 199 /* Floating Point Registers 0-7. */ 200 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, 201 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, 202 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, 203 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, 204 205 /* MMX Registers 0 - 7. 206 We have to handle those registers specifically, as their register 207 number within GDB depends on the target (or they may even not be 208 available at all). */ 209 -1, -1, -1, -1, -1, -1, -1, -1, 210 211 /* Control and Status Flags Register. */ 212 AMD64_EFLAGS_REGNUM, 213 214 /* Selector Registers. */ 215 AMD64_ES_REGNUM, 216 AMD64_CS_REGNUM, 217 AMD64_SS_REGNUM, 218 AMD64_DS_REGNUM, 219 AMD64_FS_REGNUM, 220 AMD64_GS_REGNUM, 221 -1, 222 -1, 223 224 /* Segment Base Address Registers. */ 225 -1, 226 -1, 227 -1, 228 -1, 229 230 /* Special Selector Registers. */ 231 -1, 232 -1, 233 234 /* Floating Point Control Registers. */ 235 AMD64_MXCSR_REGNUM, 236 AMD64_FCTRL_REGNUM, 237 AMD64_FSTAT_REGNUM 238 }; 239 240 static const int amd64_dwarf_regmap_len = 241 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); 242 243 /* Convert DWARF register number REG to the appropriate register 244 number used by GDB. */ 245 246 static int 247 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) 248 { 249 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 250 int ymm0_regnum = tdep->ymm0_regnum; 251 int regnum = -1; 252 253 if (reg >= 0 && reg < amd64_dwarf_regmap_len) 254 regnum = amd64_dwarf_regmap[reg]; 255 256 if (ymm0_regnum >= 0 257 && i386_xmm_regnum_p (gdbarch, regnum)) 258 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep); 259 260 return regnum; 261 } 262 263 /* Map architectural register numbers to gdb register numbers. */ 264 265 static const int amd64_arch_regmap[16] = 266 { 267 AMD64_RAX_REGNUM, /* %rax */ 268 AMD64_RCX_REGNUM, /* %rcx */ 269 AMD64_RDX_REGNUM, /* %rdx */ 270 AMD64_RBX_REGNUM, /* %rbx */ 271 AMD64_RSP_REGNUM, /* %rsp */ 272 AMD64_RBP_REGNUM, /* %rbp */ 273 AMD64_RSI_REGNUM, /* %rsi */ 274 AMD64_RDI_REGNUM, /* %rdi */ 275 AMD64_R8_REGNUM, /* %r8 */ 276 AMD64_R9_REGNUM, /* %r9 */ 277 AMD64_R10_REGNUM, /* %r10 */ 278 AMD64_R11_REGNUM, /* %r11 */ 279 AMD64_R12_REGNUM, /* %r12 */ 280 AMD64_R13_REGNUM, /* %r13 */ 281 AMD64_R14_REGNUM, /* %r14 */ 282 AMD64_R15_REGNUM /* %r15 */ 283 }; 284 285 static const int amd64_arch_regmap_len = 286 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0])); 287 288 /* Convert architectural register number REG to the appropriate register 289 number used by GDB. */ 290 291 static int 292 amd64_arch_reg_to_regnum (int reg) 293 { 294 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len); 295 296 return amd64_arch_regmap[reg]; 297 } 298 299 /* Register names for byte pseudo-registers. */ 300 301 static const char *amd64_byte_names[] = 302 { 303 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl", 304 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l", 305 "ah", "bh", "ch", "dh" 306 }; 307 308 /* Number of lower byte registers. */ 309 #define AMD64_NUM_LOWER_BYTE_REGS 16 310 311 /* Register names for word pseudo-registers. */ 312 313 static const char *amd64_word_names[] = 314 { 315 "ax", "bx", "cx", "dx", "si", "di", "bp", "", 316 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" 317 }; 318 319 /* Register names for dword pseudo-registers. */ 320 321 static const char *amd64_dword_names[] = 322 { 323 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp", 324 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", 325 "eip" 326 }; 327 328 /* Return the name of register REGNUM. */ 329 330 static const char * 331 amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) 332 { 333 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 334 if (i386_byte_regnum_p (gdbarch, regnum)) 335 return amd64_byte_names[regnum - tdep->al_regnum]; 336 else if (i386_zmm_regnum_p (gdbarch, regnum)) 337 return amd64_zmm_names[regnum - tdep->zmm0_regnum]; 338 else if (i386_ymm_regnum_p (gdbarch, regnum)) 339 return amd64_ymm_names[regnum - tdep->ymm0_regnum]; 340 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) 341 return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum]; 342 else if (i386_word_regnum_p (gdbarch, regnum)) 343 return amd64_word_names[regnum - tdep->ax_regnum]; 344 else if (i386_dword_regnum_p (gdbarch, regnum)) 345 return amd64_dword_names[regnum - tdep->eax_regnum]; 346 else 347 return i386_pseudo_register_name (gdbarch, regnum); 348 } 349 350 static struct value * 351 amd64_pseudo_register_read_value (struct gdbarch *gdbarch, 352 struct regcache *regcache, 353 int regnum) 354 { 355 gdb_byte raw_buf[MAX_REGISTER_SIZE]; 356 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 357 enum register_status status; 358 struct value *result_value; 359 gdb_byte *buf; 360 361 result_value = allocate_value (register_type (gdbarch, regnum)); 362 VALUE_LVAL (result_value) = lval_register; 363 VALUE_REGNUM (result_value) = regnum; 364 buf = value_contents_raw (result_value); 365 366 if (i386_byte_regnum_p (gdbarch, regnum)) 367 { 368 int gpnum = regnum - tdep->al_regnum; 369 370 /* Extract (always little endian). */ 371 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) 372 { 373 /* Special handling for AH, BH, CH, DH. */ 374 status = regcache_raw_read (regcache, 375 gpnum - AMD64_NUM_LOWER_BYTE_REGS, 376 raw_buf); 377 if (status == REG_VALID) 378 memcpy (buf, raw_buf + 1, 1); 379 else 380 mark_value_bytes_unavailable (result_value, 0, 381 TYPE_LENGTH (value_type (result_value))); 382 } 383 else 384 { 385 status = regcache_raw_read (regcache, gpnum, raw_buf); 386 if (status == REG_VALID) 387 memcpy (buf, raw_buf, 1); 388 else 389 mark_value_bytes_unavailable (result_value, 0, 390 TYPE_LENGTH (value_type (result_value))); 391 } 392 } 393 else if (i386_dword_regnum_p (gdbarch, regnum)) 394 { 395 int gpnum = regnum - tdep->eax_regnum; 396 /* Extract (always little endian). */ 397 status = regcache_raw_read (regcache, gpnum, raw_buf); 398 if (status == REG_VALID) 399 memcpy (buf, raw_buf, 4); 400 else 401 mark_value_bytes_unavailable (result_value, 0, 402 TYPE_LENGTH (value_type (result_value))); 403 } 404 else 405 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, 406 result_value); 407 408 return result_value; 409 } 410 411 static void 412 amd64_pseudo_register_write (struct gdbarch *gdbarch, 413 struct regcache *regcache, 414 int regnum, const gdb_byte *buf) 415 { 416 gdb_byte raw_buf[MAX_REGISTER_SIZE]; 417 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 418 419 if (i386_byte_regnum_p (gdbarch, regnum)) 420 { 421 int gpnum = regnum - tdep->al_regnum; 422 423 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) 424 { 425 /* Read ... AH, BH, CH, DH. */ 426 regcache_raw_read (regcache, 427 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); 428 /* ... Modify ... (always little endian). */ 429 memcpy (raw_buf + 1, buf, 1); 430 /* ... Write. */ 431 regcache_raw_write (regcache, 432 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); 433 } 434 else 435 { 436 /* Read ... */ 437 regcache_raw_read (regcache, gpnum, raw_buf); 438 /* ... Modify ... (always little endian). */ 439 memcpy (raw_buf, buf, 1); 440 /* ... Write. */ 441 regcache_raw_write (regcache, gpnum, raw_buf); 442 } 443 } 444 else if (i386_dword_regnum_p (gdbarch, regnum)) 445 { 446 int gpnum = regnum - tdep->eax_regnum; 447 448 /* Read ... */ 449 regcache_raw_read (regcache, gpnum, raw_buf); 450 /* ... Modify ... (always little endian). */ 451 memcpy (raw_buf, buf, 4); 452 /* ... Write. */ 453 regcache_raw_write (regcache, gpnum, raw_buf); 454 } 455 else 456 i386_pseudo_register_write (gdbarch, regcache, regnum, buf); 457 } 458 459 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */ 460 461 static int 462 amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch, 463 struct agent_expr *ax, int regnum) 464 { 465 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 466 467 if (i386_byte_regnum_p (gdbarch, regnum)) 468 { 469 int gpnum = regnum - tdep->al_regnum; 470 471 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) 472 ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS); 473 else 474 ax_reg_mask (ax, gpnum); 475 return 0; 476 } 477 else if (i386_dword_regnum_p (gdbarch, regnum)) 478 { 479 int gpnum = regnum - tdep->eax_regnum; 480 481 ax_reg_mask (ax, gpnum); 482 return 0; 483 } 484 else 485 return i386_ax_pseudo_register_collect (gdbarch, ax, regnum); 486 } 487 488 489 490 /* Register classes as defined in the psABI. */ 491 492 enum amd64_reg_class 493 { 494 AMD64_INTEGER, 495 AMD64_SSE, 496 AMD64_SSEUP, 497 AMD64_X87, 498 AMD64_X87UP, 499 AMD64_COMPLEX_X87, 500 AMD64_NO_CLASS, 501 AMD64_MEMORY 502 }; 503 504 /* Return the union class of CLASS1 and CLASS2. See the psABI for 505 details. */ 506 507 static enum amd64_reg_class 508 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) 509 { 510 /* Rule (a): If both classes are equal, this is the resulting class. */ 511 if (class1 == class2) 512 return class1; 513 514 /* Rule (b): If one of the classes is NO_CLASS, the resulting class 515 is the other class. */ 516 if (class1 == AMD64_NO_CLASS) 517 return class2; 518 if (class2 == AMD64_NO_CLASS) 519 return class1; 520 521 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ 522 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY) 523 return AMD64_MEMORY; 524 525 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ 526 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER) 527 return AMD64_INTEGER; 528 529 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class, 530 MEMORY is used as class. */ 531 if (class1 == AMD64_X87 || class1 == AMD64_X87UP 532 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87 533 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87) 534 return AMD64_MEMORY; 535 536 /* Rule (f): Otherwise class SSE is used. */ 537 return AMD64_SSE; 538 } 539 540 static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]); 541 542 /* Return non-zero if TYPE is a non-POD structure or union type. */ 543 544 static int 545 amd64_non_pod_p (struct type *type) 546 { 547 /* ??? A class with a base class certainly isn't POD, but does this 548 catch all non-POD structure types? */ 549 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) 550 return 1; 551 552 return 0; 553 } 554 555 /* Classify TYPE according to the rules for aggregate (structures and 556 arrays) and union types, and store the result in CLASS. */ 557 558 static void 559 amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2]) 560 { 561 /* 1. If the size of an object is larger than two eightbytes, or in 562 C++, is a non-POD structure or union type, or contains 563 unaligned fields, it has class memory. */ 564 if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type)) 565 { 566 theclass[0] = theclass[1] = AMD64_MEMORY; 567 return; 568 } 569 570 /* 2. Both eightbytes get initialized to class NO_CLASS. */ 571 theclass[0] = theclass[1] = AMD64_NO_CLASS; 572 573 /* 3. Each field of an object is classified recursively so that 574 always two fields are considered. The resulting class is 575 calculated according to the classes of the fields in the 576 eightbyte: */ 577 578 if (TYPE_CODE (type) == TYPE_CODE_ARRAY) 579 { 580 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); 581 582 /* All fields in an array have the same type. */ 583 amd64_classify (subtype, theclass); 584 if (TYPE_LENGTH (type) > 8 && theclass[1] == AMD64_NO_CLASS) 585 theclass[1] = theclass[0]; 586 } 587 else 588 { 589 int i; 590 591 /* Structure or union. */ 592 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT 593 || TYPE_CODE (type) == TYPE_CODE_UNION); 594 595 for (i = 0; i < TYPE_NFIELDS (type); i++) 596 { 597 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); 598 int pos = TYPE_FIELD_BITPOS (type, i) / 64; 599 enum amd64_reg_class subclass[2]; 600 int bitsize = TYPE_FIELD_BITSIZE (type, i); 601 int endpos; 602 603 if (bitsize == 0) 604 bitsize = TYPE_LENGTH (subtype) * 8; 605 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64; 606 607 /* Ignore static fields. */ 608 if (field_is_static (&TYPE_FIELD (type, i))) 609 continue; 610 611 gdb_assert (pos == 0 || pos == 1); 612 613 amd64_classify (subtype, subclass); 614 theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]); 615 if (bitsize <= 64 && pos == 0 && endpos == 1) 616 /* This is a bit of an odd case: We have a field that would 617 normally fit in one of the two eightbytes, except that 618 it is placed in a way that this field straddles them. 619 This has been seen with a structure containing an array. 620 621 The ABI is a bit unclear in this case, but we assume that 622 this field's class (stored in subclass[0]) must also be merged 623 into class[1]. In other words, our field has a piece stored 624 in the second eight-byte, and thus its class applies to 625 the second eight-byte as well. 626 627 In the case where the field length exceeds 8 bytes, 628 it should not be necessary to merge the field class 629 into class[1]. As LEN > 8, subclass[1] is necessarily 630 different from AMD64_NO_CLASS. If subclass[1] is equal 631 to subclass[0], then the normal class[1]/subclass[1] 632 merging will take care of everything. For subclass[1] 633 to be different from subclass[0], I can only see the case 634 where we have a SSE/SSEUP or X87/X87UP pair, which both 635 use up all 16 bytes of the aggregate, and are already 636 handled just fine (because each portion sits on its own 637 8-byte). */ 638 theclass[1] = amd64_merge_classes (theclass[1], subclass[0]); 639 if (pos == 0) 640 theclass[1] = amd64_merge_classes (theclass[1], subclass[1]); 641 } 642 } 643 644 /* 4. Then a post merger cleanup is done: */ 645 646 /* Rule (a): If one of the classes is MEMORY, the whole argument is 647 passed in memory. */ 648 if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY) 649 theclass[0] = theclass[1] = AMD64_MEMORY; 650 651 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to 652 SSE. */ 653 if (theclass[0] == AMD64_SSEUP) 654 theclass[0] = AMD64_SSE; 655 if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE) 656 theclass[1] = AMD64_SSE; 657 } 658 659 /* Classify TYPE, and store the result in CLASS. */ 660 661 static void 662 amd64_classify (struct type *type, enum amd64_reg_class theclass[2]) 663 { 664 enum type_code code = TYPE_CODE (type); 665 int len = TYPE_LENGTH (type); 666 667 theclass[0] = theclass[1] = AMD64_NO_CLASS; 668 669 /* Arguments of types (signed and unsigned) _Bool, char, short, int, 670 long, long long, and pointers are in the INTEGER class. Similarly, 671 range types, used by languages such as Ada, are also in the INTEGER 672 class. */ 673 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM 674 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE 675 || code == TYPE_CODE_CHAR 676 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF) 677 && (len == 1 || len == 2 || len == 4 || len == 8)) 678 theclass[0] = AMD64_INTEGER; 679 680 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64 681 are in class SSE. */ 682 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT) 683 && (len == 4 || len == 8)) 684 /* FIXME: __m64 . */ 685 theclass[0] = AMD64_SSE; 686 687 /* Arguments of types __float128, _Decimal128 and __m128 are split into 688 two halves. The least significant ones belong to class SSE, the most 689 significant one to class SSEUP. */ 690 else if (code == TYPE_CODE_DECFLOAT && len == 16) 691 /* FIXME: __float128, __m128. */ 692 theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP; 693 694 /* The 64-bit mantissa of arguments of type long double belongs to 695 class X87, the 16-bit exponent plus 6 bytes of padding belongs to 696 class X87UP. */ 697 else if (code == TYPE_CODE_FLT && len == 16) 698 /* Class X87 and X87UP. */ 699 theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP; 700 701 /* Arguments of complex T where T is one of the types float or 702 double get treated as if they are implemented as: 703 704 struct complexT { 705 T real; 706 T imag; 707 }; 708 709 */ 710 else if (code == TYPE_CODE_COMPLEX && len == 8) 711 theclass[0] = AMD64_SSE; 712 else if (code == TYPE_CODE_COMPLEX && len == 16) 713 theclass[0] = theclass[1] = AMD64_SSE; 714 715 /* A variable of type complex long double is classified as type 716 COMPLEX_X87. */ 717 else if (code == TYPE_CODE_COMPLEX && len == 32) 718 theclass[0] = AMD64_COMPLEX_X87; 719 720 /* Aggregates. */ 721 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT 722 || code == TYPE_CODE_UNION) 723 amd64_classify_aggregate (type, theclass); 724 } 725 726 static enum return_value_convention 727 amd64_return_value (struct gdbarch *gdbarch, struct value *function, 728 struct type *type, struct regcache *regcache, 729 gdb_byte *readbuf, const gdb_byte *writebuf) 730 { 731 enum amd64_reg_class theclass[2]; 732 int len = TYPE_LENGTH (type); 733 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; 734 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; 735 int integer_reg = 0; 736 int sse_reg = 0; 737 int i; 738 739 gdb_assert (!(readbuf && writebuf)); 740 741 /* 1. Classify the return type with the classification algorithm. */ 742 amd64_classify (type, theclass); 743 744 /* 2. If the type has class MEMORY, then the caller provides space 745 for the return value and passes the address of this storage in 746 %rdi as if it were the first argument to the function. In effect, 747 this address becomes a hidden first argument. 748 749 On return %rax will contain the address that has been passed in 750 by the caller in %rdi. */ 751 if (theclass[0] == AMD64_MEMORY) 752 { 753 /* As indicated by the comment above, the ABI guarantees that we 754 can always find the return value just after the function has 755 returned. */ 756 757 if (readbuf) 758 { 759 ULONGEST addr; 760 761 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr); 762 read_memory (addr, readbuf, TYPE_LENGTH (type)); 763 } 764 765 return RETURN_VALUE_ABI_RETURNS_ADDRESS; 766 } 767 768 /* 8. If the class is COMPLEX_X87, the real part of the value is 769 returned in %st0 and the imaginary part in %st1. */ 770 if (theclass[0] == AMD64_COMPLEX_X87) 771 { 772 if (readbuf) 773 { 774 regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf); 775 regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16); 776 } 777 778 if (writebuf) 779 { 780 i387_return_value (gdbarch, regcache); 781 regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf); 782 regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16); 783 784 /* Fix up the tag word such that both %st(0) and %st(1) are 785 marked as valid. */ 786 regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff); 787 } 788 789 return RETURN_VALUE_REGISTER_CONVENTION; 790 } 791 792 gdb_assert (theclass[1] != AMD64_MEMORY); 793 gdb_assert (len <= 16); 794 795 for (i = 0; len > 0; i++, len -= 8) 796 { 797 int regnum = -1; 798 int offset = 0; 799 800 switch (theclass[i]) 801 { 802 case AMD64_INTEGER: 803 /* 3. If the class is INTEGER, the next available register 804 of the sequence %rax, %rdx is used. */ 805 regnum = integer_regnum[integer_reg++]; 806 break; 807 808 case AMD64_SSE: 809 /* 4. If the class is SSE, the next available SSE register 810 of the sequence %xmm0, %xmm1 is used. */ 811 regnum = sse_regnum[sse_reg++]; 812 break; 813 814 case AMD64_SSEUP: 815 /* 5. If the class is SSEUP, the eightbyte is passed in the 816 upper half of the last used SSE register. */ 817 gdb_assert (sse_reg > 0); 818 regnum = sse_regnum[sse_reg - 1]; 819 offset = 8; 820 break; 821 822 case AMD64_X87: 823 /* 6. If the class is X87, the value is returned on the X87 824 stack in %st0 as 80-bit x87 number. */ 825 regnum = AMD64_ST0_REGNUM; 826 if (writebuf) 827 i387_return_value (gdbarch, regcache); 828 break; 829 830 case AMD64_X87UP: 831 /* 7. If the class is X87UP, the value is returned together 832 with the previous X87 value in %st0. */ 833 gdb_assert (i > 0 && theclass[0] == AMD64_X87); 834 regnum = AMD64_ST0_REGNUM; 835 offset = 8; 836 len = 2; 837 break; 838 839 case AMD64_NO_CLASS: 840 continue; 841 842 default: 843 gdb_assert (!"Unexpected register class."); 844 } 845 846 gdb_assert (regnum != -1); 847 848 if (readbuf) 849 regcache_raw_read_part (regcache, regnum, offset, min (len, 8), 850 readbuf + i * 8); 851 if (writebuf) 852 regcache_raw_write_part (regcache, regnum, offset, min (len, 8), 853 writebuf + i * 8); 854 } 855 856 return RETURN_VALUE_REGISTER_CONVENTION; 857 } 858 859 860 static CORE_ADDR 861 amd64_push_arguments (struct regcache *regcache, int nargs, 862 struct value **args, CORE_ADDR sp, int struct_return) 863 { 864 static int integer_regnum[] = 865 { 866 AMD64_RDI_REGNUM, /* %rdi */ 867 AMD64_RSI_REGNUM, /* %rsi */ 868 AMD64_RDX_REGNUM, /* %rdx */ 869 AMD64_RCX_REGNUM, /* %rcx */ 870 AMD64_R8_REGNUM, /* %r8 */ 871 AMD64_R9_REGNUM /* %r9 */ 872 }; 873 static int sse_regnum[] = 874 { 875 /* %xmm0 ... %xmm7 */ 876 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, 877 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, 878 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, 879 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, 880 }; 881 struct value **stack_args = XALLOCAVEC (struct value *, nargs); 882 int num_stack_args = 0; 883 int num_elements = 0; 884 int element = 0; 885 int integer_reg = 0; 886 int sse_reg = 0; 887 int i; 888 889 /* Reserve a register for the "hidden" argument. */ 890 if (struct_return) 891 integer_reg++; 892 893 for (i = 0; i < nargs; i++) 894 { 895 struct type *type = value_type (args[i]); 896 int len = TYPE_LENGTH (type); 897 enum amd64_reg_class theclass[2]; 898 int needed_integer_regs = 0; 899 int needed_sse_regs = 0; 900 int j; 901 902 /* Classify argument. */ 903 amd64_classify (type, theclass); 904 905 /* Calculate the number of integer and SSE registers needed for 906 this argument. */ 907 for (j = 0; j < 2; j++) 908 { 909 if (theclass[j] == AMD64_INTEGER) 910 needed_integer_regs++; 911 else if (theclass[j] == AMD64_SSE) 912 needed_sse_regs++; 913 } 914 915 /* Check whether enough registers are available, and if the 916 argument should be passed in registers at all. */ 917 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum) 918 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) 919 || (needed_integer_regs == 0 && needed_sse_regs == 0)) 920 { 921 /* The argument will be passed on the stack. */ 922 num_elements += ((len + 7) / 8); 923 stack_args[num_stack_args++] = args[i]; 924 } 925 else 926 { 927 /* The argument will be passed in registers. */ 928 const gdb_byte *valbuf = value_contents (args[i]); 929 gdb_byte buf[8]; 930 931 gdb_assert (len <= 16); 932 933 for (j = 0; len > 0; j++, len -= 8) 934 { 935 int regnum = -1; 936 int offset = 0; 937 938 switch (theclass[j]) 939 { 940 case AMD64_INTEGER: 941 regnum = integer_regnum[integer_reg++]; 942 break; 943 944 case AMD64_SSE: 945 regnum = sse_regnum[sse_reg++]; 946 break; 947 948 case AMD64_SSEUP: 949 gdb_assert (sse_reg > 0); 950 regnum = sse_regnum[sse_reg - 1]; 951 offset = 8; 952 break; 953 954 default: 955 gdb_assert (!"Unexpected register class."); 956 } 957 958 gdb_assert (regnum != -1); 959 memset (buf, 0, sizeof buf); 960 memcpy (buf, valbuf + j * 8, min (len, 8)); 961 regcache_raw_write_part (regcache, regnum, offset, 8, buf); 962 } 963 } 964 } 965 966 /* Allocate space for the arguments on the stack. */ 967 sp -= num_elements * 8; 968 969 /* The psABI says that "The end of the input argument area shall be 970 aligned on a 16 byte boundary." */ 971 sp &= ~0xf; 972 973 /* Write out the arguments to the stack. */ 974 for (i = 0; i < num_stack_args; i++) 975 { 976 struct type *type = value_type (stack_args[i]); 977 const gdb_byte *valbuf = value_contents (stack_args[i]); 978 int len = TYPE_LENGTH (type); 979 980 write_memory (sp + element * 8, valbuf, len); 981 element += ((len + 7) / 8); 982 } 983 984 /* The psABI says that "For calls that may call functions that use 985 varargs or stdargs (prototype-less calls or calls to functions 986 containing ellipsis (...) in the declaration) %al is used as 987 hidden argument to specify the number of SSE registers used. */ 988 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); 989 return sp; 990 } 991 992 static CORE_ADDR 993 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 994 struct regcache *regcache, CORE_ADDR bp_addr, 995 int nargs, struct value **args, CORE_ADDR sp, 996 int struct_return, CORE_ADDR struct_addr) 997 { 998 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 999 gdb_byte buf[8]; 1000 1001 /* Pass arguments. */ 1002 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); 1003 1004 /* Pass "hidden" argument". */ 1005 if (struct_return) 1006 { 1007 store_unsigned_integer (buf, 8, byte_order, struct_addr); 1008 regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf); 1009 } 1010 1011 /* Store return address. */ 1012 sp -= 8; 1013 store_unsigned_integer (buf, 8, byte_order, bp_addr); 1014 write_memory (sp, buf, 8); 1015 1016 /* Finally, update the stack pointer... */ 1017 store_unsigned_integer (buf, 8, byte_order, sp); 1018 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); 1019 1020 /* ...and fake a frame pointer. */ 1021 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); 1022 1023 return sp + 16; 1024 } 1025 1026 /* Displaced instruction handling. */ 1027 1028 /* A partially decoded instruction. 1029 This contains enough details for displaced stepping purposes. */ 1030 1031 struct amd64_insn 1032 { 1033 /* The number of opcode bytes. */ 1034 int opcode_len; 1035 /* The offset of the rex prefix or -1 if not present. */ 1036 int rex_offset; 1037 /* The offset to the first opcode byte. */ 1038 int opcode_offset; 1039 /* The offset to the modrm byte or -1 if not present. */ 1040 int modrm_offset; 1041 1042 /* The raw instruction. */ 1043 gdb_byte *raw_insn; 1044 }; 1045 1046 struct displaced_step_closure 1047 { 1048 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */ 1049 int tmp_used; 1050 int tmp_regno; 1051 ULONGEST tmp_save; 1052 1053 /* Details of the instruction. */ 1054 struct amd64_insn insn_details; 1055 1056 /* Amount of space allocated to insn_buf. */ 1057 int max_len; 1058 1059 /* The possibly modified insn. 1060 This is a variable-length field. */ 1061 gdb_byte insn_buf[1]; 1062 }; 1063 1064 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with 1065 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative, 1066 at which point delete these in favor of libopcodes' versions). */ 1067 1068 static const unsigned char onebyte_has_modrm[256] = { 1069 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 1070 /* ------------------------------- */ 1071 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ 1072 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ 1073 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ 1074 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ 1075 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ 1076 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ 1077 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ 1078 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ 1079 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ 1080 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ 1081 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ 1082 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ 1083 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ 1084 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ 1085 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ 1086 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ 1087 /* ------------------------------- */ 1088 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 1089 }; 1090 1091 static const unsigned char twobyte_has_modrm[256] = { 1092 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 1093 /* ------------------------------- */ 1094 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ 1095 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ 1096 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ 1097 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ 1098 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ 1099 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ 1100 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ 1101 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ 1102 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ 1103 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ 1104 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ 1105 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ 1106 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ 1107 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ 1108 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ 1109 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ 1110 /* ------------------------------- */ 1111 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 1112 }; 1113 1114 static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp); 1115 1116 static int 1117 rex_prefix_p (gdb_byte pfx) 1118 { 1119 return REX_PREFIX_P (pfx); 1120 } 1121 1122 /* Skip the legacy instruction prefixes in INSN. 1123 We assume INSN is properly sentineled so we don't have to worry 1124 about falling off the end of the buffer. */ 1125 1126 static gdb_byte * 1127 amd64_skip_prefixes (gdb_byte *insn) 1128 { 1129 while (1) 1130 { 1131 switch (*insn) 1132 { 1133 case DATA_PREFIX_OPCODE: 1134 case ADDR_PREFIX_OPCODE: 1135 case CS_PREFIX_OPCODE: 1136 case DS_PREFIX_OPCODE: 1137 case ES_PREFIX_OPCODE: 1138 case FS_PREFIX_OPCODE: 1139 case GS_PREFIX_OPCODE: 1140 case SS_PREFIX_OPCODE: 1141 case LOCK_PREFIX_OPCODE: 1142 case REPE_PREFIX_OPCODE: 1143 case REPNE_PREFIX_OPCODE: 1144 ++insn; 1145 continue; 1146 default: 1147 break; 1148 } 1149 break; 1150 } 1151 1152 return insn; 1153 } 1154 1155 /* Return an integer register (other than RSP) that is unused as an input 1156 operand in INSN. 1157 In order to not require adding a rex prefix if the insn doesn't already 1158 have one, the result is restricted to RAX ... RDI, sans RSP. 1159 The register numbering of the result follows architecture ordering, 1160 e.g. RDI = 7. */ 1161 1162 static int 1163 amd64_get_unused_input_int_reg (const struct amd64_insn *details) 1164 { 1165 /* 1 bit for each reg */ 1166 int used_regs_mask = 0; 1167 1168 /* There can be at most 3 int regs used as inputs in an insn, and we have 1169 7 to choose from (RAX ... RDI, sans RSP). 1170 This allows us to take a conservative approach and keep things simple. 1171 E.g. By avoiding RAX, we don't have to specifically watch for opcodes 1172 that implicitly specify RAX. */ 1173 1174 /* Avoid RAX. */ 1175 used_regs_mask |= 1 << EAX_REG_NUM; 1176 /* Similarily avoid RDX, implicit operand in divides. */ 1177 used_regs_mask |= 1 << EDX_REG_NUM; 1178 /* Avoid RSP. */ 1179 used_regs_mask |= 1 << ESP_REG_NUM; 1180 1181 /* If the opcode is one byte long and there's no ModRM byte, 1182 assume the opcode specifies a register. */ 1183 if (details->opcode_len == 1 && details->modrm_offset == -1) 1184 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7); 1185 1186 /* Mark used regs in the modrm/sib bytes. */ 1187 if (details->modrm_offset != -1) 1188 { 1189 int modrm = details->raw_insn[details->modrm_offset]; 1190 int mod = MODRM_MOD_FIELD (modrm); 1191 int reg = MODRM_REG_FIELD (modrm); 1192 int rm = MODRM_RM_FIELD (modrm); 1193 int have_sib = mod != 3 && rm == 4; 1194 1195 /* Assume the reg field of the modrm byte specifies a register. */ 1196 used_regs_mask |= 1 << reg; 1197 1198 if (have_sib) 1199 { 1200 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]); 1201 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]); 1202 used_regs_mask |= 1 << base; 1203 used_regs_mask |= 1 << idx; 1204 } 1205 else 1206 { 1207 used_regs_mask |= 1 << rm; 1208 } 1209 } 1210 1211 gdb_assert (used_regs_mask < 256); 1212 gdb_assert (used_regs_mask != 255); 1213 1214 /* Finally, find a free reg. */ 1215 { 1216 int i; 1217 1218 for (i = 0; i < 8; ++i) 1219 { 1220 if (! (used_regs_mask & (1 << i))) 1221 return i; 1222 } 1223 1224 /* We shouldn't get here. */ 1225 internal_error (__FILE__, __LINE__, _("unable to find free reg")); 1226 } 1227 } 1228 1229 /* Extract the details of INSN that we need. */ 1230 1231 static void 1232 amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details) 1233 { 1234 gdb_byte *start = insn; 1235 int need_modrm; 1236 1237 details->raw_insn = insn; 1238 1239 details->opcode_len = -1; 1240 details->rex_offset = -1; 1241 details->opcode_offset = -1; 1242 details->modrm_offset = -1; 1243 1244 /* Skip legacy instruction prefixes. */ 1245 insn = amd64_skip_prefixes (insn); 1246 1247 /* Skip REX instruction prefix. */ 1248 if (rex_prefix_p (*insn)) 1249 { 1250 details->rex_offset = insn - start; 1251 ++insn; 1252 } 1253 1254 details->opcode_offset = insn - start; 1255 1256 if (*insn == TWO_BYTE_OPCODE_ESCAPE) 1257 { 1258 /* Two or three-byte opcode. */ 1259 ++insn; 1260 need_modrm = twobyte_has_modrm[*insn]; 1261 1262 /* Check for three-byte opcode. */ 1263 switch (*insn) 1264 { 1265 case 0x24: 1266 case 0x25: 1267 case 0x38: 1268 case 0x3a: 1269 case 0x7a: 1270 case 0x7b: 1271 ++insn; 1272 details->opcode_len = 3; 1273 break; 1274 default: 1275 details->opcode_len = 2; 1276 break; 1277 } 1278 } 1279 else 1280 { 1281 /* One-byte opcode. */ 1282 need_modrm = onebyte_has_modrm[*insn]; 1283 details->opcode_len = 1; 1284 } 1285 1286 if (need_modrm) 1287 { 1288 ++insn; 1289 details->modrm_offset = insn - start; 1290 } 1291 } 1292 1293 /* Update %rip-relative addressing in INSN. 1294 1295 %rip-relative addressing only uses a 32-bit displacement. 1296 32 bits is not enough to be guaranteed to cover the distance between where 1297 the real instruction is and where its copy is. 1298 Convert the insn to use base+disp addressing. 1299 We set base = pc + insn_length so we can leave disp unchanged. */ 1300 1301 static void 1302 fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, 1303 CORE_ADDR from, CORE_ADDR to, struct regcache *regs) 1304 { 1305 const struct amd64_insn *insn_details = &dsc->insn_details; 1306 int modrm_offset = insn_details->modrm_offset; 1307 gdb_byte *insn = insn_details->raw_insn + modrm_offset; 1308 CORE_ADDR rip_base; 1309 int insn_length; 1310 int arch_tmp_regno, tmp_regno; 1311 ULONGEST orig_value; 1312 1313 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */ 1314 ++insn; 1315 1316 /* Compute the rip-relative address. */ 1317 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf, 1318 dsc->max_len, from); 1319 rip_base = from + insn_length; 1320 1321 /* We need a register to hold the address. 1322 Pick one not used in the insn. 1323 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */ 1324 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details); 1325 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno); 1326 1327 /* REX.B should be unset as we were using rip-relative addressing, 1328 but ensure it's unset anyway, tmp_regno is not r8-r15. */ 1329 if (insn_details->rex_offset != -1) 1330 dsc->insn_buf[insn_details->rex_offset] &= ~REX_B; 1331 1332 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value); 1333 dsc->tmp_regno = tmp_regno; 1334 dsc->tmp_save = orig_value; 1335 dsc->tmp_used = 1; 1336 1337 /* Convert the ModRM field to be base+disp. */ 1338 dsc->insn_buf[modrm_offset] &= ~0xc7; 1339 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno; 1340 1341 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base); 1342 1343 if (debug_displaced) 1344 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n" 1345 "displaced: using temp reg %d, old value %s, new value %s\n", 1346 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save), 1347 paddress (gdbarch, rip_base)); 1348 } 1349 1350 static void 1351 fixup_displaced_copy (struct gdbarch *gdbarch, 1352 struct displaced_step_closure *dsc, 1353 CORE_ADDR from, CORE_ADDR to, struct regcache *regs) 1354 { 1355 const struct amd64_insn *details = &dsc->insn_details; 1356 1357 if (details->modrm_offset != -1) 1358 { 1359 gdb_byte modrm = details->raw_insn[details->modrm_offset]; 1360 1361 if ((modrm & 0xc7) == 0x05) 1362 { 1363 /* The insn uses rip-relative addressing. 1364 Deal with it. */ 1365 fixup_riprel (gdbarch, dsc, from, to, regs); 1366 } 1367 } 1368 } 1369 1370 struct displaced_step_closure * 1371 amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, 1372 CORE_ADDR from, CORE_ADDR to, 1373 struct regcache *regs) 1374 { 1375 int len = gdbarch_max_insn_length (gdbarch); 1376 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to 1377 continually watch for running off the end of the buffer. */ 1378 int fixup_sentinel_space = len; 1379 struct displaced_step_closure *dsc 1380 = ((struct displaced_step_closure *) 1381 xmalloc (sizeof (*dsc) + len + fixup_sentinel_space)); 1382 gdb_byte *buf = &dsc->insn_buf[0]; 1383 struct amd64_insn *details = &dsc->insn_details; 1384 1385 dsc->tmp_used = 0; 1386 dsc->max_len = len + fixup_sentinel_space; 1387 1388 read_memory (from, buf, len); 1389 1390 /* Set up the sentinel space so we don't have to worry about running 1391 off the end of the buffer. An excessive number of leading prefixes 1392 could otherwise cause this. */ 1393 memset (buf + len, 0, fixup_sentinel_space); 1394 1395 amd64_get_insn_details (buf, details); 1396 1397 /* GDB may get control back after the insn after the syscall. 1398 Presumably this is a kernel bug. 1399 If this is a syscall, make sure there's a nop afterwards. */ 1400 { 1401 int syscall_length; 1402 1403 if (amd64_syscall_p (details, &syscall_length)) 1404 buf[details->opcode_offset + syscall_length] = NOP_OPCODE; 1405 } 1406 1407 /* Modify the insn to cope with the address where it will be executed from. 1408 In particular, handle any rip-relative addressing. */ 1409 fixup_displaced_copy (gdbarch, dsc, from, to, regs); 1410 1411 write_memory (to, buf, len); 1412 1413 if (debug_displaced) 1414 { 1415 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", 1416 paddress (gdbarch, from), paddress (gdbarch, to)); 1417 displaced_step_dump_bytes (gdb_stdlog, buf, len); 1418 } 1419 1420 return dsc; 1421 } 1422 1423 static int 1424 amd64_absolute_jmp_p (const struct amd64_insn *details) 1425 { 1426 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1427 1428 if (insn[0] == 0xff) 1429 { 1430 /* jump near, absolute indirect (/4) */ 1431 if ((insn[1] & 0x38) == 0x20) 1432 return 1; 1433 1434 /* jump far, absolute indirect (/5) */ 1435 if ((insn[1] & 0x38) == 0x28) 1436 return 1; 1437 } 1438 1439 return 0; 1440 } 1441 1442 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */ 1443 1444 static int 1445 amd64_jmp_p (const struct amd64_insn *details) 1446 { 1447 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1448 1449 /* jump short, relative. */ 1450 if (insn[0] == 0xeb) 1451 return 1; 1452 1453 /* jump near, relative. */ 1454 if (insn[0] == 0xe9) 1455 return 1; 1456 1457 return amd64_absolute_jmp_p (details); 1458 } 1459 1460 static int 1461 amd64_absolute_call_p (const struct amd64_insn *details) 1462 { 1463 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1464 1465 if (insn[0] == 0xff) 1466 { 1467 /* Call near, absolute indirect (/2) */ 1468 if ((insn[1] & 0x38) == 0x10) 1469 return 1; 1470 1471 /* Call far, absolute indirect (/3) */ 1472 if ((insn[1] & 0x38) == 0x18) 1473 return 1; 1474 } 1475 1476 return 0; 1477 } 1478 1479 static int 1480 amd64_ret_p (const struct amd64_insn *details) 1481 { 1482 /* NOTE: gcc can emit "repz ; ret". */ 1483 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1484 1485 switch (insn[0]) 1486 { 1487 case 0xc2: /* ret near, pop N bytes */ 1488 case 0xc3: /* ret near */ 1489 case 0xca: /* ret far, pop N bytes */ 1490 case 0xcb: /* ret far */ 1491 case 0xcf: /* iret */ 1492 return 1; 1493 1494 default: 1495 return 0; 1496 } 1497 } 1498 1499 static int 1500 amd64_call_p (const struct amd64_insn *details) 1501 { 1502 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1503 1504 if (amd64_absolute_call_p (details)) 1505 return 1; 1506 1507 /* call near, relative */ 1508 if (insn[0] == 0xe8) 1509 return 1; 1510 1511 return 0; 1512 } 1513 1514 /* Return non-zero if INSN is a system call, and set *LENGTHP to its 1515 length in bytes. Otherwise, return zero. */ 1516 1517 static int 1518 amd64_syscall_p (const struct amd64_insn *details, int *lengthp) 1519 { 1520 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1521 1522 if (insn[0] == 0x0f && insn[1] == 0x05) 1523 { 1524 *lengthp = 2; 1525 return 1; 1526 } 1527 1528 return 0; 1529 } 1530 1531 /* Classify the instruction at ADDR using PRED. 1532 Throw an error if the memory can't be read. */ 1533 1534 static int 1535 amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr, 1536 int (*pred) (const struct amd64_insn *)) 1537 { 1538 struct amd64_insn details; 1539 gdb_byte *buf; 1540 int len, classification; 1541 1542 len = gdbarch_max_insn_length (gdbarch); 1543 buf = (gdb_byte *) alloca (len); 1544 1545 read_code (addr, buf, len); 1546 amd64_get_insn_details (buf, &details); 1547 1548 classification = pred (&details); 1549 1550 return classification; 1551 } 1552 1553 /* The gdbarch insn_is_call method. */ 1554 1555 static int 1556 amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) 1557 { 1558 return amd64_classify_insn_at (gdbarch, addr, amd64_call_p); 1559 } 1560 1561 /* The gdbarch insn_is_ret method. */ 1562 1563 static int 1564 amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) 1565 { 1566 return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p); 1567 } 1568 1569 /* The gdbarch insn_is_jump method. */ 1570 1571 static int 1572 amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) 1573 { 1574 return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p); 1575 } 1576 1577 /* Fix up the state of registers and memory after having single-stepped 1578 a displaced instruction. */ 1579 1580 void 1581 amd64_displaced_step_fixup (struct gdbarch *gdbarch, 1582 struct displaced_step_closure *dsc, 1583 CORE_ADDR from, CORE_ADDR to, 1584 struct regcache *regs) 1585 { 1586 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1587 /* The offset we applied to the instruction's address. */ 1588 ULONGEST insn_offset = to - from; 1589 gdb_byte *insn = dsc->insn_buf; 1590 const struct amd64_insn *insn_details = &dsc->insn_details; 1591 1592 if (debug_displaced) 1593 fprintf_unfiltered (gdb_stdlog, 1594 "displaced: fixup (%s, %s), " 1595 "insn = 0x%02x 0x%02x ...\n", 1596 paddress (gdbarch, from), paddress (gdbarch, to), 1597 insn[0], insn[1]); 1598 1599 /* If we used a tmp reg, restore it. */ 1600 1601 if (dsc->tmp_used) 1602 { 1603 if (debug_displaced) 1604 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n", 1605 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save)); 1606 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save); 1607 } 1608 1609 /* The list of issues to contend with here is taken from 1610 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28. 1611 Yay for Free Software! */ 1612 1613 /* Relocate the %rip back to the program's instruction stream, 1614 if necessary. */ 1615 1616 /* Except in the case of absolute or indirect jump or call 1617 instructions, or a return instruction, the new rip is relative to 1618 the displaced instruction; make it relative to the original insn. 1619 Well, signal handler returns don't need relocation either, but we use the 1620 value of %rip to recognize those; see below. */ 1621 if (! amd64_absolute_jmp_p (insn_details) 1622 && ! amd64_absolute_call_p (insn_details) 1623 && ! amd64_ret_p (insn_details)) 1624 { 1625 ULONGEST orig_rip; 1626 int insn_len; 1627 1628 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip); 1629 1630 /* A signal trampoline system call changes the %rip, resuming 1631 execution of the main program after the signal handler has 1632 returned. That makes them like 'return' instructions; we 1633 shouldn't relocate %rip. 1634 1635 But most system calls don't, and we do need to relocate %rip. 1636 1637 Our heuristic for distinguishing these cases: if stepping 1638 over the system call instruction left control directly after 1639 the instruction, the we relocate --- control almost certainly 1640 doesn't belong in the displaced copy. Otherwise, we assume 1641 the instruction has put control where it belongs, and leave 1642 it unrelocated. Goodness help us if there are PC-relative 1643 system calls. */ 1644 if (amd64_syscall_p (insn_details, &insn_len) 1645 && orig_rip != to + insn_len 1646 /* GDB can get control back after the insn after the syscall. 1647 Presumably this is a kernel bug. 1648 Fixup ensures its a nop, we add one to the length for it. */ 1649 && orig_rip != to + insn_len + 1) 1650 { 1651 if (debug_displaced) 1652 fprintf_unfiltered (gdb_stdlog, 1653 "displaced: syscall changed %%rip; " 1654 "not relocating\n"); 1655 } 1656 else 1657 { 1658 ULONGEST rip = orig_rip - insn_offset; 1659 1660 /* If we just stepped over a breakpoint insn, we don't backup 1661 the pc on purpose; this is to match behaviour without 1662 stepping. */ 1663 1664 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip); 1665 1666 if (debug_displaced) 1667 fprintf_unfiltered (gdb_stdlog, 1668 "displaced: " 1669 "relocated %%rip from %s to %s\n", 1670 paddress (gdbarch, orig_rip), 1671 paddress (gdbarch, rip)); 1672 } 1673 } 1674 1675 /* If the instruction was PUSHFL, then the TF bit will be set in the 1676 pushed value, and should be cleared. We'll leave this for later, 1677 since GDB already messes up the TF flag when stepping over a 1678 pushfl. */ 1679 1680 /* If the instruction was a call, the return address now atop the 1681 stack is the address following the copied instruction. We need 1682 to make it the address following the original instruction. */ 1683 if (amd64_call_p (insn_details)) 1684 { 1685 ULONGEST rsp; 1686 ULONGEST retaddr; 1687 const ULONGEST retaddr_len = 8; 1688 1689 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp); 1690 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order); 1691 retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL; 1692 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr); 1693 1694 if (debug_displaced) 1695 fprintf_unfiltered (gdb_stdlog, 1696 "displaced: relocated return addr at %s " 1697 "to %s\n", 1698 paddress (gdbarch, rsp), 1699 paddress (gdbarch, retaddr)); 1700 } 1701 } 1702 1703 /* If the instruction INSN uses RIP-relative addressing, return the 1704 offset into the raw INSN where the displacement to be adjusted is 1705 found. Returns 0 if the instruction doesn't use RIP-relative 1706 addressing. */ 1707 1708 static int 1709 rip_relative_offset (struct amd64_insn *insn) 1710 { 1711 if (insn->modrm_offset != -1) 1712 { 1713 gdb_byte modrm = insn->raw_insn[insn->modrm_offset]; 1714 1715 if ((modrm & 0xc7) == 0x05) 1716 { 1717 /* The displacement is found right after the ModRM byte. */ 1718 return insn->modrm_offset + 1; 1719 } 1720 } 1721 1722 return 0; 1723 } 1724 1725 static void 1726 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) 1727 { 1728 target_write_memory (*to, buf, len); 1729 *to += len; 1730 } 1731 1732 static void 1733 amd64_relocate_instruction (struct gdbarch *gdbarch, 1734 CORE_ADDR *to, CORE_ADDR oldloc) 1735 { 1736 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1737 int len = gdbarch_max_insn_length (gdbarch); 1738 /* Extra space for sentinels. */ 1739 int fixup_sentinel_space = len; 1740 gdb_byte *buf = (gdb_byte *) xmalloc (len + fixup_sentinel_space); 1741 struct amd64_insn insn_details; 1742 int offset = 0; 1743 LONGEST rel32, newrel; 1744 gdb_byte *insn; 1745 int insn_length; 1746 1747 read_memory (oldloc, buf, len); 1748 1749 /* Set up the sentinel space so we don't have to worry about running 1750 off the end of the buffer. An excessive number of leading prefixes 1751 could otherwise cause this. */ 1752 memset (buf + len, 0, fixup_sentinel_space); 1753 1754 insn = buf; 1755 amd64_get_insn_details (insn, &insn_details); 1756 1757 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc); 1758 1759 /* Skip legacy instruction prefixes. */ 1760 insn = amd64_skip_prefixes (insn); 1761 1762 /* Adjust calls with 32-bit relative addresses as push/jump, with 1763 the address pushed being the location where the original call in 1764 the user program would return to. */ 1765 if (insn[0] == 0xe8) 1766 { 1767 gdb_byte push_buf[32]; 1768 CORE_ADDR ret_addr; 1769 int i = 0; 1770 1771 /* Where "ret" in the original code will return to. */ 1772 ret_addr = oldloc + insn_length; 1773 1774 /* If pushing an address higher than or equal to 0x80000000, 1775 avoid 'pushq', as that sign extends its 32-bit operand, which 1776 would be incorrect. */ 1777 if (ret_addr <= 0x7fffffff) 1778 { 1779 push_buf[0] = 0x68; /* pushq $... */ 1780 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); 1781 i = 5; 1782 } 1783 else 1784 { 1785 push_buf[i++] = 0x48; /* sub $0x8,%rsp */ 1786 push_buf[i++] = 0x83; 1787 push_buf[i++] = 0xec; 1788 push_buf[i++] = 0x08; 1789 1790 push_buf[i++] = 0xc7; /* movl $imm,(%rsp) */ 1791 push_buf[i++] = 0x04; 1792 push_buf[i++] = 0x24; 1793 store_unsigned_integer (&push_buf[i], 4, byte_order, 1794 ret_addr & 0xffffffff); 1795 i += 4; 1796 1797 push_buf[i++] = 0xc7; /* movl $imm,4(%rsp) */ 1798 push_buf[i++] = 0x44; 1799 push_buf[i++] = 0x24; 1800 push_buf[i++] = 0x04; 1801 store_unsigned_integer (&push_buf[i], 4, byte_order, 1802 ret_addr >> 32); 1803 i += 4; 1804 } 1805 gdb_assert (i <= sizeof (push_buf)); 1806 /* Push the push. */ 1807 append_insns (to, i, push_buf); 1808 1809 /* Convert the relative call to a relative jump. */ 1810 insn[0] = 0xe9; 1811 1812 /* Adjust the destination offset. */ 1813 rel32 = extract_signed_integer (insn + 1, 4, byte_order); 1814 newrel = (oldloc - *to) + rel32; 1815 store_signed_integer (insn + 1, 4, byte_order, newrel); 1816 1817 if (debug_displaced) 1818 fprintf_unfiltered (gdb_stdlog, 1819 "Adjusted insn rel32=%s at %s to" 1820 " rel32=%s at %s\n", 1821 hex_string (rel32), paddress (gdbarch, oldloc), 1822 hex_string (newrel), paddress (gdbarch, *to)); 1823 1824 /* Write the adjusted jump into its displaced location. */ 1825 append_insns (to, 5, insn); 1826 return; 1827 } 1828 1829 offset = rip_relative_offset (&insn_details); 1830 if (!offset) 1831 { 1832 /* Adjust jumps with 32-bit relative addresses. Calls are 1833 already handled above. */ 1834 if (insn[0] == 0xe9) 1835 offset = 1; 1836 /* Adjust conditional jumps. */ 1837 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) 1838 offset = 2; 1839 } 1840 1841 if (offset) 1842 { 1843 rel32 = extract_signed_integer (insn + offset, 4, byte_order); 1844 newrel = (oldloc - *to) + rel32; 1845 store_signed_integer (insn + offset, 4, byte_order, newrel); 1846 if (debug_displaced) 1847 fprintf_unfiltered (gdb_stdlog, 1848 "Adjusted insn rel32=%s at %s to" 1849 " rel32=%s at %s\n", 1850 hex_string (rel32), paddress (gdbarch, oldloc), 1851 hex_string (newrel), paddress (gdbarch, *to)); 1852 } 1853 1854 /* Write the adjusted instruction into its displaced location. */ 1855 append_insns (to, insn_length, buf); 1856 } 1857 1858 1859 /* The maximum number of saved registers. This should include %rip. */ 1860 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS 1861 1862 struct amd64_frame_cache 1863 { 1864 /* Base address. */ 1865 CORE_ADDR base; 1866 int base_p; 1867 CORE_ADDR sp_offset; 1868 CORE_ADDR pc; 1869 1870 /* Saved registers. */ 1871 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]; 1872 CORE_ADDR saved_sp; 1873 int saved_sp_reg; 1874 1875 /* Do we have a frame? */ 1876 int frameless_p; 1877 }; 1878 1879 /* Initialize a frame cache. */ 1880 1881 static void 1882 amd64_init_frame_cache (struct amd64_frame_cache *cache) 1883 { 1884 int i; 1885 1886 /* Base address. */ 1887 cache->base = 0; 1888 cache->base_p = 0; 1889 cache->sp_offset = -8; 1890 cache->pc = 0; 1891 1892 /* Saved registers. We initialize these to -1 since zero is a valid 1893 offset (that's where %rbp is supposed to be stored). 1894 The values start out as being offsets, and are later converted to 1895 addresses (at which point -1 is interpreted as an address, still meaning 1896 "invalid"). */ 1897 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) 1898 cache->saved_regs[i] = -1; 1899 cache->saved_sp = 0; 1900 cache->saved_sp_reg = -1; 1901 1902 /* Frameless until proven otherwise. */ 1903 cache->frameless_p = 1; 1904 } 1905 1906 /* Allocate and initialize a frame cache. */ 1907 1908 static struct amd64_frame_cache * 1909 amd64_alloc_frame_cache (void) 1910 { 1911 struct amd64_frame_cache *cache; 1912 1913 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache); 1914 amd64_init_frame_cache (cache); 1915 return cache; 1916 } 1917 1918 /* GCC 4.4 and later, can put code in the prologue to realign the 1919 stack pointer. Check whether PC points to such code, and update 1920 CACHE accordingly. Return the first instruction after the code 1921 sequence or CURRENT_PC, whichever is smaller. If we don't 1922 recognize the code, return PC. */ 1923 1924 static CORE_ADDR 1925 amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, 1926 struct amd64_frame_cache *cache) 1927 { 1928 /* There are 2 code sequences to re-align stack before the frame 1929 gets set up: 1930 1931 1. Use a caller-saved saved register: 1932 1933 leaq 8(%rsp), %reg 1934 andq $-XXX, %rsp 1935 pushq -8(%reg) 1936 1937 2. Use a callee-saved saved register: 1938 1939 pushq %reg 1940 leaq 16(%rsp), %reg 1941 andq $-XXX, %rsp 1942 pushq -8(%reg) 1943 1944 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: 1945 1946 0x48 0x83 0xe4 0xf0 andq $-16, %rsp 1947 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp 1948 */ 1949 1950 gdb_byte buf[18]; 1951 int reg, r; 1952 int offset, offset_and; 1953 1954 if (target_read_code (pc, buf, sizeof buf)) 1955 return pc; 1956 1957 /* Check caller-saved saved register. The first instruction has 1958 to be "leaq 8(%rsp), %reg". */ 1959 if ((buf[0] & 0xfb) == 0x48 1960 && buf[1] == 0x8d 1961 && buf[3] == 0x24 1962 && buf[4] == 0x8) 1963 { 1964 /* MOD must be binary 10 and R/M must be binary 100. */ 1965 if ((buf[2] & 0xc7) != 0x44) 1966 return pc; 1967 1968 /* REG has register number. */ 1969 reg = (buf[2] >> 3) & 7; 1970 1971 /* Check the REX.R bit. */ 1972 if (buf[0] == 0x4c) 1973 reg += 8; 1974 1975 offset = 5; 1976 } 1977 else 1978 { 1979 /* Check callee-saved saved register. The first instruction 1980 has to be "pushq %reg". */ 1981 reg = 0; 1982 if ((buf[0] & 0xf8) == 0x50) 1983 offset = 0; 1984 else if ((buf[0] & 0xf6) == 0x40 1985 && (buf[1] & 0xf8) == 0x50) 1986 { 1987 /* Check the REX.B bit. */ 1988 if ((buf[0] & 1) != 0) 1989 reg = 8; 1990 1991 offset = 1; 1992 } 1993 else 1994 return pc; 1995 1996 /* Get register. */ 1997 reg += buf[offset] & 0x7; 1998 1999 offset++; 2000 2001 /* The next instruction has to be "leaq 16(%rsp), %reg". */ 2002 if ((buf[offset] & 0xfb) != 0x48 2003 || buf[offset + 1] != 0x8d 2004 || buf[offset + 3] != 0x24 2005 || buf[offset + 4] != 0x10) 2006 return pc; 2007 2008 /* MOD must be binary 10 and R/M must be binary 100. */ 2009 if ((buf[offset + 2] & 0xc7) != 0x44) 2010 return pc; 2011 2012 /* REG has register number. */ 2013 r = (buf[offset + 2] >> 3) & 7; 2014 2015 /* Check the REX.R bit. */ 2016 if (buf[offset] == 0x4c) 2017 r += 8; 2018 2019 /* Registers in pushq and leaq have to be the same. */ 2020 if (reg != r) 2021 return pc; 2022 2023 offset += 5; 2024 } 2025 2026 /* Rigister can't be %rsp nor %rbp. */ 2027 if (reg == 4 || reg == 5) 2028 return pc; 2029 2030 /* The next instruction has to be "andq $-XXX, %rsp". */ 2031 if (buf[offset] != 0x48 2032 || buf[offset + 2] != 0xe4 2033 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) 2034 return pc; 2035 2036 offset_and = offset; 2037 offset += buf[offset + 1] == 0x81 ? 7 : 4; 2038 2039 /* The next instruction has to be "pushq -8(%reg)". */ 2040 r = 0; 2041 if (buf[offset] == 0xff) 2042 offset++; 2043 else if ((buf[offset] & 0xf6) == 0x40 2044 && buf[offset + 1] == 0xff) 2045 { 2046 /* Check the REX.B bit. */ 2047 if ((buf[offset] & 0x1) != 0) 2048 r = 8; 2049 offset += 2; 2050 } 2051 else 2052 return pc; 2053 2054 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary 2055 01. */ 2056 if (buf[offset + 1] != 0xf8 2057 || (buf[offset] & 0xf8) != 0x70) 2058 return pc; 2059 2060 /* R/M has register. */ 2061 r += buf[offset] & 7; 2062 2063 /* Registers in leaq and pushq have to be the same. */ 2064 if (reg != r) 2065 return pc; 2066 2067 if (current_pc > pc + offset_and) 2068 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); 2069 2070 return min (pc + offset + 2, current_pc); 2071 } 2072 2073 /* Similar to amd64_analyze_stack_align for x32. */ 2074 2075 static CORE_ADDR 2076 amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, 2077 struct amd64_frame_cache *cache) 2078 { 2079 /* There are 2 code sequences to re-align stack before the frame 2080 gets set up: 2081 2082 1. Use a caller-saved saved register: 2083 2084 leaq 8(%rsp), %reg 2085 andq $-XXX, %rsp 2086 pushq -8(%reg) 2087 2088 or 2089 2090 [addr32] leal 8(%rsp), %reg 2091 andl $-XXX, %esp 2092 [addr32] pushq -8(%reg) 2093 2094 2. Use a callee-saved saved register: 2095 2096 pushq %reg 2097 leaq 16(%rsp), %reg 2098 andq $-XXX, %rsp 2099 pushq -8(%reg) 2100 2101 or 2102 2103 pushq %reg 2104 [addr32] leal 16(%rsp), %reg 2105 andl $-XXX, %esp 2106 [addr32] pushq -8(%reg) 2107 2108 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: 2109 2110 0x48 0x83 0xe4 0xf0 andq $-16, %rsp 2111 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp 2112 2113 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: 2114 2115 0x83 0xe4 0xf0 andl $-16, %esp 2116 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp 2117 */ 2118 2119 gdb_byte buf[19]; 2120 int reg, r; 2121 int offset, offset_and; 2122 2123 if (target_read_memory (pc, buf, sizeof buf)) 2124 return pc; 2125 2126 /* Skip optional addr32 prefix. */ 2127 offset = buf[0] == 0x67 ? 1 : 0; 2128 2129 /* Check caller-saved saved register. The first instruction has 2130 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */ 2131 if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40) 2132 && buf[offset + 1] == 0x8d 2133 && buf[offset + 3] == 0x24 2134 && buf[offset + 4] == 0x8) 2135 { 2136 /* MOD must be binary 10 and R/M must be binary 100. */ 2137 if ((buf[offset + 2] & 0xc7) != 0x44) 2138 return pc; 2139 2140 /* REG has register number. */ 2141 reg = (buf[offset + 2] >> 3) & 7; 2142 2143 /* Check the REX.R bit. */ 2144 if ((buf[offset] & 0x4) != 0) 2145 reg += 8; 2146 2147 offset += 5; 2148 } 2149 else 2150 { 2151 /* Check callee-saved saved register. The first instruction 2152 has to be "pushq %reg". */ 2153 reg = 0; 2154 if ((buf[offset] & 0xf6) == 0x40 2155 && (buf[offset + 1] & 0xf8) == 0x50) 2156 { 2157 /* Check the REX.B bit. */ 2158 if ((buf[offset] & 1) != 0) 2159 reg = 8; 2160 2161 offset += 1; 2162 } 2163 else if ((buf[offset] & 0xf8) != 0x50) 2164 return pc; 2165 2166 /* Get register. */ 2167 reg += buf[offset] & 0x7; 2168 2169 offset++; 2170 2171 /* Skip optional addr32 prefix. */ 2172 if (buf[offset] == 0x67) 2173 offset++; 2174 2175 /* The next instruction has to be "leaq 16(%rsp), %reg" or 2176 "leal 16(%rsp), %reg". */ 2177 if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40) 2178 || buf[offset + 1] != 0x8d 2179 || buf[offset + 3] != 0x24 2180 || buf[offset + 4] != 0x10) 2181 return pc; 2182 2183 /* MOD must be binary 10 and R/M must be binary 100. */ 2184 if ((buf[offset + 2] & 0xc7) != 0x44) 2185 return pc; 2186 2187 /* REG has register number. */ 2188 r = (buf[offset + 2] >> 3) & 7; 2189 2190 /* Check the REX.R bit. */ 2191 if ((buf[offset] & 0x4) != 0) 2192 r += 8; 2193 2194 /* Registers in pushq and leaq have to be the same. */ 2195 if (reg != r) 2196 return pc; 2197 2198 offset += 5; 2199 } 2200 2201 /* Rigister can't be %rsp nor %rbp. */ 2202 if (reg == 4 || reg == 5) 2203 return pc; 2204 2205 /* The next instruction may be "andq $-XXX, %rsp" or 2206 "andl $-XXX, %esp". */ 2207 if (buf[offset] != 0x48) 2208 offset--; 2209 2210 if (buf[offset + 2] != 0xe4 2211 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) 2212 return pc; 2213 2214 offset_and = offset; 2215 offset += buf[offset + 1] == 0x81 ? 7 : 4; 2216 2217 /* Skip optional addr32 prefix. */ 2218 if (buf[offset] == 0x67) 2219 offset++; 2220 2221 /* The next instruction has to be "pushq -8(%reg)". */ 2222 r = 0; 2223 if (buf[offset] == 0xff) 2224 offset++; 2225 else if ((buf[offset] & 0xf6) == 0x40 2226 && buf[offset + 1] == 0xff) 2227 { 2228 /* Check the REX.B bit. */ 2229 if ((buf[offset] & 0x1) != 0) 2230 r = 8; 2231 offset += 2; 2232 } 2233 else 2234 return pc; 2235 2236 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary 2237 01. */ 2238 if (buf[offset + 1] != 0xf8 2239 || (buf[offset] & 0xf8) != 0x70) 2240 return pc; 2241 2242 /* R/M has register. */ 2243 r += buf[offset] & 7; 2244 2245 /* Registers in leaq and pushq have to be the same. */ 2246 if (reg != r) 2247 return pc; 2248 2249 if (current_pc > pc + offset_and) 2250 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); 2251 2252 return min (pc + offset + 2, current_pc); 2253 } 2254 2255 /* Do a limited analysis of the prologue at PC and update CACHE 2256 accordingly. Bail out early if CURRENT_PC is reached. Return the 2257 address where the analysis stopped. 2258 2259 We will handle only functions beginning with: 2260 2261 pushq %rbp 0x55 2262 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec) 2263 2264 or (for the X32 ABI): 2265 2266 pushq %rbp 0x55 2267 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec) 2268 2269 Any function that doesn't start with one of these sequences will be 2270 assumed to have no prologue and thus no valid frame pointer in 2271 %rbp. */ 2272 2273 static CORE_ADDR 2274 amd64_analyze_prologue (struct gdbarch *gdbarch, 2275 CORE_ADDR pc, CORE_ADDR current_pc, 2276 struct amd64_frame_cache *cache) 2277 { 2278 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2279 /* There are two variations of movq %rsp, %rbp. */ 2280 static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 }; 2281 static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec }; 2282 /* Ditto for movl %esp, %ebp. */ 2283 static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 }; 2284 static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec }; 2285 2286 gdb_byte buf[3]; 2287 gdb_byte op; 2288 2289 if (current_pc <= pc) 2290 return current_pc; 2291 2292 if (gdbarch_ptr_bit (gdbarch) == 32) 2293 pc = amd64_x32_analyze_stack_align (pc, current_pc, cache); 2294 else 2295 pc = amd64_analyze_stack_align (pc, current_pc, cache); 2296 2297 op = read_code_unsigned_integer (pc, 1, byte_order); 2298 2299 if (op == 0x55) /* pushq %rbp */ 2300 { 2301 /* Take into account that we've executed the `pushq %rbp' that 2302 starts this instruction sequence. */ 2303 cache->saved_regs[AMD64_RBP_REGNUM] = 0; 2304 cache->sp_offset += 8; 2305 2306 /* If that's all, return now. */ 2307 if (current_pc <= pc + 1) 2308 return current_pc; 2309 2310 read_code (pc + 1, buf, 3); 2311 2312 /* Check for `movq %rsp, %rbp'. */ 2313 if (memcmp (buf, mov_rsp_rbp_1, 3) == 0 2314 || memcmp (buf, mov_rsp_rbp_2, 3) == 0) 2315 { 2316 /* OK, we actually have a frame. */ 2317 cache->frameless_p = 0; 2318 return pc + 4; 2319 } 2320 2321 /* For X32, also check for `movq %esp, %ebp'. */ 2322 if (gdbarch_ptr_bit (gdbarch) == 32) 2323 { 2324 if (memcmp (buf, mov_esp_ebp_1, 2) == 0 2325 || memcmp (buf, mov_esp_ebp_2, 2) == 0) 2326 { 2327 /* OK, we actually have a frame. */ 2328 cache->frameless_p = 0; 2329 return pc + 3; 2330 } 2331 } 2332 2333 return pc + 1; 2334 } 2335 2336 return pc; 2337 } 2338 2339 /* Work around false termination of prologue - GCC PR debug/48827. 2340 2341 START_PC is the first instruction of a function, PC is its minimal already 2342 determined advanced address. Function returns PC if it has nothing to do. 2343 2344 84 c0 test %al,%al 2345 74 23 je after 2346 <-- here is 0 lines advance - the false prologue end marker. 2347 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp) 2348 0f 29 4d 80 movaps %xmm1,-0x80(%rbp) 2349 0f 29 55 90 movaps %xmm2,-0x70(%rbp) 2350 0f 29 5d a0 movaps %xmm3,-0x60(%rbp) 2351 0f 29 65 b0 movaps %xmm4,-0x50(%rbp) 2352 0f 29 6d c0 movaps %xmm5,-0x40(%rbp) 2353 0f 29 75 d0 movaps %xmm6,-0x30(%rbp) 2354 0f 29 7d e0 movaps %xmm7,-0x20(%rbp) 2355 after: */ 2356 2357 static CORE_ADDR 2358 amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc) 2359 { 2360 struct symtab_and_line start_pc_sal, next_sal; 2361 gdb_byte buf[4 + 8 * 7]; 2362 int offset, xmmreg; 2363 2364 if (pc == start_pc) 2365 return pc; 2366 2367 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0); 2368 if (start_pc_sal.symtab == NULL 2369 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER 2370 (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6 2371 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end) 2372 return pc; 2373 2374 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0); 2375 if (next_sal.line != start_pc_sal.line) 2376 return pc; 2377 2378 /* START_PC can be from overlayed memory, ignored here. */ 2379 if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0) 2380 return pc; 2381 2382 /* test %al,%al */ 2383 if (buf[0] != 0x84 || buf[1] != 0xc0) 2384 return pc; 2385 /* je AFTER */ 2386 if (buf[2] != 0x74) 2387 return pc; 2388 2389 offset = 4; 2390 for (xmmreg = 0; xmmreg < 8; xmmreg++) 2391 { 2392 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */ 2393 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29 2394 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5)) 2395 return pc; 2396 2397 /* 0b01?????? */ 2398 if ((buf[offset + 2] & 0xc0) == 0x40) 2399 { 2400 /* 8-bit displacement. */ 2401 offset += 4; 2402 } 2403 /* 0b10?????? */ 2404 else if ((buf[offset + 2] & 0xc0) == 0x80) 2405 { 2406 /* 32-bit displacement. */ 2407 offset += 7; 2408 } 2409 else 2410 return pc; 2411 } 2412 2413 /* je AFTER */ 2414 if (offset - 4 != buf[3]) 2415 return pc; 2416 2417 return next_sal.end; 2418 } 2419 2420 /* Return PC of first real instruction. */ 2421 2422 static CORE_ADDR 2423 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 2424 { 2425 struct amd64_frame_cache cache; 2426 CORE_ADDR pc; 2427 CORE_ADDR func_addr; 2428 2429 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) 2430 { 2431 CORE_ADDR post_prologue_pc 2432 = skip_prologue_using_sal (gdbarch, func_addr); 2433 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); 2434 2435 /* Clang always emits a line note before the prologue and another 2436 one after. We trust clang to emit usable line notes. */ 2437 if (post_prologue_pc 2438 && (cust != NULL 2439 && COMPUNIT_PRODUCER (cust) != NULL 2440 && startswith (COMPUNIT_PRODUCER (cust), "clang "))) 2441 return max (start_pc, post_prologue_pc); 2442 } 2443 2444 amd64_init_frame_cache (&cache); 2445 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL, 2446 &cache); 2447 if (cache.frameless_p) 2448 return start_pc; 2449 2450 return amd64_skip_xmm_prologue (pc, start_pc); 2451 } 2452 2453 2454 /* Normal frames. */ 2455 2456 static void 2457 amd64_frame_cache_1 (struct frame_info *this_frame, 2458 struct amd64_frame_cache *cache) 2459 { 2460 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2461 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2462 gdb_byte buf[8]; 2463 int i; 2464 2465 cache->pc = get_frame_func (this_frame); 2466 if (cache->pc != 0) 2467 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), 2468 cache); 2469 2470 if (cache->frameless_p) 2471 { 2472 /* We didn't find a valid frame. If we're at the start of a 2473 function, or somewhere half-way its prologue, the function's 2474 frame probably hasn't been fully setup yet. Try to 2475 reconstruct the base address for the stack frame by looking 2476 at the stack pointer. For truly "frameless" functions this 2477 might work too. */ 2478 2479 if (cache->saved_sp_reg != -1) 2480 { 2481 /* Stack pointer has been saved. */ 2482 get_frame_register (this_frame, cache->saved_sp_reg, buf); 2483 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order); 2484 2485 /* We're halfway aligning the stack. */ 2486 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8; 2487 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8; 2488 2489 /* This will be added back below. */ 2490 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base; 2491 } 2492 else 2493 { 2494 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); 2495 cache->base = extract_unsigned_integer (buf, 8, byte_order) 2496 + cache->sp_offset; 2497 } 2498 } 2499 else 2500 { 2501 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf); 2502 cache->base = extract_unsigned_integer (buf, 8, byte_order); 2503 } 2504 2505 /* Now that we have the base address for the stack frame we can 2506 calculate the value of %rsp in the calling frame. */ 2507 cache->saved_sp = cache->base + 16; 2508 2509 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a 2510 frame we find it at the same offset from the reconstructed base 2511 address. If we're halfway aligning the stack, %rip is handled 2512 differently (see above). */ 2513 if (!cache->frameless_p || cache->saved_sp_reg == -1) 2514 cache->saved_regs[AMD64_RIP_REGNUM] = 8; 2515 2516 /* Adjust all the saved registers such that they contain addresses 2517 instead of offsets. */ 2518 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) 2519 if (cache->saved_regs[i] != -1) 2520 cache->saved_regs[i] += cache->base; 2521 2522 cache->base_p = 1; 2523 } 2524 2525 static struct amd64_frame_cache * 2526 amd64_frame_cache (struct frame_info *this_frame, void **this_cache) 2527 { 2528 struct amd64_frame_cache *cache; 2529 2530 if (*this_cache) 2531 return (struct amd64_frame_cache *) *this_cache; 2532 2533 cache = amd64_alloc_frame_cache (); 2534 *this_cache = cache; 2535 2536 TRY 2537 { 2538 amd64_frame_cache_1 (this_frame, cache); 2539 } 2540 CATCH (ex, RETURN_MASK_ERROR) 2541 { 2542 if (ex.error != NOT_AVAILABLE_ERROR) 2543 throw_exception (ex); 2544 } 2545 END_CATCH 2546 2547 return cache; 2548 } 2549 2550 static enum unwind_stop_reason 2551 amd64_frame_unwind_stop_reason (struct frame_info *this_frame, 2552 void **this_cache) 2553 { 2554 struct amd64_frame_cache *cache = 2555 amd64_frame_cache (this_frame, this_cache); 2556 2557 if (!cache->base_p) 2558 return UNWIND_UNAVAILABLE; 2559 2560 /* This marks the outermost frame. */ 2561 if (cache->base == 0) 2562 return UNWIND_OUTERMOST; 2563 2564 return UNWIND_NO_REASON; 2565 } 2566 2567 static void 2568 amd64_frame_this_id (struct frame_info *this_frame, void **this_cache, 2569 struct frame_id *this_id) 2570 { 2571 struct amd64_frame_cache *cache = 2572 amd64_frame_cache (this_frame, this_cache); 2573 2574 if (!cache->base_p) 2575 (*this_id) = frame_id_build_unavailable_stack (cache->pc); 2576 else if (cache->base == 0) 2577 { 2578 /* This marks the outermost frame. */ 2579 return; 2580 } 2581 else 2582 (*this_id) = frame_id_build (cache->base + 16, cache->pc); 2583 } 2584 2585 static struct value * 2586 amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache, 2587 int regnum) 2588 { 2589 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2590 struct amd64_frame_cache *cache = 2591 amd64_frame_cache (this_frame, this_cache); 2592 2593 gdb_assert (regnum >= 0); 2594 2595 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) 2596 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); 2597 2598 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) 2599 return frame_unwind_got_memory (this_frame, regnum, 2600 cache->saved_regs[regnum]); 2601 2602 return frame_unwind_got_register (this_frame, regnum, regnum); 2603 } 2604 2605 static const struct frame_unwind amd64_frame_unwind = 2606 { 2607 NORMAL_FRAME, 2608 amd64_frame_unwind_stop_reason, 2609 amd64_frame_this_id, 2610 amd64_frame_prev_register, 2611 NULL, 2612 default_frame_sniffer 2613 }; 2614 2615 /* Generate a bytecode expression to get the value of the saved PC. */ 2616 2617 static void 2618 amd64_gen_return_address (struct gdbarch *gdbarch, 2619 struct agent_expr *ax, struct axs_value *value, 2620 CORE_ADDR scope) 2621 { 2622 /* The following sequence assumes the traditional use of the base 2623 register. */ 2624 ax_reg (ax, AMD64_RBP_REGNUM); 2625 ax_const_l (ax, 8); 2626 ax_simple (ax, aop_add); 2627 value->type = register_type (gdbarch, AMD64_RIP_REGNUM); 2628 value->kind = axs_lvalue_memory; 2629 } 2630 2631 2632 /* Signal trampolines. */ 2633 2634 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and 2635 64-bit variants. This would require using identical frame caches 2636 on both platforms. */ 2637 2638 static struct amd64_frame_cache * 2639 amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) 2640 { 2641 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2642 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2643 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2644 struct amd64_frame_cache *cache; 2645 CORE_ADDR addr; 2646 gdb_byte buf[8]; 2647 int i; 2648 2649 if (*this_cache) 2650 return (struct amd64_frame_cache *) *this_cache; 2651 2652 cache = amd64_alloc_frame_cache (); 2653 2654 TRY 2655 { 2656 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); 2657 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8; 2658 2659 addr = tdep->sigcontext_addr (this_frame); 2660 gdb_assert (tdep->sc_reg_offset); 2661 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS); 2662 for (i = 0; i < tdep->sc_num_regs; i++) 2663 if (tdep->sc_reg_offset[i] != -1) 2664 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; 2665 2666 cache->base_p = 1; 2667 } 2668 CATCH (ex, RETURN_MASK_ERROR) 2669 { 2670 if (ex.error != NOT_AVAILABLE_ERROR) 2671 throw_exception (ex); 2672 } 2673 END_CATCH 2674 2675 *this_cache = cache; 2676 return cache; 2677 } 2678 2679 static enum unwind_stop_reason 2680 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, 2681 void **this_cache) 2682 { 2683 struct amd64_frame_cache *cache = 2684 amd64_sigtramp_frame_cache (this_frame, this_cache); 2685 2686 if (!cache->base_p) 2687 return UNWIND_UNAVAILABLE; 2688 2689 return UNWIND_NO_REASON; 2690 } 2691 2692 static void 2693 amd64_sigtramp_frame_this_id (struct frame_info *this_frame, 2694 void **this_cache, struct frame_id *this_id) 2695 { 2696 struct amd64_frame_cache *cache = 2697 amd64_sigtramp_frame_cache (this_frame, this_cache); 2698 2699 if (!cache->base_p) 2700 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); 2701 else if (cache->base == 0) 2702 { 2703 /* This marks the outermost frame. */ 2704 return; 2705 } 2706 else 2707 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame)); 2708 } 2709 2710 static struct value * 2711 amd64_sigtramp_frame_prev_register (struct frame_info *this_frame, 2712 void **this_cache, int regnum) 2713 { 2714 /* Make sure we've initialized the cache. */ 2715 amd64_sigtramp_frame_cache (this_frame, this_cache); 2716 2717 return amd64_frame_prev_register (this_frame, this_cache, regnum); 2718 } 2719 2720 static int 2721 amd64_sigtramp_frame_sniffer (const struct frame_unwind *self, 2722 struct frame_info *this_frame, 2723 void **this_cache) 2724 { 2725 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); 2726 2727 /* We shouldn't even bother if we don't have a sigcontext_addr 2728 handler. */ 2729 if (tdep->sigcontext_addr == NULL) 2730 return 0; 2731 2732 if (tdep->sigtramp_p != NULL) 2733 { 2734 if (tdep->sigtramp_p (this_frame)) 2735 return 1; 2736 } 2737 2738 if (tdep->sigtramp_start != 0) 2739 { 2740 CORE_ADDR pc = get_frame_pc (this_frame); 2741 2742 gdb_assert (tdep->sigtramp_end != 0); 2743 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) 2744 return 1; 2745 } 2746 2747 return 0; 2748 } 2749 2750 static const struct frame_unwind amd64_sigtramp_frame_unwind = 2751 { 2752 SIGTRAMP_FRAME, 2753 amd64_sigtramp_frame_unwind_stop_reason, 2754 amd64_sigtramp_frame_this_id, 2755 amd64_sigtramp_frame_prev_register, 2756 NULL, 2757 amd64_sigtramp_frame_sniffer 2758 }; 2759 2760 2761 static CORE_ADDR 2762 amd64_frame_base_address (struct frame_info *this_frame, void **this_cache) 2763 { 2764 struct amd64_frame_cache *cache = 2765 amd64_frame_cache (this_frame, this_cache); 2766 2767 return cache->base; 2768 } 2769 2770 static const struct frame_base amd64_frame_base = 2771 { 2772 &amd64_frame_unwind, 2773 amd64_frame_base_address, 2774 amd64_frame_base_address, 2775 amd64_frame_base_address 2776 }; 2777 2778 /* Normal frames, but in a function epilogue. */ 2779 2780 /* Implement the stack_frame_destroyed_p gdbarch method. 2781 2782 The epilogue is defined here as the 'ret' instruction, which will 2783 follow any instruction such as 'leave' or 'pop %ebp' that destroys 2784 the function's stack frame. */ 2785 2786 static int 2787 amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 2788 { 2789 gdb_byte insn; 2790 struct compunit_symtab *cust; 2791 2792 cust = find_pc_compunit_symtab (pc); 2793 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust)) 2794 return 0; 2795 2796 if (target_read_memory (pc, &insn, 1)) 2797 return 0; /* Can't read memory at pc. */ 2798 2799 if (insn != 0xc3) /* 'ret' instruction. */ 2800 return 0; 2801 2802 return 1; 2803 } 2804 2805 static int 2806 amd64_epilogue_frame_sniffer (const struct frame_unwind *self, 2807 struct frame_info *this_frame, 2808 void **this_prologue_cache) 2809 { 2810 if (frame_relative_level (this_frame) == 0) 2811 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame), 2812 get_frame_pc (this_frame)); 2813 else 2814 return 0; 2815 } 2816 2817 static struct amd64_frame_cache * 2818 amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) 2819 { 2820 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2821 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2822 struct amd64_frame_cache *cache; 2823 gdb_byte buf[8]; 2824 2825 if (*this_cache) 2826 return (struct amd64_frame_cache *) *this_cache; 2827 2828 cache = amd64_alloc_frame_cache (); 2829 *this_cache = cache; 2830 2831 TRY 2832 { 2833 /* Cache base will be %esp plus cache->sp_offset (-8). */ 2834 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); 2835 cache->base = extract_unsigned_integer (buf, 8, 2836 byte_order) + cache->sp_offset; 2837 2838 /* Cache pc will be the frame func. */ 2839 cache->pc = get_frame_pc (this_frame); 2840 2841 /* The saved %esp will be at cache->base plus 16. */ 2842 cache->saved_sp = cache->base + 16; 2843 2844 /* The saved %eip will be at cache->base plus 8. */ 2845 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8; 2846 2847 cache->base_p = 1; 2848 } 2849 CATCH (ex, RETURN_MASK_ERROR) 2850 { 2851 if (ex.error != NOT_AVAILABLE_ERROR) 2852 throw_exception (ex); 2853 } 2854 END_CATCH 2855 2856 return cache; 2857 } 2858 2859 static enum unwind_stop_reason 2860 amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, 2861 void **this_cache) 2862 { 2863 struct amd64_frame_cache *cache 2864 = amd64_epilogue_frame_cache (this_frame, this_cache); 2865 2866 if (!cache->base_p) 2867 return UNWIND_UNAVAILABLE; 2868 2869 return UNWIND_NO_REASON; 2870 } 2871 2872 static void 2873 amd64_epilogue_frame_this_id (struct frame_info *this_frame, 2874 void **this_cache, 2875 struct frame_id *this_id) 2876 { 2877 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame, 2878 this_cache); 2879 2880 if (!cache->base_p) 2881 (*this_id) = frame_id_build_unavailable_stack (cache->pc); 2882 else 2883 (*this_id) = frame_id_build (cache->base + 8, cache->pc); 2884 } 2885 2886 static const struct frame_unwind amd64_epilogue_frame_unwind = 2887 { 2888 NORMAL_FRAME, 2889 amd64_epilogue_frame_unwind_stop_reason, 2890 amd64_epilogue_frame_this_id, 2891 amd64_frame_prev_register, 2892 NULL, 2893 amd64_epilogue_frame_sniffer 2894 }; 2895 2896 static struct frame_id 2897 amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 2898 { 2899 CORE_ADDR fp; 2900 2901 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM); 2902 2903 return frame_id_build (fp + 16, get_frame_pc (this_frame)); 2904 } 2905 2906 /* 16 byte align the SP per frame requirements. */ 2907 2908 static CORE_ADDR 2909 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 2910 { 2911 return sp & -(CORE_ADDR)16; 2912 } 2913 2914 2915 /* Supply register REGNUM from the buffer specified by FPREGS and LEN 2916 in the floating-point register set REGSET to register cache 2917 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 2918 2919 static void 2920 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, 2921 int regnum, const void *fpregs, size_t len) 2922 { 2923 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2924 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2925 2926 gdb_assert (len >= tdep->sizeof_fpregset); 2927 amd64_supply_fxsave (regcache, regnum, fpregs); 2928 } 2929 2930 /* Collect register REGNUM from the register cache REGCACHE and store 2931 it in the buffer specified by FPREGS and LEN as described by the 2932 floating-point register set REGSET. If REGNUM is -1, do this for 2933 all registers in REGSET. */ 2934 2935 static void 2936 amd64_collect_fpregset (const struct regset *regset, 2937 const struct regcache *regcache, 2938 int regnum, void *fpregs, size_t len) 2939 { 2940 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2941 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2942 2943 gdb_assert (len >= tdep->sizeof_fpregset); 2944 amd64_collect_fxsave (regcache, regnum, fpregs); 2945 } 2946 2947 const struct regset amd64_fpregset = 2948 { 2949 NULL, amd64_supply_fpregset, amd64_collect_fpregset 2950 }; 2951 2952 2953 /* Figure out where the longjmp will land. Slurp the jmp_buf out of 2954 %rdi. We expect its value to be a pointer to the jmp_buf structure 2955 from which we extract the address that we will land at. This 2956 address is copied into PC. This routine returns non-zero on 2957 success. */ 2958 2959 static int 2960 amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 2961 { 2962 gdb_byte buf[8]; 2963 CORE_ADDR jb_addr; 2964 struct gdbarch *gdbarch = get_frame_arch (frame); 2965 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; 2966 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr); 2967 2968 /* If JB_PC_OFFSET is -1, we have no way to find out where the 2969 longjmp will land. */ 2970 if (jb_pc_offset == -1) 2971 return 0; 2972 2973 get_frame_register (frame, AMD64_RDI_REGNUM, buf); 2974 jb_addr= extract_typed_address 2975 (buf, builtin_type (gdbarch)->builtin_data_ptr); 2976 if (target_read_memory (jb_addr + jb_pc_offset, buf, len)) 2977 return 0; 2978 2979 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); 2980 2981 return 1; 2982 } 2983 2984 static const int amd64_record_regmap[] = 2985 { 2986 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM, 2987 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, 2988 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM, 2989 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM, 2990 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM, 2991 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM 2992 }; 2993 2994 void 2995 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 2996 { 2997 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2998 const struct target_desc *tdesc = info.target_desc; 2999 static const char *const stap_integer_prefixes[] = { "$", NULL }; 3000 static const char *const stap_register_prefixes[] = { "%", NULL }; 3001 static const char *const stap_register_indirection_prefixes[] = { "(", 3002 NULL }; 3003 static const char *const stap_register_indirection_suffixes[] = { ")", 3004 NULL }; 3005 3006 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its 3007 floating-point registers. */ 3008 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; 3009 tdep->fpregset = &amd64_fpregset; 3010 3011 if (! tdesc_has_registers (tdesc)) 3012 tdesc = tdesc_amd64; 3013 tdep->tdesc = tdesc; 3014 3015 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS; 3016 tdep->register_names = amd64_register_names; 3017 3018 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL) 3019 { 3020 tdep->zmmh_register_names = amd64_zmmh_names; 3021 tdep->k_register_names = amd64_k_names; 3022 tdep->xmm_avx512_register_names = amd64_xmm_avx512_names; 3023 tdep->ymm16h_register_names = amd64_ymmh_avx512_names; 3024 3025 tdep->num_zmm_regs = 32; 3026 tdep->num_xmm_avx512_regs = 16; 3027 tdep->num_ymm_avx512_regs = 16; 3028 3029 tdep->zmm0h_regnum = AMD64_ZMM0H_REGNUM; 3030 tdep->k0_regnum = AMD64_K0_REGNUM; 3031 tdep->xmm16_regnum = AMD64_XMM16_REGNUM; 3032 tdep->ymm16h_regnum = AMD64_YMM16H_REGNUM; 3033 } 3034 3035 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL) 3036 { 3037 tdep->ymmh_register_names = amd64_ymmh_names; 3038 tdep->num_ymm_regs = 16; 3039 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM; 3040 } 3041 3042 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL) 3043 { 3044 tdep->mpx_register_names = amd64_mpx_names; 3045 tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM; 3046 tdep->bnd0r_regnum = AMD64_BND0R_REGNUM; 3047 } 3048 3049 tdep->num_byte_regs = 20; 3050 tdep->num_word_regs = 16; 3051 tdep->num_dword_regs = 16; 3052 /* Avoid wiring in the MMX registers for now. */ 3053 tdep->num_mmx_regs = 0; 3054 3055 set_gdbarch_pseudo_register_read_value (gdbarch, 3056 amd64_pseudo_register_read_value); 3057 set_gdbarch_pseudo_register_write (gdbarch, 3058 amd64_pseudo_register_write); 3059 set_gdbarch_ax_pseudo_register_collect (gdbarch, 3060 amd64_ax_pseudo_register_collect); 3061 3062 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name); 3063 3064 /* AMD64 has an FPU and 16 SSE registers. */ 3065 tdep->st0_regnum = AMD64_ST0_REGNUM; 3066 tdep->num_xmm_regs = 16; 3067 3068 /* This is what all the fuss is about. */ 3069 set_gdbarch_long_bit (gdbarch, 64); 3070 set_gdbarch_long_long_bit (gdbarch, 64); 3071 set_gdbarch_ptr_bit (gdbarch, 64); 3072 3073 /* In contrast to the i386, on AMD64 a `long double' actually takes 3074 up 128 bits, even though it's still based on the i387 extended 3075 floating-point format which has only 80 significant bits. */ 3076 set_gdbarch_long_double_bit (gdbarch, 128); 3077 3078 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); 3079 3080 /* Register numbers of various important registers. */ 3081 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ 3082 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ 3083 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ 3084 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ 3085 3086 /* The "default" register numbering scheme for AMD64 is referred to 3087 as the "DWARF Register Number Mapping" in the System V psABI. 3088 The preferred debugging format for all known AMD64 targets is 3089 actually DWARF2, and GCC doesn't seem to support DWARF (that is 3090 DWARF-1), but we provide the same mapping just in case. This 3091 mapping is also used for stabs, which GCC does support. */ 3092 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 3093 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 3094 3095 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to 3096 be in use on any of the supported AMD64 targets. */ 3097 3098 /* Call dummy code. */ 3099 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call); 3100 set_gdbarch_frame_align (gdbarch, amd64_frame_align); 3101 set_gdbarch_frame_red_zone_size (gdbarch, 128); 3102 3103 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p); 3104 set_gdbarch_register_to_value (gdbarch, i387_register_to_value); 3105 set_gdbarch_value_to_register (gdbarch, i387_value_to_register); 3106 3107 set_gdbarch_return_value (gdbarch, amd64_return_value); 3108 3109 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue); 3110 3111 tdep->record_regmap = amd64_record_regmap; 3112 3113 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id); 3114 3115 /* Hook the function epilogue frame unwinder. This unwinder is 3116 appended to the list first, so that it supercedes the other 3117 unwinders in function epilogues. */ 3118 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind); 3119 3120 /* Hook the prologue-based frame unwinders. */ 3121 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind); 3122 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind); 3123 frame_base_set_default (gdbarch, &amd64_frame_base); 3124 3125 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target); 3126 3127 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction); 3128 3129 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address); 3130 3131 /* SystemTap variables and functions. */ 3132 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); 3133 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); 3134 set_gdbarch_stap_register_indirection_prefixes (gdbarch, 3135 stap_register_indirection_prefixes); 3136 set_gdbarch_stap_register_indirection_suffixes (gdbarch, 3137 stap_register_indirection_suffixes); 3138 set_gdbarch_stap_is_single_operand (gdbarch, 3139 i386_stap_is_single_operand); 3140 set_gdbarch_stap_parse_special_token (gdbarch, 3141 i386_stap_parse_special_token); 3142 set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call); 3143 set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret); 3144 set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump); 3145 } 3146 3147 3148 static struct type * 3149 amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) 3150 { 3151 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3152 3153 switch (regnum - tdep->eax_regnum) 3154 { 3155 case AMD64_RBP_REGNUM: /* %ebp */ 3156 case AMD64_RSP_REGNUM: /* %esp */ 3157 return builtin_type (gdbarch)->builtin_data_ptr; 3158 case AMD64_RIP_REGNUM: /* %eip */ 3159 return builtin_type (gdbarch)->builtin_func_ptr; 3160 } 3161 3162 return i386_pseudo_register_type (gdbarch, regnum); 3163 } 3164 3165 void 3166 amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 3167 { 3168 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3169 const struct target_desc *tdesc = info.target_desc; 3170 3171 amd64_init_abi (info, gdbarch); 3172 3173 if (! tdesc_has_registers (tdesc)) 3174 tdesc = tdesc_x32; 3175 tdep->tdesc = tdesc; 3176 3177 tdep->num_dword_regs = 17; 3178 set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type); 3179 3180 set_gdbarch_long_bit (gdbarch, 32); 3181 set_gdbarch_ptr_bit (gdbarch, 32); 3182 } 3183 3184 /* Return the target description for a specified XSAVE feature mask. */ 3185 3186 const struct target_desc * 3187 amd64_target_description (uint64_t xcr0) 3188 { 3189 switch (xcr0 & X86_XSTATE_ALL_MASK) 3190 { 3191 case X86_XSTATE_MPX_AVX512_MASK: 3192 case X86_XSTATE_AVX512_MASK: 3193 return tdesc_amd64_avx512; 3194 case X86_XSTATE_MPX_MASK: 3195 return tdesc_amd64_mpx; 3196 case X86_XSTATE_AVX_MPX_MASK: 3197 return tdesc_amd64_avx_mpx; 3198 case X86_XSTATE_AVX_MASK: 3199 return tdesc_amd64_avx; 3200 default: 3201 return tdesc_amd64; 3202 } 3203 } 3204 3205 /* Provide a prototype to silence -Wmissing-prototypes. */ 3206 void _initialize_amd64_tdep (void); 3207 3208 void 3209 _initialize_amd64_tdep (void) 3210 { 3211 initialize_tdesc_amd64 (); 3212 initialize_tdesc_amd64_avx (); 3213 initialize_tdesc_amd64_mpx (); 3214 initialize_tdesc_amd64_avx_mpx (); 3215 initialize_tdesc_amd64_avx512 (); 3216 3217 initialize_tdesc_x32 (); 3218 initialize_tdesc_x32_avx (); 3219 initialize_tdesc_x32_avx512 (); 3220 } 3221 3222 3223 /* The 64-bit FXSAVE format differs from the 32-bit format in the 3224 sense that the instruction pointer and data pointer are simply 3225 64-bit offsets into the code segment and the data segment instead 3226 of a selector offset pair. The functions below store the upper 32 3227 bits of these pointers (instead of just the 16-bits of the segment 3228 selector). */ 3229 3230 /* Fill register REGNUM in REGCACHE with the appropriate 3231 floating-point or SSE register value from *FXSAVE. If REGNUM is 3232 -1, do this for all registers. This function masks off any of the 3233 reserved bits in *FXSAVE. */ 3234 3235 void 3236 amd64_supply_fxsave (struct regcache *regcache, int regnum, 3237 const void *fxsave) 3238 { 3239 struct gdbarch *gdbarch = get_regcache_arch (regcache); 3240 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3241 3242 i387_supply_fxsave (regcache, regnum, fxsave); 3243 3244 if (fxsave 3245 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) 3246 { 3247 const gdb_byte *regs = (const gdb_byte *) fxsave; 3248 3249 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 3250 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12); 3251 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 3252 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); 3253 } 3254 } 3255 3256 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */ 3257 3258 void 3259 amd64_supply_xsave (struct regcache *regcache, int regnum, 3260 const void *xsave) 3261 { 3262 struct gdbarch *gdbarch = get_regcache_arch (regcache); 3263 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3264 3265 i387_supply_xsave (regcache, regnum, xsave); 3266 3267 if (xsave 3268 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) 3269 { 3270 const gdb_byte *regs = (const gdb_byte *) xsave; 3271 3272 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 3273 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), 3274 regs + 12); 3275 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 3276 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), 3277 regs + 20); 3278 } 3279 } 3280 3281 /* Fill register REGNUM (if it is a floating-point or SSE register) in 3282 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for 3283 all registers. This function doesn't touch any of the reserved 3284 bits in *FXSAVE. */ 3285 3286 void 3287 amd64_collect_fxsave (const struct regcache *regcache, int regnum, 3288 void *fxsave) 3289 { 3290 struct gdbarch *gdbarch = get_regcache_arch (regcache); 3291 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3292 gdb_byte *regs = (gdb_byte *) fxsave; 3293 3294 i387_collect_fxsave (regcache, regnum, fxsave); 3295 3296 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) 3297 { 3298 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 3299 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12); 3300 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 3301 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); 3302 } 3303 } 3304 3305 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */ 3306 3307 void 3308 amd64_collect_xsave (const struct regcache *regcache, int regnum, 3309 void *xsave, int gcore) 3310 { 3311 struct gdbarch *gdbarch = get_regcache_arch (regcache); 3312 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3313 gdb_byte *regs = (gdb_byte *) xsave; 3314 3315 i387_collect_xsave (regcache, regnum, xsave, gcore); 3316 3317 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) 3318 { 3319 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 3320 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), 3321 regs + 12); 3322 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 3323 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), 3324 regs + 20); 3325 } 3326 } 3327