1 /* Target-dependent code for AMD64. 2 3 Copyright (C) 2001-2017 Free Software Foundation, Inc. 4 5 Contributed by Jiri Smid, SuSE Labs. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22 #include "defs.h" 23 #include "opcode/i386.h" 24 #include "dis-asm.h" 25 #include "arch-utils.h" 26 #include "block.h" 27 #include "dummy-frame.h" 28 #include "frame.h" 29 #include "frame-base.h" 30 #include "frame-unwind.h" 31 #include "inferior.h" 32 #include "infrun.h" 33 #include "gdbcmd.h" 34 #include "gdbcore.h" 35 #include "objfiles.h" 36 #include "regcache.h" 37 #include "regset.h" 38 #include "symfile.h" 39 #include "disasm.h" 40 #include "amd64-tdep.h" 41 #include "i387-tdep.h" 42 #include "x86-xstate.h" 43 #include <algorithm> 44 45 #include "features/i386/amd64.c" 46 #include "features/i386/amd64-avx.c" 47 #include "features/i386/amd64-mpx.c" 48 #include "features/i386/amd64-avx-mpx.c" 49 #include "features/i386/amd64-avx-avx512.c" 50 #include "features/i386/amd64-avx-mpx-avx512-pku.c" 51 52 #include "features/i386/x32.c" 53 #include "features/i386/x32-avx.c" 54 #include "features/i386/x32-avx-avx512.c" 55 56 #include "ax.h" 57 #include "ax-gdb.h" 58 59 /* Note that the AMD64 architecture was previously known as x86-64. 60 The latter is (forever) engraved into the canonical system name as 61 returned by config.guess, and used as the name for the AMD64 port 62 of GNU/Linux. The BSD's have renamed their ports to amd64; they 63 don't like to shout. For GDB we prefer the amd64_-prefix over the 64 x86_64_-prefix since it's so much easier to type. */ 65 66 /* Register information. */ 67 68 static const char *amd64_register_names[] = 69 { 70 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", 71 72 /* %r8 is indeed register number 8. */ 73 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 74 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs", 75 76 /* %st0 is register number 24. */ 77 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", 78 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop", 79 80 /* %xmm0 is register number 40. */ 81 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 82 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 83 "mxcsr", 84 }; 85 86 static const char *amd64_ymm_names[] = 87 { 88 "ymm0", "ymm1", "ymm2", "ymm3", 89 "ymm4", "ymm5", "ymm6", "ymm7", 90 "ymm8", "ymm9", "ymm10", "ymm11", 91 "ymm12", "ymm13", "ymm14", "ymm15" 92 }; 93 94 static const char *amd64_ymm_avx512_names[] = 95 { 96 "ymm16", "ymm17", "ymm18", "ymm19", 97 "ymm20", "ymm21", "ymm22", "ymm23", 98 "ymm24", "ymm25", "ymm26", "ymm27", 99 "ymm28", "ymm29", "ymm30", "ymm31" 100 }; 101 102 static const char *amd64_ymmh_names[] = 103 { 104 "ymm0h", "ymm1h", "ymm2h", "ymm3h", 105 "ymm4h", "ymm5h", "ymm6h", "ymm7h", 106 "ymm8h", "ymm9h", "ymm10h", "ymm11h", 107 "ymm12h", "ymm13h", "ymm14h", "ymm15h" 108 }; 109 110 static const char *amd64_ymmh_avx512_names[] = 111 { 112 "ymm16h", "ymm17h", "ymm18h", "ymm19h", 113 "ymm20h", "ymm21h", "ymm22h", "ymm23h", 114 "ymm24h", "ymm25h", "ymm26h", "ymm27h", 115 "ymm28h", "ymm29h", "ymm30h", "ymm31h" 116 }; 117 118 static const char *amd64_mpx_names[] = 119 { 120 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" 121 }; 122 123 static const char *amd64_k_names[] = 124 { 125 "k0", "k1", "k2", "k3", 126 "k4", "k5", "k6", "k7" 127 }; 128 129 static const char *amd64_zmmh_names[] = 130 { 131 "zmm0h", "zmm1h", "zmm2h", "zmm3h", 132 "zmm4h", "zmm5h", "zmm6h", "zmm7h", 133 "zmm8h", "zmm9h", "zmm10h", "zmm11h", 134 "zmm12h", "zmm13h", "zmm14h", "zmm15h", 135 "zmm16h", "zmm17h", "zmm18h", "zmm19h", 136 "zmm20h", "zmm21h", "zmm22h", "zmm23h", 137 "zmm24h", "zmm25h", "zmm26h", "zmm27h", 138 "zmm28h", "zmm29h", "zmm30h", "zmm31h" 139 }; 140 141 static const char *amd64_zmm_names[] = 142 { 143 "zmm0", "zmm1", "zmm2", "zmm3", 144 "zmm4", "zmm5", "zmm6", "zmm7", 145 "zmm8", "zmm9", "zmm10", "zmm11", 146 "zmm12", "zmm13", "zmm14", "zmm15", 147 "zmm16", "zmm17", "zmm18", "zmm19", 148 "zmm20", "zmm21", "zmm22", "zmm23", 149 "zmm24", "zmm25", "zmm26", "zmm27", 150 "zmm28", "zmm29", "zmm30", "zmm31" 151 }; 152 153 static const char *amd64_xmm_avx512_names[] = { 154 "xmm16", "xmm17", "xmm18", "xmm19", 155 "xmm20", "xmm21", "xmm22", "xmm23", 156 "xmm24", "xmm25", "xmm26", "xmm27", 157 "xmm28", "xmm29", "xmm30", "xmm31" 158 }; 159 160 static const char *amd64_pkeys_names[] = { 161 "pkru" 162 }; 163 164 /* DWARF Register Number Mapping as defined in the System V psABI, 165 section 3.6. */ 166 167 static int amd64_dwarf_regmap[] = 168 { 169 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ 170 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, 171 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, 172 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, 173 174 /* Frame Pointer Register RBP. */ 175 AMD64_RBP_REGNUM, 176 177 /* Stack Pointer Register RSP. */ 178 AMD64_RSP_REGNUM, 179 180 /* Extended Integer Registers 8 - 15. */ 181 AMD64_R8_REGNUM, /* %r8 */ 182 AMD64_R9_REGNUM, /* %r9 */ 183 AMD64_R10_REGNUM, /* %r10 */ 184 AMD64_R11_REGNUM, /* %r11 */ 185 AMD64_R12_REGNUM, /* %r12 */ 186 AMD64_R13_REGNUM, /* %r13 */ 187 AMD64_R14_REGNUM, /* %r14 */ 188 AMD64_R15_REGNUM, /* %r15 */ 189 190 /* Return Address RA. Mapped to RIP. */ 191 AMD64_RIP_REGNUM, 192 193 /* SSE Registers 0 - 7. */ 194 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, 195 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, 196 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, 197 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, 198 199 /* Extended SSE Registers 8 - 15. */ 200 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, 201 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, 202 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, 203 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, 204 205 /* Floating Point Registers 0-7. */ 206 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, 207 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, 208 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, 209 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, 210 211 /* MMX Registers 0 - 7. 212 We have to handle those registers specifically, as their register 213 number within GDB depends on the target (or they may even not be 214 available at all). */ 215 -1, -1, -1, -1, -1, -1, -1, -1, 216 217 /* Control and Status Flags Register. */ 218 AMD64_EFLAGS_REGNUM, 219 220 /* Selector Registers. */ 221 AMD64_ES_REGNUM, 222 AMD64_CS_REGNUM, 223 AMD64_SS_REGNUM, 224 AMD64_DS_REGNUM, 225 AMD64_FS_REGNUM, 226 AMD64_GS_REGNUM, 227 -1, 228 -1, 229 230 /* Segment Base Address Registers. */ 231 -1, 232 -1, 233 -1, 234 -1, 235 236 /* Special Selector Registers. */ 237 -1, 238 -1, 239 240 /* Floating Point Control Registers. */ 241 AMD64_MXCSR_REGNUM, 242 AMD64_FCTRL_REGNUM, 243 AMD64_FSTAT_REGNUM 244 }; 245 246 static const int amd64_dwarf_regmap_len = 247 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); 248 249 /* Convert DWARF register number REG to the appropriate register 250 number used by GDB. */ 251 252 static int 253 amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) 254 { 255 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 256 int ymm0_regnum = tdep->ymm0_regnum; 257 int regnum = -1; 258 259 if (reg >= 0 && reg < amd64_dwarf_regmap_len) 260 regnum = amd64_dwarf_regmap[reg]; 261 262 if (ymm0_regnum >= 0 263 && i386_xmm_regnum_p (gdbarch, regnum)) 264 regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep); 265 266 return regnum; 267 } 268 269 /* Map architectural register numbers to gdb register numbers. */ 270 271 static const int amd64_arch_regmap[16] = 272 { 273 AMD64_RAX_REGNUM, /* %rax */ 274 AMD64_RCX_REGNUM, /* %rcx */ 275 AMD64_RDX_REGNUM, /* %rdx */ 276 AMD64_RBX_REGNUM, /* %rbx */ 277 AMD64_RSP_REGNUM, /* %rsp */ 278 AMD64_RBP_REGNUM, /* %rbp */ 279 AMD64_RSI_REGNUM, /* %rsi */ 280 AMD64_RDI_REGNUM, /* %rdi */ 281 AMD64_R8_REGNUM, /* %r8 */ 282 AMD64_R9_REGNUM, /* %r9 */ 283 AMD64_R10_REGNUM, /* %r10 */ 284 AMD64_R11_REGNUM, /* %r11 */ 285 AMD64_R12_REGNUM, /* %r12 */ 286 AMD64_R13_REGNUM, /* %r13 */ 287 AMD64_R14_REGNUM, /* %r14 */ 288 AMD64_R15_REGNUM /* %r15 */ 289 }; 290 291 static const int amd64_arch_regmap_len = 292 (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0])); 293 294 /* Convert architectural register number REG to the appropriate register 295 number used by GDB. */ 296 297 static int 298 amd64_arch_reg_to_regnum (int reg) 299 { 300 gdb_assert (reg >= 0 && reg < amd64_arch_regmap_len); 301 302 return amd64_arch_regmap[reg]; 303 } 304 305 /* Register names for byte pseudo-registers. */ 306 307 static const char *amd64_byte_names[] = 308 { 309 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl", 310 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l", 311 "ah", "bh", "ch", "dh" 312 }; 313 314 /* Number of lower byte registers. */ 315 #define AMD64_NUM_LOWER_BYTE_REGS 16 316 317 /* Register names for word pseudo-registers. */ 318 319 static const char *amd64_word_names[] = 320 { 321 "ax", "bx", "cx", "dx", "si", "di", "bp", "", 322 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" 323 }; 324 325 /* Register names for dword pseudo-registers. */ 326 327 static const char *amd64_dword_names[] = 328 { 329 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp", 330 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", 331 "eip" 332 }; 333 334 /* Return the name of register REGNUM. */ 335 336 static const char * 337 amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) 338 { 339 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 340 if (i386_byte_regnum_p (gdbarch, regnum)) 341 return amd64_byte_names[regnum - tdep->al_regnum]; 342 else if (i386_zmm_regnum_p (gdbarch, regnum)) 343 return amd64_zmm_names[regnum - tdep->zmm0_regnum]; 344 else if (i386_ymm_regnum_p (gdbarch, regnum)) 345 return amd64_ymm_names[regnum - tdep->ymm0_regnum]; 346 else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) 347 return amd64_ymm_avx512_names[regnum - tdep->ymm16_regnum]; 348 else if (i386_word_regnum_p (gdbarch, regnum)) 349 return amd64_word_names[regnum - tdep->ax_regnum]; 350 else if (i386_dword_regnum_p (gdbarch, regnum)) 351 return amd64_dword_names[regnum - tdep->eax_regnum]; 352 else 353 return i386_pseudo_register_name (gdbarch, regnum); 354 } 355 356 static struct value * 357 amd64_pseudo_register_read_value (struct gdbarch *gdbarch, 358 struct regcache *regcache, 359 int regnum) 360 { 361 gdb_byte *raw_buf = (gdb_byte *) alloca (register_size (gdbarch, regnum)); 362 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 363 enum register_status status; 364 struct value *result_value; 365 gdb_byte *buf; 366 367 result_value = allocate_value (register_type (gdbarch, regnum)); 368 VALUE_LVAL (result_value) = lval_register; 369 VALUE_REGNUM (result_value) = regnum; 370 buf = value_contents_raw (result_value); 371 372 if (i386_byte_regnum_p (gdbarch, regnum)) 373 { 374 int gpnum = regnum - tdep->al_regnum; 375 376 /* Extract (always little endian). */ 377 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) 378 { 379 /* Special handling for AH, BH, CH, DH. */ 380 status = regcache_raw_read (regcache, 381 gpnum - AMD64_NUM_LOWER_BYTE_REGS, 382 raw_buf); 383 if (status == REG_VALID) 384 memcpy (buf, raw_buf + 1, 1); 385 else 386 mark_value_bytes_unavailable (result_value, 0, 387 TYPE_LENGTH (value_type (result_value))); 388 } 389 else 390 { 391 status = regcache_raw_read (regcache, gpnum, raw_buf); 392 if (status == REG_VALID) 393 memcpy (buf, raw_buf, 1); 394 else 395 mark_value_bytes_unavailable (result_value, 0, 396 TYPE_LENGTH (value_type (result_value))); 397 } 398 } 399 else if (i386_dword_regnum_p (gdbarch, regnum)) 400 { 401 int gpnum = regnum - tdep->eax_regnum; 402 /* Extract (always little endian). */ 403 status = regcache_raw_read (regcache, gpnum, raw_buf); 404 if (status == REG_VALID) 405 memcpy (buf, raw_buf, 4); 406 else 407 mark_value_bytes_unavailable (result_value, 0, 408 TYPE_LENGTH (value_type (result_value))); 409 } 410 else 411 i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, 412 result_value); 413 414 return result_value; 415 } 416 417 static void 418 amd64_pseudo_register_write (struct gdbarch *gdbarch, 419 struct regcache *regcache, 420 int regnum, const gdb_byte *buf) 421 { 422 gdb_byte *raw_buf = (gdb_byte *) alloca (register_size (gdbarch, regnum)); 423 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 424 425 if (i386_byte_regnum_p (gdbarch, regnum)) 426 { 427 int gpnum = regnum - tdep->al_regnum; 428 429 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) 430 { 431 /* Read ... AH, BH, CH, DH. */ 432 regcache_raw_read (regcache, 433 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); 434 /* ... Modify ... (always little endian). */ 435 memcpy (raw_buf + 1, buf, 1); 436 /* ... Write. */ 437 regcache_raw_write (regcache, 438 gpnum - AMD64_NUM_LOWER_BYTE_REGS, raw_buf); 439 } 440 else 441 { 442 /* Read ... */ 443 regcache_raw_read (regcache, gpnum, raw_buf); 444 /* ... Modify ... (always little endian). */ 445 memcpy (raw_buf, buf, 1); 446 /* ... Write. */ 447 regcache_raw_write (regcache, gpnum, raw_buf); 448 } 449 } 450 else if (i386_dword_regnum_p (gdbarch, regnum)) 451 { 452 int gpnum = regnum - tdep->eax_regnum; 453 454 /* Read ... */ 455 regcache_raw_read (regcache, gpnum, raw_buf); 456 /* ... Modify ... (always little endian). */ 457 memcpy (raw_buf, buf, 4); 458 /* ... Write. */ 459 regcache_raw_write (regcache, gpnum, raw_buf); 460 } 461 else 462 i386_pseudo_register_write (gdbarch, regcache, regnum, buf); 463 } 464 465 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */ 466 467 static int 468 amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch, 469 struct agent_expr *ax, int regnum) 470 { 471 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 472 473 if (i386_byte_regnum_p (gdbarch, regnum)) 474 { 475 int gpnum = regnum - tdep->al_regnum; 476 477 if (gpnum >= AMD64_NUM_LOWER_BYTE_REGS) 478 ax_reg_mask (ax, gpnum - AMD64_NUM_LOWER_BYTE_REGS); 479 else 480 ax_reg_mask (ax, gpnum); 481 return 0; 482 } 483 else if (i386_dword_regnum_p (gdbarch, regnum)) 484 { 485 int gpnum = regnum - tdep->eax_regnum; 486 487 ax_reg_mask (ax, gpnum); 488 return 0; 489 } 490 else 491 return i386_ax_pseudo_register_collect (gdbarch, ax, regnum); 492 } 493 494 495 496 /* Register classes as defined in the psABI. */ 497 498 enum amd64_reg_class 499 { 500 AMD64_INTEGER, 501 AMD64_SSE, 502 AMD64_SSEUP, 503 AMD64_X87, 504 AMD64_X87UP, 505 AMD64_COMPLEX_X87, 506 AMD64_NO_CLASS, 507 AMD64_MEMORY 508 }; 509 510 /* Return the union class of CLASS1 and CLASS2. See the psABI for 511 details. */ 512 513 static enum amd64_reg_class 514 amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) 515 { 516 /* Rule (a): If both classes are equal, this is the resulting class. */ 517 if (class1 == class2) 518 return class1; 519 520 /* Rule (b): If one of the classes is NO_CLASS, the resulting class 521 is the other class. */ 522 if (class1 == AMD64_NO_CLASS) 523 return class2; 524 if (class2 == AMD64_NO_CLASS) 525 return class1; 526 527 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ 528 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY) 529 return AMD64_MEMORY; 530 531 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ 532 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER) 533 return AMD64_INTEGER; 534 535 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class, 536 MEMORY is used as class. */ 537 if (class1 == AMD64_X87 || class1 == AMD64_X87UP 538 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87 539 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87) 540 return AMD64_MEMORY; 541 542 /* Rule (f): Otherwise class SSE is used. */ 543 return AMD64_SSE; 544 } 545 546 static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]); 547 548 /* Return non-zero if TYPE is a non-POD structure or union type. */ 549 550 static int 551 amd64_non_pod_p (struct type *type) 552 { 553 /* ??? A class with a base class certainly isn't POD, but does this 554 catch all non-POD structure types? */ 555 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) 556 return 1; 557 558 return 0; 559 } 560 561 /* Classify TYPE according to the rules for aggregate (structures and 562 arrays) and union types, and store the result in CLASS. */ 563 564 static void 565 amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2]) 566 { 567 /* 1. If the size of an object is larger than two eightbytes, or in 568 C++, is a non-POD structure or union type, or contains 569 unaligned fields, it has class memory. */ 570 if (TYPE_LENGTH (type) > 16 || amd64_non_pod_p (type)) 571 { 572 theclass[0] = theclass[1] = AMD64_MEMORY; 573 return; 574 } 575 576 /* 2. Both eightbytes get initialized to class NO_CLASS. */ 577 theclass[0] = theclass[1] = AMD64_NO_CLASS; 578 579 /* 3. Each field of an object is classified recursively so that 580 always two fields are considered. The resulting class is 581 calculated according to the classes of the fields in the 582 eightbyte: */ 583 584 if (TYPE_CODE (type) == TYPE_CODE_ARRAY) 585 { 586 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); 587 588 /* All fields in an array have the same type. */ 589 amd64_classify (subtype, theclass); 590 if (TYPE_LENGTH (type) > 8 && theclass[1] == AMD64_NO_CLASS) 591 theclass[1] = theclass[0]; 592 } 593 else 594 { 595 int i; 596 597 /* Structure or union. */ 598 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT 599 || TYPE_CODE (type) == TYPE_CODE_UNION); 600 601 for (i = 0; i < TYPE_NFIELDS (type); i++) 602 { 603 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); 604 int pos = TYPE_FIELD_BITPOS (type, i) / 64; 605 enum amd64_reg_class subclass[2]; 606 int bitsize = TYPE_FIELD_BITSIZE (type, i); 607 int endpos; 608 609 if (bitsize == 0) 610 bitsize = TYPE_LENGTH (subtype) * 8; 611 endpos = (TYPE_FIELD_BITPOS (type, i) + bitsize - 1) / 64; 612 613 /* Ignore static fields. */ 614 if (field_is_static (&TYPE_FIELD (type, i))) 615 continue; 616 617 gdb_assert (pos == 0 || pos == 1); 618 619 amd64_classify (subtype, subclass); 620 theclass[pos] = amd64_merge_classes (theclass[pos], subclass[0]); 621 if (bitsize <= 64 && pos == 0 && endpos == 1) 622 /* This is a bit of an odd case: We have a field that would 623 normally fit in one of the two eightbytes, except that 624 it is placed in a way that this field straddles them. 625 This has been seen with a structure containing an array. 626 627 The ABI is a bit unclear in this case, but we assume that 628 this field's class (stored in subclass[0]) must also be merged 629 into class[1]. In other words, our field has a piece stored 630 in the second eight-byte, and thus its class applies to 631 the second eight-byte as well. 632 633 In the case where the field length exceeds 8 bytes, 634 it should not be necessary to merge the field class 635 into class[1]. As LEN > 8, subclass[1] is necessarily 636 different from AMD64_NO_CLASS. If subclass[1] is equal 637 to subclass[0], then the normal class[1]/subclass[1] 638 merging will take care of everything. For subclass[1] 639 to be different from subclass[0], I can only see the case 640 where we have a SSE/SSEUP or X87/X87UP pair, which both 641 use up all 16 bytes of the aggregate, and are already 642 handled just fine (because each portion sits on its own 643 8-byte). */ 644 theclass[1] = amd64_merge_classes (theclass[1], subclass[0]); 645 if (pos == 0) 646 theclass[1] = amd64_merge_classes (theclass[1], subclass[1]); 647 } 648 } 649 650 /* 4. Then a post merger cleanup is done: */ 651 652 /* Rule (a): If one of the classes is MEMORY, the whole argument is 653 passed in memory. */ 654 if (theclass[0] == AMD64_MEMORY || theclass[1] == AMD64_MEMORY) 655 theclass[0] = theclass[1] = AMD64_MEMORY; 656 657 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to 658 SSE. */ 659 if (theclass[0] == AMD64_SSEUP) 660 theclass[0] = AMD64_SSE; 661 if (theclass[1] == AMD64_SSEUP && theclass[0] != AMD64_SSE) 662 theclass[1] = AMD64_SSE; 663 } 664 665 /* Classify TYPE, and store the result in CLASS. */ 666 667 static void 668 amd64_classify (struct type *type, enum amd64_reg_class theclass[2]) 669 { 670 enum type_code code = TYPE_CODE (type); 671 int len = TYPE_LENGTH (type); 672 673 theclass[0] = theclass[1] = AMD64_NO_CLASS; 674 675 /* Arguments of types (signed and unsigned) _Bool, char, short, int, 676 long, long long, and pointers are in the INTEGER class. Similarly, 677 range types, used by languages such as Ada, are also in the INTEGER 678 class. */ 679 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM 680 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE 681 || code == TYPE_CODE_CHAR 682 || code == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type)) 683 && (len == 1 || len == 2 || len == 4 || len == 8)) 684 theclass[0] = AMD64_INTEGER; 685 686 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64 687 are in class SSE. */ 688 else if ((code == TYPE_CODE_FLT || code == TYPE_CODE_DECFLOAT) 689 && (len == 4 || len == 8)) 690 /* FIXME: __m64 . */ 691 theclass[0] = AMD64_SSE; 692 693 /* Arguments of types __float128, _Decimal128 and __m128 are split into 694 two halves. The least significant ones belong to class SSE, the most 695 significant one to class SSEUP. */ 696 else if (code == TYPE_CODE_DECFLOAT && len == 16) 697 /* FIXME: __float128, __m128. */ 698 theclass[0] = AMD64_SSE, theclass[1] = AMD64_SSEUP; 699 700 /* The 64-bit mantissa of arguments of type long double belongs to 701 class X87, the 16-bit exponent plus 6 bytes of padding belongs to 702 class X87UP. */ 703 else if (code == TYPE_CODE_FLT && len == 16) 704 /* Class X87 and X87UP. */ 705 theclass[0] = AMD64_X87, theclass[1] = AMD64_X87UP; 706 707 /* Arguments of complex T where T is one of the types float or 708 double get treated as if they are implemented as: 709 710 struct complexT { 711 T real; 712 T imag; 713 }; 714 715 */ 716 else if (code == TYPE_CODE_COMPLEX && len == 8) 717 theclass[0] = AMD64_SSE; 718 else if (code == TYPE_CODE_COMPLEX && len == 16) 719 theclass[0] = theclass[1] = AMD64_SSE; 720 721 /* A variable of type complex long double is classified as type 722 COMPLEX_X87. */ 723 else if (code == TYPE_CODE_COMPLEX && len == 32) 724 theclass[0] = AMD64_COMPLEX_X87; 725 726 /* Aggregates. */ 727 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT 728 || code == TYPE_CODE_UNION) 729 amd64_classify_aggregate (type, theclass); 730 } 731 732 static enum return_value_convention 733 amd64_return_value (struct gdbarch *gdbarch, struct value *function, 734 struct type *type, struct regcache *regcache, 735 gdb_byte *readbuf, const gdb_byte *writebuf) 736 { 737 enum amd64_reg_class theclass[2]; 738 int len = TYPE_LENGTH (type); 739 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; 740 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; 741 int integer_reg = 0; 742 int sse_reg = 0; 743 int i; 744 745 gdb_assert (!(readbuf && writebuf)); 746 747 /* 1. Classify the return type with the classification algorithm. */ 748 amd64_classify (type, theclass); 749 750 /* 2. If the type has class MEMORY, then the caller provides space 751 for the return value and passes the address of this storage in 752 %rdi as if it were the first argument to the function. In effect, 753 this address becomes a hidden first argument. 754 755 On return %rax will contain the address that has been passed in 756 by the caller in %rdi. */ 757 if (theclass[0] == AMD64_MEMORY) 758 { 759 /* As indicated by the comment above, the ABI guarantees that we 760 can always find the return value just after the function has 761 returned. */ 762 763 if (readbuf) 764 { 765 ULONGEST addr; 766 767 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr); 768 read_memory (addr, readbuf, TYPE_LENGTH (type)); 769 } 770 771 return RETURN_VALUE_ABI_RETURNS_ADDRESS; 772 } 773 774 /* 8. If the class is COMPLEX_X87, the real part of the value is 775 returned in %st0 and the imaginary part in %st1. */ 776 if (theclass[0] == AMD64_COMPLEX_X87) 777 { 778 if (readbuf) 779 { 780 regcache_raw_read (regcache, AMD64_ST0_REGNUM, readbuf); 781 regcache_raw_read (regcache, AMD64_ST1_REGNUM, readbuf + 16); 782 } 783 784 if (writebuf) 785 { 786 i387_return_value (gdbarch, regcache); 787 regcache_raw_write (regcache, AMD64_ST0_REGNUM, writebuf); 788 regcache_raw_write (regcache, AMD64_ST1_REGNUM, writebuf + 16); 789 790 /* Fix up the tag word such that both %st(0) and %st(1) are 791 marked as valid. */ 792 regcache_raw_write_unsigned (regcache, AMD64_FTAG_REGNUM, 0xfff); 793 } 794 795 return RETURN_VALUE_REGISTER_CONVENTION; 796 } 797 798 gdb_assert (theclass[1] != AMD64_MEMORY); 799 gdb_assert (len <= 16); 800 801 for (i = 0; len > 0; i++, len -= 8) 802 { 803 int regnum = -1; 804 int offset = 0; 805 806 switch (theclass[i]) 807 { 808 case AMD64_INTEGER: 809 /* 3. If the class is INTEGER, the next available register 810 of the sequence %rax, %rdx is used. */ 811 regnum = integer_regnum[integer_reg++]; 812 break; 813 814 case AMD64_SSE: 815 /* 4. If the class is SSE, the next available SSE register 816 of the sequence %xmm0, %xmm1 is used. */ 817 regnum = sse_regnum[sse_reg++]; 818 break; 819 820 case AMD64_SSEUP: 821 /* 5. If the class is SSEUP, the eightbyte is passed in the 822 upper half of the last used SSE register. */ 823 gdb_assert (sse_reg > 0); 824 regnum = sse_regnum[sse_reg - 1]; 825 offset = 8; 826 break; 827 828 case AMD64_X87: 829 /* 6. If the class is X87, the value is returned on the X87 830 stack in %st0 as 80-bit x87 number. */ 831 regnum = AMD64_ST0_REGNUM; 832 if (writebuf) 833 i387_return_value (gdbarch, regcache); 834 break; 835 836 case AMD64_X87UP: 837 /* 7. If the class is X87UP, the value is returned together 838 with the previous X87 value in %st0. */ 839 gdb_assert (i > 0 && theclass[0] == AMD64_X87); 840 regnum = AMD64_ST0_REGNUM; 841 offset = 8; 842 len = 2; 843 break; 844 845 case AMD64_NO_CLASS: 846 continue; 847 848 default: 849 gdb_assert (!"Unexpected register class."); 850 } 851 852 gdb_assert (regnum != -1); 853 854 if (readbuf) 855 regcache_raw_read_part (regcache, regnum, offset, std::min (len, 8), 856 readbuf + i * 8); 857 if (writebuf) 858 regcache_raw_write_part (regcache, regnum, offset, std::min (len, 8), 859 writebuf + i * 8); 860 } 861 862 return RETURN_VALUE_REGISTER_CONVENTION; 863 } 864 865 866 static CORE_ADDR 867 amd64_push_arguments (struct regcache *regcache, int nargs, 868 struct value **args, CORE_ADDR sp, int struct_return) 869 { 870 static int integer_regnum[] = 871 { 872 AMD64_RDI_REGNUM, /* %rdi */ 873 AMD64_RSI_REGNUM, /* %rsi */ 874 AMD64_RDX_REGNUM, /* %rdx */ 875 AMD64_RCX_REGNUM, /* %rcx */ 876 AMD64_R8_REGNUM, /* %r8 */ 877 AMD64_R9_REGNUM /* %r9 */ 878 }; 879 static int sse_regnum[] = 880 { 881 /* %xmm0 ... %xmm7 */ 882 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, 883 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, 884 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, 885 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, 886 }; 887 struct value **stack_args = XALLOCAVEC (struct value *, nargs); 888 int num_stack_args = 0; 889 int num_elements = 0; 890 int element = 0; 891 int integer_reg = 0; 892 int sse_reg = 0; 893 int i; 894 895 /* Reserve a register for the "hidden" argument. */ 896 if (struct_return) 897 integer_reg++; 898 899 for (i = 0; i < nargs; i++) 900 { 901 struct type *type = value_type (args[i]); 902 int len = TYPE_LENGTH (type); 903 enum amd64_reg_class theclass[2]; 904 int needed_integer_regs = 0; 905 int needed_sse_regs = 0; 906 int j; 907 908 /* Classify argument. */ 909 amd64_classify (type, theclass); 910 911 /* Calculate the number of integer and SSE registers needed for 912 this argument. */ 913 for (j = 0; j < 2; j++) 914 { 915 if (theclass[j] == AMD64_INTEGER) 916 needed_integer_regs++; 917 else if (theclass[j] == AMD64_SSE) 918 needed_sse_regs++; 919 } 920 921 /* Check whether enough registers are available, and if the 922 argument should be passed in registers at all. */ 923 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum) 924 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) 925 || (needed_integer_regs == 0 && needed_sse_regs == 0)) 926 { 927 /* The argument will be passed on the stack. */ 928 num_elements += ((len + 7) / 8); 929 stack_args[num_stack_args++] = args[i]; 930 } 931 else 932 { 933 /* The argument will be passed in registers. */ 934 const gdb_byte *valbuf = value_contents (args[i]); 935 gdb_byte buf[8]; 936 937 gdb_assert (len <= 16); 938 939 for (j = 0; len > 0; j++, len -= 8) 940 { 941 int regnum = -1; 942 int offset = 0; 943 944 switch (theclass[j]) 945 { 946 case AMD64_INTEGER: 947 regnum = integer_regnum[integer_reg++]; 948 break; 949 950 case AMD64_SSE: 951 regnum = sse_regnum[sse_reg++]; 952 break; 953 954 case AMD64_SSEUP: 955 gdb_assert (sse_reg > 0); 956 regnum = sse_regnum[sse_reg - 1]; 957 offset = 8; 958 break; 959 960 default: 961 gdb_assert (!"Unexpected register class."); 962 } 963 964 gdb_assert (regnum != -1); 965 memset (buf, 0, sizeof buf); 966 memcpy (buf, valbuf + j * 8, std::min (len, 8)); 967 regcache_raw_write_part (regcache, regnum, offset, 8, buf); 968 } 969 } 970 } 971 972 /* Allocate space for the arguments on the stack. */ 973 sp -= num_elements * 8; 974 975 /* The psABI says that "The end of the input argument area shall be 976 aligned on a 16 byte boundary." */ 977 sp &= ~0xf; 978 979 /* Write out the arguments to the stack. */ 980 for (i = 0; i < num_stack_args; i++) 981 { 982 struct type *type = value_type (stack_args[i]); 983 const gdb_byte *valbuf = value_contents (stack_args[i]); 984 int len = TYPE_LENGTH (type); 985 986 write_memory (sp + element * 8, valbuf, len); 987 element += ((len + 7) / 8); 988 } 989 990 /* The psABI says that "For calls that may call functions that use 991 varargs or stdargs (prototype-less calls or calls to functions 992 containing ellipsis (...) in the declaration) %al is used as 993 hidden argument to specify the number of SSE registers used. */ 994 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); 995 return sp; 996 } 997 998 static CORE_ADDR 999 amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 1000 struct regcache *regcache, CORE_ADDR bp_addr, 1001 int nargs, struct value **args, CORE_ADDR sp, 1002 int struct_return, CORE_ADDR struct_addr) 1003 { 1004 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1005 gdb_byte buf[8]; 1006 1007 /* BND registers can be in arbitrary values at the moment of the 1008 inferior call. This can cause boundary violations that are not 1009 due to a real bug or even desired by the user. The best to be done 1010 is set the BND registers to allow access to the whole memory, INIT 1011 state, before pushing the inferior call. */ 1012 i387_reset_bnd_regs (gdbarch, regcache); 1013 1014 /* Pass arguments. */ 1015 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); 1016 1017 /* Pass "hidden" argument". */ 1018 if (struct_return) 1019 { 1020 store_unsigned_integer (buf, 8, byte_order, struct_addr); 1021 regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf); 1022 } 1023 1024 /* Store return address. */ 1025 sp -= 8; 1026 store_unsigned_integer (buf, 8, byte_order, bp_addr); 1027 write_memory (sp, buf, 8); 1028 1029 /* Finally, update the stack pointer... */ 1030 store_unsigned_integer (buf, 8, byte_order, sp); 1031 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); 1032 1033 /* ...and fake a frame pointer. */ 1034 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); 1035 1036 return sp + 16; 1037 } 1038 1039 /* Displaced instruction handling. */ 1040 1041 /* A partially decoded instruction. 1042 This contains enough details for displaced stepping purposes. */ 1043 1044 struct amd64_insn 1045 { 1046 /* The number of opcode bytes. */ 1047 int opcode_len; 1048 /* The offset of the rex prefix or -1 if not present. */ 1049 int rex_offset; 1050 /* The offset to the first opcode byte. */ 1051 int opcode_offset; 1052 /* The offset to the modrm byte or -1 if not present. */ 1053 int modrm_offset; 1054 1055 /* The raw instruction. */ 1056 gdb_byte *raw_insn; 1057 }; 1058 1059 struct displaced_step_closure 1060 { 1061 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */ 1062 int tmp_used; 1063 int tmp_regno; 1064 ULONGEST tmp_save; 1065 1066 /* Details of the instruction. */ 1067 struct amd64_insn insn_details; 1068 1069 /* Amount of space allocated to insn_buf. */ 1070 int max_len; 1071 1072 /* The possibly modified insn. 1073 This is a variable-length field. */ 1074 gdb_byte insn_buf[1]; 1075 }; 1076 1077 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with 1078 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative, 1079 at which point delete these in favor of libopcodes' versions). */ 1080 1081 static const unsigned char onebyte_has_modrm[256] = { 1082 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 1083 /* ------------------------------- */ 1084 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ 1085 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ 1086 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ 1087 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ 1088 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ 1089 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ 1090 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ 1091 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ 1092 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ 1093 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ 1094 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ 1095 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ 1096 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ 1097 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ 1098 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ 1099 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ 1100 /* ------------------------------- */ 1101 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 1102 }; 1103 1104 static const unsigned char twobyte_has_modrm[256] = { 1105 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 1106 /* ------------------------------- */ 1107 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ 1108 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ 1109 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ 1110 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ 1111 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ 1112 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ 1113 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ 1114 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ 1115 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ 1116 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ 1117 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ 1118 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ 1119 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ 1120 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ 1121 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ 1122 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ 1123 /* ------------------------------- */ 1124 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ 1125 }; 1126 1127 static int amd64_syscall_p (const struct amd64_insn *insn, int *lengthp); 1128 1129 static int 1130 rex_prefix_p (gdb_byte pfx) 1131 { 1132 return REX_PREFIX_P (pfx); 1133 } 1134 1135 /* Skip the legacy instruction prefixes in INSN. 1136 We assume INSN is properly sentineled so we don't have to worry 1137 about falling off the end of the buffer. */ 1138 1139 static gdb_byte * 1140 amd64_skip_prefixes (gdb_byte *insn) 1141 { 1142 while (1) 1143 { 1144 switch (*insn) 1145 { 1146 case DATA_PREFIX_OPCODE: 1147 case ADDR_PREFIX_OPCODE: 1148 case CS_PREFIX_OPCODE: 1149 case DS_PREFIX_OPCODE: 1150 case ES_PREFIX_OPCODE: 1151 case FS_PREFIX_OPCODE: 1152 case GS_PREFIX_OPCODE: 1153 case SS_PREFIX_OPCODE: 1154 case LOCK_PREFIX_OPCODE: 1155 case REPE_PREFIX_OPCODE: 1156 case REPNE_PREFIX_OPCODE: 1157 ++insn; 1158 continue; 1159 default: 1160 break; 1161 } 1162 break; 1163 } 1164 1165 return insn; 1166 } 1167 1168 /* Return an integer register (other than RSP) that is unused as an input 1169 operand in INSN. 1170 In order to not require adding a rex prefix if the insn doesn't already 1171 have one, the result is restricted to RAX ... RDI, sans RSP. 1172 The register numbering of the result follows architecture ordering, 1173 e.g. RDI = 7. */ 1174 1175 static int 1176 amd64_get_unused_input_int_reg (const struct amd64_insn *details) 1177 { 1178 /* 1 bit for each reg */ 1179 int used_regs_mask = 0; 1180 1181 /* There can be at most 3 int regs used as inputs in an insn, and we have 1182 7 to choose from (RAX ... RDI, sans RSP). 1183 This allows us to take a conservative approach and keep things simple. 1184 E.g. By avoiding RAX, we don't have to specifically watch for opcodes 1185 that implicitly specify RAX. */ 1186 1187 /* Avoid RAX. */ 1188 used_regs_mask |= 1 << EAX_REG_NUM; 1189 /* Similarily avoid RDX, implicit operand in divides. */ 1190 used_regs_mask |= 1 << EDX_REG_NUM; 1191 /* Avoid RSP. */ 1192 used_regs_mask |= 1 << ESP_REG_NUM; 1193 1194 /* If the opcode is one byte long and there's no ModRM byte, 1195 assume the opcode specifies a register. */ 1196 if (details->opcode_len == 1 && details->modrm_offset == -1) 1197 used_regs_mask |= 1 << (details->raw_insn[details->opcode_offset] & 7); 1198 1199 /* Mark used regs in the modrm/sib bytes. */ 1200 if (details->modrm_offset != -1) 1201 { 1202 int modrm = details->raw_insn[details->modrm_offset]; 1203 int mod = MODRM_MOD_FIELD (modrm); 1204 int reg = MODRM_REG_FIELD (modrm); 1205 int rm = MODRM_RM_FIELD (modrm); 1206 int have_sib = mod != 3 && rm == 4; 1207 1208 /* Assume the reg field of the modrm byte specifies a register. */ 1209 used_regs_mask |= 1 << reg; 1210 1211 if (have_sib) 1212 { 1213 int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]); 1214 int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]); 1215 used_regs_mask |= 1 << base; 1216 used_regs_mask |= 1 << idx; 1217 } 1218 else 1219 { 1220 used_regs_mask |= 1 << rm; 1221 } 1222 } 1223 1224 gdb_assert (used_regs_mask < 256); 1225 gdb_assert (used_regs_mask != 255); 1226 1227 /* Finally, find a free reg. */ 1228 { 1229 int i; 1230 1231 for (i = 0; i < 8; ++i) 1232 { 1233 if (! (used_regs_mask & (1 << i))) 1234 return i; 1235 } 1236 1237 /* We shouldn't get here. */ 1238 internal_error (__FILE__, __LINE__, _("unable to find free reg")); 1239 } 1240 } 1241 1242 /* Extract the details of INSN that we need. */ 1243 1244 static void 1245 amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details) 1246 { 1247 gdb_byte *start = insn; 1248 int need_modrm; 1249 1250 details->raw_insn = insn; 1251 1252 details->opcode_len = -1; 1253 details->rex_offset = -1; 1254 details->opcode_offset = -1; 1255 details->modrm_offset = -1; 1256 1257 /* Skip legacy instruction prefixes. */ 1258 insn = amd64_skip_prefixes (insn); 1259 1260 /* Skip REX instruction prefix. */ 1261 if (rex_prefix_p (*insn)) 1262 { 1263 details->rex_offset = insn - start; 1264 ++insn; 1265 } 1266 1267 details->opcode_offset = insn - start; 1268 1269 if (*insn == TWO_BYTE_OPCODE_ESCAPE) 1270 { 1271 /* Two or three-byte opcode. */ 1272 ++insn; 1273 need_modrm = twobyte_has_modrm[*insn]; 1274 1275 /* Check for three-byte opcode. */ 1276 switch (*insn) 1277 { 1278 case 0x24: 1279 case 0x25: 1280 case 0x38: 1281 case 0x3a: 1282 case 0x7a: 1283 case 0x7b: 1284 ++insn; 1285 details->opcode_len = 3; 1286 break; 1287 default: 1288 details->opcode_len = 2; 1289 break; 1290 } 1291 } 1292 else 1293 { 1294 /* One-byte opcode. */ 1295 need_modrm = onebyte_has_modrm[*insn]; 1296 details->opcode_len = 1; 1297 } 1298 1299 if (need_modrm) 1300 { 1301 ++insn; 1302 details->modrm_offset = insn - start; 1303 } 1304 } 1305 1306 /* Update %rip-relative addressing in INSN. 1307 1308 %rip-relative addressing only uses a 32-bit displacement. 1309 32 bits is not enough to be guaranteed to cover the distance between where 1310 the real instruction is and where its copy is. 1311 Convert the insn to use base+disp addressing. 1312 We set base = pc + insn_length so we can leave disp unchanged. */ 1313 1314 static void 1315 fixup_riprel (struct gdbarch *gdbarch, struct displaced_step_closure *dsc, 1316 CORE_ADDR from, CORE_ADDR to, struct regcache *regs) 1317 { 1318 const struct amd64_insn *insn_details = &dsc->insn_details; 1319 int modrm_offset = insn_details->modrm_offset; 1320 gdb_byte *insn = insn_details->raw_insn + modrm_offset; 1321 CORE_ADDR rip_base; 1322 int insn_length; 1323 int arch_tmp_regno, tmp_regno; 1324 ULONGEST orig_value; 1325 1326 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */ 1327 ++insn; 1328 1329 /* Compute the rip-relative address. */ 1330 insn_length = gdb_buffered_insn_length (gdbarch, dsc->insn_buf, 1331 dsc->max_len, from); 1332 rip_base = from + insn_length; 1333 1334 /* We need a register to hold the address. 1335 Pick one not used in the insn. 1336 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */ 1337 arch_tmp_regno = amd64_get_unused_input_int_reg (insn_details); 1338 tmp_regno = amd64_arch_reg_to_regnum (arch_tmp_regno); 1339 1340 /* REX.B should be unset as we were using rip-relative addressing, 1341 but ensure it's unset anyway, tmp_regno is not r8-r15. */ 1342 if (insn_details->rex_offset != -1) 1343 dsc->insn_buf[insn_details->rex_offset] &= ~REX_B; 1344 1345 regcache_cooked_read_unsigned (regs, tmp_regno, &orig_value); 1346 dsc->tmp_regno = tmp_regno; 1347 dsc->tmp_save = orig_value; 1348 dsc->tmp_used = 1; 1349 1350 /* Convert the ModRM field to be base+disp. */ 1351 dsc->insn_buf[modrm_offset] &= ~0xc7; 1352 dsc->insn_buf[modrm_offset] |= 0x80 + arch_tmp_regno; 1353 1354 regcache_cooked_write_unsigned (regs, tmp_regno, rip_base); 1355 1356 if (debug_displaced) 1357 fprintf_unfiltered (gdb_stdlog, "displaced: %%rip-relative addressing used.\n" 1358 "displaced: using temp reg %d, old value %s, new value %s\n", 1359 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save), 1360 paddress (gdbarch, rip_base)); 1361 } 1362 1363 static void 1364 fixup_displaced_copy (struct gdbarch *gdbarch, 1365 struct displaced_step_closure *dsc, 1366 CORE_ADDR from, CORE_ADDR to, struct regcache *regs) 1367 { 1368 const struct amd64_insn *details = &dsc->insn_details; 1369 1370 if (details->modrm_offset != -1) 1371 { 1372 gdb_byte modrm = details->raw_insn[details->modrm_offset]; 1373 1374 if ((modrm & 0xc7) == 0x05) 1375 { 1376 /* The insn uses rip-relative addressing. 1377 Deal with it. */ 1378 fixup_riprel (gdbarch, dsc, from, to, regs); 1379 } 1380 } 1381 } 1382 1383 struct displaced_step_closure * 1384 amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, 1385 CORE_ADDR from, CORE_ADDR to, 1386 struct regcache *regs) 1387 { 1388 int len = gdbarch_max_insn_length (gdbarch); 1389 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to 1390 continually watch for running off the end of the buffer. */ 1391 int fixup_sentinel_space = len; 1392 struct displaced_step_closure *dsc 1393 = ((struct displaced_step_closure *) 1394 xmalloc (sizeof (*dsc) + len + fixup_sentinel_space)); 1395 gdb_byte *buf = &dsc->insn_buf[0]; 1396 struct amd64_insn *details = &dsc->insn_details; 1397 1398 dsc->tmp_used = 0; 1399 dsc->max_len = len + fixup_sentinel_space; 1400 1401 read_memory (from, buf, len); 1402 1403 /* Set up the sentinel space so we don't have to worry about running 1404 off the end of the buffer. An excessive number of leading prefixes 1405 could otherwise cause this. */ 1406 memset (buf + len, 0, fixup_sentinel_space); 1407 1408 amd64_get_insn_details (buf, details); 1409 1410 /* GDB may get control back after the insn after the syscall. 1411 Presumably this is a kernel bug. 1412 If this is a syscall, make sure there's a nop afterwards. */ 1413 { 1414 int syscall_length; 1415 1416 if (amd64_syscall_p (details, &syscall_length)) 1417 buf[details->opcode_offset + syscall_length] = NOP_OPCODE; 1418 } 1419 1420 /* Modify the insn to cope with the address where it will be executed from. 1421 In particular, handle any rip-relative addressing. */ 1422 fixup_displaced_copy (gdbarch, dsc, from, to, regs); 1423 1424 write_memory (to, buf, len); 1425 1426 if (debug_displaced) 1427 { 1428 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", 1429 paddress (gdbarch, from), paddress (gdbarch, to)); 1430 displaced_step_dump_bytes (gdb_stdlog, buf, len); 1431 } 1432 1433 return dsc; 1434 } 1435 1436 static int 1437 amd64_absolute_jmp_p (const struct amd64_insn *details) 1438 { 1439 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1440 1441 if (insn[0] == 0xff) 1442 { 1443 /* jump near, absolute indirect (/4) */ 1444 if ((insn[1] & 0x38) == 0x20) 1445 return 1; 1446 1447 /* jump far, absolute indirect (/5) */ 1448 if ((insn[1] & 0x38) == 0x28) 1449 return 1; 1450 } 1451 1452 return 0; 1453 } 1454 1455 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */ 1456 1457 static int 1458 amd64_jmp_p (const struct amd64_insn *details) 1459 { 1460 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1461 1462 /* jump short, relative. */ 1463 if (insn[0] == 0xeb) 1464 return 1; 1465 1466 /* jump near, relative. */ 1467 if (insn[0] == 0xe9) 1468 return 1; 1469 1470 return amd64_absolute_jmp_p (details); 1471 } 1472 1473 static int 1474 amd64_absolute_call_p (const struct amd64_insn *details) 1475 { 1476 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1477 1478 if (insn[0] == 0xff) 1479 { 1480 /* Call near, absolute indirect (/2) */ 1481 if ((insn[1] & 0x38) == 0x10) 1482 return 1; 1483 1484 /* Call far, absolute indirect (/3) */ 1485 if ((insn[1] & 0x38) == 0x18) 1486 return 1; 1487 } 1488 1489 return 0; 1490 } 1491 1492 static int 1493 amd64_ret_p (const struct amd64_insn *details) 1494 { 1495 /* NOTE: gcc can emit "repz ; ret". */ 1496 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1497 1498 switch (insn[0]) 1499 { 1500 case 0xc2: /* ret near, pop N bytes */ 1501 case 0xc3: /* ret near */ 1502 case 0xca: /* ret far, pop N bytes */ 1503 case 0xcb: /* ret far */ 1504 case 0xcf: /* iret */ 1505 return 1; 1506 1507 default: 1508 return 0; 1509 } 1510 } 1511 1512 static int 1513 amd64_call_p (const struct amd64_insn *details) 1514 { 1515 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1516 1517 if (amd64_absolute_call_p (details)) 1518 return 1; 1519 1520 /* call near, relative */ 1521 if (insn[0] == 0xe8) 1522 return 1; 1523 1524 return 0; 1525 } 1526 1527 /* Return non-zero if INSN is a system call, and set *LENGTHP to its 1528 length in bytes. Otherwise, return zero. */ 1529 1530 static int 1531 amd64_syscall_p (const struct amd64_insn *details, int *lengthp) 1532 { 1533 const gdb_byte *insn = &details->raw_insn[details->opcode_offset]; 1534 1535 if (insn[0] == 0x0f && insn[1] == 0x05) 1536 { 1537 *lengthp = 2; 1538 return 1; 1539 } 1540 1541 return 0; 1542 } 1543 1544 /* Classify the instruction at ADDR using PRED. 1545 Throw an error if the memory can't be read. */ 1546 1547 static int 1548 amd64_classify_insn_at (struct gdbarch *gdbarch, CORE_ADDR addr, 1549 int (*pred) (const struct amd64_insn *)) 1550 { 1551 struct amd64_insn details; 1552 gdb_byte *buf; 1553 int len, classification; 1554 1555 len = gdbarch_max_insn_length (gdbarch); 1556 buf = (gdb_byte *) alloca (len); 1557 1558 read_code (addr, buf, len); 1559 amd64_get_insn_details (buf, &details); 1560 1561 classification = pred (&details); 1562 1563 return classification; 1564 } 1565 1566 /* The gdbarch insn_is_call method. */ 1567 1568 static int 1569 amd64_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) 1570 { 1571 return amd64_classify_insn_at (gdbarch, addr, amd64_call_p); 1572 } 1573 1574 /* The gdbarch insn_is_ret method. */ 1575 1576 static int 1577 amd64_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) 1578 { 1579 return amd64_classify_insn_at (gdbarch, addr, amd64_ret_p); 1580 } 1581 1582 /* The gdbarch insn_is_jump method. */ 1583 1584 static int 1585 amd64_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) 1586 { 1587 return amd64_classify_insn_at (gdbarch, addr, amd64_jmp_p); 1588 } 1589 1590 /* Fix up the state of registers and memory after having single-stepped 1591 a displaced instruction. */ 1592 1593 void 1594 amd64_displaced_step_fixup (struct gdbarch *gdbarch, 1595 struct displaced_step_closure *dsc, 1596 CORE_ADDR from, CORE_ADDR to, 1597 struct regcache *regs) 1598 { 1599 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1600 /* The offset we applied to the instruction's address. */ 1601 ULONGEST insn_offset = to - from; 1602 gdb_byte *insn = dsc->insn_buf; 1603 const struct amd64_insn *insn_details = &dsc->insn_details; 1604 1605 if (debug_displaced) 1606 fprintf_unfiltered (gdb_stdlog, 1607 "displaced: fixup (%s, %s), " 1608 "insn = 0x%02x 0x%02x ...\n", 1609 paddress (gdbarch, from), paddress (gdbarch, to), 1610 insn[0], insn[1]); 1611 1612 /* If we used a tmp reg, restore it. */ 1613 1614 if (dsc->tmp_used) 1615 { 1616 if (debug_displaced) 1617 fprintf_unfiltered (gdb_stdlog, "displaced: restoring reg %d to %s\n", 1618 dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save)); 1619 regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save); 1620 } 1621 1622 /* The list of issues to contend with here is taken from 1623 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28. 1624 Yay for Free Software! */ 1625 1626 /* Relocate the %rip back to the program's instruction stream, 1627 if necessary. */ 1628 1629 /* Except in the case of absolute or indirect jump or call 1630 instructions, or a return instruction, the new rip is relative to 1631 the displaced instruction; make it relative to the original insn. 1632 Well, signal handler returns don't need relocation either, but we use the 1633 value of %rip to recognize those; see below. */ 1634 if (! amd64_absolute_jmp_p (insn_details) 1635 && ! amd64_absolute_call_p (insn_details) 1636 && ! amd64_ret_p (insn_details)) 1637 { 1638 ULONGEST orig_rip; 1639 int insn_len; 1640 1641 regcache_cooked_read_unsigned (regs, AMD64_RIP_REGNUM, &orig_rip); 1642 1643 /* A signal trampoline system call changes the %rip, resuming 1644 execution of the main program after the signal handler has 1645 returned. That makes them like 'return' instructions; we 1646 shouldn't relocate %rip. 1647 1648 But most system calls don't, and we do need to relocate %rip. 1649 1650 Our heuristic for distinguishing these cases: if stepping 1651 over the system call instruction left control directly after 1652 the instruction, the we relocate --- control almost certainly 1653 doesn't belong in the displaced copy. Otherwise, we assume 1654 the instruction has put control where it belongs, and leave 1655 it unrelocated. Goodness help us if there are PC-relative 1656 system calls. */ 1657 if (amd64_syscall_p (insn_details, &insn_len) 1658 && orig_rip != to + insn_len 1659 /* GDB can get control back after the insn after the syscall. 1660 Presumably this is a kernel bug. 1661 Fixup ensures its a nop, we add one to the length for it. */ 1662 && orig_rip != to + insn_len + 1) 1663 { 1664 if (debug_displaced) 1665 fprintf_unfiltered (gdb_stdlog, 1666 "displaced: syscall changed %%rip; " 1667 "not relocating\n"); 1668 } 1669 else 1670 { 1671 ULONGEST rip = orig_rip - insn_offset; 1672 1673 /* If we just stepped over a breakpoint insn, we don't backup 1674 the pc on purpose; this is to match behaviour without 1675 stepping. */ 1676 1677 regcache_cooked_write_unsigned (regs, AMD64_RIP_REGNUM, rip); 1678 1679 if (debug_displaced) 1680 fprintf_unfiltered (gdb_stdlog, 1681 "displaced: " 1682 "relocated %%rip from %s to %s\n", 1683 paddress (gdbarch, orig_rip), 1684 paddress (gdbarch, rip)); 1685 } 1686 } 1687 1688 /* If the instruction was PUSHFL, then the TF bit will be set in the 1689 pushed value, and should be cleared. We'll leave this for later, 1690 since GDB already messes up the TF flag when stepping over a 1691 pushfl. */ 1692 1693 /* If the instruction was a call, the return address now atop the 1694 stack is the address following the copied instruction. We need 1695 to make it the address following the original instruction. */ 1696 if (amd64_call_p (insn_details)) 1697 { 1698 ULONGEST rsp; 1699 ULONGEST retaddr; 1700 const ULONGEST retaddr_len = 8; 1701 1702 regcache_cooked_read_unsigned (regs, AMD64_RSP_REGNUM, &rsp); 1703 retaddr = read_memory_unsigned_integer (rsp, retaddr_len, byte_order); 1704 retaddr = (retaddr - insn_offset) & 0xffffffffffffffffULL; 1705 write_memory_unsigned_integer (rsp, retaddr_len, byte_order, retaddr); 1706 1707 if (debug_displaced) 1708 fprintf_unfiltered (gdb_stdlog, 1709 "displaced: relocated return addr at %s " 1710 "to %s\n", 1711 paddress (gdbarch, rsp), 1712 paddress (gdbarch, retaddr)); 1713 } 1714 } 1715 1716 /* If the instruction INSN uses RIP-relative addressing, return the 1717 offset into the raw INSN where the displacement to be adjusted is 1718 found. Returns 0 if the instruction doesn't use RIP-relative 1719 addressing. */ 1720 1721 static int 1722 rip_relative_offset (struct amd64_insn *insn) 1723 { 1724 if (insn->modrm_offset != -1) 1725 { 1726 gdb_byte modrm = insn->raw_insn[insn->modrm_offset]; 1727 1728 if ((modrm & 0xc7) == 0x05) 1729 { 1730 /* The displacement is found right after the ModRM byte. */ 1731 return insn->modrm_offset + 1; 1732 } 1733 } 1734 1735 return 0; 1736 } 1737 1738 static void 1739 append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) 1740 { 1741 target_write_memory (*to, buf, len); 1742 *to += len; 1743 } 1744 1745 static void 1746 amd64_relocate_instruction (struct gdbarch *gdbarch, 1747 CORE_ADDR *to, CORE_ADDR oldloc) 1748 { 1749 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1750 int len = gdbarch_max_insn_length (gdbarch); 1751 /* Extra space for sentinels. */ 1752 int fixup_sentinel_space = len; 1753 gdb_byte *buf = (gdb_byte *) xmalloc (len + fixup_sentinel_space); 1754 struct amd64_insn insn_details; 1755 int offset = 0; 1756 LONGEST rel32, newrel; 1757 gdb_byte *insn; 1758 int insn_length; 1759 1760 read_memory (oldloc, buf, len); 1761 1762 /* Set up the sentinel space so we don't have to worry about running 1763 off the end of the buffer. An excessive number of leading prefixes 1764 could otherwise cause this. */ 1765 memset (buf + len, 0, fixup_sentinel_space); 1766 1767 insn = buf; 1768 amd64_get_insn_details (insn, &insn_details); 1769 1770 insn_length = gdb_buffered_insn_length (gdbarch, insn, len, oldloc); 1771 1772 /* Skip legacy instruction prefixes. */ 1773 insn = amd64_skip_prefixes (insn); 1774 1775 /* Adjust calls with 32-bit relative addresses as push/jump, with 1776 the address pushed being the location where the original call in 1777 the user program would return to. */ 1778 if (insn[0] == 0xe8) 1779 { 1780 gdb_byte push_buf[32]; 1781 CORE_ADDR ret_addr; 1782 int i = 0; 1783 1784 /* Where "ret" in the original code will return to. */ 1785 ret_addr = oldloc + insn_length; 1786 1787 /* If pushing an address higher than or equal to 0x80000000, 1788 avoid 'pushq', as that sign extends its 32-bit operand, which 1789 would be incorrect. */ 1790 if (ret_addr <= 0x7fffffff) 1791 { 1792 push_buf[0] = 0x68; /* pushq $... */ 1793 store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); 1794 i = 5; 1795 } 1796 else 1797 { 1798 push_buf[i++] = 0x48; /* sub $0x8,%rsp */ 1799 push_buf[i++] = 0x83; 1800 push_buf[i++] = 0xec; 1801 push_buf[i++] = 0x08; 1802 1803 push_buf[i++] = 0xc7; /* movl $imm,(%rsp) */ 1804 push_buf[i++] = 0x04; 1805 push_buf[i++] = 0x24; 1806 store_unsigned_integer (&push_buf[i], 4, byte_order, 1807 ret_addr & 0xffffffff); 1808 i += 4; 1809 1810 push_buf[i++] = 0xc7; /* movl $imm,4(%rsp) */ 1811 push_buf[i++] = 0x44; 1812 push_buf[i++] = 0x24; 1813 push_buf[i++] = 0x04; 1814 store_unsigned_integer (&push_buf[i], 4, byte_order, 1815 ret_addr >> 32); 1816 i += 4; 1817 } 1818 gdb_assert (i <= sizeof (push_buf)); 1819 /* Push the push. */ 1820 append_insns (to, i, push_buf); 1821 1822 /* Convert the relative call to a relative jump. */ 1823 insn[0] = 0xe9; 1824 1825 /* Adjust the destination offset. */ 1826 rel32 = extract_signed_integer (insn + 1, 4, byte_order); 1827 newrel = (oldloc - *to) + rel32; 1828 store_signed_integer (insn + 1, 4, byte_order, newrel); 1829 1830 if (debug_displaced) 1831 fprintf_unfiltered (gdb_stdlog, 1832 "Adjusted insn rel32=%s at %s to" 1833 " rel32=%s at %s\n", 1834 hex_string (rel32), paddress (gdbarch, oldloc), 1835 hex_string (newrel), paddress (gdbarch, *to)); 1836 1837 /* Write the adjusted jump into its displaced location. */ 1838 append_insns (to, 5, insn); 1839 return; 1840 } 1841 1842 offset = rip_relative_offset (&insn_details); 1843 if (!offset) 1844 { 1845 /* Adjust jumps with 32-bit relative addresses. Calls are 1846 already handled above. */ 1847 if (insn[0] == 0xe9) 1848 offset = 1; 1849 /* Adjust conditional jumps. */ 1850 else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) 1851 offset = 2; 1852 } 1853 1854 if (offset) 1855 { 1856 rel32 = extract_signed_integer (insn + offset, 4, byte_order); 1857 newrel = (oldloc - *to) + rel32; 1858 store_signed_integer (insn + offset, 4, byte_order, newrel); 1859 if (debug_displaced) 1860 fprintf_unfiltered (gdb_stdlog, 1861 "Adjusted insn rel32=%s at %s to" 1862 " rel32=%s at %s\n", 1863 hex_string (rel32), paddress (gdbarch, oldloc), 1864 hex_string (newrel), paddress (gdbarch, *to)); 1865 } 1866 1867 /* Write the adjusted instruction into its displaced location. */ 1868 append_insns (to, insn_length, buf); 1869 } 1870 1871 1872 /* The maximum number of saved registers. This should include %rip. */ 1873 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS 1874 1875 struct amd64_frame_cache 1876 { 1877 /* Base address. */ 1878 CORE_ADDR base; 1879 int base_p; 1880 CORE_ADDR sp_offset; 1881 CORE_ADDR pc; 1882 1883 /* Saved registers. */ 1884 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]; 1885 CORE_ADDR saved_sp; 1886 int saved_sp_reg; 1887 1888 /* Do we have a frame? */ 1889 int frameless_p; 1890 }; 1891 1892 /* Initialize a frame cache. */ 1893 1894 static void 1895 amd64_init_frame_cache (struct amd64_frame_cache *cache) 1896 { 1897 int i; 1898 1899 /* Base address. */ 1900 cache->base = 0; 1901 cache->base_p = 0; 1902 cache->sp_offset = -8; 1903 cache->pc = 0; 1904 1905 /* Saved registers. We initialize these to -1 since zero is a valid 1906 offset (that's where %rbp is supposed to be stored). 1907 The values start out as being offsets, and are later converted to 1908 addresses (at which point -1 is interpreted as an address, still meaning 1909 "invalid"). */ 1910 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) 1911 cache->saved_regs[i] = -1; 1912 cache->saved_sp = 0; 1913 cache->saved_sp_reg = -1; 1914 1915 /* Frameless until proven otherwise. */ 1916 cache->frameless_p = 1; 1917 } 1918 1919 /* Allocate and initialize a frame cache. */ 1920 1921 static struct amd64_frame_cache * 1922 amd64_alloc_frame_cache (void) 1923 { 1924 struct amd64_frame_cache *cache; 1925 1926 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache); 1927 amd64_init_frame_cache (cache); 1928 return cache; 1929 } 1930 1931 /* GCC 4.4 and later, can put code in the prologue to realign the 1932 stack pointer. Check whether PC points to such code, and update 1933 CACHE accordingly. Return the first instruction after the code 1934 sequence or CURRENT_PC, whichever is smaller. If we don't 1935 recognize the code, return PC. */ 1936 1937 static CORE_ADDR 1938 amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, 1939 struct amd64_frame_cache *cache) 1940 { 1941 /* There are 2 code sequences to re-align stack before the frame 1942 gets set up: 1943 1944 1. Use a caller-saved saved register: 1945 1946 leaq 8(%rsp), %reg 1947 andq $-XXX, %rsp 1948 pushq -8(%reg) 1949 1950 2. Use a callee-saved saved register: 1951 1952 pushq %reg 1953 leaq 16(%rsp), %reg 1954 andq $-XXX, %rsp 1955 pushq -8(%reg) 1956 1957 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: 1958 1959 0x48 0x83 0xe4 0xf0 andq $-16, %rsp 1960 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp 1961 */ 1962 1963 gdb_byte buf[18]; 1964 int reg, r; 1965 int offset, offset_and; 1966 1967 if (target_read_code (pc, buf, sizeof buf)) 1968 return pc; 1969 1970 /* Check caller-saved saved register. The first instruction has 1971 to be "leaq 8(%rsp), %reg". */ 1972 if ((buf[0] & 0xfb) == 0x48 1973 && buf[1] == 0x8d 1974 && buf[3] == 0x24 1975 && buf[4] == 0x8) 1976 { 1977 /* MOD must be binary 10 and R/M must be binary 100. */ 1978 if ((buf[2] & 0xc7) != 0x44) 1979 return pc; 1980 1981 /* REG has register number. */ 1982 reg = (buf[2] >> 3) & 7; 1983 1984 /* Check the REX.R bit. */ 1985 if (buf[0] == 0x4c) 1986 reg += 8; 1987 1988 offset = 5; 1989 } 1990 else 1991 { 1992 /* Check callee-saved saved register. The first instruction 1993 has to be "pushq %reg". */ 1994 reg = 0; 1995 if ((buf[0] & 0xf8) == 0x50) 1996 offset = 0; 1997 else if ((buf[0] & 0xf6) == 0x40 1998 && (buf[1] & 0xf8) == 0x50) 1999 { 2000 /* Check the REX.B bit. */ 2001 if ((buf[0] & 1) != 0) 2002 reg = 8; 2003 2004 offset = 1; 2005 } 2006 else 2007 return pc; 2008 2009 /* Get register. */ 2010 reg += buf[offset] & 0x7; 2011 2012 offset++; 2013 2014 /* The next instruction has to be "leaq 16(%rsp), %reg". */ 2015 if ((buf[offset] & 0xfb) != 0x48 2016 || buf[offset + 1] != 0x8d 2017 || buf[offset + 3] != 0x24 2018 || buf[offset + 4] != 0x10) 2019 return pc; 2020 2021 /* MOD must be binary 10 and R/M must be binary 100. */ 2022 if ((buf[offset + 2] & 0xc7) != 0x44) 2023 return pc; 2024 2025 /* REG has register number. */ 2026 r = (buf[offset + 2] >> 3) & 7; 2027 2028 /* Check the REX.R bit. */ 2029 if (buf[offset] == 0x4c) 2030 r += 8; 2031 2032 /* Registers in pushq and leaq have to be the same. */ 2033 if (reg != r) 2034 return pc; 2035 2036 offset += 5; 2037 } 2038 2039 /* Rigister can't be %rsp nor %rbp. */ 2040 if (reg == 4 || reg == 5) 2041 return pc; 2042 2043 /* The next instruction has to be "andq $-XXX, %rsp". */ 2044 if (buf[offset] != 0x48 2045 || buf[offset + 2] != 0xe4 2046 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) 2047 return pc; 2048 2049 offset_and = offset; 2050 offset += buf[offset + 1] == 0x81 ? 7 : 4; 2051 2052 /* The next instruction has to be "pushq -8(%reg)". */ 2053 r = 0; 2054 if (buf[offset] == 0xff) 2055 offset++; 2056 else if ((buf[offset] & 0xf6) == 0x40 2057 && buf[offset + 1] == 0xff) 2058 { 2059 /* Check the REX.B bit. */ 2060 if ((buf[offset] & 0x1) != 0) 2061 r = 8; 2062 offset += 2; 2063 } 2064 else 2065 return pc; 2066 2067 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary 2068 01. */ 2069 if (buf[offset + 1] != 0xf8 2070 || (buf[offset] & 0xf8) != 0x70) 2071 return pc; 2072 2073 /* R/M has register. */ 2074 r += buf[offset] & 7; 2075 2076 /* Registers in leaq and pushq have to be the same. */ 2077 if (reg != r) 2078 return pc; 2079 2080 if (current_pc > pc + offset_and) 2081 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); 2082 2083 return std::min (pc + offset + 2, current_pc); 2084 } 2085 2086 /* Similar to amd64_analyze_stack_align for x32. */ 2087 2088 static CORE_ADDR 2089 amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, 2090 struct amd64_frame_cache *cache) 2091 { 2092 /* There are 2 code sequences to re-align stack before the frame 2093 gets set up: 2094 2095 1. Use a caller-saved saved register: 2096 2097 leaq 8(%rsp), %reg 2098 andq $-XXX, %rsp 2099 pushq -8(%reg) 2100 2101 or 2102 2103 [addr32] leal 8(%rsp), %reg 2104 andl $-XXX, %esp 2105 [addr32] pushq -8(%reg) 2106 2107 2. Use a callee-saved saved register: 2108 2109 pushq %reg 2110 leaq 16(%rsp), %reg 2111 andq $-XXX, %rsp 2112 pushq -8(%reg) 2113 2114 or 2115 2116 pushq %reg 2117 [addr32] leal 16(%rsp), %reg 2118 andl $-XXX, %esp 2119 [addr32] pushq -8(%reg) 2120 2121 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes: 2122 2123 0x48 0x83 0xe4 0xf0 andq $-16, %rsp 2124 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp 2125 2126 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: 2127 2128 0x83 0xe4 0xf0 andl $-16, %esp 2129 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp 2130 */ 2131 2132 gdb_byte buf[19]; 2133 int reg, r; 2134 int offset, offset_and; 2135 2136 if (target_read_memory (pc, buf, sizeof buf)) 2137 return pc; 2138 2139 /* Skip optional addr32 prefix. */ 2140 offset = buf[0] == 0x67 ? 1 : 0; 2141 2142 /* Check caller-saved saved register. The first instruction has 2143 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */ 2144 if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40) 2145 && buf[offset + 1] == 0x8d 2146 && buf[offset + 3] == 0x24 2147 && buf[offset + 4] == 0x8) 2148 { 2149 /* MOD must be binary 10 and R/M must be binary 100. */ 2150 if ((buf[offset + 2] & 0xc7) != 0x44) 2151 return pc; 2152 2153 /* REG has register number. */ 2154 reg = (buf[offset + 2] >> 3) & 7; 2155 2156 /* Check the REX.R bit. */ 2157 if ((buf[offset] & 0x4) != 0) 2158 reg += 8; 2159 2160 offset += 5; 2161 } 2162 else 2163 { 2164 /* Check callee-saved saved register. The first instruction 2165 has to be "pushq %reg". */ 2166 reg = 0; 2167 if ((buf[offset] & 0xf6) == 0x40 2168 && (buf[offset + 1] & 0xf8) == 0x50) 2169 { 2170 /* Check the REX.B bit. */ 2171 if ((buf[offset] & 1) != 0) 2172 reg = 8; 2173 2174 offset += 1; 2175 } 2176 else if ((buf[offset] & 0xf8) != 0x50) 2177 return pc; 2178 2179 /* Get register. */ 2180 reg += buf[offset] & 0x7; 2181 2182 offset++; 2183 2184 /* Skip optional addr32 prefix. */ 2185 if (buf[offset] == 0x67) 2186 offset++; 2187 2188 /* The next instruction has to be "leaq 16(%rsp), %reg" or 2189 "leal 16(%rsp), %reg". */ 2190 if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40) 2191 || buf[offset + 1] != 0x8d 2192 || buf[offset + 3] != 0x24 2193 || buf[offset + 4] != 0x10) 2194 return pc; 2195 2196 /* MOD must be binary 10 and R/M must be binary 100. */ 2197 if ((buf[offset + 2] & 0xc7) != 0x44) 2198 return pc; 2199 2200 /* REG has register number. */ 2201 r = (buf[offset + 2] >> 3) & 7; 2202 2203 /* Check the REX.R bit. */ 2204 if ((buf[offset] & 0x4) != 0) 2205 r += 8; 2206 2207 /* Registers in pushq and leaq have to be the same. */ 2208 if (reg != r) 2209 return pc; 2210 2211 offset += 5; 2212 } 2213 2214 /* Rigister can't be %rsp nor %rbp. */ 2215 if (reg == 4 || reg == 5) 2216 return pc; 2217 2218 /* The next instruction may be "andq $-XXX, %rsp" or 2219 "andl $-XXX, %esp". */ 2220 if (buf[offset] != 0x48) 2221 offset--; 2222 2223 if (buf[offset + 2] != 0xe4 2224 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) 2225 return pc; 2226 2227 offset_and = offset; 2228 offset += buf[offset + 1] == 0x81 ? 7 : 4; 2229 2230 /* Skip optional addr32 prefix. */ 2231 if (buf[offset] == 0x67) 2232 offset++; 2233 2234 /* The next instruction has to be "pushq -8(%reg)". */ 2235 r = 0; 2236 if (buf[offset] == 0xff) 2237 offset++; 2238 else if ((buf[offset] & 0xf6) == 0x40 2239 && buf[offset + 1] == 0xff) 2240 { 2241 /* Check the REX.B bit. */ 2242 if ((buf[offset] & 0x1) != 0) 2243 r = 8; 2244 offset += 2; 2245 } 2246 else 2247 return pc; 2248 2249 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary 2250 01. */ 2251 if (buf[offset + 1] != 0xf8 2252 || (buf[offset] & 0xf8) != 0x70) 2253 return pc; 2254 2255 /* R/M has register. */ 2256 r += buf[offset] & 7; 2257 2258 /* Registers in leaq and pushq have to be the same. */ 2259 if (reg != r) 2260 return pc; 2261 2262 if (current_pc > pc + offset_and) 2263 cache->saved_sp_reg = amd64_arch_reg_to_regnum (reg); 2264 2265 return std::min (pc + offset + 2, current_pc); 2266 } 2267 2268 /* Do a limited analysis of the prologue at PC and update CACHE 2269 accordingly. Bail out early if CURRENT_PC is reached. Return the 2270 address where the analysis stopped. 2271 2272 We will handle only functions beginning with: 2273 2274 pushq %rbp 0x55 2275 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec) 2276 2277 or (for the X32 ABI): 2278 2279 pushq %rbp 0x55 2280 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec) 2281 2282 Any function that doesn't start with one of these sequences will be 2283 assumed to have no prologue and thus no valid frame pointer in 2284 %rbp. */ 2285 2286 static CORE_ADDR 2287 amd64_analyze_prologue (struct gdbarch *gdbarch, 2288 CORE_ADDR pc, CORE_ADDR current_pc, 2289 struct amd64_frame_cache *cache) 2290 { 2291 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2292 /* There are two variations of movq %rsp, %rbp. */ 2293 static const gdb_byte mov_rsp_rbp_1[3] = { 0x48, 0x89, 0xe5 }; 2294 static const gdb_byte mov_rsp_rbp_2[3] = { 0x48, 0x8b, 0xec }; 2295 /* Ditto for movl %esp, %ebp. */ 2296 static const gdb_byte mov_esp_ebp_1[2] = { 0x89, 0xe5 }; 2297 static const gdb_byte mov_esp_ebp_2[2] = { 0x8b, 0xec }; 2298 2299 gdb_byte buf[3]; 2300 gdb_byte op; 2301 2302 if (current_pc <= pc) 2303 return current_pc; 2304 2305 if (gdbarch_ptr_bit (gdbarch) == 32) 2306 pc = amd64_x32_analyze_stack_align (pc, current_pc, cache); 2307 else 2308 pc = amd64_analyze_stack_align (pc, current_pc, cache); 2309 2310 op = read_code_unsigned_integer (pc, 1, byte_order); 2311 2312 if (op == 0x55) /* pushq %rbp */ 2313 { 2314 /* Take into account that we've executed the `pushq %rbp' that 2315 starts this instruction sequence. */ 2316 cache->saved_regs[AMD64_RBP_REGNUM] = 0; 2317 cache->sp_offset += 8; 2318 2319 /* If that's all, return now. */ 2320 if (current_pc <= pc + 1) 2321 return current_pc; 2322 2323 read_code (pc + 1, buf, 3); 2324 2325 /* Check for `movq %rsp, %rbp'. */ 2326 if (memcmp (buf, mov_rsp_rbp_1, 3) == 0 2327 || memcmp (buf, mov_rsp_rbp_2, 3) == 0) 2328 { 2329 /* OK, we actually have a frame. */ 2330 cache->frameless_p = 0; 2331 return pc + 4; 2332 } 2333 2334 /* For X32, also check for `movq %esp, %ebp'. */ 2335 if (gdbarch_ptr_bit (gdbarch) == 32) 2336 { 2337 if (memcmp (buf, mov_esp_ebp_1, 2) == 0 2338 || memcmp (buf, mov_esp_ebp_2, 2) == 0) 2339 { 2340 /* OK, we actually have a frame. */ 2341 cache->frameless_p = 0; 2342 return pc + 3; 2343 } 2344 } 2345 2346 return pc + 1; 2347 } 2348 2349 return pc; 2350 } 2351 2352 /* Work around false termination of prologue - GCC PR debug/48827. 2353 2354 START_PC is the first instruction of a function, PC is its minimal already 2355 determined advanced address. Function returns PC if it has nothing to do. 2356 2357 84 c0 test %al,%al 2358 74 23 je after 2359 <-- here is 0 lines advance - the false prologue end marker. 2360 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp) 2361 0f 29 4d 80 movaps %xmm1,-0x80(%rbp) 2362 0f 29 55 90 movaps %xmm2,-0x70(%rbp) 2363 0f 29 5d a0 movaps %xmm3,-0x60(%rbp) 2364 0f 29 65 b0 movaps %xmm4,-0x50(%rbp) 2365 0f 29 6d c0 movaps %xmm5,-0x40(%rbp) 2366 0f 29 75 d0 movaps %xmm6,-0x30(%rbp) 2367 0f 29 7d e0 movaps %xmm7,-0x20(%rbp) 2368 after: */ 2369 2370 static CORE_ADDR 2371 amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc) 2372 { 2373 struct symtab_and_line start_pc_sal, next_sal; 2374 gdb_byte buf[4 + 8 * 7]; 2375 int offset, xmmreg; 2376 2377 if (pc == start_pc) 2378 return pc; 2379 2380 start_pc_sal = find_pc_sect_line (start_pc, NULL, 0); 2381 if (start_pc_sal.symtab == NULL 2382 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER 2383 (SYMTAB_COMPUNIT (start_pc_sal.symtab))) < 6 2384 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end) 2385 return pc; 2386 2387 next_sal = find_pc_sect_line (start_pc_sal.end, NULL, 0); 2388 if (next_sal.line != start_pc_sal.line) 2389 return pc; 2390 2391 /* START_PC can be from overlayed memory, ignored here. */ 2392 if (target_read_code (next_sal.pc - 4, buf, sizeof (buf)) != 0) 2393 return pc; 2394 2395 /* test %al,%al */ 2396 if (buf[0] != 0x84 || buf[1] != 0xc0) 2397 return pc; 2398 /* je AFTER */ 2399 if (buf[2] != 0x74) 2400 return pc; 2401 2402 offset = 4; 2403 for (xmmreg = 0; xmmreg < 8; xmmreg++) 2404 { 2405 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */ 2406 if (buf[offset] != 0x0f || buf[offset + 1] != 0x29 2407 || (buf[offset + 2] & 0x3f) != (xmmreg << 3 | 0x5)) 2408 return pc; 2409 2410 /* 0b01?????? */ 2411 if ((buf[offset + 2] & 0xc0) == 0x40) 2412 { 2413 /* 8-bit displacement. */ 2414 offset += 4; 2415 } 2416 /* 0b10?????? */ 2417 else if ((buf[offset + 2] & 0xc0) == 0x80) 2418 { 2419 /* 32-bit displacement. */ 2420 offset += 7; 2421 } 2422 else 2423 return pc; 2424 } 2425 2426 /* je AFTER */ 2427 if (offset - 4 != buf[3]) 2428 return pc; 2429 2430 return next_sal.end; 2431 } 2432 2433 /* Return PC of first real instruction. */ 2434 2435 static CORE_ADDR 2436 amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 2437 { 2438 struct amd64_frame_cache cache; 2439 CORE_ADDR pc; 2440 CORE_ADDR func_addr; 2441 2442 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) 2443 { 2444 CORE_ADDR post_prologue_pc 2445 = skip_prologue_using_sal (gdbarch, func_addr); 2446 struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); 2447 2448 /* Clang always emits a line note before the prologue and another 2449 one after. We trust clang to emit usable line notes. */ 2450 if (post_prologue_pc 2451 && (cust != NULL 2452 && COMPUNIT_PRODUCER (cust) != NULL 2453 && startswith (COMPUNIT_PRODUCER (cust), "clang "))) 2454 return std::max (start_pc, post_prologue_pc); 2455 } 2456 2457 amd64_init_frame_cache (&cache); 2458 pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL, 2459 &cache); 2460 if (cache.frameless_p) 2461 return start_pc; 2462 2463 return amd64_skip_xmm_prologue (pc, start_pc); 2464 } 2465 2466 2467 /* Normal frames. */ 2468 2469 static void 2470 amd64_frame_cache_1 (struct frame_info *this_frame, 2471 struct amd64_frame_cache *cache) 2472 { 2473 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2474 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2475 gdb_byte buf[8]; 2476 int i; 2477 2478 cache->pc = get_frame_func (this_frame); 2479 if (cache->pc != 0) 2480 amd64_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), 2481 cache); 2482 2483 if (cache->frameless_p) 2484 { 2485 /* We didn't find a valid frame. If we're at the start of a 2486 function, or somewhere half-way its prologue, the function's 2487 frame probably hasn't been fully setup yet. Try to 2488 reconstruct the base address for the stack frame by looking 2489 at the stack pointer. For truly "frameless" functions this 2490 might work too. */ 2491 2492 if (cache->saved_sp_reg != -1) 2493 { 2494 /* Stack pointer has been saved. */ 2495 get_frame_register (this_frame, cache->saved_sp_reg, buf); 2496 cache->saved_sp = extract_unsigned_integer (buf, 8, byte_order); 2497 2498 /* We're halfway aligning the stack. */ 2499 cache->base = ((cache->saved_sp - 8) & 0xfffffffffffffff0LL) - 8; 2500 cache->saved_regs[AMD64_RIP_REGNUM] = cache->saved_sp - 8; 2501 2502 /* This will be added back below. */ 2503 cache->saved_regs[AMD64_RIP_REGNUM] -= cache->base; 2504 } 2505 else 2506 { 2507 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); 2508 cache->base = extract_unsigned_integer (buf, 8, byte_order) 2509 + cache->sp_offset; 2510 } 2511 } 2512 else 2513 { 2514 get_frame_register (this_frame, AMD64_RBP_REGNUM, buf); 2515 cache->base = extract_unsigned_integer (buf, 8, byte_order); 2516 } 2517 2518 /* Now that we have the base address for the stack frame we can 2519 calculate the value of %rsp in the calling frame. */ 2520 cache->saved_sp = cache->base + 16; 2521 2522 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a 2523 frame we find it at the same offset from the reconstructed base 2524 address. If we're halfway aligning the stack, %rip is handled 2525 differently (see above). */ 2526 if (!cache->frameless_p || cache->saved_sp_reg == -1) 2527 cache->saved_regs[AMD64_RIP_REGNUM] = 8; 2528 2529 /* Adjust all the saved registers such that they contain addresses 2530 instead of offsets. */ 2531 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) 2532 if (cache->saved_regs[i] != -1) 2533 cache->saved_regs[i] += cache->base; 2534 2535 cache->base_p = 1; 2536 } 2537 2538 static struct amd64_frame_cache * 2539 amd64_frame_cache (struct frame_info *this_frame, void **this_cache) 2540 { 2541 struct amd64_frame_cache *cache; 2542 2543 if (*this_cache) 2544 return (struct amd64_frame_cache *) *this_cache; 2545 2546 cache = amd64_alloc_frame_cache (); 2547 *this_cache = cache; 2548 2549 TRY 2550 { 2551 amd64_frame_cache_1 (this_frame, cache); 2552 } 2553 CATCH (ex, RETURN_MASK_ERROR) 2554 { 2555 if (ex.error != NOT_AVAILABLE_ERROR) 2556 throw_exception (ex); 2557 } 2558 END_CATCH 2559 2560 return cache; 2561 } 2562 2563 static enum unwind_stop_reason 2564 amd64_frame_unwind_stop_reason (struct frame_info *this_frame, 2565 void **this_cache) 2566 { 2567 struct amd64_frame_cache *cache = 2568 amd64_frame_cache (this_frame, this_cache); 2569 2570 if (!cache->base_p) 2571 return UNWIND_UNAVAILABLE; 2572 2573 /* This marks the outermost frame. */ 2574 if (cache->base == 0) 2575 return UNWIND_OUTERMOST; 2576 2577 return UNWIND_NO_REASON; 2578 } 2579 2580 static void 2581 amd64_frame_this_id (struct frame_info *this_frame, void **this_cache, 2582 struct frame_id *this_id) 2583 { 2584 struct amd64_frame_cache *cache = 2585 amd64_frame_cache (this_frame, this_cache); 2586 2587 if (!cache->base_p) 2588 (*this_id) = frame_id_build_unavailable_stack (cache->pc); 2589 else if (cache->base == 0) 2590 { 2591 /* This marks the outermost frame. */ 2592 return; 2593 } 2594 else 2595 (*this_id) = frame_id_build (cache->base + 16, cache->pc); 2596 } 2597 2598 static struct value * 2599 amd64_frame_prev_register (struct frame_info *this_frame, void **this_cache, 2600 int regnum) 2601 { 2602 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2603 struct amd64_frame_cache *cache = 2604 amd64_frame_cache (this_frame, this_cache); 2605 2606 gdb_assert (regnum >= 0); 2607 2608 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) 2609 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); 2610 2611 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) 2612 return frame_unwind_got_memory (this_frame, regnum, 2613 cache->saved_regs[regnum]); 2614 2615 return frame_unwind_got_register (this_frame, regnum, regnum); 2616 } 2617 2618 static const struct frame_unwind amd64_frame_unwind = 2619 { 2620 NORMAL_FRAME, 2621 amd64_frame_unwind_stop_reason, 2622 amd64_frame_this_id, 2623 amd64_frame_prev_register, 2624 NULL, 2625 default_frame_sniffer 2626 }; 2627 2628 /* Generate a bytecode expression to get the value of the saved PC. */ 2629 2630 static void 2631 amd64_gen_return_address (struct gdbarch *gdbarch, 2632 struct agent_expr *ax, struct axs_value *value, 2633 CORE_ADDR scope) 2634 { 2635 /* The following sequence assumes the traditional use of the base 2636 register. */ 2637 ax_reg (ax, AMD64_RBP_REGNUM); 2638 ax_const_l (ax, 8); 2639 ax_simple (ax, aop_add); 2640 value->type = register_type (gdbarch, AMD64_RIP_REGNUM); 2641 value->kind = axs_lvalue_memory; 2642 } 2643 2644 2645 /* Signal trampolines. */ 2646 2647 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and 2648 64-bit variants. This would require using identical frame caches 2649 on both platforms. */ 2650 2651 static struct amd64_frame_cache * 2652 amd64_sigtramp_frame_cache (struct frame_info *this_frame, void **this_cache) 2653 { 2654 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2655 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2656 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2657 struct amd64_frame_cache *cache; 2658 CORE_ADDR addr; 2659 gdb_byte buf[8]; 2660 int i; 2661 2662 if (*this_cache) 2663 return (struct amd64_frame_cache *) *this_cache; 2664 2665 cache = amd64_alloc_frame_cache (); 2666 2667 TRY 2668 { 2669 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); 2670 cache->base = extract_unsigned_integer (buf, 8, byte_order) - 8; 2671 2672 addr = tdep->sigcontext_addr (this_frame); 2673 gdb_assert (tdep->sc_reg_offset); 2674 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS); 2675 for (i = 0; i < tdep->sc_num_regs; i++) 2676 if (tdep->sc_reg_offset[i] != -1) 2677 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; 2678 2679 cache->base_p = 1; 2680 } 2681 CATCH (ex, RETURN_MASK_ERROR) 2682 { 2683 if (ex.error != NOT_AVAILABLE_ERROR) 2684 throw_exception (ex); 2685 } 2686 END_CATCH 2687 2688 *this_cache = cache; 2689 return cache; 2690 } 2691 2692 static enum unwind_stop_reason 2693 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info *this_frame, 2694 void **this_cache) 2695 { 2696 struct amd64_frame_cache *cache = 2697 amd64_sigtramp_frame_cache (this_frame, this_cache); 2698 2699 if (!cache->base_p) 2700 return UNWIND_UNAVAILABLE; 2701 2702 return UNWIND_NO_REASON; 2703 } 2704 2705 static void 2706 amd64_sigtramp_frame_this_id (struct frame_info *this_frame, 2707 void **this_cache, struct frame_id *this_id) 2708 { 2709 struct amd64_frame_cache *cache = 2710 amd64_sigtramp_frame_cache (this_frame, this_cache); 2711 2712 if (!cache->base_p) 2713 (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); 2714 else if (cache->base == 0) 2715 { 2716 /* This marks the outermost frame. */ 2717 return; 2718 } 2719 else 2720 (*this_id) = frame_id_build (cache->base + 16, get_frame_pc (this_frame)); 2721 } 2722 2723 static struct value * 2724 amd64_sigtramp_frame_prev_register (struct frame_info *this_frame, 2725 void **this_cache, int regnum) 2726 { 2727 /* Make sure we've initialized the cache. */ 2728 amd64_sigtramp_frame_cache (this_frame, this_cache); 2729 2730 return amd64_frame_prev_register (this_frame, this_cache, regnum); 2731 } 2732 2733 static int 2734 amd64_sigtramp_frame_sniffer (const struct frame_unwind *self, 2735 struct frame_info *this_frame, 2736 void **this_cache) 2737 { 2738 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (this_frame)); 2739 2740 /* We shouldn't even bother if we don't have a sigcontext_addr 2741 handler. */ 2742 if (tdep->sigcontext_addr == NULL) 2743 return 0; 2744 2745 if (tdep->sigtramp_p != NULL) 2746 { 2747 if (tdep->sigtramp_p (this_frame)) 2748 return 1; 2749 } 2750 2751 if (tdep->sigtramp_start != 0) 2752 { 2753 CORE_ADDR pc = get_frame_pc (this_frame); 2754 2755 gdb_assert (tdep->sigtramp_end != 0); 2756 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) 2757 return 1; 2758 } 2759 2760 return 0; 2761 } 2762 2763 static const struct frame_unwind amd64_sigtramp_frame_unwind = 2764 { 2765 SIGTRAMP_FRAME, 2766 amd64_sigtramp_frame_unwind_stop_reason, 2767 amd64_sigtramp_frame_this_id, 2768 amd64_sigtramp_frame_prev_register, 2769 NULL, 2770 amd64_sigtramp_frame_sniffer 2771 }; 2772 2773 2774 static CORE_ADDR 2775 amd64_frame_base_address (struct frame_info *this_frame, void **this_cache) 2776 { 2777 struct amd64_frame_cache *cache = 2778 amd64_frame_cache (this_frame, this_cache); 2779 2780 return cache->base; 2781 } 2782 2783 static const struct frame_base amd64_frame_base = 2784 { 2785 &amd64_frame_unwind, 2786 amd64_frame_base_address, 2787 amd64_frame_base_address, 2788 amd64_frame_base_address 2789 }; 2790 2791 /* Normal frames, but in a function epilogue. */ 2792 2793 /* Implement the stack_frame_destroyed_p gdbarch method. 2794 2795 The epilogue is defined here as the 'ret' instruction, which will 2796 follow any instruction such as 'leave' or 'pop %ebp' that destroys 2797 the function's stack frame. */ 2798 2799 static int 2800 amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 2801 { 2802 gdb_byte insn; 2803 struct compunit_symtab *cust; 2804 2805 cust = find_pc_compunit_symtab (pc); 2806 if (cust != NULL && COMPUNIT_EPILOGUE_UNWIND_VALID (cust)) 2807 return 0; 2808 2809 if (target_read_memory (pc, &insn, 1)) 2810 return 0; /* Can't read memory at pc. */ 2811 2812 if (insn != 0xc3) /* 'ret' instruction. */ 2813 return 0; 2814 2815 return 1; 2816 } 2817 2818 static int 2819 amd64_epilogue_frame_sniffer (const struct frame_unwind *self, 2820 struct frame_info *this_frame, 2821 void **this_prologue_cache) 2822 { 2823 if (frame_relative_level (this_frame) == 0) 2824 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame), 2825 get_frame_pc (this_frame)); 2826 else 2827 return 0; 2828 } 2829 2830 static struct amd64_frame_cache * 2831 amd64_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) 2832 { 2833 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2834 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2835 struct amd64_frame_cache *cache; 2836 gdb_byte buf[8]; 2837 2838 if (*this_cache) 2839 return (struct amd64_frame_cache *) *this_cache; 2840 2841 cache = amd64_alloc_frame_cache (); 2842 *this_cache = cache; 2843 2844 TRY 2845 { 2846 /* Cache base will be %esp plus cache->sp_offset (-8). */ 2847 get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); 2848 cache->base = extract_unsigned_integer (buf, 8, 2849 byte_order) + cache->sp_offset; 2850 2851 /* Cache pc will be the frame func. */ 2852 cache->pc = get_frame_pc (this_frame); 2853 2854 /* The saved %esp will be at cache->base plus 16. */ 2855 cache->saved_sp = cache->base + 16; 2856 2857 /* The saved %eip will be at cache->base plus 8. */ 2858 cache->saved_regs[AMD64_RIP_REGNUM] = cache->base + 8; 2859 2860 cache->base_p = 1; 2861 } 2862 CATCH (ex, RETURN_MASK_ERROR) 2863 { 2864 if (ex.error != NOT_AVAILABLE_ERROR) 2865 throw_exception (ex); 2866 } 2867 END_CATCH 2868 2869 return cache; 2870 } 2871 2872 static enum unwind_stop_reason 2873 amd64_epilogue_frame_unwind_stop_reason (struct frame_info *this_frame, 2874 void **this_cache) 2875 { 2876 struct amd64_frame_cache *cache 2877 = amd64_epilogue_frame_cache (this_frame, this_cache); 2878 2879 if (!cache->base_p) 2880 return UNWIND_UNAVAILABLE; 2881 2882 return UNWIND_NO_REASON; 2883 } 2884 2885 static void 2886 amd64_epilogue_frame_this_id (struct frame_info *this_frame, 2887 void **this_cache, 2888 struct frame_id *this_id) 2889 { 2890 struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame, 2891 this_cache); 2892 2893 if (!cache->base_p) 2894 (*this_id) = frame_id_build_unavailable_stack (cache->pc); 2895 else 2896 (*this_id) = frame_id_build (cache->base + 8, cache->pc); 2897 } 2898 2899 static const struct frame_unwind amd64_epilogue_frame_unwind = 2900 { 2901 NORMAL_FRAME, 2902 amd64_epilogue_frame_unwind_stop_reason, 2903 amd64_epilogue_frame_this_id, 2904 amd64_frame_prev_register, 2905 NULL, 2906 amd64_epilogue_frame_sniffer 2907 }; 2908 2909 static struct frame_id 2910 amd64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 2911 { 2912 CORE_ADDR fp; 2913 2914 fp = get_frame_register_unsigned (this_frame, AMD64_RBP_REGNUM); 2915 2916 return frame_id_build (fp + 16, get_frame_pc (this_frame)); 2917 } 2918 2919 /* 16 byte align the SP per frame requirements. */ 2920 2921 static CORE_ADDR 2922 amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 2923 { 2924 return sp & -(CORE_ADDR)16; 2925 } 2926 2927 2928 /* Supply register REGNUM from the buffer specified by FPREGS and LEN 2929 in the floating-point register set REGSET to register cache 2930 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 2931 2932 static void 2933 amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, 2934 int regnum, const void *fpregs, size_t len) 2935 { 2936 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2937 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2938 2939 gdb_assert (len >= tdep->sizeof_fpregset); 2940 amd64_supply_fxsave (regcache, regnum, fpregs); 2941 } 2942 2943 /* Collect register REGNUM from the register cache REGCACHE and store 2944 it in the buffer specified by FPREGS and LEN as described by the 2945 floating-point register set REGSET. If REGNUM is -1, do this for 2946 all registers in REGSET. */ 2947 2948 static void 2949 amd64_collect_fpregset (const struct regset *regset, 2950 const struct regcache *regcache, 2951 int regnum, void *fpregs, size_t len) 2952 { 2953 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2954 const struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2955 2956 gdb_assert (len >= tdep->sizeof_fpregset); 2957 amd64_collect_fxsave (regcache, regnum, fpregs); 2958 } 2959 2960 const struct regset amd64_fpregset = 2961 { 2962 NULL, amd64_supply_fpregset, amd64_collect_fpregset 2963 }; 2964 2965 2966 /* Figure out where the longjmp will land. Slurp the jmp_buf out of 2967 %rdi. We expect its value to be a pointer to the jmp_buf structure 2968 from which we extract the address that we will land at. This 2969 address is copied into PC. This routine returns non-zero on 2970 success. */ 2971 2972 static int 2973 amd64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 2974 { 2975 gdb_byte buf[8]; 2976 CORE_ADDR jb_addr; 2977 struct gdbarch *gdbarch = get_frame_arch (frame); 2978 int jb_pc_offset = gdbarch_tdep (gdbarch)->jb_pc_offset; 2979 int len = TYPE_LENGTH (builtin_type (gdbarch)->builtin_func_ptr); 2980 2981 /* If JB_PC_OFFSET is -1, we have no way to find out where the 2982 longjmp will land. */ 2983 if (jb_pc_offset == -1) 2984 return 0; 2985 2986 get_frame_register (frame, AMD64_RDI_REGNUM, buf); 2987 jb_addr= extract_typed_address 2988 (buf, builtin_type (gdbarch)->builtin_data_ptr); 2989 if (target_read_memory (jb_addr + jb_pc_offset, buf, len)) 2990 return 0; 2991 2992 *pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); 2993 2994 return 1; 2995 } 2996 2997 static const int amd64_record_regmap[] = 2998 { 2999 AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM, 3000 AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, 3001 AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM, 3002 AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM, 3003 AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM, 3004 AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM 3005 }; 3006 3007 void 3008 amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 3009 { 3010 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3011 const struct target_desc *tdesc = info.target_desc; 3012 static const char *const stap_integer_prefixes[] = { "$", NULL }; 3013 static const char *const stap_register_prefixes[] = { "%", NULL }; 3014 static const char *const stap_register_indirection_prefixes[] = { "(", 3015 NULL }; 3016 static const char *const stap_register_indirection_suffixes[] = { ")", 3017 NULL }; 3018 3019 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its 3020 floating-point registers. */ 3021 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; 3022 tdep->fpregset = &amd64_fpregset; 3023 3024 if (! tdesc_has_registers (tdesc)) 3025 tdesc = tdesc_amd64; 3026 tdep->tdesc = tdesc; 3027 3028 tdep->num_core_regs = AMD64_NUM_GREGS + I387_NUM_REGS; 3029 tdep->register_names = amd64_register_names; 3030 3031 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512") != NULL) 3032 { 3033 tdep->zmmh_register_names = amd64_zmmh_names; 3034 tdep->k_register_names = amd64_k_names; 3035 tdep->xmm_avx512_register_names = amd64_xmm_avx512_names; 3036 tdep->ymm16h_register_names = amd64_ymmh_avx512_names; 3037 3038 tdep->num_zmm_regs = 32; 3039 tdep->num_xmm_avx512_regs = 16; 3040 tdep->num_ymm_avx512_regs = 16; 3041 3042 tdep->zmm0h_regnum = AMD64_ZMM0H_REGNUM; 3043 tdep->k0_regnum = AMD64_K0_REGNUM; 3044 tdep->xmm16_regnum = AMD64_XMM16_REGNUM; 3045 tdep->ymm16h_regnum = AMD64_YMM16H_REGNUM; 3046 } 3047 3048 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx") != NULL) 3049 { 3050 tdep->ymmh_register_names = amd64_ymmh_names; 3051 tdep->num_ymm_regs = 16; 3052 tdep->ymm0h_regnum = AMD64_YMM0H_REGNUM; 3053 } 3054 3055 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL) 3056 { 3057 tdep->mpx_register_names = amd64_mpx_names; 3058 tdep->bndcfgu_regnum = AMD64_BNDCFGU_REGNUM; 3059 tdep->bnd0r_regnum = AMD64_BND0R_REGNUM; 3060 } 3061 3062 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments") != NULL) 3063 { 3064 const struct tdesc_feature *feature = 3065 tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments"); 3066 struct tdesc_arch_data *tdesc_data_segments = 3067 (struct tdesc_arch_data *) info.tdep_info; 3068 3069 tdesc_numbered_register (feature, tdesc_data_segments, 3070 AMD64_FSBASE_REGNUM, "fs_base"); 3071 tdesc_numbered_register (feature, tdesc_data_segments, 3072 AMD64_GSBASE_REGNUM, "gs_base"); 3073 } 3074 3075 if (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys") != NULL) 3076 { 3077 tdep->pkeys_register_names = amd64_pkeys_names; 3078 tdep->pkru_regnum = AMD64_PKRU_REGNUM; 3079 tdep->num_pkeys_regs = 1; 3080 } 3081 3082 tdep->num_byte_regs = 20; 3083 tdep->num_word_regs = 16; 3084 tdep->num_dword_regs = 16; 3085 /* Avoid wiring in the MMX registers for now. */ 3086 tdep->num_mmx_regs = 0; 3087 3088 set_gdbarch_pseudo_register_read_value (gdbarch, 3089 amd64_pseudo_register_read_value); 3090 set_gdbarch_pseudo_register_write (gdbarch, 3091 amd64_pseudo_register_write); 3092 set_gdbarch_ax_pseudo_register_collect (gdbarch, 3093 amd64_ax_pseudo_register_collect); 3094 3095 set_tdesc_pseudo_register_name (gdbarch, amd64_pseudo_register_name); 3096 3097 /* AMD64 has an FPU and 16 SSE registers. */ 3098 tdep->st0_regnum = AMD64_ST0_REGNUM; 3099 tdep->num_xmm_regs = 16; 3100 3101 /* This is what all the fuss is about. */ 3102 set_gdbarch_long_bit (gdbarch, 64); 3103 set_gdbarch_long_long_bit (gdbarch, 64); 3104 set_gdbarch_ptr_bit (gdbarch, 64); 3105 3106 /* In contrast to the i386, on AMD64 a `long double' actually takes 3107 up 128 bits, even though it's still based on the i387 extended 3108 floating-point format which has only 80 significant bits. */ 3109 set_gdbarch_long_double_bit (gdbarch, 128); 3110 3111 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); 3112 3113 /* Register numbers of various important registers. */ 3114 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ 3115 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ 3116 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ 3117 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ 3118 3119 /* The "default" register numbering scheme for AMD64 is referred to 3120 as the "DWARF Register Number Mapping" in the System V psABI. 3121 The preferred debugging format for all known AMD64 targets is 3122 actually DWARF2, and GCC doesn't seem to support DWARF (that is 3123 DWARF-1), but we provide the same mapping just in case. This 3124 mapping is also used for stabs, which GCC does support. */ 3125 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 3126 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 3127 3128 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to 3129 be in use on any of the supported AMD64 targets. */ 3130 3131 /* Call dummy code. */ 3132 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call); 3133 set_gdbarch_frame_align (gdbarch, amd64_frame_align); 3134 set_gdbarch_frame_red_zone_size (gdbarch, 128); 3135 3136 set_gdbarch_convert_register_p (gdbarch, i387_convert_register_p); 3137 set_gdbarch_register_to_value (gdbarch, i387_register_to_value); 3138 set_gdbarch_value_to_register (gdbarch, i387_value_to_register); 3139 3140 set_gdbarch_return_value (gdbarch, amd64_return_value); 3141 3142 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue); 3143 3144 tdep->record_regmap = amd64_record_regmap; 3145 3146 set_gdbarch_dummy_id (gdbarch, amd64_dummy_id); 3147 3148 /* Hook the function epilogue frame unwinder. This unwinder is 3149 appended to the list first, so that it supercedes the other 3150 unwinders in function epilogues. */ 3151 frame_unwind_prepend_unwinder (gdbarch, &amd64_epilogue_frame_unwind); 3152 3153 /* Hook the prologue-based frame unwinders. */ 3154 frame_unwind_append_unwinder (gdbarch, &amd64_sigtramp_frame_unwind); 3155 frame_unwind_append_unwinder (gdbarch, &amd64_frame_unwind); 3156 frame_base_set_default (gdbarch, &amd64_frame_base); 3157 3158 set_gdbarch_get_longjmp_target (gdbarch, amd64_get_longjmp_target); 3159 3160 set_gdbarch_relocate_instruction (gdbarch, amd64_relocate_instruction); 3161 3162 set_gdbarch_gen_return_address (gdbarch, amd64_gen_return_address); 3163 3164 /* SystemTap variables and functions. */ 3165 set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); 3166 set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); 3167 set_gdbarch_stap_register_indirection_prefixes (gdbarch, 3168 stap_register_indirection_prefixes); 3169 set_gdbarch_stap_register_indirection_suffixes (gdbarch, 3170 stap_register_indirection_suffixes); 3171 set_gdbarch_stap_is_single_operand (gdbarch, 3172 i386_stap_is_single_operand); 3173 set_gdbarch_stap_parse_special_token (gdbarch, 3174 i386_stap_parse_special_token); 3175 set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call); 3176 set_gdbarch_insn_is_ret (gdbarch, amd64_insn_is_ret); 3177 set_gdbarch_insn_is_jump (gdbarch, amd64_insn_is_jump); 3178 } 3179 3180 3181 static struct type * 3182 amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) 3183 { 3184 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3185 3186 switch (regnum - tdep->eax_regnum) 3187 { 3188 case AMD64_RBP_REGNUM: /* %ebp */ 3189 case AMD64_RSP_REGNUM: /* %esp */ 3190 return builtin_type (gdbarch)->builtin_data_ptr; 3191 case AMD64_RIP_REGNUM: /* %eip */ 3192 return builtin_type (gdbarch)->builtin_func_ptr; 3193 } 3194 3195 return i386_pseudo_register_type (gdbarch, regnum); 3196 } 3197 3198 void 3199 amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 3200 { 3201 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3202 const struct target_desc *tdesc = info.target_desc; 3203 3204 amd64_init_abi (info, gdbarch); 3205 3206 if (! tdesc_has_registers (tdesc)) 3207 tdesc = tdesc_x32; 3208 tdep->tdesc = tdesc; 3209 3210 tdep->num_dword_regs = 17; 3211 set_tdesc_pseudo_register_type (gdbarch, amd64_x32_pseudo_register_type); 3212 3213 set_gdbarch_long_bit (gdbarch, 32); 3214 set_gdbarch_ptr_bit (gdbarch, 32); 3215 } 3216 3217 /* Return the target description for a specified XSAVE feature mask. */ 3218 3219 const struct target_desc * 3220 amd64_target_description (uint64_t xcr0) 3221 { 3222 switch (xcr0 & X86_XSTATE_ALL_MASK) 3223 { 3224 case X86_XSTATE_AVX_MPX_AVX512_PKU_MASK: 3225 return tdesc_amd64_avx_mpx_avx512_pku; 3226 case X86_XSTATE_AVX_AVX512_MASK: 3227 return tdesc_amd64_avx_avx512; 3228 case X86_XSTATE_MPX_MASK: 3229 return tdesc_amd64_mpx; 3230 case X86_XSTATE_AVX_MPX_MASK: 3231 return tdesc_amd64_avx_mpx; 3232 case X86_XSTATE_AVX_MASK: 3233 return tdesc_amd64_avx; 3234 default: 3235 return tdesc_amd64; 3236 } 3237 } 3238 3239 /* Provide a prototype to silence -Wmissing-prototypes. */ 3240 void _initialize_amd64_tdep (void); 3241 3242 void 3243 _initialize_amd64_tdep (void) 3244 { 3245 initialize_tdesc_amd64 (); 3246 initialize_tdesc_amd64_avx (); 3247 initialize_tdesc_amd64_mpx (); 3248 initialize_tdesc_amd64_avx_mpx (); 3249 initialize_tdesc_amd64_avx_avx512 (); 3250 initialize_tdesc_amd64_avx_mpx_avx512_pku (); 3251 3252 initialize_tdesc_x32 (); 3253 initialize_tdesc_x32_avx (); 3254 initialize_tdesc_x32_avx_avx512 (); 3255 } 3256 3257 3258 /* The 64-bit FXSAVE format differs from the 32-bit format in the 3259 sense that the instruction pointer and data pointer are simply 3260 64-bit offsets into the code segment and the data segment instead 3261 of a selector offset pair. The functions below store the upper 32 3262 bits of these pointers (instead of just the 16-bits of the segment 3263 selector). */ 3264 3265 /* Fill register REGNUM in REGCACHE with the appropriate 3266 floating-point or SSE register value from *FXSAVE. If REGNUM is 3267 -1, do this for all registers. This function masks off any of the 3268 reserved bits in *FXSAVE. */ 3269 3270 void 3271 amd64_supply_fxsave (struct regcache *regcache, int regnum, 3272 const void *fxsave) 3273 { 3274 struct gdbarch *gdbarch = get_regcache_arch (regcache); 3275 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3276 3277 i387_supply_fxsave (regcache, regnum, fxsave); 3278 3279 if (fxsave 3280 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) 3281 { 3282 const gdb_byte *regs = (const gdb_byte *) fxsave; 3283 3284 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 3285 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), regs + 12); 3286 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 3287 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); 3288 } 3289 } 3290 3291 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */ 3292 3293 void 3294 amd64_supply_xsave (struct regcache *regcache, int regnum, 3295 const void *xsave) 3296 { 3297 struct gdbarch *gdbarch = get_regcache_arch (regcache); 3298 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3299 3300 i387_supply_xsave (regcache, regnum, xsave); 3301 3302 if (xsave 3303 && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) 3304 { 3305 const gdb_byte *regs = (const gdb_byte *) xsave; 3306 3307 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 3308 regcache_raw_supply (regcache, I387_FISEG_REGNUM (tdep), 3309 regs + 12); 3310 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 3311 regcache_raw_supply (regcache, I387_FOSEG_REGNUM (tdep), 3312 regs + 20); 3313 } 3314 } 3315 3316 /* Fill register REGNUM (if it is a floating-point or SSE register) in 3317 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for 3318 all registers. This function doesn't touch any of the reserved 3319 bits in *FXSAVE. */ 3320 3321 void 3322 amd64_collect_fxsave (const struct regcache *regcache, int regnum, 3323 void *fxsave) 3324 { 3325 struct gdbarch *gdbarch = get_regcache_arch (regcache); 3326 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3327 gdb_byte *regs = (gdb_byte *) fxsave; 3328 3329 i387_collect_fxsave (regcache, regnum, fxsave); 3330 3331 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) 3332 { 3333 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 3334 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), regs + 12); 3335 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 3336 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), regs + 20); 3337 } 3338 } 3339 3340 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */ 3341 3342 void 3343 amd64_collect_xsave (const struct regcache *regcache, int regnum, 3344 void *xsave, int gcore) 3345 { 3346 struct gdbarch *gdbarch = get_regcache_arch (regcache); 3347 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3348 gdb_byte *regs = (gdb_byte *) xsave; 3349 3350 i387_collect_xsave (regcache, regnum, xsave, gcore); 3351 3352 if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) 3353 { 3354 if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) 3355 regcache_raw_collect (regcache, I387_FISEG_REGNUM (tdep), 3356 regs + 12); 3357 if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) 3358 regcache_raw_collect (regcache, I387_FOSEG_REGNUM (tdep), 3359 regs + 20); 3360 } 3361 } 3362