xref: /netbsd-src/external/gpl3/gcc.old/usr.bin/gcc/arch/armeb/arm-cpu-cdata.h (revision cef8759bd76c1b621f8eab8faa6f208faabc2e15)
1*cef8759bSmrg /* This file is automatically generated.  DO NOT EDIT! */
2*cef8759bSmrg /* Generated from: NetBSD: mknative-gcc,v 1.103 2019/10/24 03:19:14 christos Exp  */
3*cef8759bSmrg /* Generated from: NetBSD: mknative.common,v 1.16 2018/04/15 15:13:37 christos Exp  */
4*cef8759bSmrg 
5*cef8759bSmrg /* -*- buffer-read-only: t -*-
6*cef8759bSmrg    Generated automatically by parsecpu.awk from arm-cpus.in.
7*cef8759bSmrg    Do not edit.
8*cef8759bSmrg 
9*cef8759bSmrg    Copyright (C) 2011-2018 Free Software Foundation, Inc.
10*cef8759bSmrg 
11*cef8759bSmrg    This file is part of GCC.
12*cef8759bSmrg 
13*cef8759bSmrg    GCC is free software; you can redistribute it and/or modify
14*cef8759bSmrg    it under the terms of the GNU General Public License as
15*cef8759bSmrg    published by the Free Software Foundation; either version 3,
16*cef8759bSmrg    or (at your option) any later version.
17*cef8759bSmrg 
18*cef8759bSmrg    GCC is distributed in the hope that it will be useful,
19*cef8759bSmrg    but WITHOUT ANY WARRANTY; without even the implied warranty of
20*cef8759bSmrg    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21*cef8759bSmrg    GNU General Public License for more details.
22*cef8759bSmrg 
23*cef8759bSmrg    You should have received a copy of the GNU General Public
24*cef8759bSmrg    License along with GCC; see the file COPYING3.  If not see
25*cef8759bSmrg    <http://www.gnu.org/licenses/>.  */
26*cef8759bSmrg 
27*cef8759bSmrg static const cpu_arch_extension cpu_opttab_arm9e[] = {
28*cef8759bSmrg   {
29*cef8759bSmrg     "nofp", true, false,
30*cef8759bSmrg     {
31*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
32*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
33*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
34*cef8759bSmrg     }
35*cef8759bSmrg   },
36*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
37*cef8759bSmrg };
38*cef8759bSmrg 
39*cef8759bSmrg static const cpu_arch_extension cpu_opttab_arm946es[] = {
40*cef8759bSmrg   {
41*cef8759bSmrg     "nofp", true, false,
42*cef8759bSmrg     {
43*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
44*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
45*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
46*cef8759bSmrg     }
47*cef8759bSmrg   },
48*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
49*cef8759bSmrg };
50*cef8759bSmrg 
51*cef8759bSmrg static const cpu_arch_extension cpu_opttab_arm966es[] = {
52*cef8759bSmrg   {
53*cef8759bSmrg     "nofp", true, false,
54*cef8759bSmrg     {
55*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
56*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
57*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
58*cef8759bSmrg     }
59*cef8759bSmrg   },
60*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
61*cef8759bSmrg };
62*cef8759bSmrg 
63*cef8759bSmrg static const cpu_arch_extension cpu_opttab_arm968es[] = {
64*cef8759bSmrg   {
65*cef8759bSmrg     "nofp", true, false,
66*cef8759bSmrg     {
67*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
68*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
69*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
70*cef8759bSmrg     }
71*cef8759bSmrg   },
72*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
73*cef8759bSmrg };
74*cef8759bSmrg 
75*cef8759bSmrg static const cpu_arch_extension cpu_opttab_arm10e[] = {
76*cef8759bSmrg   {
77*cef8759bSmrg     "nofp", true, false,
78*cef8759bSmrg     {
79*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
80*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
81*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
82*cef8759bSmrg     }
83*cef8759bSmrg   },
84*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
85*cef8759bSmrg };
86*cef8759bSmrg 
87*cef8759bSmrg static const cpu_arch_extension cpu_opttab_arm1020e[] = {
88*cef8759bSmrg   {
89*cef8759bSmrg     "nofp", true, false,
90*cef8759bSmrg     {
91*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
92*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
93*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
94*cef8759bSmrg     }
95*cef8759bSmrg   },
96*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
97*cef8759bSmrg };
98*cef8759bSmrg 
99*cef8759bSmrg static const cpu_arch_extension cpu_opttab_arm1022e[] = {
100*cef8759bSmrg   {
101*cef8759bSmrg     "nofp", true, false,
102*cef8759bSmrg     {
103*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
104*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
105*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
106*cef8759bSmrg     }
107*cef8759bSmrg   },
108*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
109*cef8759bSmrg };
110*cef8759bSmrg 
111*cef8759bSmrg static const cpu_arch_extension cpu_opttab_arm926ejs[] = {
112*cef8759bSmrg   {
113*cef8759bSmrg     "nofp", true, false,
114*cef8759bSmrg     {
115*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
116*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
117*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
118*cef8759bSmrg     }
119*cef8759bSmrg   },
120*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
121*cef8759bSmrg };
122*cef8759bSmrg 
123*cef8759bSmrg static const cpu_arch_extension cpu_opttab_arm1026ejs[] = {
124*cef8759bSmrg   {
125*cef8759bSmrg     "nofp", true, false,
126*cef8759bSmrg     {
127*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
128*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
129*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
130*cef8759bSmrg     }
131*cef8759bSmrg   },
132*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
133*cef8759bSmrg };
134*cef8759bSmrg 
135*cef8759bSmrg static const cpu_arch_extension cpu_opttab_genericv7a[] = {
136*cef8759bSmrg   {
137*cef8759bSmrg     "mp", false, false,
138*cef8759bSmrg     {
139*cef8759bSmrg       isa_bit_mp, isa_nobit
140*cef8759bSmrg     }
141*cef8759bSmrg   },
142*cef8759bSmrg   {
143*cef8759bSmrg     "sec", false, false,
144*cef8759bSmrg     {
145*cef8759bSmrg       isa_bit_sec, isa_nobit
146*cef8759bSmrg     }
147*cef8759bSmrg   },
148*cef8759bSmrg   {
149*cef8759bSmrg     "vfpv3-d16", false, false,
150*cef8759bSmrg     {
151*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
152*cef8759bSmrg     }
153*cef8759bSmrg   },
154*cef8759bSmrg   {
155*cef8759bSmrg     "vfpv3", false, false,
156*cef8759bSmrg     {
157*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl,
158*cef8759bSmrg       isa_nobit
159*cef8759bSmrg     }
160*cef8759bSmrg   },
161*cef8759bSmrg   {
162*cef8759bSmrg     "vfpv3-d16-fp16", false, false,
163*cef8759bSmrg     {
164*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl,
165*cef8759bSmrg       isa_nobit
166*cef8759bSmrg     }
167*cef8759bSmrg   },
168*cef8759bSmrg   {
169*cef8759bSmrg     "vfpv3-fp16", false, false,
170*cef8759bSmrg     {
171*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv,
172*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
173*cef8759bSmrg     }
174*cef8759bSmrg   },
175*cef8759bSmrg   {
176*cef8759bSmrg     "vfpv4-d16", false, false,
177*cef8759bSmrg     {
178*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
179*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
180*cef8759bSmrg     }
181*cef8759bSmrg   },
182*cef8759bSmrg   {
183*cef8759bSmrg     "vfpv4", false, false,
184*cef8759bSmrg     {
185*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32,
186*cef8759bSmrg       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
187*cef8759bSmrg     }
188*cef8759bSmrg   },
189*cef8759bSmrg   {
190*cef8759bSmrg     "simd", false, false,
191*cef8759bSmrg     {
192*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
193*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
194*cef8759bSmrg     }
195*cef8759bSmrg   },
196*cef8759bSmrg   {
197*cef8759bSmrg     "neon-fp16", false, false,
198*cef8759bSmrg     {
199*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
200*cef8759bSmrg       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
201*cef8759bSmrg     }
202*cef8759bSmrg   },
203*cef8759bSmrg   {
204*cef8759bSmrg     "neon-vfpv4", false, false,
205*cef8759bSmrg     {
206*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
207*cef8759bSmrg       isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
208*cef8759bSmrg     }
209*cef8759bSmrg   },
210*cef8759bSmrg   {
211*cef8759bSmrg     "nosimd", true, false,
212*cef8759bSmrg     {
213*cef8759bSmrg       isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32,
214*cef8759bSmrg       isa_bit_crypto, isa_nobit
215*cef8759bSmrg     }
216*cef8759bSmrg   },
217*cef8759bSmrg   {
218*cef8759bSmrg     "nofp", true, false,
219*cef8759bSmrg     {
220*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
221*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
222*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
223*cef8759bSmrg     }
224*cef8759bSmrg   },
225*cef8759bSmrg   {
226*cef8759bSmrg     "neon", false, true,
227*cef8759bSmrg     {
228*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
229*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
230*cef8759bSmrg     }
231*cef8759bSmrg   },
232*cef8759bSmrg   {
233*cef8759bSmrg     "neon-vfpv3", false, true,
234*cef8759bSmrg     {
235*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
236*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
237*cef8759bSmrg     }
238*cef8759bSmrg   },
239*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
240*cef8759bSmrg };
241*cef8759bSmrg 
242*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa5[] = {
243*cef8759bSmrg   {
244*cef8759bSmrg     "nosimd", true, false,
245*cef8759bSmrg     {
246*cef8759bSmrg       isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32,
247*cef8759bSmrg       isa_bit_crypto, isa_nobit
248*cef8759bSmrg     }
249*cef8759bSmrg   },
250*cef8759bSmrg   {
251*cef8759bSmrg     "nofp", true, false,
252*cef8759bSmrg     {
253*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
254*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
255*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
256*cef8759bSmrg     }
257*cef8759bSmrg   },
258*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
259*cef8759bSmrg };
260*cef8759bSmrg 
261*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa7[] = {
262*cef8759bSmrg   {
263*cef8759bSmrg     "nosimd", true, false,
264*cef8759bSmrg     {
265*cef8759bSmrg       isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32,
266*cef8759bSmrg       isa_bit_crypto, isa_nobit
267*cef8759bSmrg     }
268*cef8759bSmrg   },
269*cef8759bSmrg   {
270*cef8759bSmrg     "nofp", true, false,
271*cef8759bSmrg     {
272*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
273*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
274*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
275*cef8759bSmrg     }
276*cef8759bSmrg   },
277*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
278*cef8759bSmrg };
279*cef8759bSmrg 
280*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa8[] = {
281*cef8759bSmrg   {
282*cef8759bSmrg     "nofp", true, false,
283*cef8759bSmrg     {
284*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
285*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
286*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
287*cef8759bSmrg     }
288*cef8759bSmrg   },
289*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
290*cef8759bSmrg };
291*cef8759bSmrg 
292*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa9[] = {
293*cef8759bSmrg   {
294*cef8759bSmrg     "nosimd", true, false,
295*cef8759bSmrg     {
296*cef8759bSmrg       isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32,
297*cef8759bSmrg       isa_bit_crypto, isa_nobit
298*cef8759bSmrg     }
299*cef8759bSmrg   },
300*cef8759bSmrg   {
301*cef8759bSmrg     "nofp", true, false,
302*cef8759bSmrg     {
303*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
304*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
305*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
306*cef8759bSmrg     }
307*cef8759bSmrg   },
308*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
309*cef8759bSmrg };
310*cef8759bSmrg 
311*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa12[] = {
312*cef8759bSmrg   {
313*cef8759bSmrg     "nofp", true, false,
314*cef8759bSmrg     {
315*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
316*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
317*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
318*cef8759bSmrg     }
319*cef8759bSmrg   },
320*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
321*cef8759bSmrg };
322*cef8759bSmrg 
323*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa15[] = {
324*cef8759bSmrg   {
325*cef8759bSmrg     "nofp", true, false,
326*cef8759bSmrg     {
327*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
328*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
329*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
330*cef8759bSmrg     }
331*cef8759bSmrg   },
332*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
333*cef8759bSmrg };
334*cef8759bSmrg 
335*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa17[] = {
336*cef8759bSmrg   {
337*cef8759bSmrg     "nofp", true, false,
338*cef8759bSmrg     {
339*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
340*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
341*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
342*cef8759bSmrg     }
343*cef8759bSmrg   },
344*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
345*cef8759bSmrg };
346*cef8759bSmrg 
347*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexr5[] = {
348*cef8759bSmrg   {
349*cef8759bSmrg     "nofp.dp", true, false,
350*cef8759bSmrg     {
351*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
352*cef8759bSmrg     }
353*cef8759bSmrg   },
354*cef8759bSmrg   {
355*cef8759bSmrg     "nofp", true, false,
356*cef8759bSmrg     {
357*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
358*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
359*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
360*cef8759bSmrg     }
361*cef8759bSmrg   },
362*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
363*cef8759bSmrg };
364*cef8759bSmrg 
365*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexr7[] = {
366*cef8759bSmrg   {
367*cef8759bSmrg     "nofp.dp", true, false,
368*cef8759bSmrg     {
369*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
370*cef8759bSmrg     }
371*cef8759bSmrg   },
372*cef8759bSmrg   {
373*cef8759bSmrg     "nofp", true, false,
374*cef8759bSmrg     {
375*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
376*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
377*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
378*cef8759bSmrg     }
379*cef8759bSmrg   },
380*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
381*cef8759bSmrg };
382*cef8759bSmrg 
383*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexr8[] = {
384*cef8759bSmrg   {
385*cef8759bSmrg     "nofp.dp", true, false,
386*cef8759bSmrg     {
387*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
388*cef8759bSmrg     }
389*cef8759bSmrg   },
390*cef8759bSmrg   {
391*cef8759bSmrg     "nofp", true, false,
392*cef8759bSmrg     {
393*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
394*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
395*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
396*cef8759bSmrg     }
397*cef8759bSmrg   },
398*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
399*cef8759bSmrg };
400*cef8759bSmrg 
401*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexm7[] = {
402*cef8759bSmrg   {
403*cef8759bSmrg     "nofp.dp", true, false,
404*cef8759bSmrg     {
405*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
406*cef8759bSmrg     }
407*cef8759bSmrg   },
408*cef8759bSmrg   {
409*cef8759bSmrg     "nofp", true, false,
410*cef8759bSmrg     {
411*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
412*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
413*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
414*cef8759bSmrg     }
415*cef8759bSmrg   },
416*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
417*cef8759bSmrg };
418*cef8759bSmrg 
419*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexm4[] = {
420*cef8759bSmrg   {
421*cef8759bSmrg     "nofp", true, false,
422*cef8759bSmrg     {
423*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
424*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
425*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
426*cef8759bSmrg     }
427*cef8759bSmrg   },
428*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
429*cef8759bSmrg };
430*cef8759bSmrg 
431*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = {
432*cef8759bSmrg   {
433*cef8759bSmrg     "nofp", true, false,
434*cef8759bSmrg     {
435*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
436*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
437*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
438*cef8759bSmrg     }
439*cef8759bSmrg   },
440*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
441*cef8759bSmrg };
442*cef8759bSmrg 
443*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = {
444*cef8759bSmrg   {
445*cef8759bSmrg     "nofp", true, false,
446*cef8759bSmrg     {
447*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
448*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
449*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
450*cef8759bSmrg     }
451*cef8759bSmrg   },
452*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
453*cef8759bSmrg };
454*cef8759bSmrg 
455*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa32[] = {
456*cef8759bSmrg   {
457*cef8759bSmrg     "crypto", false, false,
458*cef8759bSmrg     {
459*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
460*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
461*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
462*cef8759bSmrg     }
463*cef8759bSmrg   },
464*cef8759bSmrg   {
465*cef8759bSmrg     "nofp", true, false,
466*cef8759bSmrg     {
467*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
468*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
469*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
470*cef8759bSmrg     }
471*cef8759bSmrg   },
472*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
473*cef8759bSmrg };
474*cef8759bSmrg 
475*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa35[] = {
476*cef8759bSmrg   {
477*cef8759bSmrg     "crypto", false, false,
478*cef8759bSmrg     {
479*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
480*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
481*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
482*cef8759bSmrg     }
483*cef8759bSmrg   },
484*cef8759bSmrg   {
485*cef8759bSmrg     "nofp", true, false,
486*cef8759bSmrg     {
487*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
488*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
489*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
490*cef8759bSmrg     }
491*cef8759bSmrg   },
492*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
493*cef8759bSmrg };
494*cef8759bSmrg 
495*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa53[] = {
496*cef8759bSmrg   {
497*cef8759bSmrg     "crypto", false, false,
498*cef8759bSmrg     {
499*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
500*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
501*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
502*cef8759bSmrg     }
503*cef8759bSmrg   },
504*cef8759bSmrg   {
505*cef8759bSmrg     "nofp", true, false,
506*cef8759bSmrg     {
507*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
508*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
509*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
510*cef8759bSmrg     }
511*cef8759bSmrg   },
512*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
513*cef8759bSmrg };
514*cef8759bSmrg 
515*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa57[] = {
516*cef8759bSmrg   {
517*cef8759bSmrg     "crypto", false, false,
518*cef8759bSmrg     {
519*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
520*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
521*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
522*cef8759bSmrg     }
523*cef8759bSmrg   },
524*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
525*cef8759bSmrg };
526*cef8759bSmrg 
527*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa72[] = {
528*cef8759bSmrg   {
529*cef8759bSmrg     "crypto", false, false,
530*cef8759bSmrg     {
531*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
532*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
533*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
534*cef8759bSmrg     }
535*cef8759bSmrg   },
536*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
537*cef8759bSmrg };
538*cef8759bSmrg 
539*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa73[] = {
540*cef8759bSmrg   {
541*cef8759bSmrg     "crypto", false, false,
542*cef8759bSmrg     {
543*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
544*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
545*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
546*cef8759bSmrg     }
547*cef8759bSmrg   },
548*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
549*cef8759bSmrg };
550*cef8759bSmrg 
551*cef8759bSmrg static const cpu_arch_extension cpu_opttab_exynosm1[] = {
552*cef8759bSmrg   {
553*cef8759bSmrg     "crypto", false, false,
554*cef8759bSmrg     {
555*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
556*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
557*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
558*cef8759bSmrg     }
559*cef8759bSmrg   },
560*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
561*cef8759bSmrg };
562*cef8759bSmrg 
563*cef8759bSmrg static const cpu_arch_extension cpu_opttab_xgene1[] = {
564*cef8759bSmrg   {
565*cef8759bSmrg     "crypto", false, false,
566*cef8759bSmrg     {
567*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
568*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
569*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
570*cef8759bSmrg     }
571*cef8759bSmrg   },
572*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
573*cef8759bSmrg };
574*cef8759bSmrg 
575*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = {
576*cef8759bSmrg   {
577*cef8759bSmrg     "crypto", false, false,
578*cef8759bSmrg     {
579*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
580*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
581*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
582*cef8759bSmrg     }
583*cef8759bSmrg   },
584*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
585*cef8759bSmrg };
586*cef8759bSmrg 
587*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = {
588*cef8759bSmrg   {
589*cef8759bSmrg     "crypto", false, false,
590*cef8759bSmrg     {
591*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
592*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
593*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
594*cef8759bSmrg     }
595*cef8759bSmrg   },
596*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
597*cef8759bSmrg };
598*cef8759bSmrg 
599*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = {
600*cef8759bSmrg   {
601*cef8759bSmrg     "crypto", false, false,
602*cef8759bSmrg     {
603*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
604*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
605*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
606*cef8759bSmrg     }
607*cef8759bSmrg   },
608*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
609*cef8759bSmrg };
610*cef8759bSmrg 
611*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = {
612*cef8759bSmrg   {
613*cef8759bSmrg     "crypto", false, false,
614*cef8759bSmrg     {
615*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
616*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
617*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
618*cef8759bSmrg     }
619*cef8759bSmrg   },
620*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
621*cef8759bSmrg };
622*cef8759bSmrg 
623*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa55[] = {
624*cef8759bSmrg   {
625*cef8759bSmrg     "crypto", false, false,
626*cef8759bSmrg     {
627*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
628*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
629*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
630*cef8759bSmrg     }
631*cef8759bSmrg   },
632*cef8759bSmrg   {
633*cef8759bSmrg     "nofp", true, false,
634*cef8759bSmrg     {
635*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
636*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
637*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
638*cef8759bSmrg     }
639*cef8759bSmrg   },
640*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
641*cef8759bSmrg };
642*cef8759bSmrg 
643*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa75[] = {
644*cef8759bSmrg   {
645*cef8759bSmrg     "crypto", false, false,
646*cef8759bSmrg     {
647*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
648*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
649*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
650*cef8759bSmrg     }
651*cef8759bSmrg   },
652*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
653*cef8759bSmrg };
654*cef8759bSmrg 
655*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexa75cortexa55[] = {
656*cef8759bSmrg   {
657*cef8759bSmrg     "crypto", false, false,
658*cef8759bSmrg     {
659*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
660*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
661*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
662*cef8759bSmrg     }
663*cef8759bSmrg   },
664*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
665*cef8759bSmrg };
666*cef8759bSmrg 
667*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexm33[] = {
668*cef8759bSmrg   {
669*cef8759bSmrg     "nofp", true, false,
670*cef8759bSmrg     {
671*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
672*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
673*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
674*cef8759bSmrg     }
675*cef8759bSmrg   },
676*cef8759bSmrg   {
677*cef8759bSmrg     "nodsp", true, false,
678*cef8759bSmrg     {
679*cef8759bSmrg       isa_bit_armv7em, isa_nobit
680*cef8759bSmrg     }
681*cef8759bSmrg   },
682*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
683*cef8759bSmrg };
684*cef8759bSmrg 
685*cef8759bSmrg static const cpu_arch_extension cpu_opttab_cortexr52[] = {
686*cef8759bSmrg   {
687*cef8759bSmrg     "nofp.dp", true, false,
688*cef8759bSmrg     {
689*cef8759bSmrg       isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32,
690*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
691*cef8759bSmrg     }
692*cef8759bSmrg   },
693*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
694*cef8759bSmrg };
695*cef8759bSmrg 
696*cef8759bSmrg const cpu_option all_cores[] =
697*cef8759bSmrg {
698*cef8759bSmrg   {
699*cef8759bSmrg     {
700*cef8759bSmrg       "arm2",
701*cef8759bSmrg       NULL,
702*cef8759bSmrg       {
703*cef8759bSmrg         isa_bit_mode26, isa_bit_notm, isa_nobit
704*cef8759bSmrg       }
705*cef8759bSmrg     },
706*cef8759bSmrg     TARGET_ARCH_armv2
707*cef8759bSmrg   },
708*cef8759bSmrg   {
709*cef8759bSmrg     {
710*cef8759bSmrg       "arm250",
711*cef8759bSmrg       NULL,
712*cef8759bSmrg       {
713*cef8759bSmrg         isa_bit_mode26, isa_bit_notm, isa_nobit
714*cef8759bSmrg       }
715*cef8759bSmrg     },
716*cef8759bSmrg     TARGET_ARCH_armv2
717*cef8759bSmrg   },
718*cef8759bSmrg   {
719*cef8759bSmrg     {
720*cef8759bSmrg       "arm3",
721*cef8759bSmrg       NULL,
722*cef8759bSmrg       {
723*cef8759bSmrg         isa_bit_mode26, isa_bit_notm, isa_nobit
724*cef8759bSmrg       }
725*cef8759bSmrg     },
726*cef8759bSmrg     TARGET_ARCH_armv2
727*cef8759bSmrg   },
728*cef8759bSmrg   {
729*cef8759bSmrg     {
730*cef8759bSmrg       "arm6",
731*cef8759bSmrg       NULL,
732*cef8759bSmrg       {
733*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
734*cef8759bSmrg       }
735*cef8759bSmrg     },
736*cef8759bSmrg     TARGET_ARCH_armv3
737*cef8759bSmrg   },
738*cef8759bSmrg   {
739*cef8759bSmrg     {
740*cef8759bSmrg       "arm60",
741*cef8759bSmrg       NULL,
742*cef8759bSmrg       {
743*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
744*cef8759bSmrg       }
745*cef8759bSmrg     },
746*cef8759bSmrg     TARGET_ARCH_armv3
747*cef8759bSmrg   },
748*cef8759bSmrg   {
749*cef8759bSmrg     {
750*cef8759bSmrg       "arm600",
751*cef8759bSmrg       NULL,
752*cef8759bSmrg       {
753*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
754*cef8759bSmrg       }
755*cef8759bSmrg     },
756*cef8759bSmrg     TARGET_ARCH_armv3
757*cef8759bSmrg   },
758*cef8759bSmrg   {
759*cef8759bSmrg     {
760*cef8759bSmrg       "arm610",
761*cef8759bSmrg       NULL,
762*cef8759bSmrg       {
763*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
764*cef8759bSmrg       }
765*cef8759bSmrg     },
766*cef8759bSmrg     TARGET_ARCH_armv3
767*cef8759bSmrg   },
768*cef8759bSmrg   {
769*cef8759bSmrg     {
770*cef8759bSmrg       "arm620",
771*cef8759bSmrg       NULL,
772*cef8759bSmrg       {
773*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
774*cef8759bSmrg       }
775*cef8759bSmrg     },
776*cef8759bSmrg     TARGET_ARCH_armv3
777*cef8759bSmrg   },
778*cef8759bSmrg   {
779*cef8759bSmrg     {
780*cef8759bSmrg       "arm7",
781*cef8759bSmrg       NULL,
782*cef8759bSmrg       {
783*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
784*cef8759bSmrg       }
785*cef8759bSmrg     },
786*cef8759bSmrg     TARGET_ARCH_armv3
787*cef8759bSmrg   },
788*cef8759bSmrg   {
789*cef8759bSmrg     {
790*cef8759bSmrg       "arm7d",
791*cef8759bSmrg       NULL,
792*cef8759bSmrg       {
793*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
794*cef8759bSmrg       }
795*cef8759bSmrg     },
796*cef8759bSmrg     TARGET_ARCH_armv3
797*cef8759bSmrg   },
798*cef8759bSmrg   {
799*cef8759bSmrg     {
800*cef8759bSmrg       "arm7di",
801*cef8759bSmrg       NULL,
802*cef8759bSmrg       {
803*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
804*cef8759bSmrg       }
805*cef8759bSmrg     },
806*cef8759bSmrg     TARGET_ARCH_armv3
807*cef8759bSmrg   },
808*cef8759bSmrg   {
809*cef8759bSmrg     {
810*cef8759bSmrg       "arm70",
811*cef8759bSmrg       NULL,
812*cef8759bSmrg       {
813*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
814*cef8759bSmrg       }
815*cef8759bSmrg     },
816*cef8759bSmrg     TARGET_ARCH_armv3
817*cef8759bSmrg   },
818*cef8759bSmrg   {
819*cef8759bSmrg     {
820*cef8759bSmrg       "arm700",
821*cef8759bSmrg       NULL,
822*cef8759bSmrg       {
823*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
824*cef8759bSmrg       }
825*cef8759bSmrg     },
826*cef8759bSmrg     TARGET_ARCH_armv3
827*cef8759bSmrg   },
828*cef8759bSmrg   {
829*cef8759bSmrg     {
830*cef8759bSmrg       "arm700i",
831*cef8759bSmrg       NULL,
832*cef8759bSmrg       {
833*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
834*cef8759bSmrg       }
835*cef8759bSmrg     },
836*cef8759bSmrg     TARGET_ARCH_armv3
837*cef8759bSmrg   },
838*cef8759bSmrg   {
839*cef8759bSmrg     {
840*cef8759bSmrg       "arm710",
841*cef8759bSmrg       NULL,
842*cef8759bSmrg       {
843*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
844*cef8759bSmrg       }
845*cef8759bSmrg     },
846*cef8759bSmrg     TARGET_ARCH_armv3
847*cef8759bSmrg   },
848*cef8759bSmrg   {
849*cef8759bSmrg     {
850*cef8759bSmrg       "arm720",
851*cef8759bSmrg       NULL,
852*cef8759bSmrg       {
853*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
854*cef8759bSmrg       }
855*cef8759bSmrg     },
856*cef8759bSmrg     TARGET_ARCH_armv3
857*cef8759bSmrg   },
858*cef8759bSmrg   {
859*cef8759bSmrg     {
860*cef8759bSmrg       "arm710c",
861*cef8759bSmrg       NULL,
862*cef8759bSmrg       {
863*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
864*cef8759bSmrg       }
865*cef8759bSmrg     },
866*cef8759bSmrg     TARGET_ARCH_armv3
867*cef8759bSmrg   },
868*cef8759bSmrg   {
869*cef8759bSmrg     {
870*cef8759bSmrg       "arm7100",
871*cef8759bSmrg       NULL,
872*cef8759bSmrg       {
873*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
874*cef8759bSmrg       }
875*cef8759bSmrg     },
876*cef8759bSmrg     TARGET_ARCH_armv3
877*cef8759bSmrg   },
878*cef8759bSmrg   {
879*cef8759bSmrg     {
880*cef8759bSmrg       "arm7500",
881*cef8759bSmrg       NULL,
882*cef8759bSmrg       {
883*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
884*cef8759bSmrg       }
885*cef8759bSmrg     },
886*cef8759bSmrg     TARGET_ARCH_armv3
887*cef8759bSmrg   },
888*cef8759bSmrg   {
889*cef8759bSmrg     {
890*cef8759bSmrg       "arm7500fe",
891*cef8759bSmrg       NULL,
892*cef8759bSmrg       {
893*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
894*cef8759bSmrg       }
895*cef8759bSmrg     },
896*cef8759bSmrg     TARGET_ARCH_armv3
897*cef8759bSmrg   },
898*cef8759bSmrg   {
899*cef8759bSmrg     {
900*cef8759bSmrg       "arm7m",
901*cef8759bSmrg       NULL,
902*cef8759bSmrg       {
903*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_bit_armv3m,
904*cef8759bSmrg         isa_nobit
905*cef8759bSmrg       }
906*cef8759bSmrg     },
907*cef8759bSmrg     TARGET_ARCH_armv3m
908*cef8759bSmrg   },
909*cef8759bSmrg   {
910*cef8759bSmrg     {
911*cef8759bSmrg       "arm7dm",
912*cef8759bSmrg       NULL,
913*cef8759bSmrg       {
914*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_bit_armv3m,
915*cef8759bSmrg         isa_nobit
916*cef8759bSmrg       }
917*cef8759bSmrg     },
918*cef8759bSmrg     TARGET_ARCH_armv3m
919*cef8759bSmrg   },
920*cef8759bSmrg   {
921*cef8759bSmrg     {
922*cef8759bSmrg       "arm7dmi",
923*cef8759bSmrg       NULL,
924*cef8759bSmrg       {
925*cef8759bSmrg         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_bit_armv3m,
926*cef8759bSmrg         isa_nobit
927*cef8759bSmrg       }
928*cef8759bSmrg     },
929*cef8759bSmrg     TARGET_ARCH_armv3m
930*cef8759bSmrg   },
931*cef8759bSmrg   {
932*cef8759bSmrg     {
933*cef8759bSmrg       "arm8",
934*cef8759bSmrg       NULL,
935*cef8759bSmrg       {
936*cef8759bSmrg         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
937*cef8759bSmrg         isa_bit_armv3m, isa_nobit
938*cef8759bSmrg       }
939*cef8759bSmrg     },
940*cef8759bSmrg     TARGET_ARCH_armv4
941*cef8759bSmrg   },
942*cef8759bSmrg   {
943*cef8759bSmrg     {
944*cef8759bSmrg       "arm810",
945*cef8759bSmrg       NULL,
946*cef8759bSmrg       {
947*cef8759bSmrg         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
948*cef8759bSmrg         isa_bit_armv3m, isa_nobit
949*cef8759bSmrg       }
950*cef8759bSmrg     },
951*cef8759bSmrg     TARGET_ARCH_armv4
952*cef8759bSmrg   },
953*cef8759bSmrg   {
954*cef8759bSmrg     {
955*cef8759bSmrg       "strongarm",
956*cef8759bSmrg       NULL,
957*cef8759bSmrg       {
958*cef8759bSmrg         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
959*cef8759bSmrg         isa_bit_armv3m, isa_nobit
960*cef8759bSmrg       }
961*cef8759bSmrg     },
962*cef8759bSmrg     TARGET_ARCH_armv4
963*cef8759bSmrg   },
964*cef8759bSmrg   {
965*cef8759bSmrg     {
966*cef8759bSmrg       "strongarm110",
967*cef8759bSmrg       NULL,
968*cef8759bSmrg       {
969*cef8759bSmrg         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
970*cef8759bSmrg         isa_bit_armv3m, isa_nobit
971*cef8759bSmrg       }
972*cef8759bSmrg     },
973*cef8759bSmrg     TARGET_ARCH_armv4
974*cef8759bSmrg   },
975*cef8759bSmrg   {
976*cef8759bSmrg     {
977*cef8759bSmrg       "strongarm1100",
978*cef8759bSmrg       NULL,
979*cef8759bSmrg       {
980*cef8759bSmrg         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
981*cef8759bSmrg         isa_bit_armv3m, isa_nobit
982*cef8759bSmrg       }
983*cef8759bSmrg     },
984*cef8759bSmrg     TARGET_ARCH_armv4
985*cef8759bSmrg   },
986*cef8759bSmrg   {
987*cef8759bSmrg     {
988*cef8759bSmrg       "strongarm1110",
989*cef8759bSmrg       NULL,
990*cef8759bSmrg       {
991*cef8759bSmrg         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
992*cef8759bSmrg         isa_bit_armv3m, isa_nobit
993*cef8759bSmrg       }
994*cef8759bSmrg     },
995*cef8759bSmrg     TARGET_ARCH_armv4
996*cef8759bSmrg   },
997*cef8759bSmrg   {
998*cef8759bSmrg     {
999*cef8759bSmrg       "fa526",
1000*cef8759bSmrg       NULL,
1001*cef8759bSmrg       {
1002*cef8759bSmrg         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1003*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1004*cef8759bSmrg       }
1005*cef8759bSmrg     },
1006*cef8759bSmrg     TARGET_ARCH_armv4
1007*cef8759bSmrg   },
1008*cef8759bSmrg   {
1009*cef8759bSmrg     {
1010*cef8759bSmrg       "fa626",
1011*cef8759bSmrg       NULL,
1012*cef8759bSmrg       {
1013*cef8759bSmrg         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1014*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1015*cef8759bSmrg       }
1016*cef8759bSmrg     },
1017*cef8759bSmrg     TARGET_ARCH_armv4
1018*cef8759bSmrg   },
1019*cef8759bSmrg   {
1020*cef8759bSmrg     {
1021*cef8759bSmrg       "arm7tdmi",
1022*cef8759bSmrg       NULL,
1023*cef8759bSmrg       {
1024*cef8759bSmrg         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1025*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1026*cef8759bSmrg       }
1027*cef8759bSmrg     },
1028*cef8759bSmrg     TARGET_ARCH_armv4t
1029*cef8759bSmrg   },
1030*cef8759bSmrg   {
1031*cef8759bSmrg     {
1032*cef8759bSmrg       "arm7tdmi-s",
1033*cef8759bSmrg       NULL,
1034*cef8759bSmrg       {
1035*cef8759bSmrg         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1036*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1037*cef8759bSmrg       }
1038*cef8759bSmrg     },
1039*cef8759bSmrg     TARGET_ARCH_armv4t
1040*cef8759bSmrg   },
1041*cef8759bSmrg   {
1042*cef8759bSmrg     {
1043*cef8759bSmrg       "arm710t",
1044*cef8759bSmrg       NULL,
1045*cef8759bSmrg       {
1046*cef8759bSmrg         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1047*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1048*cef8759bSmrg       }
1049*cef8759bSmrg     },
1050*cef8759bSmrg     TARGET_ARCH_armv4t
1051*cef8759bSmrg   },
1052*cef8759bSmrg   {
1053*cef8759bSmrg     {
1054*cef8759bSmrg       "arm720t",
1055*cef8759bSmrg       NULL,
1056*cef8759bSmrg       {
1057*cef8759bSmrg         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1058*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1059*cef8759bSmrg       }
1060*cef8759bSmrg     },
1061*cef8759bSmrg     TARGET_ARCH_armv4t
1062*cef8759bSmrg   },
1063*cef8759bSmrg   {
1064*cef8759bSmrg     {
1065*cef8759bSmrg       "arm740t",
1066*cef8759bSmrg       NULL,
1067*cef8759bSmrg       {
1068*cef8759bSmrg         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1069*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1070*cef8759bSmrg       }
1071*cef8759bSmrg     },
1072*cef8759bSmrg     TARGET_ARCH_armv4t
1073*cef8759bSmrg   },
1074*cef8759bSmrg   {
1075*cef8759bSmrg     {
1076*cef8759bSmrg       "arm9",
1077*cef8759bSmrg       NULL,
1078*cef8759bSmrg       {
1079*cef8759bSmrg         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1080*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1081*cef8759bSmrg       }
1082*cef8759bSmrg     },
1083*cef8759bSmrg     TARGET_ARCH_armv4t
1084*cef8759bSmrg   },
1085*cef8759bSmrg   {
1086*cef8759bSmrg     {
1087*cef8759bSmrg       "arm9tdmi",
1088*cef8759bSmrg       NULL,
1089*cef8759bSmrg       {
1090*cef8759bSmrg         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1091*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1092*cef8759bSmrg       }
1093*cef8759bSmrg     },
1094*cef8759bSmrg     TARGET_ARCH_armv4t
1095*cef8759bSmrg   },
1096*cef8759bSmrg   {
1097*cef8759bSmrg     {
1098*cef8759bSmrg       "arm920",
1099*cef8759bSmrg       NULL,
1100*cef8759bSmrg       {
1101*cef8759bSmrg         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1102*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1103*cef8759bSmrg       }
1104*cef8759bSmrg     },
1105*cef8759bSmrg     TARGET_ARCH_armv4t
1106*cef8759bSmrg   },
1107*cef8759bSmrg   {
1108*cef8759bSmrg     {
1109*cef8759bSmrg       "arm920t",
1110*cef8759bSmrg       NULL,
1111*cef8759bSmrg       {
1112*cef8759bSmrg         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1113*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1114*cef8759bSmrg       }
1115*cef8759bSmrg     },
1116*cef8759bSmrg     TARGET_ARCH_armv4t
1117*cef8759bSmrg   },
1118*cef8759bSmrg   {
1119*cef8759bSmrg     {
1120*cef8759bSmrg       "arm922t",
1121*cef8759bSmrg       NULL,
1122*cef8759bSmrg       {
1123*cef8759bSmrg         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1124*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1125*cef8759bSmrg       }
1126*cef8759bSmrg     },
1127*cef8759bSmrg     TARGET_ARCH_armv4t
1128*cef8759bSmrg   },
1129*cef8759bSmrg   {
1130*cef8759bSmrg     {
1131*cef8759bSmrg       "arm940t",
1132*cef8759bSmrg       NULL,
1133*cef8759bSmrg       {
1134*cef8759bSmrg         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1135*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1136*cef8759bSmrg       }
1137*cef8759bSmrg     },
1138*cef8759bSmrg     TARGET_ARCH_armv4t
1139*cef8759bSmrg   },
1140*cef8759bSmrg   {
1141*cef8759bSmrg     {
1142*cef8759bSmrg       "ep9312",
1143*cef8759bSmrg       NULL,
1144*cef8759bSmrg       {
1145*cef8759bSmrg         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1146*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1147*cef8759bSmrg       }
1148*cef8759bSmrg     },
1149*cef8759bSmrg     TARGET_ARCH_armv4t
1150*cef8759bSmrg   },
1151*cef8759bSmrg   {
1152*cef8759bSmrg     {
1153*cef8759bSmrg       "arm10tdmi",
1154*cef8759bSmrg       NULL,
1155*cef8759bSmrg       {
1156*cef8759bSmrg         isa_bit_thumb, isa_bit_armv4, isa_bit_armv5, isa_bit_mode32,
1157*cef8759bSmrg         isa_bit_notm, isa_bit_armv3m, isa_nobit
1158*cef8759bSmrg       }
1159*cef8759bSmrg     },
1160*cef8759bSmrg     TARGET_ARCH_armv5t
1161*cef8759bSmrg   },
1162*cef8759bSmrg   {
1163*cef8759bSmrg     {
1164*cef8759bSmrg       "arm1020t",
1165*cef8759bSmrg       NULL,
1166*cef8759bSmrg       {
1167*cef8759bSmrg         isa_bit_thumb, isa_bit_armv4, isa_bit_armv5, isa_bit_mode32,
1168*cef8759bSmrg         isa_bit_notm, isa_bit_armv3m, isa_nobit
1169*cef8759bSmrg       }
1170*cef8759bSmrg     },
1171*cef8759bSmrg     TARGET_ARCH_armv5t
1172*cef8759bSmrg   },
1173*cef8759bSmrg   {
1174*cef8759bSmrg     {
1175*cef8759bSmrg       "arm9e",
1176*cef8759bSmrg       cpu_opttab_arm9e,
1177*cef8759bSmrg       {
1178*cef8759bSmrg         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1179*cef8759bSmrg         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1180*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1181*cef8759bSmrg       }
1182*cef8759bSmrg     },
1183*cef8759bSmrg     TARGET_ARCH_armv5te
1184*cef8759bSmrg   },
1185*cef8759bSmrg   {
1186*cef8759bSmrg     {
1187*cef8759bSmrg       "arm946e-s",
1188*cef8759bSmrg       cpu_opttab_arm946es,
1189*cef8759bSmrg       {
1190*cef8759bSmrg         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1191*cef8759bSmrg         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1192*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1193*cef8759bSmrg       }
1194*cef8759bSmrg     },
1195*cef8759bSmrg     TARGET_ARCH_armv5te
1196*cef8759bSmrg   },
1197*cef8759bSmrg   {
1198*cef8759bSmrg     {
1199*cef8759bSmrg       "arm966e-s",
1200*cef8759bSmrg       cpu_opttab_arm966es,
1201*cef8759bSmrg       {
1202*cef8759bSmrg         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1203*cef8759bSmrg         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1204*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1205*cef8759bSmrg       }
1206*cef8759bSmrg     },
1207*cef8759bSmrg     TARGET_ARCH_armv5te
1208*cef8759bSmrg   },
1209*cef8759bSmrg   {
1210*cef8759bSmrg     {
1211*cef8759bSmrg       "arm968e-s",
1212*cef8759bSmrg       cpu_opttab_arm968es,
1213*cef8759bSmrg       {
1214*cef8759bSmrg         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1215*cef8759bSmrg         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1216*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1217*cef8759bSmrg       }
1218*cef8759bSmrg     },
1219*cef8759bSmrg     TARGET_ARCH_armv5te
1220*cef8759bSmrg   },
1221*cef8759bSmrg   {
1222*cef8759bSmrg     {
1223*cef8759bSmrg       "arm10e",
1224*cef8759bSmrg       cpu_opttab_arm10e,
1225*cef8759bSmrg       {
1226*cef8759bSmrg         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1227*cef8759bSmrg         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1228*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1229*cef8759bSmrg       }
1230*cef8759bSmrg     },
1231*cef8759bSmrg     TARGET_ARCH_armv5te
1232*cef8759bSmrg   },
1233*cef8759bSmrg   {
1234*cef8759bSmrg     {
1235*cef8759bSmrg       "arm1020e",
1236*cef8759bSmrg       cpu_opttab_arm1020e,
1237*cef8759bSmrg       {
1238*cef8759bSmrg         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1239*cef8759bSmrg         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1240*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1241*cef8759bSmrg       }
1242*cef8759bSmrg     },
1243*cef8759bSmrg     TARGET_ARCH_armv5te
1244*cef8759bSmrg   },
1245*cef8759bSmrg   {
1246*cef8759bSmrg     {
1247*cef8759bSmrg       "arm1022e",
1248*cef8759bSmrg       cpu_opttab_arm1022e,
1249*cef8759bSmrg       {
1250*cef8759bSmrg         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1251*cef8759bSmrg         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1252*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1253*cef8759bSmrg       }
1254*cef8759bSmrg     },
1255*cef8759bSmrg     TARGET_ARCH_armv5te
1256*cef8759bSmrg   },
1257*cef8759bSmrg   {
1258*cef8759bSmrg     {
1259*cef8759bSmrg       "xscale",
1260*cef8759bSmrg       NULL,
1261*cef8759bSmrg       {
1262*cef8759bSmrg         isa_bit_armv5e, isa_bit_xscale, isa_bit_thumb, isa_bit_armv4,
1263*cef8759bSmrg         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_armv3m,
1264*cef8759bSmrg         isa_nobit
1265*cef8759bSmrg       }
1266*cef8759bSmrg     },
1267*cef8759bSmrg     TARGET_ARCH_armv5te
1268*cef8759bSmrg   },
1269*cef8759bSmrg   {
1270*cef8759bSmrg     {
1271*cef8759bSmrg       "iwmmxt",
1272*cef8759bSmrg       NULL,
1273*cef8759bSmrg       {
1274*cef8759bSmrg         isa_bit_armv5e, isa_bit_iwmmxt, isa_bit_xscale, isa_bit_thumb,
1275*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, isa_bit_notm,
1276*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1277*cef8759bSmrg       }
1278*cef8759bSmrg     },
1279*cef8759bSmrg     TARGET_ARCH_iwmmxt
1280*cef8759bSmrg   },
1281*cef8759bSmrg   {
1282*cef8759bSmrg     {
1283*cef8759bSmrg       "iwmmxt2",
1284*cef8759bSmrg       NULL,
1285*cef8759bSmrg       {
1286*cef8759bSmrg         isa_bit_armv5e, isa_bit_iwmmxt, isa_bit_xscale, isa_bit_thumb,
1287*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, isa_bit_iwmmxt2,
1288*cef8759bSmrg         isa_bit_notm, isa_bit_armv3m, isa_nobit
1289*cef8759bSmrg       }
1290*cef8759bSmrg     },
1291*cef8759bSmrg     TARGET_ARCH_iwmmxt2
1292*cef8759bSmrg   },
1293*cef8759bSmrg   {
1294*cef8759bSmrg     {
1295*cef8759bSmrg       "fa606te",
1296*cef8759bSmrg       NULL,
1297*cef8759bSmrg       {
1298*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5,
1299*cef8759bSmrg         isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit
1300*cef8759bSmrg       }
1301*cef8759bSmrg     },
1302*cef8759bSmrg     TARGET_ARCH_armv5te
1303*cef8759bSmrg   },
1304*cef8759bSmrg   {
1305*cef8759bSmrg     {
1306*cef8759bSmrg       "fa626te",
1307*cef8759bSmrg       NULL,
1308*cef8759bSmrg       {
1309*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5,
1310*cef8759bSmrg         isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit
1311*cef8759bSmrg       }
1312*cef8759bSmrg     },
1313*cef8759bSmrg     TARGET_ARCH_armv5te
1314*cef8759bSmrg   },
1315*cef8759bSmrg   {
1316*cef8759bSmrg     {
1317*cef8759bSmrg       "fmp626",
1318*cef8759bSmrg       NULL,
1319*cef8759bSmrg       {
1320*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5,
1321*cef8759bSmrg         isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit
1322*cef8759bSmrg       }
1323*cef8759bSmrg     },
1324*cef8759bSmrg     TARGET_ARCH_armv5te
1325*cef8759bSmrg   },
1326*cef8759bSmrg   {
1327*cef8759bSmrg     {
1328*cef8759bSmrg       "fa726te",
1329*cef8759bSmrg       NULL,
1330*cef8759bSmrg       {
1331*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5,
1332*cef8759bSmrg         isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit
1333*cef8759bSmrg       }
1334*cef8759bSmrg     },
1335*cef8759bSmrg     TARGET_ARCH_armv5te
1336*cef8759bSmrg   },
1337*cef8759bSmrg   {
1338*cef8759bSmrg     {
1339*cef8759bSmrg       "arm926ej-s",
1340*cef8759bSmrg       cpu_opttab_arm926ejs,
1341*cef8759bSmrg       {
1342*cef8759bSmrg         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1343*cef8759bSmrg         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1344*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1345*cef8759bSmrg       }
1346*cef8759bSmrg     },
1347*cef8759bSmrg     TARGET_ARCH_armv5tej
1348*cef8759bSmrg   },
1349*cef8759bSmrg   {
1350*cef8759bSmrg     {
1351*cef8759bSmrg       "arm1026ej-s",
1352*cef8759bSmrg       cpu_opttab_arm1026ejs,
1353*cef8759bSmrg       {
1354*cef8759bSmrg         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1355*cef8759bSmrg         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1356*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1357*cef8759bSmrg       }
1358*cef8759bSmrg     },
1359*cef8759bSmrg     TARGET_ARCH_armv5tej
1360*cef8759bSmrg   },
1361*cef8759bSmrg   {
1362*cef8759bSmrg     {
1363*cef8759bSmrg       "arm1136j-s",
1364*cef8759bSmrg       NULL,
1365*cef8759bSmrg       {
1366*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1367*cef8759bSmrg         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm,
1368*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1369*cef8759bSmrg       }
1370*cef8759bSmrg     },
1371*cef8759bSmrg     TARGET_ARCH_armv6j
1372*cef8759bSmrg   },
1373*cef8759bSmrg   {
1374*cef8759bSmrg     {
1375*cef8759bSmrg       "arm1136jf-s",
1376*cef8759bSmrg       NULL,
1377*cef8759bSmrg       {
1378*cef8759bSmrg         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
1379*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, isa_bit_mode32,
1380*cef8759bSmrg         isa_bit_notm, isa_bit_fp_dbl, isa_bit_armv3m, isa_nobit
1381*cef8759bSmrg       }
1382*cef8759bSmrg     },
1383*cef8759bSmrg     TARGET_ARCH_armv6j
1384*cef8759bSmrg   },
1385*cef8759bSmrg   {
1386*cef8759bSmrg     {
1387*cef8759bSmrg       "arm1176jz-s",
1388*cef8759bSmrg       NULL,
1389*cef8759bSmrg       {
1390*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1391*cef8759bSmrg         isa_bit_armv5, isa_bit_armv6, isa_bit_quirk_armv6kz, isa_bit_mode32,
1392*cef8759bSmrg         isa_bit_notm, isa_bit_armv6k, isa_bit_armv3m, isa_nobit
1393*cef8759bSmrg       }
1394*cef8759bSmrg     },
1395*cef8759bSmrg     TARGET_ARCH_armv6kz
1396*cef8759bSmrg   },
1397*cef8759bSmrg   {
1398*cef8759bSmrg     {
1399*cef8759bSmrg       "arm1176jzf-s",
1400*cef8759bSmrg       NULL,
1401*cef8759bSmrg       {
1402*cef8759bSmrg         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
1403*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, isa_bit_quirk_armv6kz,
1404*cef8759bSmrg         isa_bit_mode32, isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl,
1405*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1406*cef8759bSmrg       }
1407*cef8759bSmrg     },
1408*cef8759bSmrg     TARGET_ARCH_armv6kz
1409*cef8759bSmrg   },
1410*cef8759bSmrg   {
1411*cef8759bSmrg     {
1412*cef8759bSmrg       "mpcorenovfp",
1413*cef8759bSmrg       NULL,
1414*cef8759bSmrg       {
1415*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1416*cef8759bSmrg         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm,
1417*cef8759bSmrg         isa_bit_armv6k, isa_bit_armv3m, isa_nobit
1418*cef8759bSmrg       }
1419*cef8759bSmrg     },
1420*cef8759bSmrg     TARGET_ARCH_armv6k
1421*cef8759bSmrg   },
1422*cef8759bSmrg   {
1423*cef8759bSmrg     {
1424*cef8759bSmrg       "mpcore",
1425*cef8759bSmrg       NULL,
1426*cef8759bSmrg       {
1427*cef8759bSmrg         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
1428*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, isa_bit_mode32,
1429*cef8759bSmrg         isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_bit_armv3m,
1430*cef8759bSmrg         isa_nobit
1431*cef8759bSmrg       }
1432*cef8759bSmrg     },
1433*cef8759bSmrg     TARGET_ARCH_armv6k
1434*cef8759bSmrg   },
1435*cef8759bSmrg   {
1436*cef8759bSmrg     {
1437*cef8759bSmrg       "arm1156t2-s",
1438*cef8759bSmrg       NULL,
1439*cef8759bSmrg       {
1440*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1441*cef8759bSmrg         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_thumb2,
1442*cef8759bSmrg         isa_bit_notm, isa_bit_armv3m, isa_nobit
1443*cef8759bSmrg       }
1444*cef8759bSmrg     },
1445*cef8759bSmrg     TARGET_ARCH_armv6t2
1446*cef8759bSmrg   },
1447*cef8759bSmrg   {
1448*cef8759bSmrg     {
1449*cef8759bSmrg       "arm1156t2f-s",
1450*cef8759bSmrg       NULL,
1451*cef8759bSmrg       {
1452*cef8759bSmrg         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
1453*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, isa_bit_mode32,
1454*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_fp_dbl, isa_bit_armv3m,
1455*cef8759bSmrg         isa_nobit
1456*cef8759bSmrg       }
1457*cef8759bSmrg     },
1458*cef8759bSmrg     TARGET_ARCH_armv6t2
1459*cef8759bSmrg   },
1460*cef8759bSmrg   {
1461*cef8759bSmrg     {
1462*cef8759bSmrg       "cortex-m1",
1463*cef8759bSmrg       NULL,
1464*cef8759bSmrg       {
1465*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1466*cef8759bSmrg         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
1467*cef8759bSmrg         isa_nobit
1468*cef8759bSmrg       }
1469*cef8759bSmrg     },
1470*cef8759bSmrg     TARGET_ARCH_armv6s_m
1471*cef8759bSmrg   },
1472*cef8759bSmrg   {
1473*cef8759bSmrg     {
1474*cef8759bSmrg       "cortex-m0",
1475*cef8759bSmrg       NULL,
1476*cef8759bSmrg       {
1477*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1478*cef8759bSmrg         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
1479*cef8759bSmrg         isa_nobit
1480*cef8759bSmrg       }
1481*cef8759bSmrg     },
1482*cef8759bSmrg     TARGET_ARCH_armv6s_m
1483*cef8759bSmrg   },
1484*cef8759bSmrg   {
1485*cef8759bSmrg     {
1486*cef8759bSmrg       "cortex-m0plus",
1487*cef8759bSmrg       NULL,
1488*cef8759bSmrg       {
1489*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1490*cef8759bSmrg         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
1491*cef8759bSmrg         isa_nobit
1492*cef8759bSmrg       }
1493*cef8759bSmrg     },
1494*cef8759bSmrg     TARGET_ARCH_armv6s_m
1495*cef8759bSmrg   },
1496*cef8759bSmrg   {
1497*cef8759bSmrg     {
1498*cef8759bSmrg       "cortex-m1.small-multiply",
1499*cef8759bSmrg       NULL,
1500*cef8759bSmrg       {
1501*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1502*cef8759bSmrg         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
1503*cef8759bSmrg         isa_nobit
1504*cef8759bSmrg       }
1505*cef8759bSmrg     },
1506*cef8759bSmrg     TARGET_ARCH_armv6s_m
1507*cef8759bSmrg   },
1508*cef8759bSmrg   {
1509*cef8759bSmrg     {
1510*cef8759bSmrg       "cortex-m0.small-multiply",
1511*cef8759bSmrg       NULL,
1512*cef8759bSmrg       {
1513*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1514*cef8759bSmrg         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
1515*cef8759bSmrg         isa_nobit
1516*cef8759bSmrg       }
1517*cef8759bSmrg     },
1518*cef8759bSmrg     TARGET_ARCH_armv6s_m
1519*cef8759bSmrg   },
1520*cef8759bSmrg   {
1521*cef8759bSmrg     {
1522*cef8759bSmrg       "cortex-m0plus.small-multiply",
1523*cef8759bSmrg       NULL,
1524*cef8759bSmrg       {
1525*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1526*cef8759bSmrg         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
1527*cef8759bSmrg         isa_nobit
1528*cef8759bSmrg       }
1529*cef8759bSmrg     },
1530*cef8759bSmrg     TARGET_ARCH_armv6s_m
1531*cef8759bSmrg   },
1532*cef8759bSmrg   {
1533*cef8759bSmrg     {
1534*cef8759bSmrg       "generic-armv7-a",
1535*cef8759bSmrg       cpu_opttab_genericv7a,
1536*cef8759bSmrg       {
1537*cef8759bSmrg         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5e, isa_bit_thumb,
1538*cef8759bSmrg         isa_bit_be8, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
1539*cef8759bSmrg         isa_bit_armv7, isa_bit_mode32, isa_bit_thumb2, isa_bit_notm,
1540*cef8759bSmrg         isa_bit_armv6k, isa_bit_fp_dbl, isa_bit_armv3m, isa_nobit
1541*cef8759bSmrg       }
1542*cef8759bSmrg     },
1543*cef8759bSmrg     TARGET_ARCH_armv7_a
1544*cef8759bSmrg   },
1545*cef8759bSmrg   {
1546*cef8759bSmrg     {
1547*cef8759bSmrg       "cortex-a5",
1548*cef8759bSmrg       cpu_opttab_cortexa5,
1549*cef8759bSmrg       {
1550*cef8759bSmrg         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5e, isa_bit_thumb,
1551*cef8759bSmrg         isa_bit_be8, isa_bit_armv4, isa_bit_armv5, isa_bit_neon,
1552*cef8759bSmrg         isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_mode32,
1553*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1554*cef8759bSmrg         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1555*cef8759bSmrg         isa_nobit
1556*cef8759bSmrg       }
1557*cef8759bSmrg     },
1558*cef8759bSmrg     TARGET_ARCH_armv7_a
1559*cef8759bSmrg   },
1560*cef8759bSmrg   {
1561*cef8759bSmrg     {
1562*cef8759bSmrg       "cortex-a7",
1563*cef8759bSmrg       cpu_opttab_cortexa7,
1564*cef8759bSmrg       {
1565*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1566*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1567*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1568*cef8759bSmrg         isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
1569*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1570*cef8759bSmrg         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1571*cef8759bSmrg         isa_nobit
1572*cef8759bSmrg       }
1573*cef8759bSmrg     },
1574*cef8759bSmrg     TARGET_ARCH_armv7ve
1575*cef8759bSmrg   },
1576*cef8759bSmrg   {
1577*cef8759bSmrg     {
1578*cef8759bSmrg       "cortex-a8",
1579*cef8759bSmrg       cpu_opttab_cortexa8,
1580*cef8759bSmrg       {
1581*cef8759bSmrg         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5e, isa_bit_thumb,
1582*cef8759bSmrg         isa_bit_be8, isa_bit_armv4, isa_bit_armv5, isa_bit_neon,
1583*cef8759bSmrg         isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_mode32,
1584*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl,
1585*cef8759bSmrg         isa_bit_sec, isa_bit_armv3m, isa_nobit
1586*cef8759bSmrg       }
1587*cef8759bSmrg     },
1588*cef8759bSmrg     TARGET_ARCH_armv7_a
1589*cef8759bSmrg   },
1590*cef8759bSmrg   {
1591*cef8759bSmrg     {
1592*cef8759bSmrg       "cortex-a9",
1593*cef8759bSmrg       cpu_opttab_cortexa9,
1594*cef8759bSmrg       {
1595*cef8759bSmrg         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5e, isa_bit_thumb,
1596*cef8759bSmrg         isa_bit_be8, isa_bit_armv4, isa_bit_armv5, isa_bit_neon,
1597*cef8759bSmrg         isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_mode32,
1598*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1599*cef8759bSmrg         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1600*cef8759bSmrg         isa_nobit
1601*cef8759bSmrg       }
1602*cef8759bSmrg     },
1603*cef8759bSmrg     TARGET_ARCH_armv7_a
1604*cef8759bSmrg   },
1605*cef8759bSmrg   {
1606*cef8759bSmrg     {
1607*cef8759bSmrg       "cortex-a12",
1608*cef8759bSmrg       cpu_opttab_cortexa12,
1609*cef8759bSmrg       {
1610*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1611*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1612*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1613*cef8759bSmrg         isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
1614*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1615*cef8759bSmrg         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1616*cef8759bSmrg         isa_nobit
1617*cef8759bSmrg       }
1618*cef8759bSmrg     },
1619*cef8759bSmrg     TARGET_ARCH_armv7ve
1620*cef8759bSmrg   },
1621*cef8759bSmrg   {
1622*cef8759bSmrg     {
1623*cef8759bSmrg       "cortex-a15",
1624*cef8759bSmrg       cpu_opttab_cortexa15,
1625*cef8759bSmrg       {
1626*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1627*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1628*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1629*cef8759bSmrg         isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
1630*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1631*cef8759bSmrg         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1632*cef8759bSmrg         isa_nobit
1633*cef8759bSmrg       }
1634*cef8759bSmrg     },
1635*cef8759bSmrg     TARGET_ARCH_armv7ve
1636*cef8759bSmrg   },
1637*cef8759bSmrg   {
1638*cef8759bSmrg     {
1639*cef8759bSmrg       "cortex-a17",
1640*cef8759bSmrg       cpu_opttab_cortexa17,
1641*cef8759bSmrg       {
1642*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1643*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1644*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1645*cef8759bSmrg         isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
1646*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1647*cef8759bSmrg         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1648*cef8759bSmrg         isa_nobit
1649*cef8759bSmrg       }
1650*cef8759bSmrg     },
1651*cef8759bSmrg     TARGET_ARCH_armv7ve
1652*cef8759bSmrg   },
1653*cef8759bSmrg   {
1654*cef8759bSmrg     {
1655*cef8759bSmrg       "cortex-r4",
1656*cef8759bSmrg       NULL,
1657*cef8759bSmrg       {
1658*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1659*cef8759bSmrg         isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv,
1660*cef8759bSmrg         isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k,
1661*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1662*cef8759bSmrg       }
1663*cef8759bSmrg     },
1664*cef8759bSmrg     TARGET_ARCH_armv7_r
1665*cef8759bSmrg   },
1666*cef8759bSmrg   {
1667*cef8759bSmrg     {
1668*cef8759bSmrg       "cortex-r4f",
1669*cef8759bSmrg       NULL,
1670*cef8759bSmrg       {
1671*cef8759bSmrg         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5e, isa_bit_thumb,
1672*cef8759bSmrg         isa_bit_be8, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
1673*cef8759bSmrg         isa_bit_armv7, isa_bit_tdiv, isa_bit_mode32, isa_bit_thumb2,
1674*cef8759bSmrg         isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_bit_armv3m,
1675*cef8759bSmrg         isa_nobit
1676*cef8759bSmrg       }
1677*cef8759bSmrg     },
1678*cef8759bSmrg     TARGET_ARCH_armv7_r
1679*cef8759bSmrg   },
1680*cef8759bSmrg   {
1681*cef8759bSmrg     {
1682*cef8759bSmrg       "cortex-r5",
1683*cef8759bSmrg       cpu_opttab_cortexr5,
1684*cef8759bSmrg       {
1685*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5e,
1686*cef8759bSmrg         isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5,
1687*cef8759bSmrg         isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_mode32,
1688*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl,
1689*cef8759bSmrg         isa_bit_armv3m, isa_nobit
1690*cef8759bSmrg       }
1691*cef8759bSmrg     },
1692*cef8759bSmrg     TARGET_ARCH_armv7_r
1693*cef8759bSmrg   },
1694*cef8759bSmrg   {
1695*cef8759bSmrg     {
1696*cef8759bSmrg       "cortex-r7",
1697*cef8759bSmrg       cpu_opttab_cortexr7,
1698*cef8759bSmrg       {
1699*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5e,
1700*cef8759bSmrg         isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5,
1701*cef8759bSmrg         isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_mode32,
1702*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1703*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_armv3m, isa_nobit
1704*cef8759bSmrg       }
1705*cef8759bSmrg     },
1706*cef8759bSmrg     TARGET_ARCH_armv7_r
1707*cef8759bSmrg   },
1708*cef8759bSmrg   {
1709*cef8759bSmrg     {
1710*cef8759bSmrg       "cortex-r8",
1711*cef8759bSmrg       cpu_opttab_cortexr8,
1712*cef8759bSmrg       {
1713*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5e,
1714*cef8759bSmrg         isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5,
1715*cef8759bSmrg         isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_mode32,
1716*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1717*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_armv3m, isa_nobit
1718*cef8759bSmrg       }
1719*cef8759bSmrg     },
1720*cef8759bSmrg     TARGET_ARCH_armv7_r
1721*cef8759bSmrg   },
1722*cef8759bSmrg   {
1723*cef8759bSmrg     {
1724*cef8759bSmrg       "cortex-m7",
1725*cef8759bSmrg       cpu_opttab_cortexm7,
1726*cef8759bSmrg       {
1727*cef8759bSmrg         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5e,
1728*cef8759bSmrg         isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5,
1729*cef8759bSmrg         isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_fpv5,
1730*cef8759bSmrg         isa_bit_tdiv, isa_bit_quirk_no_volatile_ce, isa_bit_mode32, isa_bit_thumb2,
1731*cef8759bSmrg         isa_bit_fp16conv, isa_bit_fp_dbl, isa_bit_armv3m, isa_nobit
1732*cef8759bSmrg       }
1733*cef8759bSmrg     },
1734*cef8759bSmrg     TARGET_ARCH_armv7e_m
1735*cef8759bSmrg   },
1736*cef8759bSmrg   {
1737*cef8759bSmrg     {
1738*cef8759bSmrg       "cortex-m4",
1739*cef8759bSmrg       cpu_opttab_cortexm4,
1740*cef8759bSmrg       {
1741*cef8759bSmrg         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5e,
1742*cef8759bSmrg         isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5,
1743*cef8759bSmrg         isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_tdiv,
1744*cef8759bSmrg         isa_bit_mode32, isa_bit_thumb2, isa_bit_fp16conv, isa_bit_armv3m,
1745*cef8759bSmrg         isa_nobit
1746*cef8759bSmrg       }
1747*cef8759bSmrg     },
1748*cef8759bSmrg     TARGET_ARCH_armv7e_m
1749*cef8759bSmrg   },
1750*cef8759bSmrg   {
1751*cef8759bSmrg     {
1752*cef8759bSmrg       "cortex-m3",
1753*cef8759bSmrg       NULL,
1754*cef8759bSmrg       {
1755*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_quirk_cm3_ldrd, isa_bit_be8,
1756*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, isa_bit_armv7,
1757*cef8759bSmrg         isa_bit_tdiv, isa_bit_mode32, isa_bit_thumb2, isa_bit_armv3m,
1758*cef8759bSmrg         isa_nobit
1759*cef8759bSmrg       }
1760*cef8759bSmrg     },
1761*cef8759bSmrg     TARGET_ARCH_armv7_m
1762*cef8759bSmrg   },
1763*cef8759bSmrg   {
1764*cef8759bSmrg     {
1765*cef8759bSmrg       "marvell-pj4",
1766*cef8759bSmrg       NULL,
1767*cef8759bSmrg       {
1768*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1769*cef8759bSmrg         isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_mode32,
1770*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_mp,
1771*cef8759bSmrg         isa_bit_sec, isa_bit_armv3m, isa_nobit
1772*cef8759bSmrg       }
1773*cef8759bSmrg     },
1774*cef8759bSmrg     TARGET_ARCH_armv7_a
1775*cef8759bSmrg   },
1776*cef8759bSmrg   {
1777*cef8759bSmrg     {
1778*cef8759bSmrg       "cortex-a15.cortex-a7",
1779*cef8759bSmrg       cpu_opttab_cortexa15cortexa7,
1780*cef8759bSmrg       {
1781*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1782*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1783*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1784*cef8759bSmrg         isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
1785*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1786*cef8759bSmrg         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1787*cef8759bSmrg         isa_nobit
1788*cef8759bSmrg       }
1789*cef8759bSmrg     },
1790*cef8759bSmrg     TARGET_ARCH_armv7ve
1791*cef8759bSmrg   },
1792*cef8759bSmrg   {
1793*cef8759bSmrg     {
1794*cef8759bSmrg       "cortex-a17.cortex-a7",
1795*cef8759bSmrg       cpu_opttab_cortexa17cortexa7,
1796*cef8759bSmrg       {
1797*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1798*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1799*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1800*cef8759bSmrg         isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
1801*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1802*cef8759bSmrg         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1803*cef8759bSmrg         isa_nobit
1804*cef8759bSmrg       }
1805*cef8759bSmrg     },
1806*cef8759bSmrg     TARGET_ARCH_armv7ve
1807*cef8759bSmrg   },
1808*cef8759bSmrg   {
1809*cef8759bSmrg     {
1810*cef8759bSmrg       "cortex-a32",
1811*cef8759bSmrg       cpu_opttab_cortexa32,
1812*cef8759bSmrg       {
1813*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1814*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1815*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1816*cef8759bSmrg         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1817*cef8759bSmrg         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1818*cef8759bSmrg         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1819*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1820*cef8759bSmrg       }
1821*cef8759bSmrg     },
1822*cef8759bSmrg     TARGET_ARCH_armv8_a
1823*cef8759bSmrg   },
1824*cef8759bSmrg   {
1825*cef8759bSmrg     {
1826*cef8759bSmrg       "cortex-a35",
1827*cef8759bSmrg       cpu_opttab_cortexa35,
1828*cef8759bSmrg       {
1829*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1830*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1831*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1832*cef8759bSmrg         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1833*cef8759bSmrg         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1834*cef8759bSmrg         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1835*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1836*cef8759bSmrg       }
1837*cef8759bSmrg     },
1838*cef8759bSmrg     TARGET_ARCH_armv8_a
1839*cef8759bSmrg   },
1840*cef8759bSmrg   {
1841*cef8759bSmrg     {
1842*cef8759bSmrg       "cortex-a53",
1843*cef8759bSmrg       cpu_opttab_cortexa53,
1844*cef8759bSmrg       {
1845*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1846*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1847*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1848*cef8759bSmrg         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1849*cef8759bSmrg         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1850*cef8759bSmrg         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1851*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1852*cef8759bSmrg       }
1853*cef8759bSmrg     },
1854*cef8759bSmrg     TARGET_ARCH_armv8_a
1855*cef8759bSmrg   },
1856*cef8759bSmrg   {
1857*cef8759bSmrg     {
1858*cef8759bSmrg       "cortex-a57",
1859*cef8759bSmrg       cpu_opttab_cortexa57,
1860*cef8759bSmrg       {
1861*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1862*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1863*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1864*cef8759bSmrg         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1865*cef8759bSmrg         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1866*cef8759bSmrg         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1867*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1868*cef8759bSmrg       }
1869*cef8759bSmrg     },
1870*cef8759bSmrg     TARGET_ARCH_armv8_a
1871*cef8759bSmrg   },
1872*cef8759bSmrg   {
1873*cef8759bSmrg     {
1874*cef8759bSmrg       "cortex-a72",
1875*cef8759bSmrg       cpu_opttab_cortexa72,
1876*cef8759bSmrg       {
1877*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1878*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1879*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1880*cef8759bSmrg         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1881*cef8759bSmrg         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1882*cef8759bSmrg         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1883*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1884*cef8759bSmrg       }
1885*cef8759bSmrg     },
1886*cef8759bSmrg     TARGET_ARCH_armv8_a
1887*cef8759bSmrg   },
1888*cef8759bSmrg   {
1889*cef8759bSmrg     {
1890*cef8759bSmrg       "cortex-a73",
1891*cef8759bSmrg       cpu_opttab_cortexa73,
1892*cef8759bSmrg       {
1893*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1894*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1895*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1896*cef8759bSmrg         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1897*cef8759bSmrg         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1898*cef8759bSmrg         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1899*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1900*cef8759bSmrg       }
1901*cef8759bSmrg     },
1902*cef8759bSmrg     TARGET_ARCH_armv8_a
1903*cef8759bSmrg   },
1904*cef8759bSmrg   {
1905*cef8759bSmrg     {
1906*cef8759bSmrg       "exynos-m1",
1907*cef8759bSmrg       cpu_opttab_exynosm1,
1908*cef8759bSmrg       {
1909*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1910*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1911*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1912*cef8759bSmrg         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1913*cef8759bSmrg         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1914*cef8759bSmrg         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1915*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1916*cef8759bSmrg       }
1917*cef8759bSmrg     },
1918*cef8759bSmrg     TARGET_ARCH_armv8_a
1919*cef8759bSmrg   },
1920*cef8759bSmrg   {
1921*cef8759bSmrg     {
1922*cef8759bSmrg       "xgene1",
1923*cef8759bSmrg       cpu_opttab_xgene1,
1924*cef8759bSmrg       {
1925*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1926*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1927*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1928*cef8759bSmrg         isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, isa_bit_tdiv,
1929*cef8759bSmrg         isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2, isa_bit_notm,
1930*cef8759bSmrg         isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1931*cef8759bSmrg         isa_bit_sec, isa_bit_armv3m, isa_nobit
1932*cef8759bSmrg       }
1933*cef8759bSmrg     },
1934*cef8759bSmrg     TARGET_ARCH_armv8_a
1935*cef8759bSmrg   },
1936*cef8759bSmrg   {
1937*cef8759bSmrg     {
1938*cef8759bSmrg       "cortex-a57.cortex-a53",
1939*cef8759bSmrg       cpu_opttab_cortexa57cortexa53,
1940*cef8759bSmrg       {
1941*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1942*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1943*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1944*cef8759bSmrg         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1945*cef8759bSmrg         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1946*cef8759bSmrg         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1947*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1948*cef8759bSmrg       }
1949*cef8759bSmrg     },
1950*cef8759bSmrg     TARGET_ARCH_armv8_a
1951*cef8759bSmrg   },
1952*cef8759bSmrg   {
1953*cef8759bSmrg     {
1954*cef8759bSmrg       "cortex-a72.cortex-a53",
1955*cef8759bSmrg       cpu_opttab_cortexa72cortexa53,
1956*cef8759bSmrg       {
1957*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1958*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1959*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1960*cef8759bSmrg         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1961*cef8759bSmrg         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1962*cef8759bSmrg         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1963*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1964*cef8759bSmrg       }
1965*cef8759bSmrg     },
1966*cef8759bSmrg     TARGET_ARCH_armv8_a
1967*cef8759bSmrg   },
1968*cef8759bSmrg   {
1969*cef8759bSmrg     {
1970*cef8759bSmrg       "cortex-a73.cortex-a35",
1971*cef8759bSmrg       cpu_opttab_cortexa73cortexa35,
1972*cef8759bSmrg       {
1973*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1974*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1975*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1976*cef8759bSmrg         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1977*cef8759bSmrg         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1978*cef8759bSmrg         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1979*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1980*cef8759bSmrg       }
1981*cef8759bSmrg     },
1982*cef8759bSmrg     TARGET_ARCH_armv8_a
1983*cef8759bSmrg   },
1984*cef8759bSmrg   {
1985*cef8759bSmrg     {
1986*cef8759bSmrg       "cortex-a73.cortex-a53",
1987*cef8759bSmrg       cpu_opttab_cortexa73cortexa53,
1988*cef8759bSmrg       {
1989*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1990*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1991*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1992*cef8759bSmrg         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1993*cef8759bSmrg         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1994*cef8759bSmrg         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1995*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1996*cef8759bSmrg       }
1997*cef8759bSmrg     },
1998*cef8759bSmrg     TARGET_ARCH_armv8_a
1999*cef8759bSmrg   },
2000*cef8759bSmrg   {
2001*cef8759bSmrg     {
2002*cef8759bSmrg       "cortex-a55",
2003*cef8759bSmrg       cpu_opttab_cortexa55,
2004*cef8759bSmrg       {
2005*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
2006*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_dotprod,
2007*cef8759bSmrg         isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_neon,
2008*cef8759bSmrg         isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
2009*cef8759bSmrg         isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
2010*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1,
2011*cef8759bSmrg         isa_bit_fp16conv, isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp,
2012*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
2013*cef8759bSmrg       }
2014*cef8759bSmrg     },
2015*cef8759bSmrg     TARGET_ARCH_armv8_2_a
2016*cef8759bSmrg   },
2017*cef8759bSmrg   {
2018*cef8759bSmrg     {
2019*cef8759bSmrg       "cortex-a75",
2020*cef8759bSmrg       cpu_opttab_cortexa75,
2021*cef8759bSmrg       {
2022*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
2023*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_dotprod,
2024*cef8759bSmrg         isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_neon,
2025*cef8759bSmrg         isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
2026*cef8759bSmrg         isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
2027*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1,
2028*cef8759bSmrg         isa_bit_fp16conv, isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp,
2029*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
2030*cef8759bSmrg       }
2031*cef8759bSmrg     },
2032*cef8759bSmrg     TARGET_ARCH_armv8_2_a
2033*cef8759bSmrg   },
2034*cef8759bSmrg   {
2035*cef8759bSmrg     {
2036*cef8759bSmrg       "cortex-a75.cortex-a55",
2037*cef8759bSmrg       cpu_opttab_cortexa75cortexa55,
2038*cef8759bSmrg       {
2039*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
2040*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_dotprod,
2041*cef8759bSmrg         isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_neon,
2042*cef8759bSmrg         isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
2043*cef8759bSmrg         isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
2044*cef8759bSmrg         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1,
2045*cef8759bSmrg         isa_bit_fp16conv, isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp,
2046*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
2047*cef8759bSmrg       }
2048*cef8759bSmrg     },
2049*cef8759bSmrg     TARGET_ARCH_armv8_2_a
2050*cef8759bSmrg   },
2051*cef8759bSmrg   {
2052*cef8759bSmrg     {
2053*cef8759bSmrg       "cortex-m23",
2054*cef8759bSmrg       NULL,
2055*cef8759bSmrg       {
2056*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
2057*cef8759bSmrg         isa_bit_armv5, isa_bit_armv6, isa_bit_armv8, isa_bit_cmse,
2058*cef8759bSmrg         isa_bit_tdiv, isa_bit_mode32, isa_bit_armv3m, isa_nobit
2059*cef8759bSmrg       }
2060*cef8759bSmrg     },
2061*cef8759bSmrg     TARGET_ARCH_armv8_m_base
2062*cef8759bSmrg   },
2063*cef8759bSmrg   {
2064*cef8759bSmrg     {
2065*cef8759bSmrg       "cortex-m33",
2066*cef8759bSmrg       cpu_opttab_cortexm33,
2067*cef8759bSmrg       {
2068*cef8759bSmrg         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5e,
2069*cef8759bSmrg         isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5,
2070*cef8759bSmrg         isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_armv8,
2071*cef8759bSmrg         isa_bit_cmse, isa_bit_fpv5, isa_bit_tdiv, isa_bit_mode32,
2072*cef8759bSmrg         isa_bit_thumb2, isa_bit_fp16conv, isa_bit_armv3m, isa_nobit
2073*cef8759bSmrg       }
2074*cef8759bSmrg     },
2075*cef8759bSmrg     TARGET_ARCH_armv8_m_main
2076*cef8759bSmrg   },
2077*cef8759bSmrg   {
2078*cef8759bSmrg     {
2079*cef8759bSmrg       "cortex-r52",
2080*cef8759bSmrg       cpu_opttab_cortexr52,
2081*cef8759bSmrg       {
2082*cef8759bSmrg         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
2083*cef8759bSmrg         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
2084*cef8759bSmrg         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
2085*cef8759bSmrg         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
2086*cef8759bSmrg         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
2087*cef8759bSmrg         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
2088*cef8759bSmrg         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
2089*cef8759bSmrg       }
2090*cef8759bSmrg     },
2091*cef8759bSmrg     TARGET_ARCH_armv8_r
2092*cef8759bSmrg   },
2093*cef8759bSmrg   {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none}
2094*cef8759bSmrg };
2095*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv5e[] = {
2096*cef8759bSmrg   {
2097*cef8759bSmrg     "fp", false, false,
2098*cef8759bSmrg     {
2099*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2100*cef8759bSmrg     }
2101*cef8759bSmrg   },
2102*cef8759bSmrg   {
2103*cef8759bSmrg     "nofp", true, false,
2104*cef8759bSmrg     {
2105*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2106*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2107*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2108*cef8759bSmrg     }
2109*cef8759bSmrg   },
2110*cef8759bSmrg   {
2111*cef8759bSmrg     "vfpv2", false, true,
2112*cef8759bSmrg     {
2113*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2114*cef8759bSmrg     }
2115*cef8759bSmrg   },
2116*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2117*cef8759bSmrg };
2118*cef8759bSmrg 
2119*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv5te[] = {
2120*cef8759bSmrg   {
2121*cef8759bSmrg     "fp", false, false,
2122*cef8759bSmrg     {
2123*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2124*cef8759bSmrg     }
2125*cef8759bSmrg   },
2126*cef8759bSmrg   {
2127*cef8759bSmrg     "nofp", true, false,
2128*cef8759bSmrg     {
2129*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2130*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2131*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2132*cef8759bSmrg     }
2133*cef8759bSmrg   },
2134*cef8759bSmrg   {
2135*cef8759bSmrg     "vfpv2", false, true,
2136*cef8759bSmrg     {
2137*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2138*cef8759bSmrg     }
2139*cef8759bSmrg   },
2140*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2141*cef8759bSmrg };
2142*cef8759bSmrg 
2143*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv5tej[] = {
2144*cef8759bSmrg   {
2145*cef8759bSmrg     "fp", false, false,
2146*cef8759bSmrg     {
2147*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2148*cef8759bSmrg     }
2149*cef8759bSmrg   },
2150*cef8759bSmrg   {
2151*cef8759bSmrg     "nofp", true, false,
2152*cef8759bSmrg     {
2153*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2154*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2155*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2156*cef8759bSmrg     }
2157*cef8759bSmrg   },
2158*cef8759bSmrg   {
2159*cef8759bSmrg     "vfpv2", false, true,
2160*cef8759bSmrg     {
2161*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2162*cef8759bSmrg     }
2163*cef8759bSmrg   },
2164*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2165*cef8759bSmrg };
2166*cef8759bSmrg 
2167*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv6[] = {
2168*cef8759bSmrg   {
2169*cef8759bSmrg     "fp", false, false,
2170*cef8759bSmrg     {
2171*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2172*cef8759bSmrg     }
2173*cef8759bSmrg   },
2174*cef8759bSmrg   {
2175*cef8759bSmrg     "nofp", true, false,
2176*cef8759bSmrg     {
2177*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2178*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2179*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2180*cef8759bSmrg     }
2181*cef8759bSmrg   },
2182*cef8759bSmrg   {
2183*cef8759bSmrg     "vfpv2", false, true,
2184*cef8759bSmrg     {
2185*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2186*cef8759bSmrg     }
2187*cef8759bSmrg   },
2188*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2189*cef8759bSmrg };
2190*cef8759bSmrg 
2191*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv6j[] = {
2192*cef8759bSmrg   {
2193*cef8759bSmrg     "fp", false, false,
2194*cef8759bSmrg     {
2195*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2196*cef8759bSmrg     }
2197*cef8759bSmrg   },
2198*cef8759bSmrg   {
2199*cef8759bSmrg     "nofp", true, false,
2200*cef8759bSmrg     {
2201*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2202*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2203*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2204*cef8759bSmrg     }
2205*cef8759bSmrg   },
2206*cef8759bSmrg   {
2207*cef8759bSmrg     "vfpv2", false, true,
2208*cef8759bSmrg     {
2209*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2210*cef8759bSmrg     }
2211*cef8759bSmrg   },
2212*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2213*cef8759bSmrg };
2214*cef8759bSmrg 
2215*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv6k[] = {
2216*cef8759bSmrg   {
2217*cef8759bSmrg     "fp", false, false,
2218*cef8759bSmrg     {
2219*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2220*cef8759bSmrg     }
2221*cef8759bSmrg   },
2222*cef8759bSmrg   {
2223*cef8759bSmrg     "nofp", true, false,
2224*cef8759bSmrg     {
2225*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2226*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2227*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2228*cef8759bSmrg     }
2229*cef8759bSmrg   },
2230*cef8759bSmrg   {
2231*cef8759bSmrg     "vfpv2", false, true,
2232*cef8759bSmrg     {
2233*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2234*cef8759bSmrg     }
2235*cef8759bSmrg   },
2236*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2237*cef8759bSmrg };
2238*cef8759bSmrg 
2239*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv6z[] = {
2240*cef8759bSmrg   {
2241*cef8759bSmrg     "fp", false, false,
2242*cef8759bSmrg     {
2243*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2244*cef8759bSmrg     }
2245*cef8759bSmrg   },
2246*cef8759bSmrg   {
2247*cef8759bSmrg     "nofp", true, false,
2248*cef8759bSmrg     {
2249*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2250*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2251*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2252*cef8759bSmrg     }
2253*cef8759bSmrg   },
2254*cef8759bSmrg   {
2255*cef8759bSmrg     "vfpv2", false, true,
2256*cef8759bSmrg     {
2257*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2258*cef8759bSmrg     }
2259*cef8759bSmrg   },
2260*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2261*cef8759bSmrg };
2262*cef8759bSmrg 
2263*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv6kz[] = {
2264*cef8759bSmrg   {
2265*cef8759bSmrg     "fp", false, false,
2266*cef8759bSmrg     {
2267*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2268*cef8759bSmrg     }
2269*cef8759bSmrg   },
2270*cef8759bSmrg   {
2271*cef8759bSmrg     "nofp", true, false,
2272*cef8759bSmrg     {
2273*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2274*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2275*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2276*cef8759bSmrg     }
2277*cef8759bSmrg   },
2278*cef8759bSmrg   {
2279*cef8759bSmrg     "vfpv2", false, true,
2280*cef8759bSmrg     {
2281*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2282*cef8759bSmrg     }
2283*cef8759bSmrg   },
2284*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2285*cef8759bSmrg };
2286*cef8759bSmrg 
2287*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv6zk[] = {
2288*cef8759bSmrg   {
2289*cef8759bSmrg     "fp", false, false,
2290*cef8759bSmrg     {
2291*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2292*cef8759bSmrg     }
2293*cef8759bSmrg   },
2294*cef8759bSmrg   {
2295*cef8759bSmrg     "nofp", true, false,
2296*cef8759bSmrg     {
2297*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2298*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2299*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2300*cef8759bSmrg     }
2301*cef8759bSmrg   },
2302*cef8759bSmrg   {
2303*cef8759bSmrg     "vfpv2", false, true,
2304*cef8759bSmrg     {
2305*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2306*cef8759bSmrg     }
2307*cef8759bSmrg   },
2308*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2309*cef8759bSmrg };
2310*cef8759bSmrg 
2311*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv6t2[] = {
2312*cef8759bSmrg   {
2313*cef8759bSmrg     "fp", false, false,
2314*cef8759bSmrg     {
2315*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2316*cef8759bSmrg     }
2317*cef8759bSmrg   },
2318*cef8759bSmrg   {
2319*cef8759bSmrg     "nofp", true, false,
2320*cef8759bSmrg     {
2321*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2322*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2323*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2324*cef8759bSmrg     }
2325*cef8759bSmrg   },
2326*cef8759bSmrg   {
2327*cef8759bSmrg     "vfpv2", false, true,
2328*cef8759bSmrg     {
2329*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2330*cef8759bSmrg     }
2331*cef8759bSmrg   },
2332*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2333*cef8759bSmrg };
2334*cef8759bSmrg 
2335*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv7[] = {
2336*cef8759bSmrg   {
2337*cef8759bSmrg     "fp", false, false,
2338*cef8759bSmrg     {
2339*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2340*cef8759bSmrg     }
2341*cef8759bSmrg   },
2342*cef8759bSmrg   {
2343*cef8759bSmrg     "nofp", true, false,
2344*cef8759bSmrg     {
2345*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2346*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2347*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2348*cef8759bSmrg     }
2349*cef8759bSmrg   },
2350*cef8759bSmrg   {
2351*cef8759bSmrg     "vfpv3-d16", false, true,
2352*cef8759bSmrg     {
2353*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2354*cef8759bSmrg     }
2355*cef8759bSmrg   },
2356*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2357*cef8759bSmrg };
2358*cef8759bSmrg 
2359*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv7_a[] = {
2360*cef8759bSmrg   {
2361*cef8759bSmrg     "mp", false, false,
2362*cef8759bSmrg     {
2363*cef8759bSmrg       isa_bit_mp, isa_nobit
2364*cef8759bSmrg     }
2365*cef8759bSmrg   },
2366*cef8759bSmrg   {
2367*cef8759bSmrg     "sec", false, false,
2368*cef8759bSmrg     {
2369*cef8759bSmrg       isa_bit_sec, isa_nobit
2370*cef8759bSmrg     }
2371*cef8759bSmrg   },
2372*cef8759bSmrg   {
2373*cef8759bSmrg     "fp", false, false,
2374*cef8759bSmrg     {
2375*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2376*cef8759bSmrg     }
2377*cef8759bSmrg   },
2378*cef8759bSmrg   {
2379*cef8759bSmrg     "vfpv3", false, false,
2380*cef8759bSmrg     {
2381*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl,
2382*cef8759bSmrg       isa_nobit
2383*cef8759bSmrg     }
2384*cef8759bSmrg   },
2385*cef8759bSmrg   {
2386*cef8759bSmrg     "vfpv3-d16-fp16", false, false,
2387*cef8759bSmrg     {
2388*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl,
2389*cef8759bSmrg       isa_nobit
2390*cef8759bSmrg     }
2391*cef8759bSmrg   },
2392*cef8759bSmrg   {
2393*cef8759bSmrg     "vfpv3-fp16", false, false,
2394*cef8759bSmrg     {
2395*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv,
2396*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2397*cef8759bSmrg     }
2398*cef8759bSmrg   },
2399*cef8759bSmrg   {
2400*cef8759bSmrg     "vfpv4-d16", false, false,
2401*cef8759bSmrg     {
2402*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
2403*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2404*cef8759bSmrg     }
2405*cef8759bSmrg   },
2406*cef8759bSmrg   {
2407*cef8759bSmrg     "vfpv4", false, false,
2408*cef8759bSmrg     {
2409*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32,
2410*cef8759bSmrg       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2411*cef8759bSmrg     }
2412*cef8759bSmrg   },
2413*cef8759bSmrg   {
2414*cef8759bSmrg     "simd", false, false,
2415*cef8759bSmrg     {
2416*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2417*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2418*cef8759bSmrg     }
2419*cef8759bSmrg   },
2420*cef8759bSmrg   {
2421*cef8759bSmrg     "neon-fp16", false, false,
2422*cef8759bSmrg     {
2423*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2424*cef8759bSmrg       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2425*cef8759bSmrg     }
2426*cef8759bSmrg   },
2427*cef8759bSmrg   {
2428*cef8759bSmrg     "neon-vfpv4", false, false,
2429*cef8759bSmrg     {
2430*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2431*cef8759bSmrg       isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2432*cef8759bSmrg     }
2433*cef8759bSmrg   },
2434*cef8759bSmrg   {
2435*cef8759bSmrg     "nosimd", true, false,
2436*cef8759bSmrg     {
2437*cef8759bSmrg       isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32,
2438*cef8759bSmrg       isa_bit_crypto, isa_nobit
2439*cef8759bSmrg     }
2440*cef8759bSmrg   },
2441*cef8759bSmrg   {
2442*cef8759bSmrg     "nofp", true, false,
2443*cef8759bSmrg     {
2444*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2445*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2446*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2447*cef8759bSmrg     }
2448*cef8759bSmrg   },
2449*cef8759bSmrg   {
2450*cef8759bSmrg     "vfpv3-d16", false, true,
2451*cef8759bSmrg     {
2452*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2453*cef8759bSmrg     }
2454*cef8759bSmrg   },
2455*cef8759bSmrg   {
2456*cef8759bSmrg     "neon", false, true,
2457*cef8759bSmrg     {
2458*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2459*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2460*cef8759bSmrg     }
2461*cef8759bSmrg   },
2462*cef8759bSmrg   {
2463*cef8759bSmrg     "neon-vfpv3", false, true,
2464*cef8759bSmrg     {
2465*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2466*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2467*cef8759bSmrg     }
2468*cef8759bSmrg   },
2469*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2470*cef8759bSmrg };
2471*cef8759bSmrg 
2472*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv7ve[] = {
2473*cef8759bSmrg   {
2474*cef8759bSmrg     "vfpv3-d16", false, false,
2475*cef8759bSmrg     {
2476*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2477*cef8759bSmrg     }
2478*cef8759bSmrg   },
2479*cef8759bSmrg   {
2480*cef8759bSmrg     "vfpv3", false, false,
2481*cef8759bSmrg     {
2482*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl,
2483*cef8759bSmrg       isa_nobit
2484*cef8759bSmrg     }
2485*cef8759bSmrg   },
2486*cef8759bSmrg   {
2487*cef8759bSmrg     "vfpv3-d16-fp16", false, false,
2488*cef8759bSmrg     {
2489*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl,
2490*cef8759bSmrg       isa_nobit
2491*cef8759bSmrg     }
2492*cef8759bSmrg   },
2493*cef8759bSmrg   {
2494*cef8759bSmrg     "vfpv3-fp16", false, false,
2495*cef8759bSmrg     {
2496*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv,
2497*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2498*cef8759bSmrg     }
2499*cef8759bSmrg   },
2500*cef8759bSmrg   {
2501*cef8759bSmrg     "fp", false, false,
2502*cef8759bSmrg     {
2503*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
2504*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2505*cef8759bSmrg     }
2506*cef8759bSmrg   },
2507*cef8759bSmrg   {
2508*cef8759bSmrg     "vfpv4", false, false,
2509*cef8759bSmrg     {
2510*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32,
2511*cef8759bSmrg       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2512*cef8759bSmrg     }
2513*cef8759bSmrg   },
2514*cef8759bSmrg   {
2515*cef8759bSmrg     "neon", false, false,
2516*cef8759bSmrg     {
2517*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2518*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2519*cef8759bSmrg     }
2520*cef8759bSmrg   },
2521*cef8759bSmrg   {
2522*cef8759bSmrg     "neon-fp16", false, false,
2523*cef8759bSmrg     {
2524*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2525*cef8759bSmrg       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2526*cef8759bSmrg     }
2527*cef8759bSmrg   },
2528*cef8759bSmrg   {
2529*cef8759bSmrg     "simd", false, false,
2530*cef8759bSmrg     {
2531*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2532*cef8759bSmrg       isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2533*cef8759bSmrg     }
2534*cef8759bSmrg   },
2535*cef8759bSmrg   {
2536*cef8759bSmrg     "nosimd", true, false,
2537*cef8759bSmrg     {
2538*cef8759bSmrg       isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32,
2539*cef8759bSmrg       isa_bit_crypto, isa_nobit
2540*cef8759bSmrg     }
2541*cef8759bSmrg   },
2542*cef8759bSmrg   {
2543*cef8759bSmrg     "nofp", true, false,
2544*cef8759bSmrg     {
2545*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2546*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2547*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2548*cef8759bSmrg     }
2549*cef8759bSmrg   },
2550*cef8759bSmrg   {
2551*cef8759bSmrg     "vfpv4-d16", false, true,
2552*cef8759bSmrg     {
2553*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
2554*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2555*cef8759bSmrg     }
2556*cef8759bSmrg   },
2557*cef8759bSmrg   {
2558*cef8759bSmrg     "neon-vfpv3", false, true,
2559*cef8759bSmrg     {
2560*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2561*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2562*cef8759bSmrg     }
2563*cef8759bSmrg   },
2564*cef8759bSmrg   {
2565*cef8759bSmrg     "neon-vfpv4", false, true,
2566*cef8759bSmrg     {
2567*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2568*cef8759bSmrg       isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2569*cef8759bSmrg     }
2570*cef8759bSmrg   },
2571*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2572*cef8759bSmrg };
2573*cef8759bSmrg 
2574*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv7_r[] = {
2575*cef8759bSmrg   {
2576*cef8759bSmrg     "fp.sp", false, false,
2577*cef8759bSmrg     {
2578*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit
2579*cef8759bSmrg     }
2580*cef8759bSmrg   },
2581*cef8759bSmrg   {
2582*cef8759bSmrg     "fp", false, false,
2583*cef8759bSmrg     {
2584*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2585*cef8759bSmrg     }
2586*cef8759bSmrg   },
2587*cef8759bSmrg   {
2588*cef8759bSmrg     "vfpv3xd-fp16", false, false,
2589*cef8759bSmrg     {
2590*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit
2591*cef8759bSmrg     }
2592*cef8759bSmrg   },
2593*cef8759bSmrg   {
2594*cef8759bSmrg     "vfpv3-d16-fp16", false, false,
2595*cef8759bSmrg     {
2596*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl,
2597*cef8759bSmrg       isa_nobit
2598*cef8759bSmrg     }
2599*cef8759bSmrg   },
2600*cef8759bSmrg   {
2601*cef8759bSmrg     "idiv", false, false,
2602*cef8759bSmrg     {
2603*cef8759bSmrg       isa_bit_adiv, isa_nobit
2604*cef8759bSmrg     }
2605*cef8759bSmrg   },
2606*cef8759bSmrg   {
2607*cef8759bSmrg     "nofp", true, false,
2608*cef8759bSmrg     {
2609*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2610*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2611*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2612*cef8759bSmrg     }
2613*cef8759bSmrg   },
2614*cef8759bSmrg   {
2615*cef8759bSmrg     "noidiv", true, false,
2616*cef8759bSmrg     {
2617*cef8759bSmrg       isa_bit_adiv, isa_nobit
2618*cef8759bSmrg     }
2619*cef8759bSmrg   },
2620*cef8759bSmrg   {
2621*cef8759bSmrg     "vfpv3xd", false, true,
2622*cef8759bSmrg     {
2623*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit
2624*cef8759bSmrg     }
2625*cef8759bSmrg   },
2626*cef8759bSmrg   {
2627*cef8759bSmrg     "vfpv3-d16", false, true,
2628*cef8759bSmrg     {
2629*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2630*cef8759bSmrg     }
2631*cef8759bSmrg   },
2632*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2633*cef8759bSmrg };
2634*cef8759bSmrg 
2635*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv7e_m[] = {
2636*cef8759bSmrg   {
2637*cef8759bSmrg     "fp", false, false,
2638*cef8759bSmrg     {
2639*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
2640*cef8759bSmrg       isa_nobit
2641*cef8759bSmrg     }
2642*cef8759bSmrg   },
2643*cef8759bSmrg   {
2644*cef8759bSmrg     "fpv5", false, false,
2645*cef8759bSmrg     {
2646*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
2647*cef8759bSmrg       isa_bit_fp16conv, isa_nobit
2648*cef8759bSmrg     }
2649*cef8759bSmrg   },
2650*cef8759bSmrg   {
2651*cef8759bSmrg     "fp.dp", false, false,
2652*cef8759bSmrg     {
2653*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
2654*cef8759bSmrg       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2655*cef8759bSmrg     }
2656*cef8759bSmrg   },
2657*cef8759bSmrg   {
2658*cef8759bSmrg     "nofp", true, false,
2659*cef8759bSmrg     {
2660*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2661*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2662*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2663*cef8759bSmrg     }
2664*cef8759bSmrg   },
2665*cef8759bSmrg   {
2666*cef8759bSmrg     "vfpv4-sp-d16", false, true,
2667*cef8759bSmrg     {
2668*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
2669*cef8759bSmrg       isa_nobit
2670*cef8759bSmrg     }
2671*cef8759bSmrg   },
2672*cef8759bSmrg   {
2673*cef8759bSmrg     "fpv5-d16", false, true,
2674*cef8759bSmrg     {
2675*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
2676*cef8759bSmrg       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2677*cef8759bSmrg     }
2678*cef8759bSmrg   },
2679*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2680*cef8759bSmrg };
2681*cef8759bSmrg 
2682*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv8_a[] = {
2683*cef8759bSmrg   {
2684*cef8759bSmrg     "crc", false, false,
2685*cef8759bSmrg     {
2686*cef8759bSmrg       isa_bit_crc32, isa_nobit
2687*cef8759bSmrg     }
2688*cef8759bSmrg   },
2689*cef8759bSmrg   {
2690*cef8759bSmrg     "simd", false, false,
2691*cef8759bSmrg     {
2692*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2693*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
2694*cef8759bSmrg       isa_nobit
2695*cef8759bSmrg     }
2696*cef8759bSmrg   },
2697*cef8759bSmrg   {
2698*cef8759bSmrg     "crypto", false, false,
2699*cef8759bSmrg     {
2700*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2701*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
2702*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2703*cef8759bSmrg     }
2704*cef8759bSmrg   },
2705*cef8759bSmrg   {
2706*cef8759bSmrg     "nocrypto", true, false,
2707*cef8759bSmrg     {
2708*cef8759bSmrg       isa_bit_crypto, isa_nobit
2709*cef8759bSmrg     }
2710*cef8759bSmrg   },
2711*cef8759bSmrg   {
2712*cef8759bSmrg     "nofp", true, false,
2713*cef8759bSmrg     {
2714*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2715*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2716*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2717*cef8759bSmrg     }
2718*cef8759bSmrg   },
2719*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2720*cef8759bSmrg };
2721*cef8759bSmrg 
2722*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = {
2723*cef8759bSmrg   {
2724*cef8759bSmrg     "simd", false, false,
2725*cef8759bSmrg     {
2726*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2727*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
2728*cef8759bSmrg       isa_nobit
2729*cef8759bSmrg     }
2730*cef8759bSmrg   },
2731*cef8759bSmrg   {
2732*cef8759bSmrg     "crypto", false, false,
2733*cef8759bSmrg     {
2734*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2735*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
2736*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2737*cef8759bSmrg     }
2738*cef8759bSmrg   },
2739*cef8759bSmrg   {
2740*cef8759bSmrg     "nocrypto", true, false,
2741*cef8759bSmrg     {
2742*cef8759bSmrg       isa_bit_crypto, isa_nobit
2743*cef8759bSmrg     }
2744*cef8759bSmrg   },
2745*cef8759bSmrg   {
2746*cef8759bSmrg     "nofp", true, false,
2747*cef8759bSmrg     {
2748*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2749*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2750*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2751*cef8759bSmrg     }
2752*cef8759bSmrg   },
2753*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2754*cef8759bSmrg };
2755*cef8759bSmrg 
2756*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = {
2757*cef8759bSmrg   {
2758*cef8759bSmrg     "simd", false, false,
2759*cef8759bSmrg     {
2760*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2761*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
2762*cef8759bSmrg       isa_nobit
2763*cef8759bSmrg     }
2764*cef8759bSmrg   },
2765*cef8759bSmrg   {
2766*cef8759bSmrg     "fp16", false, false,
2767*cef8759bSmrg     {
2768*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2769*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2770*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2771*cef8759bSmrg     }
2772*cef8759bSmrg   },
2773*cef8759bSmrg   {
2774*cef8759bSmrg     "fp16fml", false, false,
2775*cef8759bSmrg     {
2776*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml,
2777*cef8759bSmrg       isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16,
2778*cef8759bSmrg       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2779*cef8759bSmrg     }
2780*cef8759bSmrg   },
2781*cef8759bSmrg   {
2782*cef8759bSmrg     "crypto", false, false,
2783*cef8759bSmrg     {
2784*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2785*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
2786*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2787*cef8759bSmrg     }
2788*cef8759bSmrg   },
2789*cef8759bSmrg   {
2790*cef8759bSmrg     "nocrypto", true, false,
2791*cef8759bSmrg     {
2792*cef8759bSmrg       isa_bit_crypto, isa_nobit
2793*cef8759bSmrg     }
2794*cef8759bSmrg   },
2795*cef8759bSmrg   {
2796*cef8759bSmrg     "nofp", true, false,
2797*cef8759bSmrg     {
2798*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2799*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2800*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2801*cef8759bSmrg     }
2802*cef8759bSmrg   },
2803*cef8759bSmrg   {
2804*cef8759bSmrg     "dotprod", false, false,
2805*cef8759bSmrg     {
2806*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
2807*cef8759bSmrg       isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2808*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2809*cef8759bSmrg     }
2810*cef8759bSmrg   },
2811*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2812*cef8759bSmrg };
2813*cef8759bSmrg 
2814*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv8_3_a[] = {
2815*cef8759bSmrg   {
2816*cef8759bSmrg     "simd", false, false,
2817*cef8759bSmrg     {
2818*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2819*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
2820*cef8759bSmrg       isa_nobit
2821*cef8759bSmrg     }
2822*cef8759bSmrg   },
2823*cef8759bSmrg   {
2824*cef8759bSmrg     "fp16", false, false,
2825*cef8759bSmrg     {
2826*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2827*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2828*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2829*cef8759bSmrg     }
2830*cef8759bSmrg   },
2831*cef8759bSmrg   {
2832*cef8759bSmrg     "fp16fml", false, false,
2833*cef8759bSmrg     {
2834*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml,
2835*cef8759bSmrg       isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16,
2836*cef8759bSmrg       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2837*cef8759bSmrg     }
2838*cef8759bSmrg   },
2839*cef8759bSmrg   {
2840*cef8759bSmrg     "crypto", false, false,
2841*cef8759bSmrg     {
2842*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2843*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
2844*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2845*cef8759bSmrg     }
2846*cef8759bSmrg   },
2847*cef8759bSmrg   {
2848*cef8759bSmrg     "nocrypto", true, false,
2849*cef8759bSmrg     {
2850*cef8759bSmrg       isa_bit_crypto, isa_nobit
2851*cef8759bSmrg     }
2852*cef8759bSmrg   },
2853*cef8759bSmrg   {
2854*cef8759bSmrg     "nofp", true, false,
2855*cef8759bSmrg     {
2856*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2857*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2858*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2859*cef8759bSmrg     }
2860*cef8759bSmrg   },
2861*cef8759bSmrg   {
2862*cef8759bSmrg     "dotprod", false, false,
2863*cef8759bSmrg     {
2864*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
2865*cef8759bSmrg       isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2866*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2867*cef8759bSmrg     }
2868*cef8759bSmrg   },
2869*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2870*cef8759bSmrg };
2871*cef8759bSmrg 
2872*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv8_4_a[] = {
2873*cef8759bSmrg   {
2874*cef8759bSmrg     "simd", false, false,
2875*cef8759bSmrg     {
2876*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
2877*cef8759bSmrg       isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2878*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2879*cef8759bSmrg     }
2880*cef8759bSmrg   },
2881*cef8759bSmrg   {
2882*cef8759bSmrg     "fp16", false, false,
2883*cef8759bSmrg     {
2884*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml,
2885*cef8759bSmrg       isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32,
2886*cef8759bSmrg       isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2887*cef8759bSmrg     }
2888*cef8759bSmrg   },
2889*cef8759bSmrg   {
2890*cef8759bSmrg     "crypto", false, false,
2891*cef8759bSmrg     {
2892*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
2893*cef8759bSmrg       isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2894*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2895*cef8759bSmrg     }
2896*cef8759bSmrg   },
2897*cef8759bSmrg   {
2898*cef8759bSmrg     "nocrypto", true, false,
2899*cef8759bSmrg     {
2900*cef8759bSmrg       isa_bit_crypto, isa_nobit
2901*cef8759bSmrg     }
2902*cef8759bSmrg   },
2903*cef8759bSmrg   {
2904*cef8759bSmrg     "nofp", true, false,
2905*cef8759bSmrg     {
2906*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2907*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2908*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2909*cef8759bSmrg     }
2910*cef8759bSmrg   },
2911*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2912*cef8759bSmrg };
2913*cef8759bSmrg 
2914*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = {
2915*cef8759bSmrg   {
2916*cef8759bSmrg     "dsp", false, false,
2917*cef8759bSmrg     {
2918*cef8759bSmrg       isa_bit_armv7em, isa_nobit
2919*cef8759bSmrg     }
2920*cef8759bSmrg   },
2921*cef8759bSmrg   {
2922*cef8759bSmrg     "fp", false, false,
2923*cef8759bSmrg     {
2924*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
2925*cef8759bSmrg       isa_bit_fp16conv, isa_nobit
2926*cef8759bSmrg     }
2927*cef8759bSmrg   },
2928*cef8759bSmrg   {
2929*cef8759bSmrg     "fp.dp", false, false,
2930*cef8759bSmrg     {
2931*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
2932*cef8759bSmrg       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2933*cef8759bSmrg     }
2934*cef8759bSmrg   },
2935*cef8759bSmrg   {
2936*cef8759bSmrg     "nofp", true, false,
2937*cef8759bSmrg     {
2938*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2939*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2940*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2941*cef8759bSmrg     }
2942*cef8759bSmrg   },
2943*cef8759bSmrg   {
2944*cef8759bSmrg     "nodsp", true, false,
2945*cef8759bSmrg     {
2946*cef8759bSmrg       isa_bit_armv7em, isa_nobit
2947*cef8759bSmrg     }
2948*cef8759bSmrg   },
2949*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2950*cef8759bSmrg };
2951*cef8759bSmrg 
2952*cef8759bSmrg static const struct cpu_arch_extension arch_opttab_armv8_r[] = {
2953*cef8759bSmrg   {
2954*cef8759bSmrg     "crc", false, false,
2955*cef8759bSmrg     {
2956*cef8759bSmrg       isa_bit_crc32, isa_nobit
2957*cef8759bSmrg     }
2958*cef8759bSmrg   },
2959*cef8759bSmrg   {
2960*cef8759bSmrg     "fp.sp", false, false,
2961*cef8759bSmrg     {
2962*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
2963*cef8759bSmrg       isa_bit_fp16conv, isa_nobit
2964*cef8759bSmrg     }
2965*cef8759bSmrg   },
2966*cef8759bSmrg   {
2967*cef8759bSmrg     "simd", false, false,
2968*cef8759bSmrg     {
2969*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2970*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
2971*cef8759bSmrg       isa_nobit
2972*cef8759bSmrg     }
2973*cef8759bSmrg   },
2974*cef8759bSmrg   {
2975*cef8759bSmrg     "crypto", false, false,
2976*cef8759bSmrg     {
2977*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2978*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
2979*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
2980*cef8759bSmrg     }
2981*cef8759bSmrg   },
2982*cef8759bSmrg   {
2983*cef8759bSmrg     "nocrypto", true, false,
2984*cef8759bSmrg     {
2985*cef8759bSmrg       isa_bit_crypto, isa_nobit
2986*cef8759bSmrg     }
2987*cef8759bSmrg   },
2988*cef8759bSmrg   {
2989*cef8759bSmrg     "nofp", true, false,
2990*cef8759bSmrg     {
2991*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2992*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2993*cef8759bSmrg       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2994*cef8759bSmrg     }
2995*cef8759bSmrg   },
2996*cef8759bSmrg   { NULL, false, false, {isa_nobit}}
2997*cef8759bSmrg };
2998*cef8759bSmrg 
2999*cef8759bSmrg const arch_option all_architectures[] =
3000*cef8759bSmrg {
3001*cef8759bSmrg   {
3002*cef8759bSmrg     "armv2",
3003*cef8759bSmrg     NULL,
3004*cef8759bSmrg     {
3005*cef8759bSmrg       isa_bit_mode26, isa_bit_notm, isa_nobit
3006*cef8759bSmrg     },
3007*cef8759bSmrg     "2", BASE_ARCH_2,
3008*cef8759bSmrg     0,
3009*cef8759bSmrg     TARGET_CPU_arm2,
3010*cef8759bSmrg   },
3011*cef8759bSmrg   {
3012*cef8759bSmrg     "armv2a",
3013*cef8759bSmrg     NULL,
3014*cef8759bSmrg     {
3015*cef8759bSmrg       isa_bit_mode26, isa_bit_notm, isa_nobit
3016*cef8759bSmrg     },
3017*cef8759bSmrg     "2", BASE_ARCH_2,
3018*cef8759bSmrg     0,
3019*cef8759bSmrg     TARGET_CPU_arm2,
3020*cef8759bSmrg   },
3021*cef8759bSmrg   {
3022*cef8759bSmrg     "armv3",
3023*cef8759bSmrg     NULL,
3024*cef8759bSmrg     {
3025*cef8759bSmrg       isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
3026*cef8759bSmrg     },
3027*cef8759bSmrg     "3", BASE_ARCH_3,
3028*cef8759bSmrg     0,
3029*cef8759bSmrg     TARGET_CPU_arm6,
3030*cef8759bSmrg   },
3031*cef8759bSmrg   {
3032*cef8759bSmrg     "armv3m",
3033*cef8759bSmrg     NULL,
3034*cef8759bSmrg     {
3035*cef8759bSmrg       isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_bit_armv3m,
3036*cef8759bSmrg       isa_nobit
3037*cef8759bSmrg     },
3038*cef8759bSmrg     "3M", BASE_ARCH_3M,
3039*cef8759bSmrg     0,
3040*cef8759bSmrg     TARGET_CPU_arm7m,
3041*cef8759bSmrg   },
3042*cef8759bSmrg   {
3043*cef8759bSmrg     "armv4",
3044*cef8759bSmrg     NULL,
3045*cef8759bSmrg     {
3046*cef8759bSmrg       isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
3047*cef8759bSmrg       isa_bit_armv3m, isa_nobit
3048*cef8759bSmrg     },
3049*cef8759bSmrg     "4", BASE_ARCH_4,
3050*cef8759bSmrg     0,
3051*cef8759bSmrg     TARGET_CPU_arm7tdmi,
3052*cef8759bSmrg   },
3053*cef8759bSmrg   {
3054*cef8759bSmrg     "armv4t",
3055*cef8759bSmrg     NULL,
3056*cef8759bSmrg     {
3057*cef8759bSmrg       isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
3058*cef8759bSmrg       isa_bit_armv3m, isa_nobit
3059*cef8759bSmrg     },
3060*cef8759bSmrg     "4T", BASE_ARCH_4T,
3061*cef8759bSmrg     0,
3062*cef8759bSmrg     TARGET_CPU_arm7tdmi,
3063*cef8759bSmrg   },
3064*cef8759bSmrg   {
3065*cef8759bSmrg     "armv5",
3066*cef8759bSmrg     NULL,
3067*cef8759bSmrg     {
3068*cef8759bSmrg       isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, isa_bit_notm,
3069*cef8759bSmrg       isa_bit_armv3m, isa_nobit
3070*cef8759bSmrg     },
3071*cef8759bSmrg     "5", BASE_ARCH_5,
3072*cef8759bSmrg     0,
3073*cef8759bSmrg     TARGET_CPU_arm10tdmi,
3074*cef8759bSmrg   },
3075*cef8759bSmrg   {
3076*cef8759bSmrg     "armv5t",
3077*cef8759bSmrg     NULL,
3078*cef8759bSmrg     {
3079*cef8759bSmrg       isa_bit_thumb, isa_bit_armv4, isa_bit_armv5, isa_bit_mode32,
3080*cef8759bSmrg       isa_bit_notm, isa_bit_armv3m, isa_nobit
3081*cef8759bSmrg     },
3082*cef8759bSmrg     "5T", BASE_ARCH_5T,
3083*cef8759bSmrg     0,
3084*cef8759bSmrg     TARGET_CPU_arm10tdmi,
3085*cef8759bSmrg   },
3086*cef8759bSmrg   {
3087*cef8759bSmrg     "armv5e",
3088*cef8759bSmrg     arch_opttab_armv5e,
3089*cef8759bSmrg     {
3090*cef8759bSmrg       isa_bit_armv5e, isa_bit_armv4, isa_bit_armv5, isa_bit_mode32,
3091*cef8759bSmrg       isa_bit_notm, isa_bit_armv3m, isa_nobit
3092*cef8759bSmrg     },
3093*cef8759bSmrg     "5E", BASE_ARCH_5E,
3094*cef8759bSmrg     0,
3095*cef8759bSmrg     TARGET_CPU_arm1026ejs,
3096*cef8759bSmrg   },
3097*cef8759bSmrg   {
3098*cef8759bSmrg     "armv5te",
3099*cef8759bSmrg     arch_opttab_armv5te,
3100*cef8759bSmrg     {
3101*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5,
3102*cef8759bSmrg       isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit
3103*cef8759bSmrg     },
3104*cef8759bSmrg     "5TE", BASE_ARCH_5TE,
3105*cef8759bSmrg     0,
3106*cef8759bSmrg     TARGET_CPU_arm1026ejs,
3107*cef8759bSmrg   },
3108*cef8759bSmrg   {
3109*cef8759bSmrg     "armv5tej",
3110*cef8759bSmrg     arch_opttab_armv5tej,
3111*cef8759bSmrg     {
3112*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5,
3113*cef8759bSmrg       isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit
3114*cef8759bSmrg     },
3115*cef8759bSmrg     "5TEJ", BASE_ARCH_5TEJ,
3116*cef8759bSmrg     0,
3117*cef8759bSmrg     TARGET_CPU_arm1026ejs,
3118*cef8759bSmrg   },
3119*cef8759bSmrg   {
3120*cef8759bSmrg     "armv6",
3121*cef8759bSmrg     arch_opttab_armv6,
3122*cef8759bSmrg     {
3123*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3124*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm,
3125*cef8759bSmrg       isa_bit_armv3m, isa_nobit
3126*cef8759bSmrg     },
3127*cef8759bSmrg     "6", BASE_ARCH_6,
3128*cef8759bSmrg     0,
3129*cef8759bSmrg     TARGET_CPU_arm1136js,
3130*cef8759bSmrg   },
3131*cef8759bSmrg   {
3132*cef8759bSmrg     "armv6j",
3133*cef8759bSmrg     arch_opttab_armv6j,
3134*cef8759bSmrg     {
3135*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3136*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm,
3137*cef8759bSmrg       isa_bit_armv3m, isa_nobit
3138*cef8759bSmrg     },
3139*cef8759bSmrg     "6J", BASE_ARCH_6J,
3140*cef8759bSmrg     0,
3141*cef8759bSmrg     TARGET_CPU_arm1136js,
3142*cef8759bSmrg   },
3143*cef8759bSmrg   {
3144*cef8759bSmrg     "armv6k",
3145*cef8759bSmrg     arch_opttab_armv6k,
3146*cef8759bSmrg     {
3147*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3148*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm,
3149*cef8759bSmrg       isa_bit_armv6k, isa_bit_armv3m, isa_nobit
3150*cef8759bSmrg     },
3151*cef8759bSmrg     "6K", BASE_ARCH_6K,
3152*cef8759bSmrg     0,
3153*cef8759bSmrg     TARGET_CPU_mpcore,
3154*cef8759bSmrg   },
3155*cef8759bSmrg   {
3156*cef8759bSmrg     "armv6z",
3157*cef8759bSmrg     arch_opttab_armv6z,
3158*cef8759bSmrg     {
3159*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3160*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm,
3161*cef8759bSmrg       isa_bit_armv3m, isa_nobit
3162*cef8759bSmrg     },
3163*cef8759bSmrg     "6Z", BASE_ARCH_6Z,
3164*cef8759bSmrg     0,
3165*cef8759bSmrg     TARGET_CPU_arm1176jzs,
3166*cef8759bSmrg   },
3167*cef8759bSmrg   {
3168*cef8759bSmrg     "armv6kz",
3169*cef8759bSmrg     arch_opttab_armv6kz,
3170*cef8759bSmrg     {
3171*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3172*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_quirk_armv6kz, isa_bit_mode32,
3173*cef8759bSmrg       isa_bit_notm, isa_bit_armv6k, isa_bit_armv3m, isa_nobit
3174*cef8759bSmrg     },
3175*cef8759bSmrg     "6KZ", BASE_ARCH_6KZ,
3176*cef8759bSmrg     0,
3177*cef8759bSmrg     TARGET_CPU_arm1176jzs,
3178*cef8759bSmrg   },
3179*cef8759bSmrg   {
3180*cef8759bSmrg     "armv6zk",
3181*cef8759bSmrg     arch_opttab_armv6zk,
3182*cef8759bSmrg     {
3183*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3184*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_quirk_armv6kz, isa_bit_mode32,
3185*cef8759bSmrg       isa_bit_notm, isa_bit_armv6k, isa_bit_armv3m, isa_nobit
3186*cef8759bSmrg     },
3187*cef8759bSmrg     "6KZ", BASE_ARCH_6KZ,
3188*cef8759bSmrg     0,
3189*cef8759bSmrg     TARGET_CPU_arm1176jzs,
3190*cef8759bSmrg   },
3191*cef8759bSmrg   {
3192*cef8759bSmrg     "armv6t2",
3193*cef8759bSmrg     arch_opttab_armv6t2,
3194*cef8759bSmrg     {
3195*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3196*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_thumb2,
3197*cef8759bSmrg       isa_bit_notm, isa_bit_armv3m, isa_nobit
3198*cef8759bSmrg     },
3199*cef8759bSmrg     "6T2", BASE_ARCH_6T2,
3200*cef8759bSmrg     0,
3201*cef8759bSmrg     TARGET_CPU_arm1156t2s,
3202*cef8759bSmrg   },
3203*cef8759bSmrg   {
3204*cef8759bSmrg     "armv6-m",
3205*cef8759bSmrg     NULL,
3206*cef8759bSmrg     {
3207*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3208*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
3209*cef8759bSmrg       isa_nobit
3210*cef8759bSmrg     },
3211*cef8759bSmrg     "6M", BASE_ARCH_6M,
3212*cef8759bSmrg     'M',
3213*cef8759bSmrg     TARGET_CPU_cortexm1,
3214*cef8759bSmrg   },
3215*cef8759bSmrg   {
3216*cef8759bSmrg     "armv6s-m",
3217*cef8759bSmrg     NULL,
3218*cef8759bSmrg     {
3219*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3220*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
3221*cef8759bSmrg       isa_nobit
3222*cef8759bSmrg     },
3223*cef8759bSmrg     "6M", BASE_ARCH_6M,
3224*cef8759bSmrg     'M',
3225*cef8759bSmrg     TARGET_CPU_cortexm1,
3226*cef8759bSmrg   },
3227*cef8759bSmrg   {
3228*cef8759bSmrg     "armv7",
3229*cef8759bSmrg     arch_opttab_armv7,
3230*cef8759bSmrg     {
3231*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3232*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_mode32,
3233*cef8759bSmrg       isa_bit_thumb2, isa_bit_armv3m, isa_nobit
3234*cef8759bSmrg     },
3235*cef8759bSmrg     "7", BASE_ARCH_7,
3236*cef8759bSmrg     0,
3237*cef8759bSmrg     TARGET_CPU_cortexa8,
3238*cef8759bSmrg   },
3239*cef8759bSmrg   {
3240*cef8759bSmrg     "armv7-a",
3241*cef8759bSmrg     arch_opttab_armv7_a,
3242*cef8759bSmrg     {
3243*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3244*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_mode32,
3245*cef8759bSmrg       isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_armv3m,
3246*cef8759bSmrg       isa_nobit
3247*cef8759bSmrg     },
3248*cef8759bSmrg     "7A", BASE_ARCH_7A,
3249*cef8759bSmrg     'A',
3250*cef8759bSmrg     TARGET_CPU_cortexa8,
3251*cef8759bSmrg   },
3252*cef8759bSmrg   {
3253*cef8759bSmrg     "armv7ve",
3254*cef8759bSmrg     arch_opttab_armv7ve,
3255*cef8759bSmrg     {
3256*cef8759bSmrg       isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
3257*cef8759bSmrg       isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
3258*cef8759bSmrg       isa_bit_armv7, isa_bit_tdiv, isa_bit_mode32, isa_bit_thumb2,
3259*cef8759bSmrg       isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec,
3260*cef8759bSmrg       isa_bit_armv3m, isa_nobit
3261*cef8759bSmrg     },
3262*cef8759bSmrg     "7A", BASE_ARCH_7A,
3263*cef8759bSmrg     'A',
3264*cef8759bSmrg     TARGET_CPU_cortexa8,
3265*cef8759bSmrg   },
3266*cef8759bSmrg   {
3267*cef8759bSmrg     "armv7-r",
3268*cef8759bSmrg     arch_opttab_armv7_r,
3269*cef8759bSmrg     {
3270*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3271*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv,
3272*cef8759bSmrg       isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k,
3273*cef8759bSmrg       isa_bit_armv3m, isa_nobit
3274*cef8759bSmrg     },
3275*cef8759bSmrg     "7R", BASE_ARCH_7R,
3276*cef8759bSmrg     'R',
3277*cef8759bSmrg     TARGET_CPU_cortexr4,
3278*cef8759bSmrg   },
3279*cef8759bSmrg   {
3280*cef8759bSmrg     "armv7-m",
3281*cef8759bSmrg     NULL,
3282*cef8759bSmrg     {
3283*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3284*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv,
3285*cef8759bSmrg       isa_bit_mode32, isa_bit_thumb2, isa_bit_armv3m, isa_nobit
3286*cef8759bSmrg     },
3287*cef8759bSmrg     "7M", BASE_ARCH_7M,
3288*cef8759bSmrg     'M',
3289*cef8759bSmrg     TARGET_CPU_cortexm3,
3290*cef8759bSmrg   },
3291*cef8759bSmrg   {
3292*cef8759bSmrg     "armv7e-m",
3293*cef8759bSmrg     arch_opttab_armv7e_m,
3294*cef8759bSmrg     {
3295*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3296*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7,
3297*cef8759bSmrg       isa_bit_tdiv, isa_bit_mode32, isa_bit_thumb2, isa_bit_armv3m,
3298*cef8759bSmrg       isa_nobit
3299*cef8759bSmrg     },
3300*cef8759bSmrg     "7EM", BASE_ARCH_7EM,
3301*cef8759bSmrg     'M',
3302*cef8759bSmrg     TARGET_CPU_cortexm4,
3303*cef8759bSmrg   },
3304*cef8759bSmrg   {
3305*cef8759bSmrg     "armv8-a",
3306*cef8759bSmrg     arch_opttab_armv8_a,
3307*cef8759bSmrg     {
3308*cef8759bSmrg       isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
3309*cef8759bSmrg       isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
3310*cef8759bSmrg       isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_mode32,
3311*cef8759bSmrg       isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_mp,
3312*cef8759bSmrg       isa_bit_sec, isa_bit_armv3m, isa_nobit
3313*cef8759bSmrg     },
3314*cef8759bSmrg     "8A", BASE_ARCH_8A,
3315*cef8759bSmrg     'A',
3316*cef8759bSmrg     TARGET_CPU_cortexa53,
3317*cef8759bSmrg   },
3318*cef8759bSmrg   {
3319*cef8759bSmrg     "armv8.1-a",
3320*cef8759bSmrg     arch_opttab_armv8_1_a,
3321*cef8759bSmrg     {
3322*cef8759bSmrg       isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
3323*cef8759bSmrg       isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
3324*cef8759bSmrg       isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, isa_bit_tdiv,
3325*cef8759bSmrg       isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1,
3326*cef8759bSmrg       isa_bit_armv6k, isa_bit_mp, isa_bit_sec, isa_bit_armv3m,
3327*cef8759bSmrg       isa_nobit
3328*cef8759bSmrg     },
3329*cef8759bSmrg     "8A", BASE_ARCH_8A,
3330*cef8759bSmrg     'A',
3331*cef8759bSmrg     TARGET_CPU_cortexa53,
3332*cef8759bSmrg   },
3333*cef8759bSmrg   {
3334*cef8759bSmrg     "armv8.2-a",
3335*cef8759bSmrg     arch_opttab_armv8_2_a,
3336*cef8759bSmrg     {
3337*cef8759bSmrg       isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
3338*cef8759bSmrg       isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
3339*cef8759bSmrg       isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv,
3340*cef8759bSmrg       isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1,
3341*cef8759bSmrg       isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_sec,
3342*cef8759bSmrg       isa_bit_armv3m, isa_nobit
3343*cef8759bSmrg     },
3344*cef8759bSmrg     "8A", BASE_ARCH_8A,
3345*cef8759bSmrg     'A',
3346*cef8759bSmrg     TARGET_CPU_cortexa53,
3347*cef8759bSmrg   },
3348*cef8759bSmrg   {
3349*cef8759bSmrg     "armv8.3-a",
3350*cef8759bSmrg     arch_opttab_armv8_3_a,
3351*cef8759bSmrg     {
3352*cef8759bSmrg       isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
3353*cef8759bSmrg       isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
3354*cef8759bSmrg       isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv,
3355*cef8759bSmrg       isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1,
3356*cef8759bSmrg       isa_bit_armv8_2, isa_bit_armv6k, isa_bit_armv8_3, isa_bit_mp,
3357*cef8759bSmrg       isa_bit_sec, isa_bit_armv3m, isa_nobit
3358*cef8759bSmrg     },
3359*cef8759bSmrg     "8A", BASE_ARCH_8A,
3360*cef8759bSmrg     'A',
3361*cef8759bSmrg     TARGET_CPU_cortexa53,
3362*cef8759bSmrg   },
3363*cef8759bSmrg   {
3364*cef8759bSmrg     "armv8.4-a",
3365*cef8759bSmrg     arch_opttab_armv8_4_a,
3366*cef8759bSmrg     {
3367*cef8759bSmrg       isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
3368*cef8759bSmrg       isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
3369*cef8759bSmrg       isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv,
3370*cef8759bSmrg       isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1,
3371*cef8759bSmrg       isa_bit_armv8_2, isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4,
3372*cef8759bSmrg       isa_bit_mp, isa_bit_sec, isa_bit_armv3m, isa_nobit
3373*cef8759bSmrg     },
3374*cef8759bSmrg     "8A", BASE_ARCH_8A,
3375*cef8759bSmrg     'A',
3376*cef8759bSmrg     TARGET_CPU_cortexa53,
3377*cef8759bSmrg   },
3378*cef8759bSmrg   {
3379*cef8759bSmrg     "armv8-m.base",
3380*cef8759bSmrg     NULL,
3381*cef8759bSmrg     {
3382*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3383*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_armv8, isa_bit_cmse,
3384*cef8759bSmrg       isa_bit_tdiv, isa_bit_mode32, isa_bit_armv3m, isa_nobit
3385*cef8759bSmrg     },
3386*cef8759bSmrg     "8M_BASE", BASE_ARCH_8M_BASE,
3387*cef8759bSmrg     'M',
3388*cef8759bSmrg     TARGET_CPU_cortexm23,
3389*cef8759bSmrg   },
3390*cef8759bSmrg   {
3391*cef8759bSmrg     "armv8-m.main",
3392*cef8759bSmrg     arch_opttab_armv8_m_main,
3393*cef8759bSmrg     {
3394*cef8759bSmrg       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3395*cef8759bSmrg       isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_armv8,
3396*cef8759bSmrg       isa_bit_cmse, isa_bit_tdiv, isa_bit_mode32, isa_bit_thumb2,
3397*cef8759bSmrg       isa_bit_armv3m, isa_nobit
3398*cef8759bSmrg     },
3399*cef8759bSmrg     "8M_MAIN", BASE_ARCH_8M_MAIN,
3400*cef8759bSmrg     'M',
3401*cef8759bSmrg     TARGET_CPU_cortexm7,
3402*cef8759bSmrg   },
3403*cef8759bSmrg   {
3404*cef8759bSmrg     "armv8-r",
3405*cef8759bSmrg     arch_opttab_armv8_r,
3406*cef8759bSmrg     {
3407*cef8759bSmrg       isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
3408*cef8759bSmrg       isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
3409*cef8759bSmrg       isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_mode32,
3410*cef8759bSmrg       isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_mp,
3411*cef8759bSmrg       isa_bit_sec, isa_bit_armv3m, isa_nobit
3412*cef8759bSmrg     },
3413*cef8759bSmrg     "8R", BASE_ARCH_8R,
3414*cef8759bSmrg     'R',
3415*cef8759bSmrg     TARGET_CPU_cortexr52,
3416*cef8759bSmrg   },
3417*cef8759bSmrg   {
3418*cef8759bSmrg     "iwmmxt",
3419*cef8759bSmrg     NULL,
3420*cef8759bSmrg     {
3421*cef8759bSmrg       isa_bit_armv5e, isa_bit_iwmmxt, isa_bit_xscale, isa_bit_thumb,
3422*cef8759bSmrg       isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, isa_bit_notm,
3423*cef8759bSmrg       isa_bit_armv3m, isa_nobit
3424*cef8759bSmrg     },
3425*cef8759bSmrg     "5TE", BASE_ARCH_5TE,
3426*cef8759bSmrg     0,
3427*cef8759bSmrg     TARGET_CPU_iwmmxt,
3428*cef8759bSmrg   },
3429*cef8759bSmrg   {
3430*cef8759bSmrg     "iwmmxt2",
3431*cef8759bSmrg     NULL,
3432*cef8759bSmrg     {
3433*cef8759bSmrg       isa_bit_armv5e, isa_bit_iwmmxt, isa_bit_xscale, isa_bit_thumb,
3434*cef8759bSmrg       isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, isa_bit_iwmmxt2,
3435*cef8759bSmrg       isa_bit_notm, isa_bit_armv3m, isa_nobit
3436*cef8759bSmrg     },
3437*cef8759bSmrg     "5TE", BASE_ARCH_5TE,
3438*cef8759bSmrg     0,
3439*cef8759bSmrg     TARGET_CPU_iwmmxt2,
3440*cef8759bSmrg   },
3441*cef8759bSmrg   {{NULL, NULL, {isa_nobit}},
3442*cef8759bSmrg    NULL, BASE_ARCH_0, 0, TARGET_CPU_arm_none}
3443*cef8759bSmrg };
3444*cef8759bSmrg 
3445*cef8759bSmrg const arm_fpu_desc all_fpus[] =
3446*cef8759bSmrg {
3447*cef8759bSmrg   {
3448*cef8759bSmrg     "vfp",
3449*cef8759bSmrg     {
3450*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
3451*cef8759bSmrg     }
3452*cef8759bSmrg   },
3453*cef8759bSmrg   {
3454*cef8759bSmrg     "vfpv2",
3455*cef8759bSmrg     {
3456*cef8759bSmrg       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
3457*cef8759bSmrg     }
3458*cef8759bSmrg   },
3459*cef8759bSmrg   {
3460*cef8759bSmrg     "vfpv3",
3461*cef8759bSmrg     {
3462*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl,
3463*cef8759bSmrg       isa_nobit
3464*cef8759bSmrg     }
3465*cef8759bSmrg   },
3466*cef8759bSmrg   {
3467*cef8759bSmrg     "vfpv3-fp16",
3468*cef8759bSmrg     {
3469*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv,
3470*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
3471*cef8759bSmrg     }
3472*cef8759bSmrg   },
3473*cef8759bSmrg   {
3474*cef8759bSmrg     "vfpv3-d16",
3475*cef8759bSmrg     {
3476*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
3477*cef8759bSmrg     }
3478*cef8759bSmrg   },
3479*cef8759bSmrg   {
3480*cef8759bSmrg     "vfpv3-d16-fp16",
3481*cef8759bSmrg     {
3482*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl,
3483*cef8759bSmrg       isa_nobit
3484*cef8759bSmrg     }
3485*cef8759bSmrg   },
3486*cef8759bSmrg   {
3487*cef8759bSmrg     "vfpv3xd",
3488*cef8759bSmrg     {
3489*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit
3490*cef8759bSmrg     }
3491*cef8759bSmrg   },
3492*cef8759bSmrg   {
3493*cef8759bSmrg     "vfpv3xd-fp16",
3494*cef8759bSmrg     {
3495*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit
3496*cef8759bSmrg     }
3497*cef8759bSmrg   },
3498*cef8759bSmrg   {
3499*cef8759bSmrg     "neon",
3500*cef8759bSmrg     {
3501*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
3502*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
3503*cef8759bSmrg     }
3504*cef8759bSmrg   },
3505*cef8759bSmrg   {
3506*cef8759bSmrg     "neon-vfpv3",
3507*cef8759bSmrg     {
3508*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
3509*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
3510*cef8759bSmrg     }
3511*cef8759bSmrg   },
3512*cef8759bSmrg   {
3513*cef8759bSmrg     "neon-fp16",
3514*cef8759bSmrg     {
3515*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
3516*cef8759bSmrg       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3517*cef8759bSmrg     }
3518*cef8759bSmrg   },
3519*cef8759bSmrg   {
3520*cef8759bSmrg     "vfpv4",
3521*cef8759bSmrg     {
3522*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32,
3523*cef8759bSmrg       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3524*cef8759bSmrg     }
3525*cef8759bSmrg   },
3526*cef8759bSmrg   {
3527*cef8759bSmrg     "neon-vfpv4",
3528*cef8759bSmrg     {
3529*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
3530*cef8759bSmrg       isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3531*cef8759bSmrg     }
3532*cef8759bSmrg   },
3533*cef8759bSmrg   {
3534*cef8759bSmrg     "vfpv4-d16",
3535*cef8759bSmrg     {
3536*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
3537*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
3538*cef8759bSmrg     }
3539*cef8759bSmrg   },
3540*cef8759bSmrg   {
3541*cef8759bSmrg     "fpv4-sp-d16",
3542*cef8759bSmrg     {
3543*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
3544*cef8759bSmrg       isa_nobit
3545*cef8759bSmrg     }
3546*cef8759bSmrg   },
3547*cef8759bSmrg   {
3548*cef8759bSmrg     "fpv5-sp-d16",
3549*cef8759bSmrg     {
3550*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
3551*cef8759bSmrg       isa_bit_fp16conv, isa_nobit
3552*cef8759bSmrg     }
3553*cef8759bSmrg   },
3554*cef8759bSmrg   {
3555*cef8759bSmrg     "fpv5-d16",
3556*cef8759bSmrg     {
3557*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
3558*cef8759bSmrg       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3559*cef8759bSmrg     }
3560*cef8759bSmrg   },
3561*cef8759bSmrg   {
3562*cef8759bSmrg     "fp-armv8",
3563*cef8759bSmrg     {
3564*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
3565*cef8759bSmrg       isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3566*cef8759bSmrg     }
3567*cef8759bSmrg   },
3568*cef8759bSmrg   {
3569*cef8759bSmrg     "neon-fp-armv8",
3570*cef8759bSmrg     {
3571*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
3572*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
3573*cef8759bSmrg       isa_nobit
3574*cef8759bSmrg     }
3575*cef8759bSmrg   },
3576*cef8759bSmrg   {
3577*cef8759bSmrg     "crypto-neon-fp-armv8",
3578*cef8759bSmrg     {
3579*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
3580*cef8759bSmrg       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
3581*cef8759bSmrg       isa_bit_fp_dbl, isa_nobit
3582*cef8759bSmrg     }
3583*cef8759bSmrg   },
3584*cef8759bSmrg   {
3585*cef8759bSmrg     "vfp3",
3586*cef8759bSmrg     {
3587*cef8759bSmrg       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl,
3588*cef8759bSmrg       isa_nobit
3589*cef8759bSmrg     }
3590*cef8759bSmrg   },
3591*cef8759bSmrg };
3592