xref: /netbsd-src/external/gpl3/gcc.old/usr.bin/gcc/arch/armeb/arm-cpu-cdata.h (revision cef8759bd76c1b621f8eab8faa6f208faabc2e15)
1 /* This file is automatically generated.  DO NOT EDIT! */
2 /* Generated from: NetBSD: mknative-gcc,v 1.103 2019/10/24 03:19:14 christos Exp  */
3 /* Generated from: NetBSD: mknative.common,v 1.16 2018/04/15 15:13:37 christos Exp  */
4 
5 /* -*- buffer-read-only: t -*-
6    Generated automatically by parsecpu.awk from arm-cpus.in.
7    Do not edit.
8 
9    Copyright (C) 2011-2018 Free Software Foundation, Inc.
10 
11    This file is part of GCC.
12 
13    GCC is free software; you can redistribute it and/or modify
14    it under the terms of the GNU General Public License as
15    published by the Free Software Foundation; either version 3,
16    or (at your option) any later version.
17 
18    GCC is distributed in the hope that it will be useful,
19    but WITHOUT ANY WARRANTY; without even the implied warranty of
20    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21    GNU General Public License for more details.
22 
23    You should have received a copy of the GNU General Public
24    License along with GCC; see the file COPYING3.  If not see
25    <http://www.gnu.org/licenses/>.  */
26 
27 static const cpu_arch_extension cpu_opttab_arm9e[] = {
28   {
29     "nofp", true, false,
30     {
31       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
32       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
33       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
34     }
35   },
36   { NULL, false, false, {isa_nobit}}
37 };
38 
39 static const cpu_arch_extension cpu_opttab_arm946es[] = {
40   {
41     "nofp", true, false,
42     {
43       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
44       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
45       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
46     }
47   },
48   { NULL, false, false, {isa_nobit}}
49 };
50 
51 static const cpu_arch_extension cpu_opttab_arm966es[] = {
52   {
53     "nofp", true, false,
54     {
55       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
56       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
57       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
58     }
59   },
60   { NULL, false, false, {isa_nobit}}
61 };
62 
63 static const cpu_arch_extension cpu_opttab_arm968es[] = {
64   {
65     "nofp", true, false,
66     {
67       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
68       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
69       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
70     }
71   },
72   { NULL, false, false, {isa_nobit}}
73 };
74 
75 static const cpu_arch_extension cpu_opttab_arm10e[] = {
76   {
77     "nofp", true, false,
78     {
79       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
80       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
81       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
82     }
83   },
84   { NULL, false, false, {isa_nobit}}
85 };
86 
87 static const cpu_arch_extension cpu_opttab_arm1020e[] = {
88   {
89     "nofp", true, false,
90     {
91       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
92       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
93       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
94     }
95   },
96   { NULL, false, false, {isa_nobit}}
97 };
98 
99 static const cpu_arch_extension cpu_opttab_arm1022e[] = {
100   {
101     "nofp", true, false,
102     {
103       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
104       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
105       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
106     }
107   },
108   { NULL, false, false, {isa_nobit}}
109 };
110 
111 static const cpu_arch_extension cpu_opttab_arm926ejs[] = {
112   {
113     "nofp", true, false,
114     {
115       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
116       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
117       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
118     }
119   },
120   { NULL, false, false, {isa_nobit}}
121 };
122 
123 static const cpu_arch_extension cpu_opttab_arm1026ejs[] = {
124   {
125     "nofp", true, false,
126     {
127       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
128       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
129       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
130     }
131   },
132   { NULL, false, false, {isa_nobit}}
133 };
134 
135 static const cpu_arch_extension cpu_opttab_genericv7a[] = {
136   {
137     "mp", false, false,
138     {
139       isa_bit_mp, isa_nobit
140     }
141   },
142   {
143     "sec", false, false,
144     {
145       isa_bit_sec, isa_nobit
146     }
147   },
148   {
149     "vfpv3-d16", false, false,
150     {
151       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
152     }
153   },
154   {
155     "vfpv3", false, false,
156     {
157       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl,
158       isa_nobit
159     }
160   },
161   {
162     "vfpv3-d16-fp16", false, false,
163     {
164       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl,
165       isa_nobit
166     }
167   },
168   {
169     "vfpv3-fp16", false, false,
170     {
171       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv,
172       isa_bit_fp_dbl, isa_nobit
173     }
174   },
175   {
176     "vfpv4-d16", false, false,
177     {
178       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
179       isa_bit_fp_dbl, isa_nobit
180     }
181   },
182   {
183     "vfpv4", false, false,
184     {
185       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32,
186       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
187     }
188   },
189   {
190     "simd", false, false,
191     {
192       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
193       isa_bit_fp_dbl, isa_nobit
194     }
195   },
196   {
197     "neon-fp16", false, false,
198     {
199       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
200       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
201     }
202   },
203   {
204     "neon-vfpv4", false, false,
205     {
206       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
207       isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
208     }
209   },
210   {
211     "nosimd", true, false,
212     {
213       isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32,
214       isa_bit_crypto, isa_nobit
215     }
216   },
217   {
218     "nofp", true, false,
219     {
220       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
221       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
222       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
223     }
224   },
225   {
226     "neon", false, true,
227     {
228       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
229       isa_bit_fp_dbl, isa_nobit
230     }
231   },
232   {
233     "neon-vfpv3", false, true,
234     {
235       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
236       isa_bit_fp_dbl, isa_nobit
237     }
238   },
239   { NULL, false, false, {isa_nobit}}
240 };
241 
242 static const cpu_arch_extension cpu_opttab_cortexa5[] = {
243   {
244     "nosimd", true, false,
245     {
246       isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32,
247       isa_bit_crypto, isa_nobit
248     }
249   },
250   {
251     "nofp", true, false,
252     {
253       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
254       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
255       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
256     }
257   },
258   { NULL, false, false, {isa_nobit}}
259 };
260 
261 static const cpu_arch_extension cpu_opttab_cortexa7[] = {
262   {
263     "nosimd", true, false,
264     {
265       isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32,
266       isa_bit_crypto, isa_nobit
267     }
268   },
269   {
270     "nofp", true, false,
271     {
272       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
273       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
274       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
275     }
276   },
277   { NULL, false, false, {isa_nobit}}
278 };
279 
280 static const cpu_arch_extension cpu_opttab_cortexa8[] = {
281   {
282     "nofp", true, false,
283     {
284       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
285       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
286       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
287     }
288   },
289   { NULL, false, false, {isa_nobit}}
290 };
291 
292 static const cpu_arch_extension cpu_opttab_cortexa9[] = {
293   {
294     "nosimd", true, false,
295     {
296       isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32,
297       isa_bit_crypto, isa_nobit
298     }
299   },
300   {
301     "nofp", true, false,
302     {
303       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
304       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
305       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
306     }
307   },
308   { NULL, false, false, {isa_nobit}}
309 };
310 
311 static const cpu_arch_extension cpu_opttab_cortexa12[] = {
312   {
313     "nofp", true, false,
314     {
315       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
316       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
317       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
318     }
319   },
320   { NULL, false, false, {isa_nobit}}
321 };
322 
323 static const cpu_arch_extension cpu_opttab_cortexa15[] = {
324   {
325     "nofp", true, false,
326     {
327       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
328       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
329       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
330     }
331   },
332   { NULL, false, false, {isa_nobit}}
333 };
334 
335 static const cpu_arch_extension cpu_opttab_cortexa17[] = {
336   {
337     "nofp", true, false,
338     {
339       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
340       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
341       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
342     }
343   },
344   { NULL, false, false, {isa_nobit}}
345 };
346 
347 static const cpu_arch_extension cpu_opttab_cortexr5[] = {
348   {
349     "nofp.dp", true, false,
350     {
351       isa_bit_fp_dbl, isa_nobit
352     }
353   },
354   {
355     "nofp", true, false,
356     {
357       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
358       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
359       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
360     }
361   },
362   { NULL, false, false, {isa_nobit}}
363 };
364 
365 static const cpu_arch_extension cpu_opttab_cortexr7[] = {
366   {
367     "nofp.dp", true, false,
368     {
369       isa_bit_fp_dbl, isa_nobit
370     }
371   },
372   {
373     "nofp", true, false,
374     {
375       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
376       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
377       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
378     }
379   },
380   { NULL, false, false, {isa_nobit}}
381 };
382 
383 static const cpu_arch_extension cpu_opttab_cortexr8[] = {
384   {
385     "nofp.dp", true, false,
386     {
387       isa_bit_fp_dbl, isa_nobit
388     }
389   },
390   {
391     "nofp", true, false,
392     {
393       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
394       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
395       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
396     }
397   },
398   { NULL, false, false, {isa_nobit}}
399 };
400 
401 static const cpu_arch_extension cpu_opttab_cortexm7[] = {
402   {
403     "nofp.dp", true, false,
404     {
405       isa_bit_fp_dbl, isa_nobit
406     }
407   },
408   {
409     "nofp", true, false,
410     {
411       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
412       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
413       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
414     }
415   },
416   { NULL, false, false, {isa_nobit}}
417 };
418 
419 static const cpu_arch_extension cpu_opttab_cortexm4[] = {
420   {
421     "nofp", true, false,
422     {
423       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
424       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
425       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
426     }
427   },
428   { NULL, false, false, {isa_nobit}}
429 };
430 
431 static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = {
432   {
433     "nofp", true, false,
434     {
435       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
436       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
437       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
438     }
439   },
440   { NULL, false, false, {isa_nobit}}
441 };
442 
443 static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = {
444   {
445     "nofp", true, false,
446     {
447       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
448       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
449       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
450     }
451   },
452   { NULL, false, false, {isa_nobit}}
453 };
454 
455 static const cpu_arch_extension cpu_opttab_cortexa32[] = {
456   {
457     "crypto", false, false,
458     {
459       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
460       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
461       isa_bit_fp_dbl, isa_nobit
462     }
463   },
464   {
465     "nofp", true, false,
466     {
467       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
468       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
469       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
470     }
471   },
472   { NULL, false, false, {isa_nobit}}
473 };
474 
475 static const cpu_arch_extension cpu_opttab_cortexa35[] = {
476   {
477     "crypto", false, false,
478     {
479       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
480       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
481       isa_bit_fp_dbl, isa_nobit
482     }
483   },
484   {
485     "nofp", true, false,
486     {
487       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
488       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
489       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
490     }
491   },
492   { NULL, false, false, {isa_nobit}}
493 };
494 
495 static const cpu_arch_extension cpu_opttab_cortexa53[] = {
496   {
497     "crypto", false, false,
498     {
499       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
500       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
501       isa_bit_fp_dbl, isa_nobit
502     }
503   },
504   {
505     "nofp", true, false,
506     {
507       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
508       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
509       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
510     }
511   },
512   { NULL, false, false, {isa_nobit}}
513 };
514 
515 static const cpu_arch_extension cpu_opttab_cortexa57[] = {
516   {
517     "crypto", false, false,
518     {
519       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
520       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
521       isa_bit_fp_dbl, isa_nobit
522     }
523   },
524   { NULL, false, false, {isa_nobit}}
525 };
526 
527 static const cpu_arch_extension cpu_opttab_cortexa72[] = {
528   {
529     "crypto", false, false,
530     {
531       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
532       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
533       isa_bit_fp_dbl, isa_nobit
534     }
535   },
536   { NULL, false, false, {isa_nobit}}
537 };
538 
539 static const cpu_arch_extension cpu_opttab_cortexa73[] = {
540   {
541     "crypto", false, false,
542     {
543       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
544       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
545       isa_bit_fp_dbl, isa_nobit
546     }
547   },
548   { NULL, false, false, {isa_nobit}}
549 };
550 
551 static const cpu_arch_extension cpu_opttab_exynosm1[] = {
552   {
553     "crypto", false, false,
554     {
555       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
556       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
557       isa_bit_fp_dbl, isa_nobit
558     }
559   },
560   { NULL, false, false, {isa_nobit}}
561 };
562 
563 static const cpu_arch_extension cpu_opttab_xgene1[] = {
564   {
565     "crypto", false, false,
566     {
567       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
568       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
569       isa_bit_fp_dbl, isa_nobit
570     }
571   },
572   { NULL, false, false, {isa_nobit}}
573 };
574 
575 static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = {
576   {
577     "crypto", false, false,
578     {
579       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
580       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
581       isa_bit_fp_dbl, isa_nobit
582     }
583   },
584   { NULL, false, false, {isa_nobit}}
585 };
586 
587 static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = {
588   {
589     "crypto", false, false,
590     {
591       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
592       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
593       isa_bit_fp_dbl, isa_nobit
594     }
595   },
596   { NULL, false, false, {isa_nobit}}
597 };
598 
599 static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = {
600   {
601     "crypto", false, false,
602     {
603       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
604       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
605       isa_bit_fp_dbl, isa_nobit
606     }
607   },
608   { NULL, false, false, {isa_nobit}}
609 };
610 
611 static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = {
612   {
613     "crypto", false, false,
614     {
615       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
616       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
617       isa_bit_fp_dbl, isa_nobit
618     }
619   },
620   { NULL, false, false, {isa_nobit}}
621 };
622 
623 static const cpu_arch_extension cpu_opttab_cortexa55[] = {
624   {
625     "crypto", false, false,
626     {
627       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
628       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
629       isa_bit_fp_dbl, isa_nobit
630     }
631   },
632   {
633     "nofp", true, false,
634     {
635       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
636       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
637       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
638     }
639   },
640   { NULL, false, false, {isa_nobit}}
641 };
642 
643 static const cpu_arch_extension cpu_opttab_cortexa75[] = {
644   {
645     "crypto", false, false,
646     {
647       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
648       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
649       isa_bit_fp_dbl, isa_nobit
650     }
651   },
652   { NULL, false, false, {isa_nobit}}
653 };
654 
655 static const cpu_arch_extension cpu_opttab_cortexa75cortexa55[] = {
656   {
657     "crypto", false, false,
658     {
659       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
660       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
661       isa_bit_fp_dbl, isa_nobit
662     }
663   },
664   { NULL, false, false, {isa_nobit}}
665 };
666 
667 static const cpu_arch_extension cpu_opttab_cortexm33[] = {
668   {
669     "nofp", true, false,
670     {
671       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
672       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
673       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
674     }
675   },
676   {
677     "nodsp", true, false,
678     {
679       isa_bit_armv7em, isa_nobit
680     }
681   },
682   { NULL, false, false, {isa_nobit}}
683 };
684 
685 static const cpu_arch_extension cpu_opttab_cortexr52[] = {
686   {
687     "nofp.dp", true, false,
688     {
689       isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32,
690       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
691     }
692   },
693   { NULL, false, false, {isa_nobit}}
694 };
695 
696 const cpu_option all_cores[] =
697 {
698   {
699     {
700       "arm2",
701       NULL,
702       {
703         isa_bit_mode26, isa_bit_notm, isa_nobit
704       }
705     },
706     TARGET_ARCH_armv2
707   },
708   {
709     {
710       "arm250",
711       NULL,
712       {
713         isa_bit_mode26, isa_bit_notm, isa_nobit
714       }
715     },
716     TARGET_ARCH_armv2
717   },
718   {
719     {
720       "arm3",
721       NULL,
722       {
723         isa_bit_mode26, isa_bit_notm, isa_nobit
724       }
725     },
726     TARGET_ARCH_armv2
727   },
728   {
729     {
730       "arm6",
731       NULL,
732       {
733         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
734       }
735     },
736     TARGET_ARCH_armv3
737   },
738   {
739     {
740       "arm60",
741       NULL,
742       {
743         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
744       }
745     },
746     TARGET_ARCH_armv3
747   },
748   {
749     {
750       "arm600",
751       NULL,
752       {
753         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
754       }
755     },
756     TARGET_ARCH_armv3
757   },
758   {
759     {
760       "arm610",
761       NULL,
762       {
763         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
764       }
765     },
766     TARGET_ARCH_armv3
767   },
768   {
769     {
770       "arm620",
771       NULL,
772       {
773         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
774       }
775     },
776     TARGET_ARCH_armv3
777   },
778   {
779     {
780       "arm7",
781       NULL,
782       {
783         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
784       }
785     },
786     TARGET_ARCH_armv3
787   },
788   {
789     {
790       "arm7d",
791       NULL,
792       {
793         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
794       }
795     },
796     TARGET_ARCH_armv3
797   },
798   {
799     {
800       "arm7di",
801       NULL,
802       {
803         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
804       }
805     },
806     TARGET_ARCH_armv3
807   },
808   {
809     {
810       "arm70",
811       NULL,
812       {
813         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
814       }
815     },
816     TARGET_ARCH_armv3
817   },
818   {
819     {
820       "arm700",
821       NULL,
822       {
823         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
824       }
825     },
826     TARGET_ARCH_armv3
827   },
828   {
829     {
830       "arm700i",
831       NULL,
832       {
833         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
834       }
835     },
836     TARGET_ARCH_armv3
837   },
838   {
839     {
840       "arm710",
841       NULL,
842       {
843         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
844       }
845     },
846     TARGET_ARCH_armv3
847   },
848   {
849     {
850       "arm720",
851       NULL,
852       {
853         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
854       }
855     },
856     TARGET_ARCH_armv3
857   },
858   {
859     {
860       "arm710c",
861       NULL,
862       {
863         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
864       }
865     },
866     TARGET_ARCH_armv3
867   },
868   {
869     {
870       "arm7100",
871       NULL,
872       {
873         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
874       }
875     },
876     TARGET_ARCH_armv3
877   },
878   {
879     {
880       "arm7500",
881       NULL,
882       {
883         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
884       }
885     },
886     TARGET_ARCH_armv3
887   },
888   {
889     {
890       "arm7500fe",
891       NULL,
892       {
893         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
894       }
895     },
896     TARGET_ARCH_armv3
897   },
898   {
899     {
900       "arm7m",
901       NULL,
902       {
903         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_bit_armv3m,
904         isa_nobit
905       }
906     },
907     TARGET_ARCH_armv3m
908   },
909   {
910     {
911       "arm7dm",
912       NULL,
913       {
914         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_bit_armv3m,
915         isa_nobit
916       }
917     },
918     TARGET_ARCH_armv3m
919   },
920   {
921     {
922       "arm7dmi",
923       NULL,
924       {
925         isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_bit_armv3m,
926         isa_nobit
927       }
928     },
929     TARGET_ARCH_armv3m
930   },
931   {
932     {
933       "arm8",
934       NULL,
935       {
936         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
937         isa_bit_armv3m, isa_nobit
938       }
939     },
940     TARGET_ARCH_armv4
941   },
942   {
943     {
944       "arm810",
945       NULL,
946       {
947         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
948         isa_bit_armv3m, isa_nobit
949       }
950     },
951     TARGET_ARCH_armv4
952   },
953   {
954     {
955       "strongarm",
956       NULL,
957       {
958         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
959         isa_bit_armv3m, isa_nobit
960       }
961     },
962     TARGET_ARCH_armv4
963   },
964   {
965     {
966       "strongarm110",
967       NULL,
968       {
969         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
970         isa_bit_armv3m, isa_nobit
971       }
972     },
973     TARGET_ARCH_armv4
974   },
975   {
976     {
977       "strongarm1100",
978       NULL,
979       {
980         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
981         isa_bit_armv3m, isa_nobit
982       }
983     },
984     TARGET_ARCH_armv4
985   },
986   {
987     {
988       "strongarm1110",
989       NULL,
990       {
991         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
992         isa_bit_armv3m, isa_nobit
993       }
994     },
995     TARGET_ARCH_armv4
996   },
997   {
998     {
999       "fa526",
1000       NULL,
1001       {
1002         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1003         isa_bit_armv3m, isa_nobit
1004       }
1005     },
1006     TARGET_ARCH_armv4
1007   },
1008   {
1009     {
1010       "fa626",
1011       NULL,
1012       {
1013         isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1014         isa_bit_armv3m, isa_nobit
1015       }
1016     },
1017     TARGET_ARCH_armv4
1018   },
1019   {
1020     {
1021       "arm7tdmi",
1022       NULL,
1023       {
1024         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1025         isa_bit_armv3m, isa_nobit
1026       }
1027     },
1028     TARGET_ARCH_armv4t
1029   },
1030   {
1031     {
1032       "arm7tdmi-s",
1033       NULL,
1034       {
1035         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1036         isa_bit_armv3m, isa_nobit
1037       }
1038     },
1039     TARGET_ARCH_armv4t
1040   },
1041   {
1042     {
1043       "arm710t",
1044       NULL,
1045       {
1046         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1047         isa_bit_armv3m, isa_nobit
1048       }
1049     },
1050     TARGET_ARCH_armv4t
1051   },
1052   {
1053     {
1054       "arm720t",
1055       NULL,
1056       {
1057         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1058         isa_bit_armv3m, isa_nobit
1059       }
1060     },
1061     TARGET_ARCH_armv4t
1062   },
1063   {
1064     {
1065       "arm740t",
1066       NULL,
1067       {
1068         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1069         isa_bit_armv3m, isa_nobit
1070       }
1071     },
1072     TARGET_ARCH_armv4t
1073   },
1074   {
1075     {
1076       "arm9",
1077       NULL,
1078       {
1079         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1080         isa_bit_armv3m, isa_nobit
1081       }
1082     },
1083     TARGET_ARCH_armv4t
1084   },
1085   {
1086     {
1087       "arm9tdmi",
1088       NULL,
1089       {
1090         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1091         isa_bit_armv3m, isa_nobit
1092       }
1093     },
1094     TARGET_ARCH_armv4t
1095   },
1096   {
1097     {
1098       "arm920",
1099       NULL,
1100       {
1101         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1102         isa_bit_armv3m, isa_nobit
1103       }
1104     },
1105     TARGET_ARCH_armv4t
1106   },
1107   {
1108     {
1109       "arm920t",
1110       NULL,
1111       {
1112         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1113         isa_bit_armv3m, isa_nobit
1114       }
1115     },
1116     TARGET_ARCH_armv4t
1117   },
1118   {
1119     {
1120       "arm922t",
1121       NULL,
1122       {
1123         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1124         isa_bit_armv3m, isa_nobit
1125       }
1126     },
1127     TARGET_ARCH_armv4t
1128   },
1129   {
1130     {
1131       "arm940t",
1132       NULL,
1133       {
1134         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1135         isa_bit_armv3m, isa_nobit
1136       }
1137     },
1138     TARGET_ARCH_armv4t
1139   },
1140   {
1141     {
1142       "ep9312",
1143       NULL,
1144       {
1145         isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
1146         isa_bit_armv3m, isa_nobit
1147       }
1148     },
1149     TARGET_ARCH_armv4t
1150   },
1151   {
1152     {
1153       "arm10tdmi",
1154       NULL,
1155       {
1156         isa_bit_thumb, isa_bit_armv4, isa_bit_armv5, isa_bit_mode32,
1157         isa_bit_notm, isa_bit_armv3m, isa_nobit
1158       }
1159     },
1160     TARGET_ARCH_armv5t
1161   },
1162   {
1163     {
1164       "arm1020t",
1165       NULL,
1166       {
1167         isa_bit_thumb, isa_bit_armv4, isa_bit_armv5, isa_bit_mode32,
1168         isa_bit_notm, isa_bit_armv3m, isa_nobit
1169       }
1170     },
1171     TARGET_ARCH_armv5t
1172   },
1173   {
1174     {
1175       "arm9e",
1176       cpu_opttab_arm9e,
1177       {
1178         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1179         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1180         isa_bit_armv3m, isa_nobit
1181       }
1182     },
1183     TARGET_ARCH_armv5te
1184   },
1185   {
1186     {
1187       "arm946e-s",
1188       cpu_opttab_arm946es,
1189       {
1190         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1191         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1192         isa_bit_armv3m, isa_nobit
1193       }
1194     },
1195     TARGET_ARCH_armv5te
1196   },
1197   {
1198     {
1199       "arm966e-s",
1200       cpu_opttab_arm966es,
1201       {
1202         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1203         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1204         isa_bit_armv3m, isa_nobit
1205       }
1206     },
1207     TARGET_ARCH_armv5te
1208   },
1209   {
1210     {
1211       "arm968e-s",
1212       cpu_opttab_arm968es,
1213       {
1214         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1215         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1216         isa_bit_armv3m, isa_nobit
1217       }
1218     },
1219     TARGET_ARCH_armv5te
1220   },
1221   {
1222     {
1223       "arm10e",
1224       cpu_opttab_arm10e,
1225       {
1226         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1227         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1228         isa_bit_armv3m, isa_nobit
1229       }
1230     },
1231     TARGET_ARCH_armv5te
1232   },
1233   {
1234     {
1235       "arm1020e",
1236       cpu_opttab_arm1020e,
1237       {
1238         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1239         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1240         isa_bit_armv3m, isa_nobit
1241       }
1242     },
1243     TARGET_ARCH_armv5te
1244   },
1245   {
1246     {
1247       "arm1022e",
1248       cpu_opttab_arm1022e,
1249       {
1250         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1251         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1252         isa_bit_armv3m, isa_nobit
1253       }
1254     },
1255     TARGET_ARCH_armv5te
1256   },
1257   {
1258     {
1259       "xscale",
1260       NULL,
1261       {
1262         isa_bit_armv5e, isa_bit_xscale, isa_bit_thumb, isa_bit_armv4,
1263         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_armv3m,
1264         isa_nobit
1265       }
1266     },
1267     TARGET_ARCH_armv5te
1268   },
1269   {
1270     {
1271       "iwmmxt",
1272       NULL,
1273       {
1274         isa_bit_armv5e, isa_bit_iwmmxt, isa_bit_xscale, isa_bit_thumb,
1275         isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, isa_bit_notm,
1276         isa_bit_armv3m, isa_nobit
1277       }
1278     },
1279     TARGET_ARCH_iwmmxt
1280   },
1281   {
1282     {
1283       "iwmmxt2",
1284       NULL,
1285       {
1286         isa_bit_armv5e, isa_bit_iwmmxt, isa_bit_xscale, isa_bit_thumb,
1287         isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, isa_bit_iwmmxt2,
1288         isa_bit_notm, isa_bit_armv3m, isa_nobit
1289       }
1290     },
1291     TARGET_ARCH_iwmmxt2
1292   },
1293   {
1294     {
1295       "fa606te",
1296       NULL,
1297       {
1298         isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5,
1299         isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit
1300       }
1301     },
1302     TARGET_ARCH_armv5te
1303   },
1304   {
1305     {
1306       "fa626te",
1307       NULL,
1308       {
1309         isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5,
1310         isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit
1311       }
1312     },
1313     TARGET_ARCH_armv5te
1314   },
1315   {
1316     {
1317       "fmp626",
1318       NULL,
1319       {
1320         isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5,
1321         isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit
1322       }
1323     },
1324     TARGET_ARCH_armv5te
1325   },
1326   {
1327     {
1328       "fa726te",
1329       NULL,
1330       {
1331         isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5,
1332         isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit
1333       }
1334     },
1335     TARGET_ARCH_armv5te
1336   },
1337   {
1338     {
1339       "arm926ej-s",
1340       cpu_opttab_arm926ejs,
1341       {
1342         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1343         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1344         isa_bit_armv3m, isa_nobit
1345       }
1346     },
1347     TARGET_ARCH_armv5tej
1348   },
1349   {
1350     {
1351       "arm1026ej-s",
1352       cpu_opttab_arm1026ejs,
1353       {
1354         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4,
1355         isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl,
1356         isa_bit_armv3m, isa_nobit
1357       }
1358     },
1359     TARGET_ARCH_armv5tej
1360   },
1361   {
1362     {
1363       "arm1136j-s",
1364       NULL,
1365       {
1366         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1367         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm,
1368         isa_bit_armv3m, isa_nobit
1369       }
1370     },
1371     TARGET_ARCH_armv6j
1372   },
1373   {
1374     {
1375       "arm1136jf-s",
1376       NULL,
1377       {
1378         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
1379         isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, isa_bit_mode32,
1380         isa_bit_notm, isa_bit_fp_dbl, isa_bit_armv3m, isa_nobit
1381       }
1382     },
1383     TARGET_ARCH_armv6j
1384   },
1385   {
1386     {
1387       "arm1176jz-s",
1388       NULL,
1389       {
1390         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1391         isa_bit_armv5, isa_bit_armv6, isa_bit_quirk_armv6kz, isa_bit_mode32,
1392         isa_bit_notm, isa_bit_armv6k, isa_bit_armv3m, isa_nobit
1393       }
1394     },
1395     TARGET_ARCH_armv6kz
1396   },
1397   {
1398     {
1399       "arm1176jzf-s",
1400       NULL,
1401       {
1402         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
1403         isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, isa_bit_quirk_armv6kz,
1404         isa_bit_mode32, isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl,
1405         isa_bit_armv3m, isa_nobit
1406       }
1407     },
1408     TARGET_ARCH_armv6kz
1409   },
1410   {
1411     {
1412       "mpcorenovfp",
1413       NULL,
1414       {
1415         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1416         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm,
1417         isa_bit_armv6k, isa_bit_armv3m, isa_nobit
1418       }
1419     },
1420     TARGET_ARCH_armv6k
1421   },
1422   {
1423     {
1424       "mpcore",
1425       NULL,
1426       {
1427         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
1428         isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, isa_bit_mode32,
1429         isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_bit_armv3m,
1430         isa_nobit
1431       }
1432     },
1433     TARGET_ARCH_armv6k
1434   },
1435   {
1436     {
1437       "arm1156t2-s",
1438       NULL,
1439       {
1440         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1441         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_thumb2,
1442         isa_bit_notm, isa_bit_armv3m, isa_nobit
1443       }
1444     },
1445     TARGET_ARCH_armv6t2
1446   },
1447   {
1448     {
1449       "arm1156t2f-s",
1450       NULL,
1451       {
1452         isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
1453         isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, isa_bit_mode32,
1454         isa_bit_thumb2, isa_bit_notm, isa_bit_fp_dbl, isa_bit_armv3m,
1455         isa_nobit
1456       }
1457     },
1458     TARGET_ARCH_armv6t2
1459   },
1460   {
1461     {
1462       "cortex-m1",
1463       NULL,
1464       {
1465         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1466         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
1467         isa_nobit
1468       }
1469     },
1470     TARGET_ARCH_armv6s_m
1471   },
1472   {
1473     {
1474       "cortex-m0",
1475       NULL,
1476       {
1477         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1478         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
1479         isa_nobit
1480       }
1481     },
1482     TARGET_ARCH_armv6s_m
1483   },
1484   {
1485     {
1486       "cortex-m0plus",
1487       NULL,
1488       {
1489         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1490         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
1491         isa_nobit
1492       }
1493     },
1494     TARGET_ARCH_armv6s_m
1495   },
1496   {
1497     {
1498       "cortex-m1.small-multiply",
1499       NULL,
1500       {
1501         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1502         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
1503         isa_nobit
1504       }
1505     },
1506     TARGET_ARCH_armv6s_m
1507   },
1508   {
1509     {
1510       "cortex-m0.small-multiply",
1511       NULL,
1512       {
1513         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1514         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
1515         isa_nobit
1516       }
1517     },
1518     TARGET_ARCH_armv6s_m
1519   },
1520   {
1521     {
1522       "cortex-m0plus.small-multiply",
1523       NULL,
1524       {
1525         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1526         isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
1527         isa_nobit
1528       }
1529     },
1530     TARGET_ARCH_armv6s_m
1531   },
1532   {
1533     {
1534       "generic-armv7-a",
1535       cpu_opttab_genericv7a,
1536       {
1537         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5e, isa_bit_thumb,
1538         isa_bit_be8, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
1539         isa_bit_armv7, isa_bit_mode32, isa_bit_thumb2, isa_bit_notm,
1540         isa_bit_armv6k, isa_bit_fp_dbl, isa_bit_armv3m, isa_nobit
1541       }
1542     },
1543     TARGET_ARCH_armv7_a
1544   },
1545   {
1546     {
1547       "cortex-a5",
1548       cpu_opttab_cortexa5,
1549       {
1550         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5e, isa_bit_thumb,
1551         isa_bit_be8, isa_bit_armv4, isa_bit_armv5, isa_bit_neon,
1552         isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_mode32,
1553         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1554         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1555         isa_nobit
1556       }
1557     },
1558     TARGET_ARCH_armv7_a
1559   },
1560   {
1561     {
1562       "cortex-a7",
1563       cpu_opttab_cortexa7,
1564       {
1565         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1566         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1567         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1568         isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
1569         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1570         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1571         isa_nobit
1572       }
1573     },
1574     TARGET_ARCH_armv7ve
1575   },
1576   {
1577     {
1578       "cortex-a8",
1579       cpu_opttab_cortexa8,
1580       {
1581         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5e, isa_bit_thumb,
1582         isa_bit_be8, isa_bit_armv4, isa_bit_armv5, isa_bit_neon,
1583         isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_mode32,
1584         isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl,
1585         isa_bit_sec, isa_bit_armv3m, isa_nobit
1586       }
1587     },
1588     TARGET_ARCH_armv7_a
1589   },
1590   {
1591     {
1592       "cortex-a9",
1593       cpu_opttab_cortexa9,
1594       {
1595         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5e, isa_bit_thumb,
1596         isa_bit_be8, isa_bit_armv4, isa_bit_armv5, isa_bit_neon,
1597         isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_mode32,
1598         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1599         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1600         isa_nobit
1601       }
1602     },
1603     TARGET_ARCH_armv7_a
1604   },
1605   {
1606     {
1607       "cortex-a12",
1608       cpu_opttab_cortexa12,
1609       {
1610         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1611         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1612         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1613         isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
1614         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1615         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1616         isa_nobit
1617       }
1618     },
1619     TARGET_ARCH_armv7ve
1620   },
1621   {
1622     {
1623       "cortex-a15",
1624       cpu_opttab_cortexa15,
1625       {
1626         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1627         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1628         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1629         isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
1630         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1631         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1632         isa_nobit
1633       }
1634     },
1635     TARGET_ARCH_armv7ve
1636   },
1637   {
1638     {
1639       "cortex-a17",
1640       cpu_opttab_cortexa17,
1641       {
1642         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1643         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1644         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1645         isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
1646         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1647         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1648         isa_nobit
1649       }
1650     },
1651     TARGET_ARCH_armv7ve
1652   },
1653   {
1654     {
1655       "cortex-r4",
1656       NULL,
1657       {
1658         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1659         isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv,
1660         isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k,
1661         isa_bit_armv3m, isa_nobit
1662       }
1663     },
1664     TARGET_ARCH_armv7_r
1665   },
1666   {
1667     {
1668       "cortex-r4f",
1669       NULL,
1670       {
1671         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5e, isa_bit_thumb,
1672         isa_bit_be8, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
1673         isa_bit_armv7, isa_bit_tdiv, isa_bit_mode32, isa_bit_thumb2,
1674         isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_bit_armv3m,
1675         isa_nobit
1676       }
1677     },
1678     TARGET_ARCH_armv7_r
1679   },
1680   {
1681     {
1682       "cortex-r5",
1683       cpu_opttab_cortexr5,
1684       {
1685         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5e,
1686         isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5,
1687         isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_mode32,
1688         isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl,
1689         isa_bit_armv3m, isa_nobit
1690       }
1691     },
1692     TARGET_ARCH_armv7_r
1693   },
1694   {
1695     {
1696       "cortex-r7",
1697       cpu_opttab_cortexr7,
1698       {
1699         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5e,
1700         isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5,
1701         isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_mode32,
1702         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1703         isa_bit_fp_dbl, isa_bit_armv3m, isa_nobit
1704       }
1705     },
1706     TARGET_ARCH_armv7_r
1707   },
1708   {
1709     {
1710       "cortex-r8",
1711       cpu_opttab_cortexr8,
1712       {
1713         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5e,
1714         isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5,
1715         isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_mode32,
1716         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1717         isa_bit_fp_dbl, isa_bit_armv3m, isa_nobit
1718       }
1719     },
1720     TARGET_ARCH_armv7_r
1721   },
1722   {
1723     {
1724       "cortex-m7",
1725       cpu_opttab_cortexm7,
1726       {
1727         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5e,
1728         isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5,
1729         isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_fpv5,
1730         isa_bit_tdiv, isa_bit_quirk_no_volatile_ce, isa_bit_mode32, isa_bit_thumb2,
1731         isa_bit_fp16conv, isa_bit_fp_dbl, isa_bit_armv3m, isa_nobit
1732       }
1733     },
1734     TARGET_ARCH_armv7e_m
1735   },
1736   {
1737     {
1738       "cortex-m4",
1739       cpu_opttab_cortexm4,
1740       {
1741         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5e,
1742         isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5,
1743         isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_tdiv,
1744         isa_bit_mode32, isa_bit_thumb2, isa_bit_fp16conv, isa_bit_armv3m,
1745         isa_nobit
1746       }
1747     },
1748     TARGET_ARCH_armv7e_m
1749   },
1750   {
1751     {
1752       "cortex-m3",
1753       NULL,
1754       {
1755         isa_bit_armv5e, isa_bit_thumb, isa_bit_quirk_cm3_ldrd, isa_bit_be8,
1756         isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, isa_bit_armv7,
1757         isa_bit_tdiv, isa_bit_mode32, isa_bit_thumb2, isa_bit_armv3m,
1758         isa_nobit
1759       }
1760     },
1761     TARGET_ARCH_armv7_m
1762   },
1763   {
1764     {
1765       "marvell-pj4",
1766       NULL,
1767       {
1768         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
1769         isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_mode32,
1770         isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_mp,
1771         isa_bit_sec, isa_bit_armv3m, isa_nobit
1772       }
1773     },
1774     TARGET_ARCH_armv7_a
1775   },
1776   {
1777     {
1778       "cortex-a15.cortex-a7",
1779       cpu_opttab_cortexa15cortexa7,
1780       {
1781         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1782         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1783         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1784         isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
1785         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1786         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1787         isa_nobit
1788       }
1789     },
1790     TARGET_ARCH_armv7ve
1791   },
1792   {
1793     {
1794       "cortex-a17.cortex-a7",
1795       cpu_opttab_cortexa17cortexa7,
1796       {
1797         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1798         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1799         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1800         isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
1801         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k,
1802         isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m,
1803         isa_nobit
1804       }
1805     },
1806     TARGET_ARCH_armv7ve
1807   },
1808   {
1809     {
1810       "cortex-a32",
1811       cpu_opttab_cortexa32,
1812       {
1813         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1814         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1815         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1816         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1817         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1818         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1819         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1820       }
1821     },
1822     TARGET_ARCH_armv8_a
1823   },
1824   {
1825     {
1826       "cortex-a35",
1827       cpu_opttab_cortexa35,
1828       {
1829         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1830         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1831         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1832         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1833         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1834         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1835         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1836       }
1837     },
1838     TARGET_ARCH_armv8_a
1839   },
1840   {
1841     {
1842       "cortex-a53",
1843       cpu_opttab_cortexa53,
1844       {
1845         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1846         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1847         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1848         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1849         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1850         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1851         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1852       }
1853     },
1854     TARGET_ARCH_armv8_a
1855   },
1856   {
1857     {
1858       "cortex-a57",
1859       cpu_opttab_cortexa57,
1860       {
1861         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1862         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1863         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1864         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1865         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1866         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1867         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1868       }
1869     },
1870     TARGET_ARCH_armv8_a
1871   },
1872   {
1873     {
1874       "cortex-a72",
1875       cpu_opttab_cortexa72,
1876       {
1877         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1878         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1879         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1880         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1881         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1882         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1883         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1884       }
1885     },
1886     TARGET_ARCH_armv8_a
1887   },
1888   {
1889     {
1890       "cortex-a73",
1891       cpu_opttab_cortexa73,
1892       {
1893         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1894         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1895         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1896         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1897         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1898         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1899         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1900       }
1901     },
1902     TARGET_ARCH_armv8_a
1903   },
1904   {
1905     {
1906       "exynos-m1",
1907       cpu_opttab_exynosm1,
1908       {
1909         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1910         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1911         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1912         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1913         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1914         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1915         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1916       }
1917     },
1918     TARGET_ARCH_armv8_a
1919   },
1920   {
1921     {
1922       "xgene1",
1923       cpu_opttab_xgene1,
1924       {
1925         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1926         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1927         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1928         isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, isa_bit_tdiv,
1929         isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2, isa_bit_notm,
1930         isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl,
1931         isa_bit_sec, isa_bit_armv3m, isa_nobit
1932       }
1933     },
1934     TARGET_ARCH_armv8_a
1935   },
1936   {
1937     {
1938       "cortex-a57.cortex-a53",
1939       cpu_opttab_cortexa57cortexa53,
1940       {
1941         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1942         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1943         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1944         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1945         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1946         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1947         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1948       }
1949     },
1950     TARGET_ARCH_armv8_a
1951   },
1952   {
1953     {
1954       "cortex-a72.cortex-a53",
1955       cpu_opttab_cortexa72cortexa53,
1956       {
1957         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1958         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1959         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1960         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1961         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1962         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1963         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1964       }
1965     },
1966     TARGET_ARCH_armv8_a
1967   },
1968   {
1969     {
1970       "cortex-a73.cortex-a35",
1971       cpu_opttab_cortexa73cortexa35,
1972       {
1973         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1974         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1975         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1976         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1977         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1978         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1979         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1980       }
1981     },
1982     TARGET_ARCH_armv8_a
1983   },
1984   {
1985     {
1986       "cortex-a73.cortex-a53",
1987       cpu_opttab_cortexa73cortexa53,
1988       {
1989         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
1990         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
1991         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
1992         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
1993         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
1994         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
1995         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
1996       }
1997     },
1998     TARGET_ARCH_armv8_a
1999   },
2000   {
2001     {
2002       "cortex-a55",
2003       cpu_opttab_cortexa55,
2004       {
2005         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
2006         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_dotprod,
2007         isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_neon,
2008         isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
2009         isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
2010         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1,
2011         isa_bit_fp16conv, isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp,
2012         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
2013       }
2014     },
2015     TARGET_ARCH_armv8_2_a
2016   },
2017   {
2018     {
2019       "cortex-a75",
2020       cpu_opttab_cortexa75,
2021       {
2022         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
2023         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_dotprod,
2024         isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_neon,
2025         isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
2026         isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
2027         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1,
2028         isa_bit_fp16conv, isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp,
2029         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
2030       }
2031     },
2032     TARGET_ARCH_armv8_2_a
2033   },
2034   {
2035     {
2036       "cortex-a75.cortex-a55",
2037       cpu_opttab_cortexa75cortexa55,
2038       {
2039         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
2040         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_dotprod,
2041         isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_neon,
2042         isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8,
2043         isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32,
2044         isa_bit_thumb2, isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1,
2045         isa_bit_fp16conv, isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp,
2046         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
2047       }
2048     },
2049     TARGET_ARCH_armv8_2_a
2050   },
2051   {
2052     {
2053       "cortex-m23",
2054       NULL,
2055       {
2056         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
2057         isa_bit_armv5, isa_bit_armv6, isa_bit_armv8, isa_bit_cmse,
2058         isa_bit_tdiv, isa_bit_mode32, isa_bit_armv3m, isa_nobit
2059       }
2060     },
2061     TARGET_ARCH_armv8_m_base
2062   },
2063   {
2064     {
2065       "cortex-m33",
2066       cpu_opttab_cortexm33,
2067       {
2068         isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5e,
2069         isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5,
2070         isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_armv8,
2071         isa_bit_cmse, isa_bit_fpv5, isa_bit_tdiv, isa_bit_mode32,
2072         isa_bit_thumb2, isa_bit_fp16conv, isa_bit_armv3m, isa_nobit
2073       }
2074     },
2075     TARGET_ARCH_armv8_m_main
2076   },
2077   {
2078     {
2079       "cortex-r52",
2080       cpu_opttab_cortexr52,
2081       {
2082         isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4,
2083         isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae,
2084         isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6,
2085         isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5,
2086         isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2,
2087         isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp,
2088         isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit
2089       }
2090     },
2091     TARGET_ARCH_armv8_r
2092   },
2093   {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none}
2094 };
2095 static const struct cpu_arch_extension arch_opttab_armv5e[] = {
2096   {
2097     "fp", false, false,
2098     {
2099       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2100     }
2101   },
2102   {
2103     "nofp", true, false,
2104     {
2105       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2106       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2107       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2108     }
2109   },
2110   {
2111     "vfpv2", false, true,
2112     {
2113       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2114     }
2115   },
2116   { NULL, false, false, {isa_nobit}}
2117 };
2118 
2119 static const struct cpu_arch_extension arch_opttab_armv5te[] = {
2120   {
2121     "fp", false, false,
2122     {
2123       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2124     }
2125   },
2126   {
2127     "nofp", true, false,
2128     {
2129       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2130       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2131       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2132     }
2133   },
2134   {
2135     "vfpv2", false, true,
2136     {
2137       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2138     }
2139   },
2140   { NULL, false, false, {isa_nobit}}
2141 };
2142 
2143 static const struct cpu_arch_extension arch_opttab_armv5tej[] = {
2144   {
2145     "fp", false, false,
2146     {
2147       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2148     }
2149   },
2150   {
2151     "nofp", true, false,
2152     {
2153       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2154       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2155       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2156     }
2157   },
2158   {
2159     "vfpv2", false, true,
2160     {
2161       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2162     }
2163   },
2164   { NULL, false, false, {isa_nobit}}
2165 };
2166 
2167 static const struct cpu_arch_extension arch_opttab_armv6[] = {
2168   {
2169     "fp", false, false,
2170     {
2171       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2172     }
2173   },
2174   {
2175     "nofp", true, false,
2176     {
2177       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2178       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2179       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2180     }
2181   },
2182   {
2183     "vfpv2", false, true,
2184     {
2185       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2186     }
2187   },
2188   { NULL, false, false, {isa_nobit}}
2189 };
2190 
2191 static const struct cpu_arch_extension arch_opttab_armv6j[] = {
2192   {
2193     "fp", false, false,
2194     {
2195       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2196     }
2197   },
2198   {
2199     "nofp", true, false,
2200     {
2201       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2202       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2203       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2204     }
2205   },
2206   {
2207     "vfpv2", false, true,
2208     {
2209       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2210     }
2211   },
2212   { NULL, false, false, {isa_nobit}}
2213 };
2214 
2215 static const struct cpu_arch_extension arch_opttab_armv6k[] = {
2216   {
2217     "fp", false, false,
2218     {
2219       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2220     }
2221   },
2222   {
2223     "nofp", true, false,
2224     {
2225       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2226       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2227       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2228     }
2229   },
2230   {
2231     "vfpv2", false, true,
2232     {
2233       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2234     }
2235   },
2236   { NULL, false, false, {isa_nobit}}
2237 };
2238 
2239 static const struct cpu_arch_extension arch_opttab_armv6z[] = {
2240   {
2241     "fp", false, false,
2242     {
2243       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2244     }
2245   },
2246   {
2247     "nofp", true, false,
2248     {
2249       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2250       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2251       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2252     }
2253   },
2254   {
2255     "vfpv2", false, true,
2256     {
2257       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2258     }
2259   },
2260   { NULL, false, false, {isa_nobit}}
2261 };
2262 
2263 static const struct cpu_arch_extension arch_opttab_armv6kz[] = {
2264   {
2265     "fp", false, false,
2266     {
2267       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2268     }
2269   },
2270   {
2271     "nofp", true, false,
2272     {
2273       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2274       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2275       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2276     }
2277   },
2278   {
2279     "vfpv2", false, true,
2280     {
2281       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2282     }
2283   },
2284   { NULL, false, false, {isa_nobit}}
2285 };
2286 
2287 static const struct cpu_arch_extension arch_opttab_armv6zk[] = {
2288   {
2289     "fp", false, false,
2290     {
2291       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2292     }
2293   },
2294   {
2295     "nofp", true, false,
2296     {
2297       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2298       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2299       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2300     }
2301   },
2302   {
2303     "vfpv2", false, true,
2304     {
2305       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2306     }
2307   },
2308   { NULL, false, false, {isa_nobit}}
2309 };
2310 
2311 static const struct cpu_arch_extension arch_opttab_armv6t2[] = {
2312   {
2313     "fp", false, false,
2314     {
2315       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2316     }
2317   },
2318   {
2319     "nofp", true, false,
2320     {
2321       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2322       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2323       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2324     }
2325   },
2326   {
2327     "vfpv2", false, true,
2328     {
2329       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
2330     }
2331   },
2332   { NULL, false, false, {isa_nobit}}
2333 };
2334 
2335 static const struct cpu_arch_extension arch_opttab_armv7[] = {
2336   {
2337     "fp", false, false,
2338     {
2339       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2340     }
2341   },
2342   {
2343     "nofp", true, false,
2344     {
2345       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2346       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2347       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2348     }
2349   },
2350   {
2351     "vfpv3-d16", false, true,
2352     {
2353       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2354     }
2355   },
2356   { NULL, false, false, {isa_nobit}}
2357 };
2358 
2359 static const struct cpu_arch_extension arch_opttab_armv7_a[] = {
2360   {
2361     "mp", false, false,
2362     {
2363       isa_bit_mp, isa_nobit
2364     }
2365   },
2366   {
2367     "sec", false, false,
2368     {
2369       isa_bit_sec, isa_nobit
2370     }
2371   },
2372   {
2373     "fp", false, false,
2374     {
2375       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2376     }
2377   },
2378   {
2379     "vfpv3", false, false,
2380     {
2381       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl,
2382       isa_nobit
2383     }
2384   },
2385   {
2386     "vfpv3-d16-fp16", false, false,
2387     {
2388       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl,
2389       isa_nobit
2390     }
2391   },
2392   {
2393     "vfpv3-fp16", false, false,
2394     {
2395       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv,
2396       isa_bit_fp_dbl, isa_nobit
2397     }
2398   },
2399   {
2400     "vfpv4-d16", false, false,
2401     {
2402       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
2403       isa_bit_fp_dbl, isa_nobit
2404     }
2405   },
2406   {
2407     "vfpv4", false, false,
2408     {
2409       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32,
2410       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2411     }
2412   },
2413   {
2414     "simd", false, false,
2415     {
2416       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2417       isa_bit_fp_dbl, isa_nobit
2418     }
2419   },
2420   {
2421     "neon-fp16", false, false,
2422     {
2423       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2424       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2425     }
2426   },
2427   {
2428     "neon-vfpv4", false, false,
2429     {
2430       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2431       isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2432     }
2433   },
2434   {
2435     "nosimd", true, false,
2436     {
2437       isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32,
2438       isa_bit_crypto, isa_nobit
2439     }
2440   },
2441   {
2442     "nofp", true, false,
2443     {
2444       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2445       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2446       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2447     }
2448   },
2449   {
2450     "vfpv3-d16", false, true,
2451     {
2452       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2453     }
2454   },
2455   {
2456     "neon", false, true,
2457     {
2458       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2459       isa_bit_fp_dbl, isa_nobit
2460     }
2461   },
2462   {
2463     "neon-vfpv3", false, true,
2464     {
2465       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2466       isa_bit_fp_dbl, isa_nobit
2467     }
2468   },
2469   { NULL, false, false, {isa_nobit}}
2470 };
2471 
2472 static const struct cpu_arch_extension arch_opttab_armv7ve[] = {
2473   {
2474     "vfpv3-d16", false, false,
2475     {
2476       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2477     }
2478   },
2479   {
2480     "vfpv3", false, false,
2481     {
2482       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl,
2483       isa_nobit
2484     }
2485   },
2486   {
2487     "vfpv3-d16-fp16", false, false,
2488     {
2489       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl,
2490       isa_nobit
2491     }
2492   },
2493   {
2494     "vfpv3-fp16", false, false,
2495     {
2496       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv,
2497       isa_bit_fp_dbl, isa_nobit
2498     }
2499   },
2500   {
2501     "fp", false, false,
2502     {
2503       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
2504       isa_bit_fp_dbl, isa_nobit
2505     }
2506   },
2507   {
2508     "vfpv4", false, false,
2509     {
2510       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32,
2511       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2512     }
2513   },
2514   {
2515     "neon", false, false,
2516     {
2517       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2518       isa_bit_fp_dbl, isa_nobit
2519     }
2520   },
2521   {
2522     "neon-fp16", false, false,
2523     {
2524       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2525       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2526     }
2527   },
2528   {
2529     "simd", false, false,
2530     {
2531       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2532       isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2533     }
2534   },
2535   {
2536     "nosimd", true, false,
2537     {
2538       isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32,
2539       isa_bit_crypto, isa_nobit
2540     }
2541   },
2542   {
2543     "nofp", true, false,
2544     {
2545       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2546       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2547       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2548     }
2549   },
2550   {
2551     "vfpv4-d16", false, true,
2552     {
2553       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
2554       isa_bit_fp_dbl, isa_nobit
2555     }
2556   },
2557   {
2558     "neon-vfpv3", false, true,
2559     {
2560       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
2561       isa_bit_fp_dbl, isa_nobit
2562     }
2563   },
2564   {
2565     "neon-vfpv4", false, true,
2566     {
2567       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2568       isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2569     }
2570   },
2571   { NULL, false, false, {isa_nobit}}
2572 };
2573 
2574 static const struct cpu_arch_extension arch_opttab_armv7_r[] = {
2575   {
2576     "fp.sp", false, false,
2577     {
2578       isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit
2579     }
2580   },
2581   {
2582     "fp", false, false,
2583     {
2584       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2585     }
2586   },
2587   {
2588     "vfpv3xd-fp16", false, false,
2589     {
2590       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit
2591     }
2592   },
2593   {
2594     "vfpv3-d16-fp16", false, false,
2595     {
2596       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl,
2597       isa_nobit
2598     }
2599   },
2600   {
2601     "idiv", false, false,
2602     {
2603       isa_bit_adiv, isa_nobit
2604     }
2605   },
2606   {
2607     "nofp", true, false,
2608     {
2609       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2610       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2611       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2612     }
2613   },
2614   {
2615     "noidiv", true, false,
2616     {
2617       isa_bit_adiv, isa_nobit
2618     }
2619   },
2620   {
2621     "vfpv3xd", false, true,
2622     {
2623       isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit
2624     }
2625   },
2626   {
2627     "vfpv3-d16", false, true,
2628     {
2629       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
2630     }
2631   },
2632   { NULL, false, false, {isa_nobit}}
2633 };
2634 
2635 static const struct cpu_arch_extension arch_opttab_armv7e_m[] = {
2636   {
2637     "fp", false, false,
2638     {
2639       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
2640       isa_nobit
2641     }
2642   },
2643   {
2644     "fpv5", false, false,
2645     {
2646       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
2647       isa_bit_fp16conv, isa_nobit
2648     }
2649   },
2650   {
2651     "fp.dp", false, false,
2652     {
2653       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
2654       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2655     }
2656   },
2657   {
2658     "nofp", true, false,
2659     {
2660       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2661       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2662       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2663     }
2664   },
2665   {
2666     "vfpv4-sp-d16", false, true,
2667     {
2668       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
2669       isa_nobit
2670     }
2671   },
2672   {
2673     "fpv5-d16", false, true,
2674     {
2675       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
2676       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2677     }
2678   },
2679   { NULL, false, false, {isa_nobit}}
2680 };
2681 
2682 static const struct cpu_arch_extension arch_opttab_armv8_a[] = {
2683   {
2684     "crc", false, false,
2685     {
2686       isa_bit_crc32, isa_nobit
2687     }
2688   },
2689   {
2690     "simd", false, false,
2691     {
2692       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2693       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
2694       isa_nobit
2695     }
2696   },
2697   {
2698     "crypto", false, false,
2699     {
2700       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2701       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
2702       isa_bit_fp_dbl, isa_nobit
2703     }
2704   },
2705   {
2706     "nocrypto", true, false,
2707     {
2708       isa_bit_crypto, isa_nobit
2709     }
2710   },
2711   {
2712     "nofp", true, false,
2713     {
2714       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2715       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2716       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2717     }
2718   },
2719   { NULL, false, false, {isa_nobit}}
2720 };
2721 
2722 static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = {
2723   {
2724     "simd", false, false,
2725     {
2726       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2727       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
2728       isa_nobit
2729     }
2730   },
2731   {
2732     "crypto", false, false,
2733     {
2734       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2735       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
2736       isa_bit_fp_dbl, isa_nobit
2737     }
2738   },
2739   {
2740     "nocrypto", true, false,
2741     {
2742       isa_bit_crypto, isa_nobit
2743     }
2744   },
2745   {
2746     "nofp", true, false,
2747     {
2748       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2749       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2750       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2751     }
2752   },
2753   { NULL, false, false, {isa_nobit}}
2754 };
2755 
2756 static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = {
2757   {
2758     "simd", false, false,
2759     {
2760       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2761       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
2762       isa_nobit
2763     }
2764   },
2765   {
2766     "fp16", false, false,
2767     {
2768       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2769       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2770       isa_bit_fp_dbl, isa_nobit
2771     }
2772   },
2773   {
2774     "fp16fml", false, false,
2775     {
2776       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml,
2777       isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16,
2778       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2779     }
2780   },
2781   {
2782     "crypto", false, false,
2783     {
2784       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2785       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
2786       isa_bit_fp_dbl, isa_nobit
2787     }
2788   },
2789   {
2790     "nocrypto", true, false,
2791     {
2792       isa_bit_crypto, isa_nobit
2793     }
2794   },
2795   {
2796     "nofp", true, false,
2797     {
2798       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2799       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2800       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2801     }
2802   },
2803   {
2804     "dotprod", false, false,
2805     {
2806       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
2807       isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2808       isa_bit_fp_dbl, isa_nobit
2809     }
2810   },
2811   { NULL, false, false, {isa_nobit}}
2812 };
2813 
2814 static const struct cpu_arch_extension arch_opttab_armv8_3_a[] = {
2815   {
2816     "simd", false, false,
2817     {
2818       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2819       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
2820       isa_nobit
2821     }
2822   },
2823   {
2824     "fp16", false, false,
2825     {
2826       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2827       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2828       isa_bit_fp_dbl, isa_nobit
2829     }
2830   },
2831   {
2832     "fp16fml", false, false,
2833     {
2834       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml,
2835       isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16,
2836       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2837     }
2838   },
2839   {
2840     "crypto", false, false,
2841     {
2842       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2843       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
2844       isa_bit_fp_dbl, isa_nobit
2845     }
2846   },
2847   {
2848     "nocrypto", true, false,
2849     {
2850       isa_bit_crypto, isa_nobit
2851     }
2852   },
2853   {
2854     "nofp", true, false,
2855     {
2856       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2857       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2858       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2859     }
2860   },
2861   {
2862     "dotprod", false, false,
2863     {
2864       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
2865       isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2866       isa_bit_fp_dbl, isa_nobit
2867     }
2868   },
2869   { NULL, false, false, {isa_nobit}}
2870 };
2871 
2872 static const struct cpu_arch_extension arch_opttab_armv8_4_a[] = {
2873   {
2874     "simd", false, false,
2875     {
2876       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
2877       isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2878       isa_bit_fp_dbl, isa_nobit
2879     }
2880   },
2881   {
2882     "fp16", false, false,
2883     {
2884       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml,
2885       isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32,
2886       isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2887     }
2888   },
2889   {
2890     "crypto", false, false,
2891     {
2892       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod,
2893       isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv,
2894       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2895     }
2896   },
2897   {
2898     "nocrypto", true, false,
2899     {
2900       isa_bit_crypto, isa_nobit
2901     }
2902   },
2903   {
2904     "nofp", true, false,
2905     {
2906       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2907       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2908       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2909     }
2910   },
2911   { NULL, false, false, {isa_nobit}}
2912 };
2913 
2914 static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = {
2915   {
2916     "dsp", false, false,
2917     {
2918       isa_bit_armv7em, isa_nobit
2919     }
2920   },
2921   {
2922     "fp", false, false,
2923     {
2924       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
2925       isa_bit_fp16conv, isa_nobit
2926     }
2927   },
2928   {
2929     "fp.dp", false, false,
2930     {
2931       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
2932       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
2933     }
2934   },
2935   {
2936     "nofp", true, false,
2937     {
2938       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2939       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2940       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2941     }
2942   },
2943   {
2944     "nodsp", true, false,
2945     {
2946       isa_bit_armv7em, isa_nobit
2947     }
2948   },
2949   { NULL, false, false, {isa_nobit}}
2950 };
2951 
2952 static const struct cpu_arch_extension arch_opttab_armv8_r[] = {
2953   {
2954     "crc", false, false,
2955     {
2956       isa_bit_crc32, isa_nobit
2957     }
2958   },
2959   {
2960     "fp.sp", false, false,
2961     {
2962       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
2963       isa_bit_fp16conv, isa_nobit
2964     }
2965   },
2966   {
2967     "simd", false, false,
2968     {
2969       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2970       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
2971       isa_nobit
2972     }
2973   },
2974   {
2975     "crypto", false, false,
2976     {
2977       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2978       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
2979       isa_bit_fp_dbl, isa_nobit
2980     }
2981   },
2982   {
2983     "nocrypto", true, false,
2984     {
2985       isa_bit_crypto, isa_nobit
2986     }
2987   },
2988   {
2989     "nofp", true, false,
2990     {
2991       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
2992       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv,
2993       isa_bit_crypto, isa_bit_fp_dbl, isa_nobit
2994     }
2995   },
2996   { NULL, false, false, {isa_nobit}}
2997 };
2998 
2999 const arch_option all_architectures[] =
3000 {
3001   {
3002     "armv2",
3003     NULL,
3004     {
3005       isa_bit_mode26, isa_bit_notm, isa_nobit
3006     },
3007     "2", BASE_ARCH_2,
3008     0,
3009     TARGET_CPU_arm2,
3010   },
3011   {
3012     "armv2a",
3013     NULL,
3014     {
3015       isa_bit_mode26, isa_bit_notm, isa_nobit
3016     },
3017     "2", BASE_ARCH_2,
3018     0,
3019     TARGET_CPU_arm2,
3020   },
3021   {
3022     "armv3",
3023     NULL,
3024     {
3025       isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit
3026     },
3027     "3", BASE_ARCH_3,
3028     0,
3029     TARGET_CPU_arm6,
3030   },
3031   {
3032     "armv3m",
3033     NULL,
3034     {
3035       isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_bit_armv3m,
3036       isa_nobit
3037     },
3038     "3M", BASE_ARCH_3M,
3039     0,
3040     TARGET_CPU_arm7m,
3041   },
3042   {
3043     "armv4",
3044     NULL,
3045     {
3046       isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
3047       isa_bit_armv3m, isa_nobit
3048     },
3049     "4", BASE_ARCH_4,
3050     0,
3051     TARGET_CPU_arm7tdmi,
3052   },
3053   {
3054     "armv4t",
3055     NULL,
3056     {
3057       isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm,
3058       isa_bit_armv3m, isa_nobit
3059     },
3060     "4T", BASE_ARCH_4T,
3061     0,
3062     TARGET_CPU_arm7tdmi,
3063   },
3064   {
3065     "armv5",
3066     NULL,
3067     {
3068       isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, isa_bit_notm,
3069       isa_bit_armv3m, isa_nobit
3070     },
3071     "5", BASE_ARCH_5,
3072     0,
3073     TARGET_CPU_arm10tdmi,
3074   },
3075   {
3076     "armv5t",
3077     NULL,
3078     {
3079       isa_bit_thumb, isa_bit_armv4, isa_bit_armv5, isa_bit_mode32,
3080       isa_bit_notm, isa_bit_armv3m, isa_nobit
3081     },
3082     "5T", BASE_ARCH_5T,
3083     0,
3084     TARGET_CPU_arm10tdmi,
3085   },
3086   {
3087     "armv5e",
3088     arch_opttab_armv5e,
3089     {
3090       isa_bit_armv5e, isa_bit_armv4, isa_bit_armv5, isa_bit_mode32,
3091       isa_bit_notm, isa_bit_armv3m, isa_nobit
3092     },
3093     "5E", BASE_ARCH_5E,
3094     0,
3095     TARGET_CPU_arm1026ejs,
3096   },
3097   {
3098     "armv5te",
3099     arch_opttab_armv5te,
3100     {
3101       isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5,
3102       isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit
3103     },
3104     "5TE", BASE_ARCH_5TE,
3105     0,
3106     TARGET_CPU_arm1026ejs,
3107   },
3108   {
3109     "armv5tej",
3110     arch_opttab_armv5tej,
3111     {
3112       isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5,
3113       isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit
3114     },
3115     "5TEJ", BASE_ARCH_5TEJ,
3116     0,
3117     TARGET_CPU_arm1026ejs,
3118   },
3119   {
3120     "armv6",
3121     arch_opttab_armv6,
3122     {
3123       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3124       isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm,
3125       isa_bit_armv3m, isa_nobit
3126     },
3127     "6", BASE_ARCH_6,
3128     0,
3129     TARGET_CPU_arm1136js,
3130   },
3131   {
3132     "armv6j",
3133     arch_opttab_armv6j,
3134     {
3135       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3136       isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm,
3137       isa_bit_armv3m, isa_nobit
3138     },
3139     "6J", BASE_ARCH_6J,
3140     0,
3141     TARGET_CPU_arm1136js,
3142   },
3143   {
3144     "armv6k",
3145     arch_opttab_armv6k,
3146     {
3147       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3148       isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm,
3149       isa_bit_armv6k, isa_bit_armv3m, isa_nobit
3150     },
3151     "6K", BASE_ARCH_6K,
3152     0,
3153     TARGET_CPU_mpcore,
3154   },
3155   {
3156     "armv6z",
3157     arch_opttab_armv6z,
3158     {
3159       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3160       isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm,
3161       isa_bit_armv3m, isa_nobit
3162     },
3163     "6Z", BASE_ARCH_6Z,
3164     0,
3165     TARGET_CPU_arm1176jzs,
3166   },
3167   {
3168     "armv6kz",
3169     arch_opttab_armv6kz,
3170     {
3171       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3172       isa_bit_armv5, isa_bit_armv6, isa_bit_quirk_armv6kz, isa_bit_mode32,
3173       isa_bit_notm, isa_bit_armv6k, isa_bit_armv3m, isa_nobit
3174     },
3175     "6KZ", BASE_ARCH_6KZ,
3176     0,
3177     TARGET_CPU_arm1176jzs,
3178   },
3179   {
3180     "armv6zk",
3181     arch_opttab_armv6zk,
3182     {
3183       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3184       isa_bit_armv5, isa_bit_armv6, isa_bit_quirk_armv6kz, isa_bit_mode32,
3185       isa_bit_notm, isa_bit_armv6k, isa_bit_armv3m, isa_nobit
3186     },
3187     "6KZ", BASE_ARCH_6KZ,
3188     0,
3189     TARGET_CPU_arm1176jzs,
3190   },
3191   {
3192     "armv6t2",
3193     arch_opttab_armv6t2,
3194     {
3195       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3196       isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_thumb2,
3197       isa_bit_notm, isa_bit_armv3m, isa_nobit
3198     },
3199     "6T2", BASE_ARCH_6T2,
3200     0,
3201     TARGET_CPU_arm1156t2s,
3202   },
3203   {
3204     "armv6-m",
3205     NULL,
3206     {
3207       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3208       isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
3209       isa_nobit
3210     },
3211     "6M", BASE_ARCH_6M,
3212     'M',
3213     TARGET_CPU_cortexm1,
3214   },
3215   {
3216     "armv6s-m",
3217     NULL,
3218     {
3219       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3220       isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m,
3221       isa_nobit
3222     },
3223     "6M", BASE_ARCH_6M,
3224     'M',
3225     TARGET_CPU_cortexm1,
3226   },
3227   {
3228     "armv7",
3229     arch_opttab_armv7,
3230     {
3231       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3232       isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_mode32,
3233       isa_bit_thumb2, isa_bit_armv3m, isa_nobit
3234     },
3235     "7", BASE_ARCH_7,
3236     0,
3237     TARGET_CPU_cortexa8,
3238   },
3239   {
3240     "armv7-a",
3241     arch_opttab_armv7_a,
3242     {
3243       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3244       isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_mode32,
3245       isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_armv3m,
3246       isa_nobit
3247     },
3248     "7A", BASE_ARCH_7A,
3249     'A',
3250     TARGET_CPU_cortexa8,
3251   },
3252   {
3253     "armv7ve",
3254     arch_opttab_armv7ve,
3255     {
3256       isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
3257       isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
3258       isa_bit_armv7, isa_bit_tdiv, isa_bit_mode32, isa_bit_thumb2,
3259       isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec,
3260       isa_bit_armv3m, isa_nobit
3261     },
3262     "7A", BASE_ARCH_7A,
3263     'A',
3264     TARGET_CPU_cortexa8,
3265   },
3266   {
3267     "armv7-r",
3268     arch_opttab_armv7_r,
3269     {
3270       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3271       isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv,
3272       isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k,
3273       isa_bit_armv3m, isa_nobit
3274     },
3275     "7R", BASE_ARCH_7R,
3276     'R',
3277     TARGET_CPU_cortexr4,
3278   },
3279   {
3280     "armv7-m",
3281     NULL,
3282     {
3283       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3284       isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv,
3285       isa_bit_mode32, isa_bit_thumb2, isa_bit_armv3m, isa_nobit
3286     },
3287     "7M", BASE_ARCH_7M,
3288     'M',
3289     TARGET_CPU_cortexm3,
3290   },
3291   {
3292     "armv7e-m",
3293     arch_opttab_armv7e_m,
3294     {
3295       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3296       isa_bit_armv5, isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7,
3297       isa_bit_tdiv, isa_bit_mode32, isa_bit_thumb2, isa_bit_armv3m,
3298       isa_nobit
3299     },
3300     "7EM", BASE_ARCH_7EM,
3301     'M',
3302     TARGET_CPU_cortexm4,
3303   },
3304   {
3305     "armv8-a",
3306     arch_opttab_armv8_a,
3307     {
3308       isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
3309       isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
3310       isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_mode32,
3311       isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_mp,
3312       isa_bit_sec, isa_bit_armv3m, isa_nobit
3313     },
3314     "8A", BASE_ARCH_8A,
3315     'A',
3316     TARGET_CPU_cortexa53,
3317   },
3318   {
3319     "armv8.1-a",
3320     arch_opttab_armv8_1_a,
3321     {
3322       isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
3323       isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
3324       isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, isa_bit_tdiv,
3325       isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1,
3326       isa_bit_armv6k, isa_bit_mp, isa_bit_sec, isa_bit_armv3m,
3327       isa_nobit
3328     },
3329     "8A", BASE_ARCH_8A,
3330     'A',
3331     TARGET_CPU_cortexa53,
3332   },
3333   {
3334     "armv8.2-a",
3335     arch_opttab_armv8_2_a,
3336     {
3337       isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
3338       isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
3339       isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv,
3340       isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1,
3341       isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_sec,
3342       isa_bit_armv3m, isa_nobit
3343     },
3344     "8A", BASE_ARCH_8A,
3345     'A',
3346     TARGET_CPU_cortexa53,
3347   },
3348   {
3349     "armv8.3-a",
3350     arch_opttab_armv8_3_a,
3351     {
3352       isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
3353       isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
3354       isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv,
3355       isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1,
3356       isa_bit_armv8_2, isa_bit_armv6k, isa_bit_armv8_3, isa_bit_mp,
3357       isa_bit_sec, isa_bit_armv3m, isa_nobit
3358     },
3359     "8A", BASE_ARCH_8A,
3360     'A',
3361     TARGET_CPU_cortexa53,
3362   },
3363   {
3364     "armv8.4-a",
3365     arch_opttab_armv8_4_a,
3366     {
3367       isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
3368       isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
3369       isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv,
3370       isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1,
3371       isa_bit_armv8_2, isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4,
3372       isa_bit_mp, isa_bit_sec, isa_bit_armv3m, isa_nobit
3373     },
3374     "8A", BASE_ARCH_8A,
3375     'A',
3376     TARGET_CPU_cortexa53,
3377   },
3378   {
3379     "armv8-m.base",
3380     NULL,
3381     {
3382       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3383       isa_bit_armv5, isa_bit_armv6, isa_bit_armv8, isa_bit_cmse,
3384       isa_bit_tdiv, isa_bit_mode32, isa_bit_armv3m, isa_nobit
3385     },
3386     "8M_BASE", BASE_ARCH_8M_BASE,
3387     'M',
3388     TARGET_CPU_cortexm23,
3389   },
3390   {
3391     "armv8-m.main",
3392     arch_opttab_armv8_m_main,
3393     {
3394       isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4,
3395       isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_armv8,
3396       isa_bit_cmse, isa_bit_tdiv, isa_bit_mode32, isa_bit_thumb2,
3397       isa_bit_armv3m, isa_nobit
3398     },
3399     "8M_MAIN", BASE_ARCH_8M_MAIN,
3400     'M',
3401     TARGET_CPU_cortexm7,
3402   },
3403   {
3404     "armv8-r",
3405     arch_opttab_armv8_r,
3406     {
3407       isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8,
3408       isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6,
3409       isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_mode32,
3410       isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_mp,
3411       isa_bit_sec, isa_bit_armv3m, isa_nobit
3412     },
3413     "8R", BASE_ARCH_8R,
3414     'R',
3415     TARGET_CPU_cortexr52,
3416   },
3417   {
3418     "iwmmxt",
3419     NULL,
3420     {
3421       isa_bit_armv5e, isa_bit_iwmmxt, isa_bit_xscale, isa_bit_thumb,
3422       isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, isa_bit_notm,
3423       isa_bit_armv3m, isa_nobit
3424     },
3425     "5TE", BASE_ARCH_5TE,
3426     0,
3427     TARGET_CPU_iwmmxt,
3428   },
3429   {
3430     "iwmmxt2",
3431     NULL,
3432     {
3433       isa_bit_armv5e, isa_bit_iwmmxt, isa_bit_xscale, isa_bit_thumb,
3434       isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, isa_bit_iwmmxt2,
3435       isa_bit_notm, isa_bit_armv3m, isa_nobit
3436     },
3437     "5TE", BASE_ARCH_5TE,
3438     0,
3439     TARGET_CPU_iwmmxt2,
3440   },
3441   {{NULL, NULL, {isa_nobit}},
3442    NULL, BASE_ARCH_0, 0, TARGET_CPU_arm_none}
3443 };
3444 
3445 const arm_fpu_desc all_fpus[] =
3446 {
3447   {
3448     "vfp",
3449     {
3450       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
3451     }
3452   },
3453   {
3454     "vfpv2",
3455     {
3456       isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit
3457     }
3458   },
3459   {
3460     "vfpv3",
3461     {
3462       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl,
3463       isa_nobit
3464     }
3465   },
3466   {
3467     "vfpv3-fp16",
3468     {
3469       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv,
3470       isa_bit_fp_dbl, isa_nobit
3471     }
3472   },
3473   {
3474     "vfpv3-d16",
3475     {
3476       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit
3477     }
3478   },
3479   {
3480     "vfpv3-d16-fp16",
3481     {
3482       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl,
3483       isa_nobit
3484     }
3485   },
3486   {
3487     "vfpv3xd",
3488     {
3489       isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit
3490     }
3491   },
3492   {
3493     "vfpv3xd-fp16",
3494     {
3495       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit
3496     }
3497   },
3498   {
3499     "neon",
3500     {
3501       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
3502       isa_bit_fp_dbl, isa_nobit
3503     }
3504   },
3505   {
3506     "neon-vfpv3",
3507     {
3508       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
3509       isa_bit_fp_dbl, isa_nobit
3510     }
3511   },
3512   {
3513     "neon-fp16",
3514     {
3515       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32,
3516       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3517     }
3518   },
3519   {
3520     "vfpv4",
3521     {
3522       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32,
3523       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3524     }
3525   },
3526   {
3527     "neon-vfpv4",
3528     {
3529       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
3530       isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3531     }
3532   },
3533   {
3534     "vfpv4-d16",
3535     {
3536       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
3537       isa_bit_fp_dbl, isa_nobit
3538     }
3539   },
3540   {
3541     "fpv4-sp-d16",
3542     {
3543       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv,
3544       isa_nobit
3545     }
3546   },
3547   {
3548     "fpv5-sp-d16",
3549     {
3550       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
3551       isa_bit_fp16conv, isa_nobit
3552     }
3553   },
3554   {
3555     "fpv5-d16",
3556     {
3557       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
3558       isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3559     }
3560   },
3561   {
3562     "fp-armv8",
3563     {
3564       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5,
3565       isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit
3566     }
3567   },
3568   {
3569     "neon-fp-armv8",
3570     {
3571       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
3572       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl,
3573       isa_nobit
3574     }
3575   },
3576   {
3577     "crypto-neon-fp-armv8",
3578     {
3579       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon,
3580       isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto,
3581       isa_bit_fp_dbl, isa_nobit
3582     }
3583   },
3584   {
3585     "vfp3",
3586     {
3587       isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl,
3588       isa_nobit
3589     }
3590   },
3591 };
3592