1 /* Definitions of target machine for GNU compiler, for Sun SPARC. 2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 4 Free Software Foundation, Inc. 5 Contributed by Michael Tiemann (tiemann@cygnus.com). 6 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 7 at Cygnus Support. 8 9 This file is part of GCC. 10 11 GCC is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 3, or (at your option) 14 any later version. 15 16 GCC is distributed in the hope that it will be useful, 17 but WITHOUT ANY WARRANTY; without even the implied warranty of 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 GNU General Public License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with GCC; see the file COPYING3. If not see 23 <http://www.gnu.org/licenses/>. */ 24 25 #include "config/vxworks-dummy.h" 26 27 /* Note that some other tm.h files include this one and then override 28 whatever definitions are necessary. */ 29 30 /* Define the specific costs for a given cpu */ 31 32 struct processor_costs { 33 /* Integer load */ 34 const int int_load; 35 36 /* Integer signed load */ 37 const int int_sload; 38 39 /* Integer zeroed load */ 40 const int int_zload; 41 42 /* Float load */ 43 const int float_load; 44 45 /* fmov, fneg, fabs */ 46 const int float_move; 47 48 /* fadd, fsub */ 49 const int float_plusminus; 50 51 /* fcmp */ 52 const int float_cmp; 53 54 /* fmov, fmovr */ 55 const int float_cmove; 56 57 /* fmul */ 58 const int float_mul; 59 60 /* fdivs */ 61 const int float_div_sf; 62 63 /* fdivd */ 64 const int float_div_df; 65 66 /* fsqrts */ 67 const int float_sqrt_sf; 68 69 /* fsqrtd */ 70 const int float_sqrt_df; 71 72 /* umul/smul */ 73 const int int_mul; 74 75 /* mulX */ 76 const int int_mulX; 77 78 /* integer multiply cost for each bit set past the most 79 significant 3, so the formula for multiply cost becomes: 80 81 if (rs1 < 0) 82 highest_bit = highest_clear_bit(rs1); 83 else 84 highest_bit = highest_set_bit(rs1); 85 if (highest_bit < 3) 86 highest_bit = 3; 87 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor); 88 89 A value of zero indicates that the multiply costs is fixed, 90 and not variable. */ 91 const int int_mul_bit_factor; 92 93 /* udiv/sdiv */ 94 const int int_div; 95 96 /* divX */ 97 const int int_divX; 98 99 /* movcc, movr */ 100 const int int_cmove; 101 102 /* penalty for shifts, due to scheduling rules etc. */ 103 const int shift_penalty; 104 }; 105 106 extern const struct processor_costs *sparc_costs; 107 108 /* Target CPU builtins. FIXME: Defining sparc is for the benefit of 109 Solaris only; otherwise just define __sparc__. Sadly the headers 110 are such a mess there is no Solaris-specific header. */ 111 #define TARGET_CPU_CPP_BUILTINS() \ 112 do \ 113 { \ 114 builtin_define_std ("sparc"); \ 115 if (TARGET_64BIT) \ 116 { \ 117 builtin_assert ("cpu=sparc64"); \ 118 builtin_assert ("machine=sparc64"); \ 119 } \ 120 else \ 121 { \ 122 builtin_assert ("cpu=sparc"); \ 123 builtin_assert ("machine=sparc"); \ 124 } \ 125 } \ 126 while (0) 127 128 /* Specify this in a cover file to provide bi-architecture (32/64) support. */ 129 /* #define SPARC_BI_ARCH */ 130 131 /* Macro used later in this file to determine default architecture. */ 132 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) 133 134 /* TARGET_ARCH{32,64} are the main macros to decide which of the two 135 architectures to compile for. We allow targets to choose compile time or 136 runtime selection. */ 137 #ifdef IN_LIBGCC2 138 #if defined(__sparcv9) || defined(__arch64__) 139 #define TARGET_ARCH32 0 140 #else 141 #define TARGET_ARCH32 1 142 #endif /* sparc64 */ 143 #else 144 #ifdef SPARC_BI_ARCH 145 #define TARGET_ARCH32 (! TARGET_64BIT) 146 #else 147 #define TARGET_ARCH32 (DEFAULT_ARCH32_P) 148 #endif /* SPARC_BI_ARCH */ 149 #endif /* IN_LIBGCC2 */ 150 #define TARGET_ARCH64 (! TARGET_ARCH32) 151 152 /* Code model selection in 64-bit environment. 153 154 The machine mode used for addresses is 32-bit wide: 155 156 TARGET_CM_32: 32-bit address space. 157 It is the code model used when generating 32-bit code. 158 159 The machine mode used for addresses is 64-bit wide: 160 161 TARGET_CM_MEDLOW: 32-bit address space. 162 The executable must be in the low 32 bits of memory. 163 This avoids generating %uhi and %ulo terms. Programs 164 can be statically or dynamically linked. 165 166 TARGET_CM_MEDMID: 44-bit address space. 167 The executable must be in the low 44 bits of memory, 168 and the %[hml]44 terms are used. The text and data 169 segments have a maximum size of 2GB (31-bit span). 170 The maximum offset from any instruction to the label 171 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 172 173 TARGET_CM_MEDANY: 64-bit address space. 174 The text and data segments have a maximum size of 2GB 175 (31-bit span) and may be located anywhere in memory. 176 The maximum offset from any instruction to the label 177 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 178 179 TARGET_CM_EMBMEDANY: 64-bit address space. 180 The text and data segments have a maximum size of 2GB 181 (31-bit span) and may be located anywhere in memory. 182 The global register %g4 contains the start address of 183 the data segment. Programs are statically linked and 184 PIC is not supported. 185 186 Different code models are not supported in 32-bit environment. */ 187 188 enum cmodel { 189 CM_32, 190 CM_MEDLOW, 191 CM_MEDMID, 192 CM_MEDANY, 193 CM_EMBMEDANY 194 }; 195 196 /* One of CM_FOO. */ 197 extern enum cmodel sparc_cmodel; 198 199 /* V9 code model selection. */ 200 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW) 201 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID) 202 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY) 203 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY) 204 205 #define SPARC_DEFAULT_CMODEL CM_32 206 207 /* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO) 208 which requires the following macro to be true if enabled. Prior to V9, 209 there are no instructions to even talk about memory synchronization. 210 Note that the UltraSPARC III processors don't implement RMO, unlike the 211 UltraSPARC II processors. Niagara and Niagara-2 do not implement RMO 212 either. 213 214 Default to false; for example, Solaris never enables RMO, only ever uses 215 total memory ordering (TMO). */ 216 #define SPARC_RELAXED_ORDERING false 217 218 /* Do not use the .note.GNU-stack convention by default. */ 219 #define NEED_INDICATE_EXEC_STACK 0 220 221 /* This is call-clobbered in the normal ABI, but is reserved in the 222 home grown (aka upward compatible) embedded ABI. */ 223 #define EMBMEDANY_BASE_REG "%g4" 224 225 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, 226 and specified by the user via --with-cpu=foo. 227 This specifies the cpu implementation, not the architecture size. */ 228 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit 229 capable cpu's. */ 230 #define TARGET_CPU_sparc 0 231 #define TARGET_CPU_v7 0 /* alias for previous */ 232 #define TARGET_CPU_sparclet 1 233 #define TARGET_CPU_sparclite 2 234 #define TARGET_CPU_v8 3 /* generic v8 implementation */ 235 #define TARGET_CPU_supersparc 4 236 #define TARGET_CPU_hypersparc 5 237 #define TARGET_CPU_sparc86x 6 238 #define TARGET_CPU_sparclite86x 6 239 #define TARGET_CPU_v9 7 /* generic v9 implementation */ 240 #define TARGET_CPU_sparcv9 7 /* alias */ 241 #define TARGET_CPU_sparc64 7 /* alias */ 242 #define TARGET_CPU_ultrasparc 8 243 #define TARGET_CPU_ultrasparc3 9 244 #define TARGET_CPU_niagara 10 245 #define TARGET_CPU_niagara2 11 246 247 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ 248 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ 249 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ 250 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \ 251 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 252 253 #define CPP_CPU32_DEFAULT_SPEC "" 254 #define ASM_CPU32_DEFAULT_SPEC "" 255 256 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 257 /* ??? What does Sun's CC pass? */ 258 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 259 /* ??? It's not clear how other assemblers will handle this, so by default 260 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case 261 is handled in sol2.h. */ 262 #define ASM_CPU64_DEFAULT_SPEC "-Av9" 263 #endif 264 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc 265 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 266 #define ASM_CPU64_DEFAULT_SPEC "-Av9a" 267 #endif 268 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 269 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 270 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 271 #endif 272 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara 273 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 274 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 275 #endif 276 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 277 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 278 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 279 #endif 280 281 #else 282 283 #define CPP_CPU64_DEFAULT_SPEC "" 284 #define ASM_CPU64_DEFAULT_SPEC "" 285 286 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ 287 || TARGET_CPU_DEFAULT == TARGET_CPU_v8 288 #define CPP_CPU32_DEFAULT_SPEC "" 289 #define ASM_CPU32_DEFAULT_SPEC "" 290 #endif 291 292 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet 293 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" 294 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet" 295 #endif 296 297 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite 298 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" 299 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 300 #endif 301 302 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc 303 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" 304 #define ASM_CPU32_DEFAULT_SPEC "" 305 #endif 306 307 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc 308 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" 309 #define ASM_CPU32_DEFAULT_SPEC "" 310 #endif 311 312 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x 313 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" 314 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 315 #endif 316 317 #endif 318 319 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) 320 #error Unrecognized value in TARGET_CPU_DEFAULT. 321 #endif 322 323 #ifdef SPARC_BI_ARCH 324 325 #define CPP_CPU_DEFAULT_SPEC \ 326 (DEFAULT_ARCH32_P ? "\ 327 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \ 328 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ 329 " : "\ 330 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \ 331 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ 332 ") 333 #define ASM_CPU_DEFAULT_SPEC \ 334 (DEFAULT_ARCH32_P ? "\ 335 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \ 336 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ 337 " : "\ 338 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \ 339 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ 340 ") 341 342 #else /* !SPARC_BI_ARCH */ 343 344 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) 345 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) 346 347 #endif /* !SPARC_BI_ARCH */ 348 349 /* Define macros to distinguish architectures. */ 350 351 /* Common CPP definitions used by CPP_SPEC amongst the various targets 352 for handling -mcpu=xxx switches. */ 353 #define CPP_CPU_SPEC "\ 354 %{msoft-float:-D_SOFT_FLOAT} \ 355 %{mcypress:} \ 356 %{msparclite:-D__sparclite__} \ 357 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ 358 %{mv8:-D__sparc_v8__} \ 359 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \ 360 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ 361 %{mcpu=sparclite:-D__sparclite__} \ 362 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ 363 %{mcpu=v8:-D__sparc_v8__} \ 364 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ 365 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ 366 %{mcpu=sparclite86x:-D__sparclite86x__} \ 367 %{mcpu=v9:-D__sparc_v9__} \ 368 %{mcpu=ultrasparc:-D__sparc_v9__} \ 369 %{mcpu=ultrasparc3:-D__sparc_v9__} \ 370 %{mcpu=niagara:-D__sparc_v9__} \ 371 %{mcpu=niagara2:-D__sparc_v9__} \ 372 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ 373 " 374 #define CPP_ARCH32_SPEC "" 375 #define CPP_ARCH64_SPEC "-D__arch64__" 376 377 #define CPP_ARCH_DEFAULT_SPEC \ 378 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) 379 380 #define CPP_ARCH_SPEC "\ 381 %{m32:%(cpp_arch32)} \ 382 %{m64:%(cpp_arch64)} \ 383 %{!m32:%{!m64:%(cpp_arch_default)}} \ 384 " 385 386 /* Macros to distinguish endianness. */ 387 #define CPP_ENDIAN_SPEC "\ 388 %{mlittle-endian:-D__LITTLE_ENDIAN__} \ 389 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}" 390 391 /* Macros to distinguish the particular subtarget. */ 392 #define CPP_SUBTARGET_SPEC "" 393 394 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)" 395 396 /* Prevent error on `-sun4' and `-target sun4' options. */ 397 /* This used to translate -dalign to -malign, but that is no good 398 because it can't turn off the usual meaning of making debugging dumps. */ 399 /* Translate old style -m<cpu> into new style -mcpu=<cpu>. 400 ??? Delete support for -m<cpu> for 2.9. */ 401 402 #define CC1_SPEC "\ 403 %{sun4:} %{target:} \ 404 %{mcypress:-mcpu=cypress} \ 405 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \ 406 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \ 407 " 408 409 /* Override in target specific files. */ 410 #define ASM_CPU_SPEC "\ 411 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ 412 %{msparclite:-Asparclite} \ 413 %{mf930:-Asparclite} %{mf934:-Asparclite} \ 414 %{mcpu=sparclite:-Asparclite} \ 415 %{mcpu=sparclite86x:-Asparclite} \ 416 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ 417 %{mcpu=v8:-Av8} \ 418 %{mv8plus:-Av8plus} \ 419 %{mcpu=v9:-Av9} \ 420 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ 421 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ 422 %{mcpu=niagara:%{!mv8plus:-Av9b}} \ 423 %{mcpu=niagara2:%{!mv8plus:-Av9b}} \ 424 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \ 425 " 426 427 /* Word size selection, among other things. 428 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ 429 430 #define ASM_ARCH32_SPEC "-32" 431 #ifdef HAVE_AS_REGISTER_PSEUDO_OP 432 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" 433 #else 434 #define ASM_ARCH64_SPEC "-64" 435 #endif 436 #define ASM_ARCH_DEFAULT_SPEC \ 437 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) 438 439 #define ASM_ARCH_SPEC "\ 440 %{m32:%(asm_arch32)} \ 441 %{m64:%(asm_arch64)} \ 442 %{!m32:%{!m64:%(asm_arch_default)}} \ 443 " 444 445 #ifdef HAVE_AS_RELAX_OPTION 446 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}" 447 #else 448 #define ASM_RELAX_SPEC "" 449 #endif 450 451 /* Special flags to the Sun-4 assembler when using pipe for input. */ 452 453 #define ASM_SPEC "\ 454 %{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \ 455 %(asm_cpu) %(asm_relax)" 456 457 #define AS_NEEDS_DASH_FOR_PIPED_INPUT 458 459 /* This macro defines names of additional specifications to put in the specs 460 that can be used in various specifications like CC1_SPEC. Its definition 461 is an initializer with a subgrouping for each command option. 462 463 Each subgrouping contains a string constant, that defines the 464 specification name, and a string constant that used by the GCC driver 465 program. 466 467 Do not define this macro if it does not need to do anything. */ 468 469 #define EXTRA_SPECS \ 470 { "cpp_cpu", CPP_CPU_SPEC }, \ 471 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 472 { "cpp_arch32", CPP_ARCH32_SPEC }, \ 473 { "cpp_arch64", CPP_ARCH64_SPEC }, \ 474 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ 475 { "cpp_arch", CPP_ARCH_SPEC }, \ 476 { "cpp_endian", CPP_ENDIAN_SPEC }, \ 477 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ 478 { "asm_cpu", ASM_CPU_SPEC }, \ 479 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ 480 { "asm_arch32", ASM_ARCH32_SPEC }, \ 481 { "asm_arch64", ASM_ARCH64_SPEC }, \ 482 { "asm_relax", ASM_RELAX_SPEC }, \ 483 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ 484 { "asm_arch", ASM_ARCH_SPEC }, \ 485 SUBTARGET_EXTRA_SPECS 486 487 #define SUBTARGET_EXTRA_SPECS 488 489 /* Because libgcc can generate references back to libc (via .umul etc.) we have 490 to list libc again after the second libgcc. */ 491 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L" 492 493 494 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") 495 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") 496 497 /* ??? This should be 32 bits for v9 but what can we do? */ 498 #define WCHAR_TYPE "short unsigned int" 499 #define WCHAR_TYPE_SIZE 16 500 501 /* Show we can debug even without a frame pointer. */ 502 #define CAN_DEBUG_WITHOUT_FP 503 504 /* Option handling. */ 505 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 506 sparc_optimization_options ((LEVEL), (SIZE)) 507 #define OVERRIDE_OPTIONS sparc_override_options () 508 509 /* Mask of all CPU selection flags. */ 510 #define MASK_ISA \ 511 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS) 512 513 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y. 514 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y 515 to get high 32 bits. False in V8+ or V9 because multiply stores 516 a 64-bit result in a register. */ 517 518 #define TARGET_HARD_MUL32 \ 519 ((TARGET_V8 || TARGET_SPARCLITE \ 520 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \ 521 && ! TARGET_V8PLUS && TARGET_ARCH32) 522 523 #define TARGET_HARD_MUL \ 524 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \ 525 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS) 526 527 /* MASK_APP_REGS must always be the default because that's what 528 FIXED_REGISTERS is set to and -ffixed- is processed before 529 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */ 530 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) 531 532 /* Processor type. 533 These must match the values for the cpu attribute in sparc.md. */ 534 enum processor_type { 535 PROCESSOR_V7, 536 PROCESSOR_CYPRESS, 537 PROCESSOR_V8, 538 PROCESSOR_SUPERSPARC, 539 PROCESSOR_SPARCLITE, 540 PROCESSOR_F930, 541 PROCESSOR_F934, 542 PROCESSOR_HYPERSPARC, 543 PROCESSOR_SPARCLITE86X, 544 PROCESSOR_SPARCLET, 545 PROCESSOR_TSC701, 546 PROCESSOR_V9, 547 PROCESSOR_ULTRASPARC, 548 PROCESSOR_ULTRASPARC3, 549 PROCESSOR_NIAGARA, 550 PROCESSOR_NIAGARA2 551 }; 552 553 /* This is set from -m{cpu,tune}=xxx. */ 554 extern enum processor_type sparc_cpu; 555 556 /* Recast the cpu class to be the cpu attribute. 557 Every file includes us, but not every file includes insn-attr.h. */ 558 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) 559 560 /* Support for a compile-time default CPU, et cetera. The rules are: 561 --with-cpu is ignored if -mcpu is specified. 562 --with-tune is ignored if -mtune is specified. 563 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu 564 are specified. */ 565 #define OPTION_DEFAULT_SPECS \ 566 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 567 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 568 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" } 569 570 /* sparc_select[0] is reserved for the default cpu. */ 571 struct sparc_cpu_select 572 { 573 const char *string; 574 const char *const name; 575 const int set_tune_p; 576 const int set_arch_p; 577 }; 578 579 extern struct sparc_cpu_select sparc_select[]; 580 581 /* target machine storage layout */ 582 583 /* Define this if most significant bit is lowest numbered 584 in instructions that operate on numbered bit-fields. */ 585 #define BITS_BIG_ENDIAN 1 586 587 /* Define this if most significant byte of a word is the lowest numbered. */ 588 #define BYTES_BIG_ENDIAN 1 589 590 /* Define this if most significant word of a multiword number is the lowest 591 numbered. */ 592 #define WORDS_BIG_ENDIAN 1 593 594 /* Define this to set the endianness to use in libgcc2.c, which can 595 not depend on target_flags. */ 596 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__) 597 #define LIBGCC2_WORDS_BIG_ENDIAN 0 598 #else 599 #define LIBGCC2_WORDS_BIG_ENDIAN 1 600 #endif 601 602 #define MAX_BITS_PER_WORD 64 603 604 /* Width of a word, in units (bytes). */ 605 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) 606 #ifdef IN_LIBGCC2 607 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 608 #else 609 #define MIN_UNITS_PER_WORD 4 610 #endif 611 612 #define UNITS_PER_SIMD_WORD(MODE) (TARGET_VIS ? 8 : UNITS_PER_WORD) 613 614 /* Now define the sizes of the C data types. */ 615 616 #define SHORT_TYPE_SIZE 16 617 #define INT_TYPE_SIZE 32 618 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) 619 #define LONG_LONG_TYPE_SIZE 64 620 #define FLOAT_TYPE_SIZE 32 621 #define DOUBLE_TYPE_SIZE 64 622 623 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the 624 SPARC ABI says that it is 128-bit wide. */ 625 /* #define LONG_DOUBLE_TYPE_SIZE 128 */ 626 627 /* The widest floating-point format really supported by the hardware. */ 628 #define WIDEST_HARDWARE_FP_SIZE 64 629 630 /* Width in bits of a pointer. This is the size of ptr_mode. */ 631 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) 632 633 /* This is the machine mode used for addresses. */ 634 #define Pmode (TARGET_ARCH64 ? DImode : SImode) 635 636 /* If we have to extend pointers (only when TARGET_ARCH64 and not 637 TARGET_PTR64), we want to do it unsigned. This macro does nothing 638 if ptr_mode and Pmode are the same. */ 639 #define POINTERS_EXTEND_UNSIGNED 1 640 641 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 642 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 643 644 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 645 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because 646 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */ 647 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) 648 /* Temporary hack until the FIXME above is fixed. */ 649 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS) 650 651 /* ALIGN FRAMES on double word boundaries */ 652 653 #define SPARC_STACK_ALIGN(LOC) \ 654 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) 655 656 /* Allocation boundary (in *bits*) for the code of a function. */ 657 #define FUNCTION_BOUNDARY 32 658 659 /* Alignment of field after `int : 0' in a structure. */ 660 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 661 662 /* Every structure's size must be a multiple of this. */ 663 #define STRUCTURE_SIZE_BOUNDARY 8 664 665 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 666 #define PCC_BITFIELD_TYPE_MATTERS 1 667 668 /* No data type wants to be aligned rounder than this. */ 669 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) 670 671 /* The best alignment to use in cases where we have a choice. */ 672 #define FASTEST_ALIGNMENT 64 673 674 /* Define this macro as an expression for the alignment of a structure 675 (given by STRUCT as a tree node) if the alignment computed in the 676 usual way is COMPUTED and the alignment explicitly specified was 677 SPECIFIED. 678 679 The default is to use SPECIFIED if it is larger; otherwise, use 680 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ 681 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ 682 (TARGET_FASTER_STRUCTS ? \ 683 ((TREE_CODE (STRUCT) == RECORD_TYPE \ 684 || TREE_CODE (STRUCT) == UNION_TYPE \ 685 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ 686 && TYPE_FIELDS (STRUCT) != 0 \ 687 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ 688 : MAX ((COMPUTED), (SPECIFIED))) \ 689 : MAX ((COMPUTED), (SPECIFIED))) 690 691 /* Make strings word-aligned so strcpy from constants will be faster. */ 692 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 693 ((TREE_CODE (EXP) == STRING_CST \ 694 && (ALIGN) < FASTEST_ALIGNMENT) \ 695 ? FASTEST_ALIGNMENT : (ALIGN)) 696 697 /* Make arrays of chars word-aligned for the same reasons. */ 698 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 699 (TREE_CODE (TYPE) == ARRAY_TYPE \ 700 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 701 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 702 703 /* Make local arrays of chars word-aligned for the same reasons. */ 704 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN) 705 706 /* Set this nonzero if move instructions will actually fail to work 707 when given unaligned data. */ 708 #define STRICT_ALIGNMENT 1 709 710 /* Things that must be doubleword aligned cannot go in the text section, 711 because the linker fails to align the text section enough! 712 Put them in the data section. This macro is only used in this file. */ 713 #define MAX_TEXT_ALIGN 32 714 715 /* Standard register usage. */ 716 717 /* Number of actual hardware registers. 718 The hardware registers are assigned numbers for the compiler 719 from 0 to just below FIRST_PSEUDO_REGISTER. 720 All registers that the compiler knows about must be given numbers, 721 even those that are not normally considered general registers. 722 723 SPARC has 32 integer registers and 32 floating point registers. 724 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not 725 accessible. We still account for them to simplify register computations 726 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so 727 32+32+32+4 == 100. 728 Register 100 is used as the integer condition code register. 729 Register 101 is used as the soft frame pointer register. */ 730 731 #define FIRST_PSEUDO_REGISTER 102 732 733 #define SPARC_FIRST_FP_REG 32 734 /* Additional V9 fp regs. */ 735 #define SPARC_FIRST_V9_FP_REG 64 736 #define SPARC_LAST_V9_FP_REG 95 737 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ 738 #define SPARC_FIRST_V9_FCC_REG 96 739 #define SPARC_LAST_V9_FCC_REG 99 740 /* V8 fcc reg. */ 741 #define SPARC_FCC_REG 96 742 /* Integer CC reg. We don't distinguish %icc from %xcc. */ 743 #define SPARC_ICC_REG 100 744 745 /* Nonzero if REGNO is an fp reg. */ 746 #define SPARC_FP_REG_P(REGNO) \ 747 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) 748 749 /* Argument passing regs. */ 750 #define SPARC_OUTGOING_INT_ARG_FIRST 8 751 #define SPARC_INCOMING_INT_ARG_FIRST 24 752 #define SPARC_FP_ARG_FIRST 32 753 754 /* 1 for registers that have pervasive standard uses 755 and are not available for the register allocator. 756 757 On non-v9 systems: 758 g1 is free to use as temporary. 759 g2-g4 are reserved for applications. Gcc normally uses them as 760 temporaries, but this can be disabled via the -mno-app-regs option. 761 g5 through g7 are reserved for the operating system. 762 763 On v9 systems: 764 g1,g5 are free to use as temporaries, and are free to use between calls 765 if the call is to an external function via the PLT. 766 g4 is free to use as a temporary in the non-embedded case. 767 g4 is reserved in the embedded case. 768 g2-g3 are reserved for applications. Gcc normally uses them as 769 temporaries, but this can be disabled via the -mno-app-regs option. 770 g6-g7 are reserved for the operating system (or application in 771 embedded case). 772 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must 773 currently be a fixed register until this pattern is rewritten. 774 Register 1 is also used when restoring call-preserved registers in large 775 stack frames. 776 777 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in 778 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. 779 */ 780 781 #define FIXED_REGISTERS \ 782 {1, 0, 2, 2, 2, 2, 1, 1, \ 783 0, 0, 0, 0, 0, 0, 1, 0, \ 784 0, 0, 0, 0, 0, 0, 0, 0, \ 785 0, 0, 0, 0, 0, 0, 1, 1, \ 786 \ 787 0, 0, 0, 0, 0, 0, 0, 0, \ 788 0, 0, 0, 0, 0, 0, 0, 0, \ 789 0, 0, 0, 0, 0, 0, 0, 0, \ 790 0, 0, 0, 0, 0, 0, 0, 0, \ 791 \ 792 0, 0, 0, 0, 0, 0, 0, 0, \ 793 0, 0, 0, 0, 0, 0, 0, 0, \ 794 0, 0, 0, 0, 0, 0, 0, 0, \ 795 0, 0, 0, 0, 0, 0, 0, 0, \ 796 \ 797 0, 0, 0, 0, 0, 1} 798 799 /* 1 for registers not available across function calls. 800 These must include the FIXED_REGISTERS and also any 801 registers that can be used without being saved. 802 The latter must include the registers where values are returned 803 and the register where structure-value addresses are passed. 804 Aside from that, you can include as many other registers as you like. */ 805 806 #define CALL_USED_REGISTERS \ 807 {1, 1, 1, 1, 1, 1, 1, 1, \ 808 1, 1, 1, 1, 1, 1, 1, 1, \ 809 0, 0, 0, 0, 0, 0, 0, 0, \ 810 0, 0, 0, 0, 0, 0, 1, 1, \ 811 \ 812 1, 1, 1, 1, 1, 1, 1, 1, \ 813 1, 1, 1, 1, 1, 1, 1, 1, \ 814 1, 1, 1, 1, 1, 1, 1, 1, \ 815 1, 1, 1, 1, 1, 1, 1, 1, \ 816 \ 817 1, 1, 1, 1, 1, 1, 1, 1, \ 818 1, 1, 1, 1, 1, 1, 1, 1, \ 819 1, 1, 1, 1, 1, 1, 1, 1, \ 820 1, 1, 1, 1, 1, 1, 1, 1, \ 821 \ 822 1, 1, 1, 1, 1, 1} 823 824 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that 825 they won't be allocated. */ 826 827 #define CONDITIONAL_REGISTER_USAGE \ 828 do \ 829 { \ 830 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 831 { \ 832 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 833 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 834 } \ 835 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \ 836 /* then honor it. */ \ 837 if (TARGET_ARCH32 && fixed_regs[5]) \ 838 fixed_regs[5] = 1; \ 839 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \ 840 fixed_regs[5] = 0; \ 841 if (! TARGET_V9) \ 842 { \ 843 int regno; \ 844 for (regno = SPARC_FIRST_V9_FP_REG; \ 845 regno <= SPARC_LAST_V9_FP_REG; \ 846 regno++) \ 847 fixed_regs[regno] = 1; \ 848 /* %fcc0 is used by v8 and v9. */ \ 849 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \ 850 regno <= SPARC_LAST_V9_FCC_REG; \ 851 regno++) \ 852 fixed_regs[regno] = 1; \ 853 } \ 854 if (! TARGET_FPU) \ 855 { \ 856 int regno; \ 857 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \ 858 fixed_regs[regno] = 1; \ 859 } \ 860 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \ 861 /* then honor it. Likewise with g3 and g4. */ \ 862 if (fixed_regs[2] == 2) \ 863 fixed_regs[2] = ! TARGET_APP_REGS; \ 864 if (fixed_regs[3] == 2) \ 865 fixed_regs[3] = ! TARGET_APP_REGS; \ 866 if (TARGET_ARCH32 && fixed_regs[4] == 2) \ 867 fixed_regs[4] = ! TARGET_APP_REGS; \ 868 else if (TARGET_CM_EMBMEDANY) \ 869 fixed_regs[4] = 1; \ 870 else if (fixed_regs[4] == 2) \ 871 fixed_regs[4] = 0; \ 872 } \ 873 while (0) 874 875 /* Return number of consecutive hard regs needed starting at reg REGNO 876 to hold something of mode MODE. 877 This is ordinarily the length in words of a value of mode MODE 878 but can be less for certain modes in special long registers. 879 880 On SPARC, ordinary registers hold 32 bits worth; 881 this means both integer and floating point registers. 882 On v9, integer regs hold 64 bits worth; floating point regs hold 883 32 bits worth (this includes the new fp regs as even the odd ones are 884 included in the hard register count). */ 885 886 #define HARD_REGNO_NREGS(REGNO, MODE) \ 887 (TARGET_ARCH64 \ 888 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \ 889 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ 890 : (GET_MODE_SIZE (MODE) + 3) / 4) \ 891 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 892 893 /* Due to the ARCH64 discrepancy above we must override this next 894 macro too. */ 895 #define REGMODE_NATURAL_SIZE(MODE) \ 896 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD) 897 898 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 899 See sparc.c for how we initialize this. */ 900 extern const int *hard_regno_mode_classes; 901 extern int sparc_mode_class[]; 902 903 /* ??? Because of the funny way we pass parameters we should allow certain 904 ??? types of float/complex values to be in integer registers during 905 ??? RTL generation. This only matters on arch32. */ 906 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 907 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) 908 909 /* Value is 1 if it is OK to rename a hard register FROM to another hard 910 register TO. We cannot rename %g1 as it may be used before the save 911 register window instruction in the prologue. */ 912 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1) 913 914 /* Value is 1 if it is a good idea to tie two pseudo registers 915 when one has mode MODE1 and one has mode MODE2. 916 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 917 for any hard reg, then this must be 0 for correct output. 918 919 For V9: SFmode can't be combined with other float modes, because they can't 920 be allocated to the %d registers. Also, DFmode won't fit in odd %f 921 registers, but SFmode will. */ 922 #define MODES_TIEABLE_P(MODE1, MODE2) \ 923 ((MODE1) == (MODE2) \ 924 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ 925 && (! TARGET_V9 \ 926 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \ 927 || (MODE1 != SFmode && MODE2 != SFmode))))) 928 929 /* Specify the registers used for certain standard purposes. 930 The values of these macros are register numbers. */ 931 932 /* Register to use for pushing function arguments. */ 933 #define STACK_POINTER_REGNUM 14 934 935 /* The stack bias (amount by which the hardware register is offset by). */ 936 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) 937 938 /* Actual top-of-stack address is 92/176 greater than the contents of the 939 stack pointer register for !v9/v9. That is: 940 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return 941 address, and 6*4 bytes for the 6 register parameters. 942 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer 943 parameter regs. */ 944 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) 945 946 /* Base register for access to local variables of the function. */ 947 #define HARD_FRAME_POINTER_REGNUM 30 948 949 /* The soft frame pointer does not have the stack bias applied. */ 950 #define FRAME_POINTER_REGNUM 101 951 952 /* Given the stack bias, the stack pointer isn't actually aligned. */ 953 #define INIT_EXPANDERS \ 954 do { \ 955 if (crtl->emit.regno_pointer_align && SPARC_STACK_BIAS) \ 956 { \ 957 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \ 958 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \ 959 } \ 960 } while (0) 961 962 /* Base register for access to arguments of the function. */ 963 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 964 965 /* Register in which static-chain is passed to a function. This must 966 not be a register used by the prologue. */ 967 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) 968 969 /* Register which holds the global offset table, if any. */ 970 971 #define GLOBAL_OFFSET_TABLE_REGNUM 23 972 973 /* Register which holds offset table for position-independent 974 data references. */ 975 976 #define PIC_OFFSET_TABLE_REGNUM \ 977 (flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM) 978 979 /* Pick a default value we can notice from override_options: 980 !v9: Default is on. 981 v9: Default is off. 982 Originally it was -1, but later on the container of options changed to 983 unsigned byte, so we decided to pick 127 as default value, which does 984 reflect an undefined default value in case of 0/1. */ 985 986 #define DEFAULT_PCC_STRUCT_RETURN 127 987 988 /* Functions which return large structures get the address 989 to place the wanted value at offset 64 from the frame. 990 Must reserve 64 bytes for the in and local registers. 991 v9: Functions which return large structures get the address to place the 992 wanted value from an invisible first argument. */ 993 #define STRUCT_VALUE_OFFSET 64 994 995 /* Define the classes of registers for register constraints in the 996 machine description. Also define ranges of constants. 997 998 One of the classes must always be named ALL_REGS and include all hard regs. 999 If there is more than one class, another class must be named NO_REGS 1000 and contain no registers. 1001 1002 The name GENERAL_REGS must be the name of a class (or an alias for 1003 another name such as ALL_REGS). This is the class of registers 1004 that is allowed by "g" or "r" in a register constraint. 1005 Also, registers outside this class are allocated only when 1006 instructions express preferences for them. 1007 1008 The classes must be numbered in nondecreasing order; that is, 1009 a larger-numbered class must never be contained completely 1010 in a smaller-numbered class. 1011 1012 For any two classes, it is very desirable that there be another 1013 class that represents their union. */ 1014 1015 /* The SPARC has various kinds of registers: general, floating point, 1016 and condition codes [well, it has others as well, but none that we 1017 care directly about]. 1018 1019 For v9 we must distinguish between the upper and lower floating point 1020 registers because the upper ones can't hold SFmode values. 1021 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) 1022 satisfying a group need for a class will also satisfy a single need for 1023 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp 1024 regs. 1025 1026 It is important that one class contains all the general and all the standard 1027 fp regs. Otherwise find_reg() won't properly allocate int regs for moves, 1028 because reg_class_record() will bias the selection in favor of fp regs, 1029 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, 1030 because FP_REGS > GENERAL_REGS. 1031 1032 It is also important that one class contain all the general and all 1033 the fp regs. Otherwise when spilling a DFmode reg, it may be from 1034 EXTRA_FP_REGS but find_reloads() may use class 1035 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die 1036 because the compiler thinks it doesn't have a spill reg when in 1037 fact it does. 1038 1039 v9 also has 4 floating point condition code registers. Since we don't 1040 have a class that is the union of FPCC_REGS with either of the others, 1041 it is important that it appear first. Otherwise the compiler will die 1042 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its 1043 constraints. 1044 1045 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine 1046 may try to use it to hold an SImode value. See register_operand. 1047 ??? Should %fcc[0123] be handled similarly? 1048 */ 1049 1050 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, 1051 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, 1052 ALL_REGS, LIM_REG_CLASSES }; 1053 1054 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1055 1056 /* Give names of register classes as strings for dump file. */ 1057 1058 #define REG_CLASS_NAMES \ 1059 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ 1060 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ 1061 "ALL_REGS" } 1062 1063 /* Define which registers fit in which classes. 1064 This is an initializer for a vector of HARD_REG_SET 1065 of length N_REG_CLASSES. */ 1066 1067 #define REG_CLASS_CONTENTS \ 1068 {{0, 0, 0, 0}, /* NO_REGS */ \ 1069 {0, 0, 0, 0xf}, /* FPCC_REGS */ \ 1070 {0xffff, 0, 0, 0}, /* I64_REGS */ \ 1071 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ 1072 {0, -1, 0, 0}, /* FP_REGS */ \ 1073 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ 1074 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ 1075 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ 1076 {-1, -1, -1, 0x3f}} /* ALL_REGS */ 1077 1078 /* The same information, inverted: 1079 Return the class number of the smallest class containing 1080 reg number REGNO. This could be a conditional expression 1081 or could index an array. */ 1082 1083 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 1084 1085 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] 1086 1087 /* The following macro defines cover classes for Integrated Register 1088 Allocator. Cover classes is a set of non-intersected register 1089 classes covering all hard registers used for register allocation 1090 purpose. Any move between two registers of a cover class should be 1091 cheaper than load or store of the registers. The macro value is 1092 array of register classes with LIM_REG_CLASSES used as the end 1093 marker. */ 1094 1095 #define IRA_COVER_CLASSES \ 1096 { \ 1097 GENERAL_REGS, EXTRA_FP_REGS, FPCC_REGS, LIM_REG_CLASSES \ 1098 } 1099 1100 /* Defines invalid mode changes. Borrowed from pa64-regs.h. 1101 1102 SImode loads to floating-point registers are not zero-extended. 1103 The definition for LOAD_EXTEND_OP specifies that integer loads 1104 narrower than BITS_PER_WORD will be zero-extended. As a result, 1105 we inhibit changes from SImode unless they are to a mode that is 1106 identical in size. */ 1107 1108 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1109 (TARGET_ARCH64 \ 1110 && (FROM) == SImode \ 1111 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1112 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) 1113 1114 /* This is the order in which to allocate registers normally. 1115 1116 We put %f0-%f7 last among the float registers, so as to make it more 1117 likely that a pseudo-register which dies in the float return register 1118 area will get allocated to the float return register, thus saving a move 1119 instruction at the end of the function. 1120 1121 Similarly for integer return value registers. 1122 1123 We know in this case that we will not end up with a leaf function. 1124 1125 The register allocator is given the global and out registers first 1126 because these registers are call clobbered and thus less useful to 1127 global register allocation. 1128 1129 Next we list the local and in registers. They are not call clobbered 1130 and thus very useful for global register allocation. We list the input 1131 registers before the locals so that it is more likely the incoming 1132 arguments received in those registers can just stay there and not be 1133 reloaded. */ 1134 1135 #define REG_ALLOC_ORDER \ 1136 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 1137 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 1138 15, /* %o7 */ \ 1139 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 1140 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ 1141 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 1142 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 1143 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 1144 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 1145 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 1146 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 1147 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 1148 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 1149 96, 97, 98, 99, /* %fcc0-3 */ \ 1150 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */ 1151 1152 /* This is the order in which to allocate registers for 1153 leaf functions. If all registers can fit in the global and 1154 output registers, then we have the possibility of having a leaf 1155 function. 1156 1157 The macro actually mentioned the input registers first, 1158 because they get renumbered into the output registers once 1159 we know really do have a leaf function. 1160 1161 To be more precise, this register allocation order is used 1162 when %o7 is found to not be clobbered right before register 1163 allocation. Normally, the reason %o7 would be clobbered is 1164 due to a call which could not be transformed into a sibling 1165 call. 1166 1167 As a consequence, it is possible to use the leaf register 1168 allocation order and not end up with a leaf function. We will 1169 not get suboptimal register allocation in that case because by 1170 definition of being potentially leaf, there were no function 1171 calls. Therefore, allocation order within the local register 1172 window is not critical like it is when we do have function calls. */ 1173 1174 #define REG_LEAF_ALLOC_ORDER \ 1175 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 1176 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ 1177 15, /* %o7 */ \ 1178 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 1179 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 1180 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 1181 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 1182 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 1183 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 1184 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 1185 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 1186 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 1187 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 1188 96, 97, 98, 99, /* %fcc0-3 */ \ 1189 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */ 1190 1191 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () 1192 1193 extern char sparc_leaf_regs[]; 1194 #define LEAF_REGISTERS sparc_leaf_regs 1195 1196 extern char leaf_reg_remap[]; 1197 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) 1198 1199 /* The class value for index registers, and the one for base regs. */ 1200 #define INDEX_REG_CLASS GENERAL_REGS 1201 #define BASE_REG_CLASS GENERAL_REGS 1202 1203 /* Local macro to handle the two v9 classes of FP regs. */ 1204 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) 1205 1206 /* Predicates for 10-bit, 11-bit and 13-bit signed constants. */ 1207 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) 1208 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) 1209 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) 1210 1211 /* 10- and 11-bit immediates are only used for a few specific insns. 1212 SMALL_INT is used throughout the port so we continue to use it. */ 1213 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) 1214 1215 /* Predicate for constants that can be loaded with a sethi instruction. 1216 This is the general, 64-bit aware, bitwise version that ensures that 1217 only constants whose representation fits in the mask 1218 1219 0x00000000fffffc00 1220 1221 are accepted. It will reject, for example, negative SImode constants 1222 on 64-bit hosts, so correct handling is to mask the value beforehand 1223 according to the mode of the instruction. */ 1224 #define SPARC_SETHI_P(X) \ 1225 (((unsigned HOST_WIDE_INT) (X) \ 1226 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) 1227 1228 /* Version of the above predicate for SImode constants and below. */ 1229 #define SPARC_SETHI32_P(X) \ 1230 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) 1231 1232 /* Given an rtx X being reloaded into a reg required to be 1233 in class CLASS, return the class of reg to actually use. 1234 In general this is just CLASS; but on some machines 1235 in some cases it is preferable to use a more restrictive class. */ 1236 /* - We can't load constants into FP registers. 1237 - We can't load FP constants into integer registers when soft-float, 1238 because there is no soft-float pattern with a r/F constraint. 1239 - We can't load FP constants into integer registers for TFmode unless 1240 it is 0.0L, because there is no movtf pattern with a r/F constraint. 1241 - Try and reload integer constants (symbolic or otherwise) back into 1242 registers directly, rather than having them dumped to memory. */ 1243 1244 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1245 (CONSTANT_P (X) \ 1246 ? ((FP_REG_CLASS_P (CLASS) \ 1247 || (CLASS) == GENERAL_OR_FP_REGS \ 1248 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \ 1249 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 1250 && ! TARGET_FPU) \ 1251 || (GET_MODE (X) == TFmode \ 1252 && ! const_zero_operand (X, TFmode))) \ 1253 ? NO_REGS \ 1254 : (!FP_REG_CLASS_P (CLASS) \ 1255 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \ 1256 ? GENERAL_REGS \ 1257 : (CLASS)) \ 1258 : (CLASS)) 1259 1260 /* Return the register class of a scratch register needed to load IN into 1261 a register of class CLASS in MODE. 1262 1263 We need a temporary when loading/storing a HImode/QImode value 1264 between memory and the FPU registers. This can happen when combine puts 1265 a paradoxical subreg in a float/fix conversion insn. 1266 1267 We need a temporary when loading/storing a DFmode value between 1268 unaligned memory and the upper FPU registers. */ 1269 1270 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1271 ((FP_REG_CLASS_P (CLASS) \ 1272 && ((MODE) == HImode || (MODE) == QImode) \ 1273 && (GET_CODE (IN) == MEM \ 1274 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ 1275 && true_regnum (IN) == -1))) \ 1276 ? GENERAL_REGS \ 1277 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ 1278 && GET_CODE (IN) == MEM && TARGET_ARCH32 \ 1279 && ! mem_min_alignment ((IN), 8)) \ 1280 ? FP_REGS \ 1281 : (((TARGET_CM_MEDANY \ 1282 && symbolic_operand ((IN), (MODE))) \ 1283 || (TARGET_CM_EMBMEDANY \ 1284 && text_segment_operand ((IN), (MODE)))) \ 1285 && !flag_pic) \ 1286 ? GENERAL_REGS \ 1287 : NO_REGS) 1288 1289 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ 1290 ((FP_REG_CLASS_P (CLASS) \ 1291 && ((MODE) == HImode || (MODE) == QImode) \ 1292 && (GET_CODE (IN) == MEM \ 1293 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ 1294 && true_regnum (IN) == -1))) \ 1295 ? GENERAL_REGS \ 1296 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ 1297 && GET_CODE (IN) == MEM && TARGET_ARCH32 \ 1298 && ! mem_min_alignment ((IN), 8)) \ 1299 ? FP_REGS \ 1300 : (((TARGET_CM_MEDANY \ 1301 && symbolic_operand ((IN), (MODE))) \ 1302 || (TARGET_CM_EMBMEDANY \ 1303 && text_segment_operand ((IN), (MODE)))) \ 1304 && !flag_pic) \ 1305 ? GENERAL_REGS \ 1306 : NO_REGS) 1307 1308 /* On SPARC it is not possible to directly move data between 1309 GENERAL_REGS and FP_REGS. */ 1310 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1311 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) 1312 1313 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9 1314 because the movsi and movsf patterns don't handle r/f moves. 1315 For v8 we copy the default definition. */ 1316 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1317 (TARGET_ARCH64 \ 1318 ? (GET_MODE_BITSIZE (MODE) < 32 \ 1319 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 1320 : MODE) \ 1321 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ 1322 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ 1323 : MODE)) 1324 1325 /* Return the maximum number of consecutive registers 1326 needed to represent mode MODE in a register of class CLASS. */ 1327 /* On SPARC, this is the size of MODE in words. */ 1328 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1329 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ 1330 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1331 1332 /* Stack layout; function entry, exit and calling. */ 1333 1334 /* Define this if pushing a word on the stack 1335 makes the stack pointer a smaller address. */ 1336 #define STACK_GROWS_DOWNWARD 1337 1338 /* Define this to nonzero if the nominal address of the stack frame 1339 is at the high-address end of the local variables; 1340 that is, each additional local variable allocated 1341 goes at a more negative offset in the frame. */ 1342 #define FRAME_GROWS_DOWNWARD 1 1343 1344 /* Offset within stack frame to start allocating local variables at. 1345 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1346 first local allocated. Otherwise, it is the offset to the BEGINNING 1347 of the first local allocated. */ 1348 #define STARTING_FRAME_OFFSET 0 1349 1350 /* Offset of first parameter from the argument pointer register value. 1351 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg 1352 even if this function isn't going to use it. 1353 v9: This is 128 for the ins and locals. */ 1354 #define FIRST_PARM_OFFSET(FNDECL) \ 1355 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) 1356 1357 /* Offset from the argument pointer register value to the CFA. 1358 This is different from FIRST_PARM_OFFSET because the register window 1359 comes between the CFA and the arguments. */ 1360 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1361 1362 /* When a parameter is passed in a register, stack space is still 1363 allocated for it. 1364 !v9: All 6 possible integer registers have backing store allocated. 1365 v9: Only space for the arguments passed is allocated. */ 1366 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special 1367 meaning to the backend. Further, we need to be able to detect if a 1368 varargs/unprototyped function is called, as they may want to spill more 1369 registers than we've provided space. Ugly, ugly. So for now we retain 1370 all 6 slots even for v9. */ 1371 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) 1372 1373 /* Definitions for register elimination. */ 1374 1375 #define ELIMINABLE_REGS \ 1376 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1377 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } 1378 1379 /* We always pretend that this is a leaf function because if it's not, 1380 there's no point in trying to eliminate the frame pointer. If it 1381 is a leaf function, we guessed right! */ 1382 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1383 do { \ 1384 if ((TO) == STACK_POINTER_REGNUM) \ 1385 (OFFSET) = sparc_compute_frame_size (get_frame_size (), 1); \ 1386 else \ 1387 (OFFSET) = 0; \ 1388 (OFFSET) += SPARC_STACK_BIAS; \ 1389 } while (0) 1390 1391 /* Keep the stack pointer constant throughout the function. 1392 This is both an optimization and a necessity: longjmp 1393 doesn't behave itself when the stack pointer moves within 1394 the function! */ 1395 #define ACCUMULATE_OUTGOING_ARGS 1 1396 1397 /* Value is the number of bytes of arguments automatically 1398 popped when returning from a subroutine call. 1399 FUNDECL is the declaration node of the function (as a tree), 1400 FUNTYPE is the data type of the function (as a tree), 1401 or for a library call it is an identifier node for the subroutine name. 1402 SIZE is the number of bytes of arguments passed on the stack. */ 1403 1404 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1405 1406 /* Define this macro if the target machine has "register windows". This 1407 C expression returns the register number as seen by the called function 1408 corresponding to register number OUT as seen by the calling function. 1409 Return OUT if register number OUT is not an outbound register. */ 1410 1411 #define INCOMING_REGNO(OUT) \ 1412 (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) 1413 1414 /* Define this macro if the target machine has "register windows". This 1415 C expression returns the register number as seen by the calling function 1416 corresponding to register number IN as seen by the called function. 1417 Return IN if register number IN is not an inbound register. */ 1418 1419 #define OUTGOING_REGNO(IN) \ 1420 (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) 1421 1422 /* Define this macro if the target machine has register windows. This 1423 C expression returns true if the register is call-saved but is in the 1424 register window. */ 1425 1426 #define LOCAL_REGNO(REGNO) \ 1427 ((REGNO) >= 16 && (REGNO) <= 31) 1428 1429 /* Define how to find the value returned by a function. 1430 VALTYPE is the data type of the value (as a tree). 1431 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1432 otherwise, FUNC is 0. */ 1433 1434 /* On SPARC the value is found in the first "output" register. */ 1435 1436 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1437 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1) 1438 1439 /* But the called function leaves it in the first "input" register. */ 1440 1441 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \ 1442 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0) 1443 1444 /* Define how to find the value returned by a library function 1445 assuming the value has mode MODE. */ 1446 1447 #define LIBCALL_VALUE(MODE) \ 1448 function_value (NULL_TREE, (MODE), 1) 1449 1450 /* 1 if N is a possible register number for a function value 1451 as seen by the caller. 1452 On SPARC, the first "output" reg is used for integer values, 1453 and the first floating point register is used for floating point values. */ 1454 1455 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32) 1456 1457 /* Define the size of space to allocate for the return value of an 1458 untyped_call. */ 1459 1460 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16) 1461 1462 /* 1 if N is a possible register number for function argument passing. 1463 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ 1464 1465 #define FUNCTION_ARG_REGNO_P(N) \ 1466 (TARGET_ARCH64 \ 1467 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \ 1468 : ((N) >= 8 && (N) <= 13)) 1469 1470 /* Define a data type for recording info about an argument list 1471 during the scan of that argument list. This data type should 1472 hold all necessary information about the function itself 1473 and about the args processed so far, enough to enable macros 1474 such as FUNCTION_ARG to determine where the next arg should go. 1475 1476 On SPARC (!v9), this is a single integer, which is a number of words 1477 of arguments scanned so far (including the invisible argument, 1478 if any, which holds the structure-value-address). 1479 Thus 7 or more means all following args should go on the stack. 1480 1481 For v9, we also need to know whether a prototype is present. */ 1482 1483 struct sparc_args { 1484 int words; /* number of words passed so far */ 1485 int prototype_p; /* nonzero if a prototype is present */ 1486 int libcall_p; /* nonzero if a library call */ 1487 }; 1488 #define CUMULATIVE_ARGS struct sparc_args 1489 1490 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1491 for a call to a function whose data type is FNTYPE. 1492 For a library call, FNTYPE is 0. */ 1493 1494 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1495 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL)); 1496 1497 /* Update the data in CUM to advance over an argument 1498 of mode MODE and data type TYPE. 1499 TYPE is null for libcalls where that information may not be available. */ 1500 1501 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1502 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED)) 1503 1504 /* Determine where to put an argument to a function. 1505 Value is zero to push the argument on the stack, 1506 or a hard register in which to store the argument. 1507 1508 MODE is the argument's machine mode. 1509 TYPE is the data type of the argument (as a tree). 1510 This is null for libcalls where that information may 1511 not be available. 1512 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1513 the preceding args and about the function being called. 1514 NAMED is nonzero if this argument is a named parameter 1515 (otherwise it is an extra parameter matching an ellipsis). */ 1516 1517 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1518 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0) 1519 1520 /* Define where a function finds its arguments. 1521 This is different from FUNCTION_ARG because of register windows. */ 1522 1523 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ 1524 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1) 1525 1526 /* If defined, a C expression which determines whether, and in which direction, 1527 to pad out an argument with extra space. The value should be of type 1528 `enum direction': either `upward' to pad above the argument, 1529 `downward' to pad below, or `none' to inhibit padding. */ 1530 1531 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1532 function_arg_padding ((MODE), (TYPE)) 1533 1534 /* If defined, a C expression that gives the alignment boundary, in bits, 1535 of an argument with the specified mode and type. If it is not defined, 1536 PARM_BOUNDARY is used for all arguments. 1537 For sparc64, objects requiring 16 byte alignment are passed that way. */ 1538 1539 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 1540 ((TARGET_ARCH64 \ 1541 && (GET_MODE_ALIGNMENT (MODE) == 128 \ 1542 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \ 1543 ? 128 : PARM_BOUNDARY) 1544 1545 1546 /* Generate the special assembly code needed to tell the assembler whatever 1547 it might need to know about the return value of a function. 1548 1549 For SPARC assemblers, we need to output a .proc pseudo-op which conveys 1550 information to the assembler relating to peephole optimization (done in 1551 the assembler). */ 1552 1553 #define ASM_DECLARE_RESULT(FILE, RESULT) \ 1554 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) 1555 1556 /* Output the special assembly code needed to tell the assembler some 1557 register is used as global register variable. 1558 1559 SPARC 64bit psABI declares registers %g2 and %g3 as application 1560 registers and %g6 and %g7 as OS registers. Any object using them 1561 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them 1562 and how they are used (scratch or some global variable). 1563 Linker will then refuse to link together objects which use those 1564 registers incompatibly. 1565 1566 Unless the registers are used for scratch, two different global 1567 registers cannot be declared to the same name, so in the unlikely 1568 case of a global register variable occupying more than one register 1569 we prefix the second and following registers with .gnu.part1. etc. */ 1570 1571 extern GTY(()) char sparc_hard_reg_printed[8]; 1572 1573 #ifdef HAVE_AS_REGISTER_PSEUDO_OP 1574 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ 1575 do { \ 1576 if (TARGET_ARCH64) \ 1577 { \ 1578 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \ 1579 int reg; \ 1580 for (reg = (REGNO); reg < 8 && reg < end; reg++) \ 1581 if ((reg & ~1) == 2 || (reg & ~1) == 6) \ 1582 { \ 1583 if (reg == (REGNO)) \ 1584 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ 1585 else \ 1586 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ 1587 reg, reg - (REGNO), (NAME)); \ 1588 sparc_hard_reg_printed[reg] = 1; \ 1589 } \ 1590 } \ 1591 } while (0) 1592 #endif 1593 1594 1595 /* Emit rtl for profiling. */ 1596 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) 1597 1598 /* All the work done in PROFILE_HOOK, but still required. */ 1599 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) 1600 1601 /* Set the name of the mcount function for the system. */ 1602 #define MCOUNT_FUNCTION "*mcount" 1603 1604 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1605 the stack pointer does not matter. The value is tested only in 1606 functions that have frame pointers. 1607 No definition is equivalent to always zero. */ 1608 1609 #define EXIT_IGNORE_STACK \ 1610 (get_frame_size () != 0 \ 1611 || cfun->calls_alloca || crtl->outgoing_args_size) 1612 1613 /* Define registers used by the epilogue and return instruction. */ 1614 #define EPILOGUE_USES(REGNO) ((REGNO) == 31 \ 1615 || (crtl->calls_eh_return && (REGNO) == 1)) 1616 1617 /* Length in units of the trampoline for entering a nested function. */ 1618 1619 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) 1620 1621 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */ 1622 1623 /* Generate RTL to flush the register windows so as to make arbitrary frames 1624 available. */ 1625 #define SETUP_FRAME_ADDRESSES() \ 1626 emit_insn (gen_flush_register_windows ()) 1627 1628 /* Given an rtx for the address of a frame, 1629 return an rtx for the address of the word in the frame 1630 that holds the dynamic chain--the previous frame's address. */ 1631 #define DYNAMIC_CHAIN_ADDRESS(frame) \ 1632 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) 1633 1634 /* Given an rtx for the frame pointer, 1635 return an rtx for the address of the frame. */ 1636 #define FRAME_ADDR_RTX(frame) plus_constant (frame, SPARC_STACK_BIAS) 1637 1638 /* The return address isn't on the stack, it is in a register, so we can't 1639 access it from the current frame pointer. We can access it from the 1640 previous frame pointer though by reading a value from the register window 1641 save area. */ 1642 #define RETURN_ADDR_IN_PREVIOUS_FRAME 1643 1644 /* This is the offset of the return address to the true next instruction to be 1645 executed for the current function. */ 1646 #define RETURN_ADDR_OFFSET \ 1647 (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct)) 1648 1649 /* The current return address is in %i7. The return address of anything 1650 farther back is in the register window save area at [%fp+60]. */ 1651 /* ??? This ignores the fact that the actual return address is +8 for normal 1652 returns, and +12 for structure returns. */ 1653 #define RETURN_ADDR_RTX(count, frame) \ 1654 ((count == -1) \ 1655 ? gen_rtx_REG (Pmode, 31) \ 1656 : gen_rtx_MEM (Pmode, \ 1657 memory_address (Pmode, plus_constant (frame, \ 1658 15 * UNITS_PER_WORD \ 1659 + SPARC_STACK_BIAS)))) 1660 1661 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's 1662 +12, but always using +8 is close enough for frame unwind purposes. 1663 Actually, just using %o7 is close enough for unwinding, but %o7+8 1664 is something you can return to. */ 1665 #define INCOMING_RETURN_ADDR_RTX \ 1666 plus_constant (gen_rtx_REG (word_mode, 15), 8) 1667 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15) 1668 1669 /* The offset from the incoming value of %sp to the top of the stack frame 1670 for the current function. On sparc64, we have to account for the stack 1671 bias if present. */ 1672 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS 1673 1674 /* Describe how we implement __builtin_eh_return. */ 1675 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) 1676 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */ 1677 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */ 1678 1679 /* Select a format to encode pointers in exception handling data. CODE 1680 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1681 true if the symbol may be affected by dynamic relocations. 1682 1683 If assembler and linker properly support .uaword %r_disp32(foo), 1684 then use PC relative 32-bit relocations instead of absolute relocs 1685 for shared libraries. On sparc64, use pc relative 32-bit relocs even 1686 for binaries, to save memory. 1687 1688 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the 1689 symbol %r_disp32() is against was not local, but .hidden. In that 1690 case, we have to use DW_EH_PE_absptr for pic personality. */ 1691 #ifdef HAVE_AS_SPARC_UA_PCREL 1692 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN 1693 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1694 (flag_pic \ 1695 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 1696 : ((TARGET_ARCH64 && ! GLOBAL) \ 1697 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1698 : DW_EH_PE_absptr)) 1699 #else 1700 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1701 (flag_pic \ 1702 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ 1703 : ((TARGET_ARCH64 && ! GLOBAL) \ 1704 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1705 : DW_EH_PE_absptr)) 1706 #endif 1707 1708 /* Emit a PC-relative relocation. */ 1709 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 1710 do { \ 1711 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1712 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ 1713 assemble_name (FILE, LABEL); \ 1714 fputc (')', FILE); \ 1715 } while (0) 1716 #endif 1717 1718 /* Addressing modes, and classification of registers for them. */ 1719 1720 /* Macros to check register numbers against specific register classes. */ 1721 1722 /* These assume that REGNO is a hard or pseudo reg number. 1723 They give nonzero only if REGNO is a hard reg of the suitable class 1724 or a pseudo reg currently allocated to a suitable hard reg. 1725 Since they use reg_renumber, they are safe only once reg_renumber 1726 has been allocated, which happens in local-alloc.c. */ 1727 1728 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1729 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \ 1730 || (REGNO) == FRAME_POINTER_REGNUM \ 1731 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) 1732 1733 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 1734 1735 #define REGNO_OK_FOR_FP_P(REGNO) \ 1736 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ 1737 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) 1738 #define REGNO_OK_FOR_CCFP_P(REGNO) \ 1739 (TARGET_V9 \ 1740 && (((unsigned) (REGNO) - 96 < (unsigned)4) \ 1741 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) 1742 1743 /* Now macros that check whether X is a register and also, 1744 strictly, whether it is in a specified class. 1745 1746 These macros are specific to the SPARC, and may be used only 1747 in code for printing assembler insns and in conditions for 1748 define_optimization. */ 1749 1750 /* 1 if X is an fp register. */ 1751 1752 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 1753 1754 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */ 1755 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31)) 1756 1757 /* Maximum number of registers that can appear in a valid memory address. */ 1758 1759 #define MAX_REGS_PER_ADDRESS 2 1760 1761 /* Recognize any constant value that is a valid address. 1762 When PIC, we do not accept an address that would require a scratch reg 1763 to load into a register. */ 1764 1765 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1766 1767 /* Define this, so that when PIC, reload won't try to reload invalid 1768 addresses which require two reload registers. */ 1769 1770 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1771 1772 /* Nonzero if the constant value X is a legitimate general operand. 1773 Anything can be made to work except floating point constants. 1774 If TARGET_VIS, 0.0 can be made to work as well. */ 1775 1776 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) 1777 1778 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1779 and check its validity for a certain class. 1780 We have two alternate definitions for each of them. 1781 The usual definition accepts all pseudo regs; the other rejects 1782 them unless they have been allocated suitable hard regs. 1783 The symbol REG_OK_STRICT causes the latter definition to be used. 1784 1785 Most source files want to accept pseudo regs in the hope that 1786 they will get allocated to the class that the insn wants them to be in. 1787 Source files for reload pass need to be strict. 1788 After reload, it makes no difference, since pseudo regs have 1789 been eliminated by then. */ 1790 1791 #ifndef REG_OK_STRICT 1792 1793 /* Nonzero if X is a hard reg that can be used as an index 1794 or if it is a pseudo reg. */ 1795 #define REG_OK_FOR_INDEX_P(X) \ 1796 (REGNO (X) < 32 \ 1797 || REGNO (X) == FRAME_POINTER_REGNUM \ 1798 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1799 1800 /* Nonzero if X is a hard reg that can be used as a base reg 1801 or if it is a pseudo reg. */ 1802 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X) 1803 1804 #else 1805 1806 /* Nonzero if X is a hard reg that can be used as an index. */ 1807 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1808 /* Nonzero if X is a hard reg that can be used as a base reg. */ 1809 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1810 1811 #endif 1812 1813 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */ 1814 1815 #ifdef HAVE_AS_OFFSETABLE_LO10 1816 #define USE_AS_OFFSETABLE_LO10 1 1817 #else 1818 #define USE_AS_OFFSETABLE_LO10 0 1819 #endif 1820 1821 /* On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT 1822 ordinarily. This changes a bit when generating PIC. The details are 1823 in sparc.c's implementation of TARGET_LEGITIMATE_ADDRESS_P. */ 1824 1825 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode) 1826 1827 #define RTX_OK_FOR_BASE_P(X) \ 1828 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 1829 || (GET_CODE (X) == SUBREG \ 1830 && GET_CODE (SUBREG_REG (X)) == REG \ 1831 && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 1832 1833 #define RTX_OK_FOR_INDEX_P(X) \ 1834 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 1835 || (GET_CODE (X) == SUBREG \ 1836 && GET_CODE (SUBREG_REG (X)) == REG \ 1837 && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) 1838 1839 #define RTX_OK_FOR_OFFSET_P(X) \ 1840 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8) 1841 1842 #define RTX_OK_FOR_OLO10_P(X) \ 1843 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8) 1844 1845 /* Go to LABEL if ADDR (a legitimate address expression) 1846 has an effect that depends on the machine mode it is used for. 1847 1848 In PIC mode, 1849 1850 (mem:HI [%l7+a]) 1851 1852 is not equivalent to 1853 1854 (mem:QI [%l7+a]) (mem:QI [%l7+a+1]) 1855 1856 because [%l7+a+1] is interpreted as the address of (a+1). */ 1857 1858 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 1859 { \ 1860 if (flag_pic == 1) \ 1861 { \ 1862 if (GET_CODE (ADDR) == PLUS) \ 1863 { \ 1864 rtx op0 = XEXP (ADDR, 0); \ 1865 rtx op1 = XEXP (ADDR, 1); \ 1866 if (op0 == pic_offset_table_rtx \ 1867 && SYMBOLIC_CONST (op1)) \ 1868 goto LABEL; \ 1869 } \ 1870 } \ 1871 } 1872 1873 /* Try a machine-dependent way of reloading an illegitimate address 1874 operand. If we find one, push the reload and jump to WIN. This 1875 macro is used in only one place: `find_reloads_address' in reload.c. 1876 1877 For SPARC 32, we wish to handle addresses by splitting them into 1878 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference. 1879 This cuts the number of extra insns by one. 1880 1881 Do nothing when generating PIC code and the address is a 1882 symbolic operand or requires a scratch register. */ 1883 1884 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1885 do { \ 1886 /* Decompose SImode constants into hi+lo_sum. We do have to \ 1887 rerecognize what we produce, so be careful. */ \ 1888 if (CONSTANT_P (X) \ 1889 && (MODE != TFmode || TARGET_ARCH64) \ 1890 && GET_MODE (X) == SImode \ 1891 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \ 1892 && ! (flag_pic \ 1893 && (symbolic_operand (X, Pmode) \ 1894 || pic_address_needs_scratch (X))) \ 1895 && sparc_cmodel <= CM_MEDLOW) \ 1896 { \ 1897 X = gen_rtx_LO_SUM (GET_MODE (X), \ 1898 gen_rtx_HIGH (GET_MODE (X), X), X); \ 1899 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 1900 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \ 1901 OPNUM, TYPE); \ 1902 goto WIN; \ 1903 } \ 1904 /* ??? 64-bit reloads. */ \ 1905 } while (0) 1906 1907 /* Specify the machine mode that this machine uses 1908 for the index in the tablejump instruction. */ 1909 /* If we ever implement any of the full models (such as CM_FULLANY), 1910 this has to be DImode in that case */ 1911 #ifdef HAVE_GAS_SUBSECTION_ORDERING 1912 #define CASE_VECTOR_MODE \ 1913 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) 1914 #else 1915 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise 1916 we have to sign extend which slows things down. */ 1917 #define CASE_VECTOR_MODE \ 1918 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) 1919 #endif 1920 1921 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1922 #define DEFAULT_SIGNED_CHAR 1 1923 1924 /* Max number of bytes we can move from memory to memory 1925 in one reasonably fast instruction. */ 1926 #define MOVE_MAX 8 1927 1928 /* If a memory-to-memory move would take MOVE_RATIO or more simple 1929 move-instruction pairs, we will do a movmem or libcall instead. */ 1930 1931 #define MOVE_RATIO(speed) ((speed) ? 8 : 3) 1932 1933 /* Define if operations between registers always perform the operation 1934 on the full register even if a narrower mode is specified. */ 1935 #define WORD_REGISTER_OPERATIONS 1936 1937 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1938 will either zero-extend or sign-extend. The value of this macro should 1939 be the code that says which one of the two operations is implicitly 1940 done, UNKNOWN if none. */ 1941 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1942 1943 /* Nonzero if access to memory by bytes is slow and undesirable. 1944 For RISC chips, it means that access to memory by bytes is no 1945 better than access by words when possible, so grab a whole word 1946 and maybe make use of that. */ 1947 #define SLOW_BYTE_ACCESS 1 1948 1949 /* Define this to be nonzero if shift instructions ignore all but the low-order 1950 few bits. */ 1951 #define SHIFT_COUNT_TRUNCATED 1 1952 1953 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1954 is done just by pretending it is already truncated. */ 1955 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1956 1957 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1958 return the mode to be used for the comparison. For floating-point, 1959 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand 1960 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 1961 processing is needed. */ 1962 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) 1963 1964 /* Return nonzero if MODE implies a floating point inequality can be 1965 reversed. For SPARC this is always true because we have a full 1966 compliment of ordered and unordered comparisons, but until generic 1967 code knows how to reverse it correctly we keep the old definition. */ 1968 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) 1969 1970 /* A function address in a call instruction for indexing purposes. */ 1971 #define FUNCTION_MODE Pmode 1972 1973 /* Define this if addresses of constant functions 1974 shouldn't be put through pseudo regs where they can be cse'd. 1975 Desirable on machines where ordinary constants are expensive 1976 but a CALL with constant address is cheap. */ 1977 #define NO_FUNCTION_CSE 1978 1979 /* alloca should avoid clobbering the old register save area. */ 1980 #define SETJMP_VIA_SAVE_AREA 1981 1982 /* The _Q_* comparison libcalls return booleans. */ 1983 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) 1984 1985 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such 1986 that the inputs are fully consumed before the output memory is clobbered. */ 1987 1988 #define TARGET_BUGGY_QP_LIB 0 1989 1990 /* Assume by default that we do not have the Solaris-specific conversion 1991 routines nor 64-bit integer multiply and divide routines. */ 1992 1993 #define SUN_CONVERSION_LIBFUNCS 0 1994 #define DITF_CONVERSION_LIBFUNCS 0 1995 #define SUN_INTEGER_MULTIPLY_64 0 1996 1997 /* Compute extra cost of moving data between one register class 1998 and another. */ 1999 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS) 2000 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 2001 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \ 2002 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \ 2003 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \ 2004 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \ 2005 || sparc_cpu == PROCESSOR_ULTRASPARC3 \ 2006 || sparc_cpu == PROCESSOR_NIAGARA \ 2007 || sparc_cpu == PROCESSOR_NIAGARA2) ? 12 : 6) : 2) 2008 2009 /* Provide the cost of a branch. For pre-v9 processors we use 2010 a value of 3 to take into account the potential annulling of 2011 the delay slot (which ends up being a bubble in the pipeline slot) 2012 plus a cycle to take into consideration the instruction cache 2013 effects. 2014 2015 On v9 and later, which have branch prediction facilities, we set 2016 it to the depth of the pipeline as that is the cost of a 2017 mispredicted branch. 2018 2019 On Niagara, normal branches insert 3 bubbles into the pipe 2020 and annulled branches insert 4 bubbles. 2021 2022 On Niagara-2, a not-taken branch costs 1 cycle whereas a taken 2023 branch costs 6 cycles. */ 2024 2025 #define BRANCH_COST(speed_p, predictable_p) \ 2026 ((sparc_cpu == PROCESSOR_V9 \ 2027 || sparc_cpu == PROCESSOR_ULTRASPARC) \ 2028 ? 7 \ 2029 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ 2030 ? 9 \ 2031 : (sparc_cpu == PROCESSOR_NIAGARA \ 2032 ? 4 \ 2033 : (sparc_cpu == PROCESSOR_NIAGARA2 \ 2034 ? 5 \ 2035 : 3)))) 2036 2037 /* Control the assembler format that we output. */ 2038 2039 /* A C string constant describing how to begin a comment in the target 2040 assembler language. The compiler assumes that the comment will end at 2041 the end of the line. */ 2042 2043 #define ASM_COMMENT_START "!" 2044 2045 /* Output to assembler file text saying following lines 2046 may contain character constants, extra white space, comments, etc. */ 2047 2048 #define ASM_APP_ON "" 2049 2050 /* Output to assembler file text saying following lines 2051 no longer contain unusual constructs. */ 2052 2053 #define ASM_APP_OFF "" 2054 2055 /* How to refer to registers in assembler output. 2056 This sequence is indexed by compiler's hard-register-number (see above). */ 2057 2058 #define REGISTER_NAMES \ 2059 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 2060 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 2061 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 2062 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 2063 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 2064 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 2065 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 2066 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ 2067 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ 2068 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ 2069 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ 2070 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ 2071 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" } 2072 2073 /* Define additional names for use in asm clobbers and asm declarations. */ 2074 2075 #define ADDITIONAL_REGISTER_NAMES \ 2076 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} 2077 2078 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length 2079 can run past this up to a continuation point. Once we used 1500, but 2080 a single entry in C++ can run more than 500 bytes, due to the length of 2081 mangled symbol names. dbxout.c should really be fixed to do 2082 continuations when they are actually needed instead of trying to 2083 guess... */ 2084 #define DBX_CONTIN_LENGTH 1000 2085 2086 /* This is how to output a command to make the user-level label named NAME 2087 defined for reference from other files. */ 2088 2089 /* Globalizing directive for a label. */ 2090 #define GLOBAL_ASM_OP "\t.global " 2091 2092 /* The prefix to add to user-visible assembler symbols. */ 2093 2094 #define USER_LABEL_PREFIX "_" 2095 2096 /* This is how to store into the string LABEL 2097 the symbol_ref name of an internal numbered label where 2098 PREFIX is the class of label and NUM is the number within the class. 2099 This is suitable for output with `assemble_name'. */ 2100 2101 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 2102 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) 2103 2104 /* This is how we hook in and defer the case-vector until the end of 2105 the function. */ 2106 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ 2107 sparc_defer_case_vector ((LAB),(VEC), 0) 2108 2109 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ 2110 sparc_defer_case_vector ((LAB),(VEC), 1) 2111 2112 /* This is how to output an element of a case-vector that is absolute. */ 2113 2114 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2115 do { \ 2116 char label[30]; \ 2117 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 2118 if (CASE_VECTOR_MODE == SImode) \ 2119 fprintf (FILE, "\t.word\t"); \ 2120 else \ 2121 fprintf (FILE, "\t.xword\t"); \ 2122 assemble_name (FILE, label); \ 2123 fputc ('\n', FILE); \ 2124 } while (0) 2125 2126 /* This is how to output an element of a case-vector that is relative. 2127 (SPARC uses such vectors only when generating PIC.) */ 2128 2129 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2130 do { \ 2131 char label[30]; \ 2132 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ 2133 if (CASE_VECTOR_MODE == SImode) \ 2134 fprintf (FILE, "\t.word\t"); \ 2135 else \ 2136 fprintf (FILE, "\t.xword\t"); \ 2137 assemble_name (FILE, label); \ 2138 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ 2139 fputc ('-', FILE); \ 2140 assemble_name (FILE, label); \ 2141 fputc ('\n', FILE); \ 2142 } while (0) 2143 2144 /* This is what to output before and after case-vector (both 2145 relative and absolute). If .subsection -1 works, we put case-vectors 2146 at the beginning of the current section. */ 2147 2148 #ifdef HAVE_GAS_SUBSECTION_ORDERING 2149 2150 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \ 2151 fprintf(FILE, "\t.subsection\t-1\n") 2152 2153 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \ 2154 fprintf(FILE, "\t.previous\n") 2155 2156 #endif 2157 2158 /* This is how to output an assembler line 2159 that says to advance the location counter 2160 to a multiple of 2**LOG bytes. */ 2161 2162 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2163 if ((LOG) != 0) \ 2164 fprintf (FILE, "\t.align %d\n", (1<<(LOG))) 2165 2166 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 2167 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 2168 2169 /* This says how to output an assembler line 2170 to define a global common symbol. */ 2171 2172 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 2173 ( fputs ("\t.common ", (FILE)), \ 2174 assemble_name ((FILE), (NAME)), \ 2175 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE))) 2176 2177 /* This says how to output an assembler line to define a local common 2178 symbol. */ 2179 2180 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ 2181 ( fputs ("\t.reserve ", (FILE)), \ 2182 assemble_name ((FILE), (NAME)), \ 2183 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \ 2184 (SIZE), ((ALIGNED) / BITS_PER_UNIT))) 2185 2186 /* A C statement (sans semicolon) to output to the stdio stream 2187 FILE the assembler definition of uninitialized global DECL named 2188 NAME whose size is SIZE bytes and alignment is ALIGN bytes. 2189 Try to use asm_output_aligned_bss to implement this macro. */ 2190 2191 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 2192 do { \ 2193 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ 2194 } while (0) 2195 2196 #define IDENT_ASM_OP "\t.ident\t" 2197 2198 /* Output #ident as a .ident. */ 2199 2200 #define ASM_OUTPUT_IDENT(FILE, NAME) \ 2201 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME); 2202 2203 /* Prettify the assembly. */ 2204 2205 extern int sparc_indent_opcode; 2206 2207 #define ASM_OUTPUT_OPCODE(FILE, PTR) \ 2208 do { \ 2209 if (sparc_indent_opcode) \ 2210 { \ 2211 putc (' ', FILE); \ 2212 sparc_indent_opcode = 0; \ 2213 } \ 2214 } while (0) 2215 2216 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 2217 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '(' \ 2218 || (CHAR) == ')' || (CHAR) == '_' || (CHAR) == '&') 2219 2220 /* Print operand X (an rtx) in assembler syntax to file FILE. 2221 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2222 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2223 2224 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2225 2226 /* Print a memory address as an operand to reference that memory location. */ 2227 2228 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2229 { register rtx base, index = 0; \ 2230 int offset = 0; \ 2231 register rtx addr = ADDR; \ 2232 if (GET_CODE (addr) == REG) \ 2233 fputs (reg_names[REGNO (addr)], FILE); \ 2234 else if (GET_CODE (addr) == PLUS) \ 2235 { \ 2236 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \ 2237 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\ 2238 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \ 2239 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\ 2240 else \ 2241 base = XEXP (addr, 0), index = XEXP (addr, 1); \ 2242 if (GET_CODE (base) == LO_SUM) \ 2243 { \ 2244 gcc_assert (USE_AS_OFFSETABLE_LO10 \ 2245 && TARGET_ARCH64 \ 2246 && ! TARGET_CM_MEDMID); \ 2247 output_operand (XEXP (base, 0), 0); \ 2248 fputs ("+%lo(", FILE); \ 2249 output_address (XEXP (base, 1)); \ 2250 fprintf (FILE, ")+%d", offset); \ 2251 } \ 2252 else \ 2253 { \ 2254 fputs (reg_names[REGNO (base)], FILE); \ 2255 if (index == 0) \ 2256 fprintf (FILE, "%+d", offset); \ 2257 else if (GET_CODE (index) == REG) \ 2258 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \ 2259 else if (GET_CODE (index) == SYMBOL_REF \ 2260 || GET_CODE (index) == LABEL_REF \ 2261 || GET_CODE (index) == CONST) \ 2262 fputc ('+', FILE), output_addr_const (FILE, index); \ 2263 else gcc_unreachable (); \ 2264 } \ 2265 } \ 2266 else if (GET_CODE (addr) == MINUS \ 2267 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \ 2268 { \ 2269 output_addr_const (FILE, XEXP (addr, 0)); \ 2270 fputs ("-(", FILE); \ 2271 output_addr_const (FILE, XEXP (addr, 1)); \ 2272 fputs ("-.)", FILE); \ 2273 } \ 2274 else if (GET_CODE (addr) == LO_SUM) \ 2275 { \ 2276 output_operand (XEXP (addr, 0), 0); \ 2277 if (TARGET_CM_MEDMID) \ 2278 fputs ("+%l44(", FILE); \ 2279 else \ 2280 fputs ("+%lo(", FILE); \ 2281 output_address (XEXP (addr, 1)); \ 2282 fputc (')', FILE); \ 2283 } \ 2284 else if (flag_pic && GET_CODE (addr) == CONST \ 2285 && GET_CODE (XEXP (addr, 0)) == MINUS \ 2286 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \ 2287 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \ 2288 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \ 2289 { \ 2290 addr = XEXP (addr, 0); \ 2291 output_addr_const (FILE, XEXP (addr, 0)); \ 2292 /* Group the args of the second CONST in parenthesis. */ \ 2293 fputs ("-(", FILE); \ 2294 /* Skip past the second CONST--it does nothing for us. */\ 2295 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \ 2296 /* Close the parenthesis. */ \ 2297 fputc (')', FILE); \ 2298 } \ 2299 else \ 2300 { \ 2301 output_addr_const (FILE, addr); \ 2302 } \ 2303 } 2304 2305 /* TLS support defaulting to original Sun flavor. GNU extensions 2306 must be activated in separate configuration files. */ 2307 #ifdef HAVE_AS_TLS 2308 #define TARGET_TLS 1 2309 #else 2310 #define TARGET_TLS 0 2311 #endif 2312 2313 #define TARGET_SUN_TLS TARGET_TLS 2314 #define TARGET_GNU_TLS 0 2315 2316 /* The number of Pmode words for the setjmp buffer. */ 2317 #define JMP_BUF_SIZE 12 2318 2319 /* We use gcc _mcount for profiling. */ 2320 #define NO_PROFILE_COUNTERS 0 2321