1 /* Definitions of target machine for GNU compiler, for Sun SPARC. 2 Copyright (C) 1987-2020 Free Software Foundation, Inc. 3 Contributed by Michael Tiemann (tiemann@cygnus.com). 4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 5 at Cygnus Support. 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 GCC is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING3. If not see 21 <http://www.gnu.org/licenses/>. */ 22 23 #include "config/vxworks-dummy.h" 24 25 /* Note that some other tm.h files include this one and then override 26 whatever definitions are necessary. */ 27 28 #define TARGET_CPU_CPP_BUILTINS() sparc_target_macros () 29 30 /* Target CPU versions for D. */ 31 #define TARGET_D_CPU_VERSIONS sparc_d_target_versions 32 33 /* Specify this in a cover file to provide bi-architecture (32/64) support. */ 34 /* #define SPARC_BI_ARCH */ 35 36 /* Macro used later in this file to determine default architecture. */ 37 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) 38 39 /* TARGET_ARCH{32,64} are the main macros to decide which of the two 40 architectures to compile for. We allow targets to choose compile time or 41 runtime selection. */ 42 #ifdef IN_LIBGCC2 43 #if defined(__sparcv9) || defined(__arch64__) 44 #define TARGET_ARCH32 0 45 #else 46 #define TARGET_ARCH32 1 47 #endif /* sparc64 */ 48 #else 49 #ifdef SPARC_BI_ARCH 50 #define TARGET_ARCH32 (!TARGET_64BIT) 51 #else 52 #define TARGET_ARCH32 (DEFAULT_ARCH32_P) 53 #endif /* SPARC_BI_ARCH */ 54 #endif /* IN_LIBGCC2 */ 55 #define TARGET_ARCH64 (!TARGET_ARCH32) 56 57 /* Code model selection in 64-bit environment. 58 59 The machine mode used for addresses is 32-bit wide: 60 61 TARGET_CM_32: 32-bit address space. 62 It is the code model used when generating 32-bit code. 63 64 The machine mode used for addresses is 64-bit wide: 65 66 TARGET_CM_MEDLOW: 32-bit address space. 67 The executable must be in the low 32 bits of memory. 68 This avoids generating %uhi and %ulo terms. Programs 69 can be statically or dynamically linked. 70 71 TARGET_CM_MEDMID: 44-bit address space. 72 The executable must be in the low 44 bits of memory, 73 and the %[hml]44 terms are used. The text and data 74 segments have a maximum size of 2GB (31-bit span). 75 The maximum offset from any instruction to the label 76 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 77 78 TARGET_CM_MEDANY: 64-bit address space. 79 The text and data segments have a maximum size of 2GB 80 (31-bit span) and may be located anywhere in memory. 81 The maximum offset from any instruction to the label 82 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 83 84 TARGET_CM_EMBMEDANY: 64-bit address space. 85 The text and data segments have a maximum size of 2GB 86 (31-bit span) and may be located anywhere in memory. 87 The global register %g4 contains the start address of 88 the data segment. Programs are statically linked and 89 PIC is not supported. 90 91 Different code models are not supported in 32-bit environment. */ 92 93 #define TARGET_CM_MEDLOW (sparc_code_model == CM_MEDLOW) 94 #define TARGET_CM_MEDMID (sparc_code_model == CM_MEDMID) 95 #define TARGET_CM_MEDANY (sparc_code_model == CM_MEDANY) 96 #define TARGET_CM_EMBMEDANY (sparc_code_model == CM_EMBMEDANY) 97 98 /* Default code model to be overridden in 64-bit environment. */ 99 #define SPARC_DEFAULT_CMODEL CM_32 100 101 /* Do not use the .note.GNU-stack convention by default. */ 102 #define NEED_INDICATE_EXEC_STACK 0 103 104 /* This is call-clobbered in the normal ABI, but is reserved in the 105 home grown (aka upward compatible) embedded ABI. */ 106 #define EMBMEDANY_BASE_REG "%g4" 107 108 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, 109 and specified by the user via --with-cpu=foo. 110 This specifies the cpu implementation, not the architecture size. */ 111 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit 112 capable cpu's. */ 113 #define TARGET_CPU_sparc 0 114 #define TARGET_CPU_v7 0 /* alias */ 115 #define TARGET_CPU_cypress 0 /* alias */ 116 #define TARGET_CPU_v8 1 /* generic v8 implementation */ 117 #define TARGET_CPU_supersparc 2 118 #define TARGET_CPU_hypersparc 3 119 #define TARGET_CPU_leon 4 120 #define TARGET_CPU_leon3 5 121 #define TARGET_CPU_leon3v7 6 122 #define TARGET_CPU_leon5 7 123 #define TARGET_CPU_sparclite 8 124 #define TARGET_CPU_f930 8 /* alias */ 125 #define TARGET_CPU_f934 8 /* alias */ 126 #define TARGET_CPU_sparclite86x 9 127 #define TARGET_CPU_sparclet 10 128 #define TARGET_CPU_tsc701 10 /* alias */ 129 #define TARGET_CPU_v9 11 /* generic v9 implementation */ 130 #define TARGET_CPU_sparcv9 11 /* alias */ 131 #define TARGET_CPU_sparc64 11 /* alias */ 132 #define TARGET_CPU_ultrasparc 12 133 #define TARGET_CPU_ultrasparc3 13 134 #define TARGET_CPU_niagara 14 135 #define TARGET_CPU_niagara2 15 136 #define TARGET_CPU_niagara3 16 137 #define TARGET_CPU_niagara4 17 138 #define TARGET_CPU_niagara7 19 139 #define TARGET_CPU_m8 20 140 141 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ 142 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ 143 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ 144 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \ 145 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \ 146 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \ 147 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 \ 148 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 \ 149 || TARGET_CPU_DEFAULT == TARGET_CPU_m8 150 151 #define CPP_CPU32_DEFAULT_SPEC "" 152 #define ASM_CPU32_DEFAULT_SPEC "" 153 154 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 155 /* ??? What does Sun's CC pass? */ 156 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 157 /* ??? It's not clear how other assemblers will handle this, so by default 158 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case 159 is handled in sol2.h. */ 160 #define ASM_CPU64_DEFAULT_SPEC "-Av9" 161 #endif 162 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc 163 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 164 #define ASM_CPU64_DEFAULT_SPEC "-Av9a" 165 #endif 166 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 167 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 168 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 169 #endif 170 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara 171 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 172 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 173 #endif 174 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 175 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 176 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 177 #endif 178 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 179 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 180 #define ASM_CPU64_DEFAULT_SPEC "-Av9" AS_NIAGARA3_FLAG 181 #endif 182 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 183 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 184 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA4_FLAG 185 #endif 186 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 187 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 188 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA7_FLAG 189 #endif 190 #if TARGET_CPU_DEFAULT == TARGET_CPU_m8 191 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 192 #define ASM_CPU64_DEFAULT_SPEC AS_M8_FLAG 193 #endif 194 195 #else 196 197 #define CPP_CPU64_DEFAULT_SPEC "" 198 #define ASM_CPU64_DEFAULT_SPEC "" 199 200 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ 201 || TARGET_CPU_DEFAULT == TARGET_CPU_v8 202 #define CPP_CPU32_DEFAULT_SPEC "" 203 #define ASM_CPU32_DEFAULT_SPEC "" 204 #endif 205 206 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet 207 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" 208 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet" 209 #endif 210 211 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite 212 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" 213 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 214 #endif 215 216 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x 217 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" 218 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 219 #endif 220 221 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc 222 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" 223 #define ASM_CPU32_DEFAULT_SPEC "" 224 #endif 225 226 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc 227 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" 228 #define ASM_CPU32_DEFAULT_SPEC "" 229 #endif 230 231 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon \ 232 || TARGET_CPU_DEFAULT == TARGET_CPU_leon3 \ 233 || TARGET_CPU_DEFAULT == TARGET_CPU_leon5 234 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__" 235 #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG 236 #endif 237 238 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7 239 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__" 240 #define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG 241 #endif 242 243 #endif 244 245 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) 246 #error Unrecognized value in TARGET_CPU_DEFAULT. 247 #endif 248 249 #ifdef SPARC_BI_ARCH 250 251 #define CPP_CPU_DEFAULT_SPEC \ 252 (DEFAULT_ARCH32_P ? "\ 253 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \ 254 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ 255 " : "\ 256 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \ 257 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ 258 ") 259 #define ASM_CPU_DEFAULT_SPEC \ 260 (DEFAULT_ARCH32_P ? "\ 261 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \ 262 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ 263 " : "\ 264 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \ 265 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ 266 ") 267 268 #else /* !SPARC_BI_ARCH */ 269 270 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) 271 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) 272 273 #endif /* !SPARC_BI_ARCH */ 274 275 /* Define macros to distinguish architectures. */ 276 277 /* Common CPP definitions used by CPP_SPEC amongst the various targets 278 for handling -mcpu=xxx switches. */ 279 #define CPP_CPU_SPEC "\ 280 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ 281 %{mcpu=sparclite:-D__sparclite__} \ 282 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ 283 %{mcpu=sparclite86x:-D__sparclite86x__} \ 284 %{mcpu=v8:-D__sparc_v8__} \ 285 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ 286 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ 287 %{mcpu=leon:-D__leon__ -D__sparc_v8__} \ 288 %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \ 289 %{mcpu=leon5:-D__leon__ -D__sparc_v8__} \ 290 %{mcpu=leon3v7:-D__leon__} \ 291 %{mcpu=v9:-D__sparc_v9__} \ 292 %{mcpu=ultrasparc:-D__sparc_v9__} \ 293 %{mcpu=ultrasparc3:-D__sparc_v9__} \ 294 %{mcpu=niagara:-D__sparc_v9__} \ 295 %{mcpu=niagara2:-D__sparc_v9__} \ 296 %{mcpu=niagara3:-D__sparc_v9__} \ 297 %{mcpu=niagara4:-D__sparc_v9__} \ 298 %{mcpu=niagara7:-D__sparc_v9__} \ 299 %{mcpu=m8:-D__sparc_v9__} \ 300 %{!mcpu*:%(cpp_cpu_default)} \ 301 " 302 #define CPP_ARCH32_SPEC "" 303 #define CPP_ARCH64_SPEC "-D__arch64__" 304 305 #define CPP_ARCH_DEFAULT_SPEC \ 306 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) 307 308 #define CPP_ARCH_SPEC "\ 309 %{m32:%(cpp_arch32)} \ 310 %{m64:%(cpp_arch64)} \ 311 %{!m32:%{!m64:%(cpp_arch_default)}} \ 312 " 313 314 /* Macros to distinguish the endianness, window model and FP support. */ 315 #define CPP_OTHER_SPEC "\ 316 %{mflat:-D_FLAT} \ 317 %{msoft-float:-D_SOFT_FLOAT} \ 318 " 319 320 /* Macros to distinguish the particular subtarget. */ 321 #define CPP_SUBTARGET_SPEC "" 322 323 #define CPP_SPEC \ 324 "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_other) %(cpp_subtarget)" 325 326 /* This used to translate -dalign to -malign, but that is no good 327 because it can't turn off the usual meaning of making debugging dumps. */ 328 329 #define CC1_SPEC "" 330 331 /* Override in target specific files. */ 332 #define ASM_CPU_SPEC "\ 333 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ 334 %{mcpu=sparclite:-Asparclite} \ 335 %{mcpu=sparclite86x:-Asparclite} \ 336 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ 337 %{mcpu=v8:-Av8} \ 338 %{mcpu=supersparc:-Av8} \ 339 %{mcpu=hypersparc:-Av8} \ 340 %{mcpu=leon:" AS_LEON_FLAG "} \ 341 %{mcpu=leon3:" AS_LEON_FLAG "} \ 342 %{mcpu=leon5:" AS_LEON_FLAG "} \ 343 %{mcpu=leon3v7:" AS_LEONV7_FLAG "} \ 344 %{mv8plus:-Av8plus} \ 345 %{mcpu=v9:-Av9} \ 346 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ 347 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ 348 %{mcpu=niagara:%{!mv8plus:-Av9b}} \ 349 %{mcpu=niagara2:%{!mv8plus:-Av9b}} \ 350 %{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \ 351 %{mcpu=niagara4:%{!mv8plus:" AS_NIAGARA4_FLAG "}} \ 352 %{mcpu=niagara7:%{!mv8plus:" AS_NIAGARA7_FLAG "}} \ 353 %{mcpu=m8:%{!mv8plus:" AS_M8_FLAG "}} \ 354 %{!mcpu*:%(asm_cpu_default)} \ 355 " 356 357 /* Word size selection, among other things. 358 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ 359 360 #define ASM_ARCH32_SPEC "-32" 361 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" 362 #define ASM_ARCH_DEFAULT_SPEC \ 363 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) 364 365 #define ASM_ARCH_SPEC "\ 366 %{m32:%(asm_arch32)} \ 367 %{m64:%(asm_arch64)} \ 368 %{!m32:%{!m64:%(asm_arch_default)}} \ 369 " 370 371 #ifdef HAVE_AS_RELAX_OPTION 372 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}" 373 #else 374 #define ASM_RELAX_SPEC "" 375 #endif 376 377 /* Special flags to the Sun-4 assembler when using pipe for input. */ 378 379 #define ASM_SPEC "\ 380 %{!pg:%{!p:%{" FPIE_OR_FPIC_SPEC ":-k}}} %{keep-local-as-symbols:-L} \ 381 %(asm_cpu) %(asm_relax)" 382 383 /* This macro defines names of additional specifications to put in the specs 384 that can be used in various specifications like CC1_SPEC. Its definition 385 is an initializer with a subgrouping for each command option. 386 387 Each subgrouping contains a string constant, that defines the 388 specification name, and a string constant that used by the GCC driver 389 program. 390 391 Do not define this macro if it does not need to do anything. */ 392 393 #define EXTRA_SPECS \ 394 { "cpp_cpu", CPP_CPU_SPEC }, \ 395 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 396 { "cpp_arch32", CPP_ARCH32_SPEC }, \ 397 { "cpp_arch64", CPP_ARCH64_SPEC }, \ 398 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ 399 { "cpp_arch", CPP_ARCH_SPEC }, \ 400 { "cpp_other", CPP_OTHER_SPEC }, \ 401 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ 402 { "asm_cpu", ASM_CPU_SPEC }, \ 403 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ 404 { "asm_arch32", ASM_ARCH32_SPEC }, \ 405 { "asm_arch64", ASM_ARCH64_SPEC }, \ 406 { "asm_relax", ASM_RELAX_SPEC }, \ 407 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ 408 { "asm_arch", ASM_ARCH_SPEC }, \ 409 SUBTARGET_EXTRA_SPECS 410 411 #define SUBTARGET_EXTRA_SPECS 412 413 /* Because libgcc can generate references back to libc (via .umul etc.) we have 414 to list libc again after the second libgcc. */ 415 #define LINK_GCC_C_SEQUENCE_SPEC "%G %{!nolibc:%L} %G %{!nolibc:%L}" 416 417 418 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") 419 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") 420 421 /* ??? This should be 32 bits for v9 but what can we do? */ 422 #define WCHAR_TYPE "short unsigned int" 423 #define WCHAR_TYPE_SIZE 16 424 425 /* Mask of all CPU selection flags. */ 426 #define MASK_ISA \ 427 (MASK_SPARCLITE + MASK_SPARCLET + MASK_LEON + MASK_LEON3 \ 428 + MASK_V8 + MASK_V9 + MASK_DEPRECATED_V8_INSNS) 429 430 /* Mask of all CPU feature flags. */ 431 #define MASK_FEATURES \ 432 (MASK_FPU + MASK_HARD_QUAD + MASK_VIS + MASK_VIS2 + MASK_VIS3 \ 433 + MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_FSMULD \ 434 + MASK_POPC + MASK_SUBXC) 435 436 /* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */ 437 #define TARGET_HARD_MUL \ 438 (TARGET_SPARCLITE || TARGET_SPARCLET \ 439 || TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) 440 441 /* TARGET_HARD_MUL32: Use 32-bit hardware multiply instructions with %y 442 to get high 32 bits. False in 64-bit or V8+ because multiply stores 443 a 64-bit result in a register. */ 444 #define TARGET_HARD_MUL32 \ 445 (TARGET_HARD_MUL && TARGET_ARCH32 && !TARGET_V8PLUS) 446 447 /* MASK_APP_REGS must always be the default because that's what 448 FIXED_REGISTERS is set to and -ffixed- is processed before 449 TARGET_CONDITIONAL_REGISTER_USAGE is called (where we process 450 -mno-app-regs). */ 451 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) 452 453 /* Recast the cpu class to be the cpu attribute. 454 Every file includes us, but not every file includes insn-attr.h. */ 455 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) 456 457 /* Support for a compile-time default CPU, et cetera. The rules are: 458 --with-cpu is ignored if -mcpu is specified. 459 --with-tune is ignored if -mtune is specified. 460 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu 461 are specified. */ 462 #define OPTION_DEFAULT_SPECS \ 463 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 464 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 465 {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" } 466 467 /* target machine storage layout */ 468 469 /* Define this if most significant bit is lowest numbered 470 in instructions that operate on numbered bit-fields. */ 471 #define BITS_BIG_ENDIAN 1 472 473 /* Define this if most significant byte of a word is the lowest numbered. */ 474 #define BYTES_BIG_ENDIAN 1 475 476 /* Define this if most significant word of a multiword number is the lowest 477 numbered. */ 478 #define WORDS_BIG_ENDIAN 1 479 480 #define MAX_BITS_PER_WORD 64 481 482 /* Width of a word, in units (bytes). */ 483 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) 484 #ifdef IN_LIBGCC2 485 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 486 #else 487 #define MIN_UNITS_PER_WORD 4 488 #endif 489 490 /* Now define the sizes of the C data types. */ 491 #define SHORT_TYPE_SIZE 16 492 #define INT_TYPE_SIZE 32 493 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) 494 #define LONG_LONG_TYPE_SIZE 64 495 #define FLOAT_TYPE_SIZE 32 496 #define DOUBLE_TYPE_SIZE 64 497 498 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the 499 SPARC ABI says that it is 128-bit wide. */ 500 /* #define LONG_DOUBLE_TYPE_SIZE 128 */ 501 502 /* The widest floating-point format really supported by the hardware. */ 503 #define WIDEST_HARDWARE_FP_SIZE 64 504 505 /* Width in bits of a pointer. This is the size of ptr_mode. */ 506 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) 507 508 /* This is the machine mode used for addresses. */ 509 #define Pmode (TARGET_ARCH64 ? DImode : SImode) 510 511 /* If we have to extend pointers (only when TARGET_ARCH64 and not 512 TARGET_PTR64), we want to do it unsigned. This macro does nothing 513 if ptr_mode and Pmode are the same. */ 514 #define POINTERS_EXTEND_UNSIGNED 1 515 516 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 517 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 518 519 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 520 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because 521 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */ 522 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) 523 524 /* Temporary hack until the FIXME above is fixed. */ 525 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS) 526 527 /* ALIGN FRAMES on double word boundaries */ 528 #define SPARC_STACK_ALIGN(LOC) ROUND_UP ((LOC), UNITS_PER_WORD * 2) 529 530 /* Allocation boundary (in *bits*) for the code of a function. */ 531 #define FUNCTION_BOUNDARY 32 532 533 /* Alignment of field after `int : 0' in a structure. */ 534 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 535 536 /* Every structure's size must be a multiple of this. */ 537 #define STRUCTURE_SIZE_BOUNDARY 8 538 539 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 540 #define PCC_BITFIELD_TYPE_MATTERS 1 541 542 /* No data type wants to be aligned rounder than this. */ 543 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) 544 545 /* The best alignment to use in cases where we have a choice. */ 546 #define FASTEST_ALIGNMENT 64 547 548 /* Define this macro as an expression for the alignment of a structure 549 (given by STRUCT as a tree node) if the alignment computed in the 550 usual way is COMPUTED and the alignment explicitly specified was 551 SPECIFIED. 552 553 The default is to use SPECIFIED if it is larger; otherwise, use 554 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ 555 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ 556 (TARGET_FASTER_STRUCTS ? \ 557 ((TREE_CODE (STRUCT) == RECORD_TYPE \ 558 || TREE_CODE (STRUCT) == UNION_TYPE \ 559 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ 560 && TYPE_FIELDS (STRUCT) != 0 \ 561 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ 562 : MAX ((COMPUTED), (SPECIFIED))) \ 563 : MAX ((COMPUTED), (SPECIFIED))) 564 565 /* An integer expression for the size in bits of the largest integer machine 566 mode that should actually be used. We allow pairs of registers. */ 567 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_ARCH64 ? TImode : DImode) 568 569 /* We need 2 words, so we can save the stack pointer and the return register 570 of the function containing a non-local goto target. */ 571 #define STACK_SAVEAREA_MODE(LEVEL) \ 572 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_ARCH64 ? TImode : DImode) : Pmode) 573 574 /* Make arrays of chars word-aligned for the same reasons. */ 575 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 576 (TREE_CODE (TYPE) == ARRAY_TYPE \ 577 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 578 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 579 580 /* Make local arrays of chars word-aligned for the same reasons. */ 581 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN) 582 583 /* Set this nonzero if move instructions will actually fail to work 584 when given unaligned data. */ 585 #define STRICT_ALIGNMENT 1 586 587 /* Things that must be doubleword aligned cannot go in the text section, 588 because the linker fails to align the text section enough! 589 Put them in the data section. This macro is only used in this file. */ 590 #define MAX_TEXT_ALIGN 32 591 592 /* Standard register usage. */ 593 594 /* Number of actual hardware registers. 595 The hardware registers are assigned numbers for the compiler 596 from 0 to just below FIRST_PSEUDO_REGISTER. 597 All registers that the compiler knows about must be given numbers, 598 even those that are not normally considered general registers. 599 600 SPARC has 32 integer registers and 32 floating point registers. 601 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not 602 accessible. We still account for them to simplify register computations 603 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so 604 32+32+32+4 == 100. 605 Register 100 is used as the integer condition code register. 606 Register 101 is used as the soft frame pointer register. 607 Register 102 is used as the general status register by VIS instructions. */ 608 609 #define FIRST_PSEUDO_REGISTER 103 610 611 #define SPARC_FIRST_INT_REG 0 612 #define SPARC_LAST_INT_REG 31 613 #define SPARC_FIRST_FP_REG 32 614 /* Additional V9 fp regs. */ 615 #define SPARC_FIRST_V9_FP_REG 64 616 #define SPARC_LAST_V9_FP_REG 95 617 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ 618 #define SPARC_FIRST_V9_FCC_REG 96 619 #define SPARC_LAST_V9_FCC_REG 99 620 /* V8 fcc reg. */ 621 #define SPARC_FCC_REG 96 622 /* Integer CC reg. We don't distinguish %icc from %xcc. */ 623 #define SPARC_ICC_REG 100 624 #define SPARC_GSR_REG 102 625 626 /* Nonzero if REGNO is an fp reg. */ 627 #define SPARC_FP_REG_P(REGNO) \ 628 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) 629 630 /* Nonzero if REGNO is an int reg. */ 631 #define SPARC_INT_REG_P(REGNO) \ 632 (((unsigned) (REGNO)) <= SPARC_LAST_INT_REG) 633 634 /* Argument passing regs. */ 635 #define SPARC_OUTGOING_INT_ARG_FIRST 8 636 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24) 637 #define SPARC_FP_ARG_FIRST 32 638 639 /* 1 for registers that have pervasive standard uses 640 and are not available for the register allocator. 641 642 On non-v9 systems: 643 g1 is free to use as temporary. 644 g2-g4 are reserved for applications. Gcc normally uses them as 645 temporaries, but this can be disabled via the -mno-app-regs option. 646 g5 through g7 are reserved for the operating system. 647 648 On v9 systems: 649 g1,g5 are free to use as temporaries, and are free to use between calls 650 if the call is to an external function via the PLT. 651 g4 is free to use as a temporary in the non-embedded case. 652 g4 is reserved in the embedded case. 653 g2-g3 are reserved for applications. Gcc normally uses them as 654 temporaries, but this can be disabled via the -mno-app-regs option. 655 g6-g7 are reserved for the operating system (or application in 656 embedded case). 657 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must 658 currently be a fixed register until this pattern is rewritten. 659 Register 1 is also used when restoring call-preserved registers in large 660 stack frames. 661 662 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in 663 TARGET_CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. 664 */ 665 666 #define FIXED_REGISTERS \ 667 {1, 0, 2, 2, 2, 2, 1, 1, \ 668 0, 0, 0, 0, 0, 0, 1, 0, \ 669 0, 0, 0, 0, 0, 0, 0, 0, \ 670 0, 0, 0, 0, 0, 0, 0, 1, \ 671 \ 672 0, 0, 0, 0, 0, 0, 0, 0, \ 673 0, 0, 0, 0, 0, 0, 0, 0, \ 674 0, 0, 0, 0, 0, 0, 0, 0, \ 675 0, 0, 0, 0, 0, 0, 0, 0, \ 676 \ 677 0, 0, 0, 0, 0, 0, 0, 0, \ 678 0, 0, 0, 0, 0, 0, 0, 0, \ 679 0, 0, 0, 0, 0, 0, 0, 0, \ 680 0, 0, 0, 0, 0, 0, 0, 0, \ 681 \ 682 0, 0, 0, 0, 1, 1, 1} 683 684 /* 1 for registers not available across function calls. 685 Unlike the above, this need not include the FIXED_REGISTERS, but any 686 registers that can be used without being saved. 687 The latter must include the registers where values are returned 688 and the register where structure-value addresses are passed. 689 Aside from that, you can include as many other registers as you like. */ 690 691 #define CALL_REALLY_USED_REGISTERS \ 692 {1, 1, 1, 1, 1, 1, 1, 1, \ 693 1, 1, 1, 1, 1, 1, 1, 1, \ 694 0, 0, 0, 0, 0, 0, 0, 0, \ 695 0, 0, 0, 0, 0, 0, 0, 0, \ 696 \ 697 1, 1, 1, 1, 1, 1, 1, 1, \ 698 1, 1, 1, 1, 1, 1, 1, 1, \ 699 1, 1, 1, 1, 1, 1, 1, 1, \ 700 1, 1, 1, 1, 1, 1, 1, 1, \ 701 \ 702 1, 1, 1, 1, 1, 1, 1, 1, \ 703 1, 1, 1, 1, 1, 1, 1, 1, \ 704 1, 1, 1, 1, 1, 1, 1, 1, \ 705 1, 1, 1, 1, 1, 1, 1, 1, \ 706 \ 707 1, 1, 1, 1, 1, 1, 1} 708 709 /* Due to the ARCH64 discrepancy above we must override this next 710 macro too. */ 711 #define REGMODE_NATURAL_SIZE(MODE) sparc_regmode_natural_size (MODE) 712 713 /* Value is 1 if it is OK to rename a hard register FROM to another hard 714 register TO. We cannot rename %g1 as it may be used before the save 715 register window instruction in the prologue. */ 716 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1) 717 718 /* Select a register mode required for caller save of hard regno REGNO. 719 Contrary to what is documented, the default is not the smallest suitable 720 mode but the largest suitable mode for the given (REGNO, NREGS) pair and 721 it quickly creates paradoxical subregs that can be problematic. */ 722 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 723 ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE)) 724 725 /* Specify the registers used for certain standard purposes. 726 The values of these macros are register numbers. */ 727 728 /* Register to use for pushing function arguments. */ 729 #define STACK_POINTER_REGNUM 14 730 731 /* The stack bias (amount by which the hardware register is offset by). */ 732 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) 733 734 /* Actual top-of-stack address is 92/176 greater than the contents of the 735 stack pointer register for !v9/v9. That is: 736 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return 737 address, and 6*4 bytes for the 6 register parameters. 738 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer 739 parameter regs. */ 740 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) 741 742 /* Base register for access to local variables of the function. */ 743 #define HARD_FRAME_POINTER_REGNUM 30 744 745 /* The soft frame pointer does not have the stack bias applied. */ 746 #define FRAME_POINTER_REGNUM 101 747 748 #define INIT_EXPANDERS \ 749 do { \ 750 if (crtl->emit.regno_pointer_align) \ 751 { \ 752 /* The biased stack pointer is only aligned on BITS_PER_UNIT. */\ 753 if (SPARC_STACK_BIAS) \ 754 { \ 755 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) \ 756 = BITS_PER_UNIT; \ 757 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) \ 758 = BITS_PER_UNIT; \ 759 } \ 760 \ 761 /* In 32-bit mode, not everything is double-word aligned. */ \ 762 if (TARGET_ARCH32) \ 763 { \ 764 REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) \ 765 = BITS_PER_WORD; \ 766 REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) \ 767 = BITS_PER_WORD; \ 768 REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) \ 769 = BITS_PER_WORD; \ 770 } \ 771 } \ 772 } while (0) 773 774 /* Base register for access to arguments of the function. */ 775 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 776 777 /* Register in which static-chain is passed to a function. This must 778 not be a register used by the prologue. */ 779 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) 780 781 /* Register which holds the global offset table, if any. */ 782 #define GLOBAL_OFFSET_TABLE_REGNUM 23 783 784 /* Register which holds offset table for position-independent data references. 785 The original SPARC ABI imposes no requirement on the choice of the register 786 so we use a pseudo-register to make sure it is properly saved and restored 787 around calls to setjmp. Now the ABI of VxWorks RTP makes it live on entry 788 to PLT entries so we use the canonical GOT register in this case. */ 789 #define PIC_OFFSET_TABLE_REGNUM \ 790 (TARGET_VXWORKS_RTP && flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM) 791 792 /* Pick a default value we can notice from override_options: 793 !v9: Default is on. 794 v9: Default is off. 795 Originally it was -1, but later on the container of options changed to 796 unsigned byte, so we decided to pick 127 as default value, which does 797 reflect an undefined default value in case of 0/1. */ 798 #define DEFAULT_PCC_STRUCT_RETURN 127 799 800 /* Functions which return large structures get the address 801 to place the wanted value at offset 64 from the frame. 802 Must reserve 64 bytes for the in and local registers. 803 v9: Functions which return large structures get the address to place the 804 wanted value from an invisible first argument. */ 805 #define STRUCT_VALUE_OFFSET 64 806 807 /* Define the classes of registers for register constraints in the 808 machine description. Also define ranges of constants. 809 810 One of the classes must always be named ALL_REGS and include all hard regs. 811 If there is more than one class, another class must be named NO_REGS 812 and contain no registers. 813 814 The name GENERAL_REGS must be the name of a class (or an alias for 815 another name such as ALL_REGS). This is the class of registers 816 that is allowed by "g" or "r" in a register constraint. 817 Also, registers outside this class are allocated only when 818 instructions express preferences for them. 819 820 The classes must be numbered in nondecreasing order; that is, 821 a larger-numbered class must never be contained completely 822 in a smaller-numbered class. 823 824 For any two classes, it is very desirable that there be another 825 class that represents their union. */ 826 827 /* The SPARC has various kinds of registers: general, floating point, 828 and condition codes [well, it has others as well, but none that we 829 care directly about]. 830 831 For v9 we must distinguish between the upper and lower floating point 832 registers because the upper ones can't hold SFmode values. 833 TARGET_HARD_REGNO_MODE_OK won't help here because reload assumes that 834 register(s) satisfying a group need for a class will also satisfy a 835 single need for that class. EXTRA_FP_REGS is a bit of a misnomer as 836 it covers all 64 fp regs. 837 838 It is important that one class contains all the general and all the standard 839 fp regs. Otherwise find_reg() won't properly allocate int regs for moves, 840 because reg_class_record() will bias the selection in favor of fp regs, 841 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, 842 because FP_REGS > GENERAL_REGS. 843 844 It is also important that one class contain all the general and all 845 the fp regs. Otherwise when spilling a DFmode reg, it may be from 846 EXTRA_FP_REGS but find_reloads() may use class 847 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die 848 because the compiler thinks it doesn't have a spill reg when in 849 fact it does. 850 851 v9 also has 4 floating point condition code registers. Since we don't 852 have a class that is the union of FPCC_REGS with either of the others, 853 it is important that it appear first. Otherwise the compiler will die 854 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its 855 constraints. */ 856 857 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, 858 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, 859 ALL_REGS, LIM_REG_CLASSES }; 860 861 #define N_REG_CLASSES (int) LIM_REG_CLASSES 862 863 /* Give names of register classes as strings for dump file. */ 864 865 #define REG_CLASS_NAMES \ 866 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ 867 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ 868 "ALL_REGS" } 869 870 /* Define which registers fit in which classes. 871 This is an initializer for a vector of HARD_REG_SET 872 of length N_REG_CLASSES. */ 873 874 #define REG_CLASS_CONTENTS \ 875 {{0, 0, 0, 0}, /* NO_REGS */ \ 876 {0, 0, 0, 0xf}, /* FPCC_REGS */ \ 877 {0xffff, 0, 0, 0}, /* I64_REGS */ \ 878 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ 879 {0, -1, 0, 0}, /* FP_REGS */ \ 880 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ 881 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ 882 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ 883 {-1, -1, -1, 0x7f}} /* ALL_REGS */ 884 885 /* The same information, inverted: 886 Return the class number of the smallest class containing 887 reg number REGNO. This could be a conditional expression 888 or could index an array. */ 889 890 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 891 892 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] 893 894 /* This is the order in which to allocate registers normally. 895 896 We put %f0-%f7 last among the float registers, so as to make it more 897 likely that a pseudo-register which dies in the float return register 898 area will get allocated to the float return register, thus saving a move 899 instruction at the end of the function. 900 901 Similarly for integer return value registers. 902 903 We know in this case that we will not end up with a leaf function. 904 905 The register allocator is given the global and out registers first 906 because these registers are call clobbered and thus less useful to 907 global register allocation. 908 909 Next we list the local and in registers. They are not call clobbered 910 and thus very useful for global register allocation. We list the input 911 registers before the locals so that it is more likely the incoming 912 arguments received in those registers can just stay there and not be 913 reloaded. */ 914 915 #define REG_ALLOC_ORDER \ 916 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 917 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 918 15, /* %o7 */ \ 919 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 920 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ 921 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 922 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 923 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 924 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 925 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 926 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 927 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 928 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 929 96, 97, 98, 99, /* %fcc0-3 */ \ 930 100, 0, 14, 30, 101, 102 } /* %icc, %g0, %o6, %i6, %sfp, %gsr */ 931 932 /* This is the order in which to allocate registers for 933 leaf functions. If all registers can fit in the global and 934 output registers, then we have the possibility of having a leaf 935 function. 936 937 The macro actually mentioned the input registers first, 938 because they get renumbered into the output registers once 939 we know really do have a leaf function. 940 941 To be more precise, this register allocation order is used 942 when %o7 is found to not be clobbered right before register 943 allocation. Normally, the reason %o7 would be clobbered is 944 due to a call which could not be transformed into a sibling 945 call. 946 947 As a consequence, it is possible to use the leaf register 948 allocation order and not end up with a leaf function. We will 949 not get suboptimal register allocation in that case because by 950 definition of being potentially leaf, there were no function 951 calls. Therefore, allocation order within the local register 952 window is not critical like it is when we do have function calls. */ 953 954 #define REG_LEAF_ALLOC_ORDER \ 955 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 956 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ 957 15, /* %o7 */ \ 958 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 959 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 960 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 961 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 962 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 963 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 964 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 965 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 966 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 967 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 968 96, 97, 98, 99, /* %fcc0-3 */ \ 969 100, 0, 14, 30, 31, 101, 102 } /* %icc, %g0, %o6, %i6, %i7, %sfp, %gsr */ 970 971 #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () 972 973 extern char sparc_leaf_regs[]; 974 #define LEAF_REGISTERS sparc_leaf_regs 975 976 extern char leaf_reg_remap[]; 977 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) 978 979 /* The class value for index registers, and the one for base regs. */ 980 #define INDEX_REG_CLASS GENERAL_REGS 981 #define BASE_REG_CLASS GENERAL_REGS 982 983 /* Local macro to handle the two v9 classes of FP regs. */ 984 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) 985 986 /* Predicate for 2-bit and 5-bit unsigned constants. */ 987 #define SPARC_IMM2_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x3) == 0) 988 #define SPARC_IMM5_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x1F) == 0) 989 990 /* Predicates for 5-bit, 10-bit, 11-bit and 13-bit signed constants. */ 991 #define SPARC_SIMM5_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x10 < 0x20) 992 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) 993 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) 994 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) 995 996 /* 10- and 11-bit immediates are only used for a few specific insns. 997 SMALL_INT is used throughout the port so we continue to use it. */ 998 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) 999 1000 /* Predicate for constants that can be loaded with a sethi instruction. 1001 This is the general, 64-bit aware, bitwise version that ensures that 1002 only constants whose representation fits in the mask 1003 1004 0x00000000fffffc00 1005 1006 are accepted. It will reject, for example, negative SImode constants 1007 on 64-bit hosts, so correct handling is to mask the value beforehand 1008 according to the mode of the instruction. */ 1009 #define SPARC_SETHI_P(X) \ 1010 (((unsigned HOST_WIDE_INT) (X) \ 1011 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) 1012 1013 /* Version of the above predicate for SImode constants and below. */ 1014 #define SPARC_SETHI32_P(X) \ 1015 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) 1016 1017 /* Return the maximum number of consecutive registers 1018 needed to represent mode MODE in a register of class CLASS. */ 1019 /* On SPARC, this is the size of MODE in words. */ 1020 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1021 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ 1022 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1023 1024 /* Stack layout; function entry, exit and calling. */ 1025 1026 /* Define this if pushing a word on the stack 1027 makes the stack pointer a smaller address. */ 1028 #define STACK_GROWS_DOWNWARD 1 1029 1030 /* Define this to nonzero if the nominal address of the stack frame 1031 is at the high-address end of the local variables; 1032 that is, each additional local variable allocated 1033 goes at a more negative offset in the frame. */ 1034 #define FRAME_GROWS_DOWNWARD 1 1035 1036 /* Offset of first parameter from the argument pointer register value. 1037 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg 1038 even if this function isn't going to use it. 1039 v9: This is 128 for the ins and locals. */ 1040 #define FIRST_PARM_OFFSET(FNDECL) \ 1041 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) 1042 1043 /* Offset from the argument pointer register value to the CFA. 1044 This is different from FIRST_PARM_OFFSET because the register window 1045 comes between the CFA and the arguments. */ 1046 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1047 1048 /* When a parameter is passed in a register, stack space is still 1049 allocated for it. 1050 !v9: All 6 possible integer registers have backing store allocated. 1051 v9: Only space for the arguments passed is allocated. */ 1052 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special 1053 meaning to the backend. Further, we need to be able to detect if a 1054 varargs/unprototyped function is called, as they may want to spill more 1055 registers than we've provided space. Ugly, ugly. So for now we retain 1056 all 6 slots even for v9. */ 1057 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) 1058 1059 /* Definitions for register elimination. */ 1060 1061 #define ELIMINABLE_REGS \ 1062 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1063 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } 1064 1065 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1066 do \ 1067 { \ 1068 (OFFSET) = sparc_initial_elimination_offset ((TO)); \ 1069 } \ 1070 while (0) 1071 1072 /* Keep the stack pointer constant throughout the function. 1073 This is both an optimization and a necessity: longjmp 1074 doesn't behave itself when the stack pointer moves within 1075 the function! */ 1076 #define ACCUMULATE_OUTGOING_ARGS 1 1077 1078 /* Define this macro if the target machine has "register windows". This 1079 C expression returns the register number as seen by the called function 1080 corresponding to register number OUT as seen by the calling function. 1081 Return OUT if register number OUT is not an outbound register. */ 1082 1083 #define INCOMING_REGNO(OUT) \ 1084 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) 1085 1086 /* Define this macro if the target machine has "register windows". This 1087 C expression returns the register number as seen by the calling function 1088 corresponding to register number IN as seen by the called function. 1089 Return IN if register number IN is not an inbound register. */ 1090 1091 #define OUTGOING_REGNO(IN) \ 1092 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) 1093 1094 /* Define this macro if the target machine has register windows. This 1095 C expression returns true if the register is call-saved but is in the 1096 register window. */ 1097 1098 #define LOCAL_REGNO(REGNO) \ 1099 (!TARGET_FLAT && (REGNO) >= 16 && (REGNO) <= 31) 1100 1101 /* Define the size of space to allocate for the return value of an 1102 untyped_call. */ 1103 1104 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16) 1105 1106 /* 1 if N is a possible register number for function argument passing. 1107 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ 1108 1109 #define FUNCTION_ARG_REGNO_P(N) \ 1110 (((N) >= 8 && (N) <= 13) \ 1111 || (TARGET_ARCH64 && TARGET_FPU && (N) >= 32 && (N) <= 63)) 1112 1113 /* Define a data type for recording info about an argument list 1114 during the scan of that argument list. This data type should 1115 hold all necessary information about the function itself 1116 and about the args processed so far, enough to enable macros 1117 such as FUNCTION_ARG to determine where the next arg should go. 1118 1119 On SPARC (!v9), this is a single integer, which is a number of words 1120 of arguments scanned so far (including the invisible argument, 1121 if any, which holds the structure-value-address). 1122 Thus 7 or more means all following args should go on the stack. 1123 1124 For v9, we also need to know whether a prototype is present. */ 1125 1126 struct sparc_args { 1127 int words; /* number of words passed so far */ 1128 int prototype_p; /* nonzero if a prototype is present */ 1129 int libcall_p; /* nonzero if a library call */ 1130 }; 1131 #define CUMULATIVE_ARGS struct sparc_args 1132 1133 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1134 for a call to a function whose data type is FNTYPE. 1135 For a library call, FNTYPE is 0. */ 1136 1137 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1138 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL)); 1139 1140 1141 /* Generate the special assembly code needed to tell the assembler whatever 1142 it might need to know about the return value of a function. 1143 1144 For SPARC assemblers, we need to output a .proc pseudo-op which conveys 1145 information to the assembler relating to peephole optimization (done in 1146 the assembler). */ 1147 1148 #define ASM_DECLARE_RESULT(FILE, RESULT) \ 1149 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) 1150 1151 /* Output the special assembly code needed to tell the assembler some 1152 register is used as global register variable. 1153 1154 SPARC 64bit psABI declares registers %g2 and %g3 as application 1155 registers and %g6 and %g7 as OS registers. Any object using them 1156 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them 1157 and how they are used (scratch or some global variable). 1158 Linker will then refuse to link together objects which use those 1159 registers incompatibly. 1160 1161 Unless the registers are used for scratch, two different global 1162 registers cannot be declared to the same name, so in the unlikely 1163 case of a global register variable occupying more than one register 1164 we prefix the second and following registers with .gnu.part1. etc. */ 1165 1166 extern GTY(()) char sparc_hard_reg_printed[8]; 1167 1168 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ 1169 do { \ 1170 if (TARGET_ARCH64) \ 1171 { \ 1172 int end = end_hard_regno (DECL_MODE (decl), REGNO); \ 1173 int reg; \ 1174 for (reg = (REGNO); reg < 8 && reg < end; reg++) \ 1175 if ((reg & ~1) == 2 || (reg & ~1) == 6) \ 1176 { \ 1177 if (reg == (REGNO)) \ 1178 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ 1179 else \ 1180 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ 1181 reg, reg - (REGNO), (NAME)); \ 1182 sparc_hard_reg_printed[reg] = 1; \ 1183 } \ 1184 } \ 1185 } while (0) 1186 1187 /* Emit rtl for profiling. */ 1188 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) 1189 1190 /* All the work done in PROFILE_HOOK, but still required. */ 1191 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) 1192 1193 /* Set the name of the mcount function for the system. */ 1194 #define MCOUNT_FUNCTION "*mcount" 1195 1196 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1197 the stack pointer does not matter. The value is tested only in 1198 functions that have frame pointers. */ 1199 #define EXIT_IGNORE_STACK 1 1200 1201 /* Length in units of the trampoline for entering a nested function. */ 1202 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) 1203 1204 /* Alignment required for trampolines, in bits. */ 1205 #define TRAMPOLINE_ALIGNMENT 128 1206 1207 /* Generate RTL to flush the register windows so as to make arbitrary frames 1208 available. */ 1209 #define SETUP_FRAME_ADDRESSES() \ 1210 do { \ 1211 if (!TARGET_FLAT) \ 1212 emit_insn (gen_flush_register_windows ());\ 1213 } while (0) 1214 1215 /* Given an rtx for the address of a frame, 1216 return an rtx for the address of the word in the frame 1217 that holds the dynamic chain--the previous frame's address. */ 1218 #define DYNAMIC_CHAIN_ADDRESS(frame) \ 1219 plus_constant (Pmode, frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) 1220 1221 /* Given an rtx for the frame pointer, 1222 return an rtx for the address of the frame. */ 1223 #define FRAME_ADDR_RTX(frame) plus_constant (Pmode, frame, SPARC_STACK_BIAS) 1224 1225 /* The return address isn't on the stack, it is in a register, so we can't 1226 access it from the current frame pointer. We can access it from the 1227 previous frame pointer though by reading a value from the register window 1228 save area. */ 1229 #define RETURN_ADDR_IN_PREVIOUS_FRAME 1 1230 1231 /* This is the offset of the return address to the true next instruction to be 1232 executed for the current function. */ 1233 #define RETURN_ADDR_OFFSET \ 1234 (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct)) 1235 1236 /* The current return address is in %i7. The return address of anything 1237 farther back is in the register window save area at [%fp+60]. */ 1238 /* ??? This ignores the fact that the actual return address is +8 for normal 1239 returns, and +12 for structure returns. */ 1240 #define RETURN_ADDR_REGNUM 31 1241 #define RETURN_ADDR_RTX(count, frame) \ 1242 ((count == -1) \ 1243 ? gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) \ 1244 : gen_rtx_MEM (Pmode, \ 1245 memory_address (Pmode, plus_constant (Pmode, frame, \ 1246 15 * UNITS_PER_WORD \ 1247 + SPARC_STACK_BIAS)))) 1248 1249 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's 1250 +12, but always using +8 is close enough for frame unwind purposes. 1251 Actually, just using %o7 is close enough for unwinding, but %o7+8 1252 is something you can return to. */ 1253 #define INCOMING_RETURN_ADDR_REGNUM 15 1254 #define INCOMING_RETURN_ADDR_RTX \ 1255 plus_constant (word_mode, \ 1256 gen_rtx_REG (word_mode, INCOMING_RETURN_ADDR_REGNUM), 8) 1257 #define DWARF_FRAME_RETURN_COLUMN \ 1258 DWARF_FRAME_REGNUM (INCOMING_RETURN_ADDR_REGNUM) 1259 1260 /* The offset from the incoming value of %sp to the top of the stack frame 1261 for the current function. On sparc64, we have to account for the stack 1262 bias if present. */ 1263 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS 1264 1265 /* Describe how we implement __builtin_eh_return. */ 1266 #define EH_RETURN_REGNUM 1 1267 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) 1268 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM) 1269 1270 /* Define registers used by the epilogue and return instruction. */ 1271 #define EPILOGUE_USES(REGNO) \ 1272 ((REGNO) == RETURN_ADDR_REGNUM \ 1273 || (TARGET_FLAT \ 1274 && epilogue_completed \ 1275 && (REGNO) == INCOMING_RETURN_ADDR_REGNUM) \ 1276 || (crtl->calls_eh_return && (REGNO) == EH_RETURN_REGNUM)) 1277 1278 /* Select a format to encode pointers in exception handling data. CODE 1279 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1280 true if the symbol may be affected by dynamic relocations. 1281 1282 If assembler and linker properly support .uaword %r_disp32(foo), 1283 then use PC relative 32-bit relocations instead of absolute relocs 1284 for shared libraries. On sparc64, use pc relative 32-bit relocs even 1285 for binaries, to save memory. 1286 1287 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the 1288 symbol %r_disp32() is against was not local, but .hidden. In that 1289 case, we have to use DW_EH_PE_absptr for pic personality. */ 1290 #ifdef HAVE_AS_SPARC_UA_PCREL 1291 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN 1292 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1293 (flag_pic \ 1294 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 1295 : ((TARGET_ARCH64 && ! GLOBAL) \ 1296 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1297 : DW_EH_PE_absptr)) 1298 #else 1299 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1300 (flag_pic \ 1301 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ 1302 : ((TARGET_ARCH64 && ! GLOBAL) \ 1303 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1304 : DW_EH_PE_absptr)) 1305 #endif 1306 1307 /* Emit a PC-relative relocation. */ 1308 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 1309 do { \ 1310 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1311 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ 1312 assemble_name (FILE, LABEL); \ 1313 fputc (')', FILE); \ 1314 } while (0) 1315 #endif 1316 1317 /* Addressing modes, and classification of registers for them. */ 1318 1319 /* Macros to check register numbers against specific register classes. */ 1320 1321 /* These assume that REGNO is a hard or pseudo reg number. 1322 They give nonzero only if REGNO is a hard reg of the suitable class 1323 or a pseudo reg currently allocated to a suitable hard reg. 1324 Since they use reg_renumber, they are safe only once reg_renumber 1325 has been allocated, which happens in reginfo.c during register 1326 allocation. */ 1327 1328 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1329 (SPARC_INT_REG_P (REGNO) || SPARC_INT_REG_P (reg_renumber[REGNO]) \ 1330 || (REGNO) == FRAME_POINTER_REGNUM \ 1331 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) 1332 1333 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 1334 1335 #define REGNO_OK_FOR_FP_P(REGNO) \ 1336 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ 1337 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) 1338 1339 #define REGNO_OK_FOR_CCFP_P(REGNO) \ 1340 (TARGET_V9 \ 1341 && (((unsigned) (REGNO) - 96 < (unsigned)4) \ 1342 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) 1343 1344 /* Maximum number of registers that can appear in a valid memory address. */ 1345 1346 #define MAX_REGS_PER_ADDRESS 2 1347 1348 /* Recognize any constant value that is a valid address. 1349 When PIC, we do not accept an address that would require a scratch reg 1350 to load into a register. */ 1351 1352 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1353 1354 /* Define this, so that when PIC, reload won't try to reload invalid 1355 addresses which require two reload registers. */ 1356 1357 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1358 1359 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */ 1360 1361 #ifdef HAVE_AS_OFFSETABLE_LO10 1362 #define USE_AS_OFFSETABLE_LO10 1 1363 #else 1364 #define USE_AS_OFFSETABLE_LO10 0 1365 #endif 1366 1367 /* Try a machine-dependent way of reloading an illegitimate address 1368 operand. If we find one, push the reload and jump to WIN. This 1369 macro is used in only one place: `find_reloads_address' in reload.c. */ 1370 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1371 do { \ 1372 int win; \ 1373 (X) = sparc_legitimize_reload_address ((X), (MODE), (OPNUM), \ 1374 (int)(TYPE), (IND_LEVELS), &win); \ 1375 if (win) \ 1376 goto WIN; \ 1377 } while (0) 1378 1379 /* Specify the machine mode that this machine uses 1380 for the index in the tablejump instruction. */ 1381 /* If we ever implement any of the full models (such as CM_FULLANY), 1382 this has to be DImode in that case */ 1383 #ifdef HAVE_GAS_SUBSECTION_ORDERING 1384 #define CASE_VECTOR_MODE \ 1385 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) 1386 #else 1387 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise 1388 we have to sign extend which slows things down. */ 1389 #define CASE_VECTOR_MODE \ 1390 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) 1391 #endif 1392 1393 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1394 #define DEFAULT_SIGNED_CHAR 1 1395 1396 /* Max number of bytes we can move from memory to memory 1397 in one reasonably fast instruction. */ 1398 #define MOVE_MAX 8 1399 1400 /* If a memory-to-memory move would take MOVE_RATIO or more simple 1401 move-instruction pairs, we will do a cpymem or libcall instead. */ 1402 1403 #define MOVE_RATIO(speed) ((speed) ? 8 : 3) 1404 1405 /* Define if operations between registers always perform the operation 1406 on the full register even if a narrower mode is specified. */ 1407 #define WORD_REGISTER_OPERATIONS 1 1408 1409 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1410 will either zero-extend or sign-extend. The value of this macro should 1411 be the code that says which one of the two operations is implicitly 1412 done, UNKNOWN if none. */ 1413 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1414 1415 /* Nonzero if access to memory by bytes is slow and undesirable. 1416 For RISC chips, it means that access to memory by bytes is no 1417 better than access by words when possible, so grab a whole word 1418 and maybe make use of that. */ 1419 #define SLOW_BYTE_ACCESS 1 1420 1421 /* Define this to be nonzero if shift instructions ignore all but the low-order 1422 few bits. */ 1423 #define SHIFT_COUNT_TRUNCATED 1 1424 1425 /* For SImode, we make sure the top 32-bits of the register are clear and 1426 then we subtract 32 from the lzd instruction result. */ 1427 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1428 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) 1429 1430 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1431 return the mode to be used for the comparison. For floating-point, 1432 CCFP[E]mode is used. CCNZmode should be used when the first operand 1433 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 1434 processing is needed. */ 1435 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) 1436 1437 /* Return nonzero if MODE implies a floating point inequality can be 1438 reversed. For SPARC this is always true because we have a full 1439 compliment of ordered and unordered comparisons, but until generic 1440 code knows how to reverse it correctly we keep the old definition. */ 1441 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) 1442 1443 /* A function address in a call instruction for indexing purposes. */ 1444 #define FUNCTION_MODE Pmode 1445 1446 /* Define this if addresses of constant functions 1447 shouldn't be put through pseudo regs where they can be cse'd. 1448 Desirable on machines where ordinary constants are expensive 1449 but a CALL with constant address is cheap. */ 1450 #define NO_FUNCTION_CSE 1 1451 1452 /* The _Q_* comparison libcalls return booleans. */ 1453 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) 1454 1455 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such 1456 that the inputs are fully consumed before the output memory is clobbered. */ 1457 1458 #define TARGET_BUGGY_QP_LIB 0 1459 1460 /* Assume by default that we do not have the Solaris-specific conversion 1461 routines nor 64-bit integer multiply and divide routines. */ 1462 1463 #define SUN_CONVERSION_LIBFUNCS 0 1464 #define DITF_CONVERSION_LIBFUNCS 0 1465 #define SUN_INTEGER_MULTIPLY_64 0 1466 1467 /* A C expression for the cost of a branch instruction. A value of 1 1468 is the default; other values are interpreted relative to that. */ 1469 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ 1470 (sparc_branch_cost (SPEED_P, PREDICTABLE_P)) 1471 1472 /* Control the assembler format that we output. */ 1473 1474 /* A C string constant describing how to begin a comment in the target 1475 assembler language. The compiler assumes that the comment will end at 1476 the end of the line. */ 1477 1478 #define ASM_COMMENT_START "!" 1479 1480 /* Output to assembler file text saying following lines 1481 may contain character constants, extra white space, comments, etc. */ 1482 1483 #define ASM_APP_ON "" 1484 1485 /* Output to assembler file text saying following lines 1486 no longer contain unusual constructs. */ 1487 1488 #define ASM_APP_OFF "" 1489 1490 /* How to refer to registers in assembler output. 1491 This sequence is indexed by compiler's hard-register-number (see above). */ 1492 1493 #define REGISTER_NAMES \ 1494 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 1495 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 1496 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 1497 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 1498 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 1499 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 1500 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 1501 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ 1502 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ 1503 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ 1504 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ 1505 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ 1506 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp", "%gsr" } 1507 1508 /* Define additional names for use in asm clobbers and asm declarations. */ 1509 1510 #define ADDITIONAL_REGISTER_NAMES \ 1511 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} 1512 1513 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length 1514 can run past this up to a continuation point. Once we used 1500, but 1515 a single entry in C++ can run more than 500 bytes, due to the length of 1516 mangled symbol names. dbxout.c should really be fixed to do 1517 continuations when they are actually needed instead of trying to 1518 guess... */ 1519 #define DBX_CONTIN_LENGTH 1000 1520 1521 /* This is how to output a command to make the user-level label named NAME 1522 defined for reference from other files. */ 1523 1524 /* Globalizing directive for a label. */ 1525 #define GLOBAL_ASM_OP "\t.global " 1526 1527 /* The prefix to add to user-visible assembler symbols. */ 1528 1529 #define USER_LABEL_PREFIX "_" 1530 1531 /* This is how to store into the string LABEL 1532 the symbol_ref name of an internal numbered label where 1533 PREFIX is the class of label and NUM is the number within the class. 1534 This is suitable for output with `assemble_name'. */ 1535 1536 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1537 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) 1538 1539 /* This is how we hook in and defer the case-vector until the end of 1540 the function. */ 1541 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ 1542 sparc_defer_case_vector ((LAB),(VEC), 0) 1543 1544 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ 1545 sparc_defer_case_vector ((LAB),(VEC), 1) 1546 1547 /* This is how to output an element of a case-vector that is absolute. */ 1548 1549 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1550 do { \ 1551 char label[30]; \ 1552 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1553 if (CASE_VECTOR_MODE == SImode) \ 1554 fprintf (FILE, "\t.word\t"); \ 1555 else \ 1556 fprintf (FILE, "\t.xword\t"); \ 1557 assemble_name (FILE, label); \ 1558 fputc ('\n', FILE); \ 1559 } while (0) 1560 1561 /* This is how to output an element of a case-vector that is relative. 1562 (SPARC uses such vectors only when generating PIC.) */ 1563 1564 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1565 do { \ 1566 char label[30]; \ 1567 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ 1568 if (CASE_VECTOR_MODE == SImode) \ 1569 fprintf (FILE, "\t.word\t"); \ 1570 else \ 1571 fprintf (FILE, "\t.xword\t"); \ 1572 assemble_name (FILE, label); \ 1573 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ 1574 fputc ('-', FILE); \ 1575 assemble_name (FILE, label); \ 1576 fputc ('\n', FILE); \ 1577 } while (0) 1578 1579 /* This is what to output before and after case-vector (both 1580 relative and absolute). If .subsection -1 works, we put case-vectors 1581 at the beginning of the current section. */ 1582 1583 #ifdef HAVE_GAS_SUBSECTION_ORDERING 1584 1585 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \ 1586 fprintf(FILE, "\t.subsection\t-1\n") 1587 1588 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \ 1589 fprintf(FILE, "\t.previous\n") 1590 1591 #endif 1592 1593 /* This is how to output an assembler line 1594 that says to advance the location counter 1595 to a multiple of 2**LOG bytes. */ 1596 1597 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1598 if ((LOG) != 0) \ 1599 fprintf (FILE, "\t.align %d\n", (1 << (LOG))) 1600 1601 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1602 fprintf (FILE, "\t.skip " HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 1603 1604 /* This says how to output an assembler line 1605 to define a global common symbol. */ 1606 1607 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1608 ( fputs ("\t.common ", (FILE)), \ 1609 assemble_name ((FILE), (NAME)), \ 1610 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE))) 1611 1612 /* This says how to output an assembler line to define a local common 1613 symbol. */ 1614 1615 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ 1616 ( fputs ("\t.reserve ", (FILE)), \ 1617 assemble_name ((FILE), (NAME)), \ 1618 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \ 1619 (SIZE), ((ALIGNED) / BITS_PER_UNIT))) 1620 1621 /* A C statement (sans semicolon) to output to the stdio stream 1622 FILE the assembler definition of uninitialized global DECL named 1623 NAME whose size is SIZE bytes and alignment is ALIGN bytes. 1624 Try to use asm_output_aligned_bss to implement this macro. */ 1625 1626 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 1627 do { \ 1628 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ 1629 } while (0) 1630 1631 /* Output #ident as a .ident. */ 1632 1633 #undef TARGET_ASM_OUTPUT_IDENT 1634 #define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive 1635 1636 /* Prettify the assembly. */ 1637 1638 extern int sparc_indent_opcode; 1639 1640 #define ASM_OUTPUT_OPCODE(FILE, PTR) \ 1641 do { \ 1642 if (sparc_indent_opcode) \ 1643 { \ 1644 putc (' ', FILE); \ 1645 sparc_indent_opcode = 0; \ 1646 } \ 1647 } while (0) 1648 1649 /* TLS support defaulting to original Sun flavor. GNU extensions 1650 must be activated in separate configuration files. */ 1651 #ifdef HAVE_AS_TLS 1652 #define TARGET_TLS 1 1653 #else 1654 #define TARGET_TLS 0 1655 #endif 1656 1657 #define TARGET_SUN_TLS TARGET_TLS 1658 #define TARGET_GNU_TLS 0 1659 1660 #ifdef HAVE_AS_FMAF_HPC_VIS3 1661 #define AS_NIAGARA3_FLAG "d" 1662 #else 1663 #define AS_NIAGARA3_FLAG "b" 1664 #endif 1665 1666 #ifdef HAVE_AS_SPARC4 1667 #define AS_NIAGARA4_FLAG "-xarch=sparc4" 1668 #else 1669 #define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG 1670 #endif 1671 1672 #ifdef HAVE_AS_SPARC5_VIS4 1673 #define AS_NIAGARA7_FLAG "-xarch=sparc5" 1674 #else 1675 #define AS_NIAGARA7_FLAG AS_NIAGARA4_FLAG 1676 #endif 1677 1678 #ifdef HAVE_AS_SPARC6 1679 #define AS_M8_FLAG "-xarch=sparc6" 1680 #else 1681 #define AS_M8_FLAG AS_NIAGARA7_FLAG 1682 #endif 1683 1684 #ifdef HAVE_AS_LEON 1685 #define AS_LEON_FLAG "-Aleon" 1686 #define AS_LEONV7_FLAG "-Aleon" 1687 #else 1688 #define AS_LEON_FLAG "-Av8" 1689 #define AS_LEONV7_FLAG "-Av7" 1690 #endif 1691 1692 /* We use gcc _mcount for profiling. */ 1693 #define NO_PROFILE_COUNTERS 0 1694 1695 /* Debug support */ 1696 #define MASK_DEBUG_OPTIONS 0x01 /* debug option handling */ 1697 #define MASK_DEBUG_ALL MASK_DEBUG_OPTIONS 1698 1699 #define TARGET_DEBUG_OPTIONS (sparc_debug & MASK_DEBUG_OPTIONS) 1700 1701 /* By default, use the weakest memory model for the cpu. */ 1702 #ifndef SUBTARGET_DEFAULT_MEMORY_MODEL 1703 #define SUBTARGET_DEFAULT_MEMORY_MODEL SMM_DEFAULT 1704 #endif 1705 1706 /* Define this to 1 if the FE_EXCEPT values defined in fenv.h start at 1. */ 1707 #define SPARC_LOW_FE_EXCEPT_VALUES 0 1708 1709 #define TARGET_SUPPORTS_WIDE_INT 1 1710