1/* Definitions of target machine for GCC, for Sun SPARC. 2 Copyright (C) 2002-2015 Free Software Foundation, Inc. 3 Contributed by Michael Tiemann (tiemann@cygnus.com). 4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 5 at Cygnus Support. 6 7This file is part of GCC. 8 9GCC is free software; you can redistribute it and/or modify 10it under the terms of the GNU General Public License as published by 11the Free Software Foundation; either version 3, or (at your option) 12any later version. 13 14GCC is distributed in the hope that it will be useful, 15but WITHOUT ANY WARRANTY; without even the implied warranty of 16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17GNU General Public License for more details. 18 19You should have received a copy of the GNU General Public License 20along with GCC; see the file COPYING3. If not see 21<http://www.gnu.org/licenses/>. */ 22 23/* 128-bit floating point */ 24FLOAT_MODE (TF, 16, ieee_quad_format); 25 26/* Add any extra modes needed to represent the condition code. 27 28 On the SPARC, we have a "no-overflow" mode which is used when an add or 29 subtract insn is used to set the condition code. Different branches are 30 used in this case for some operations. 31 32 We also have two modes to indicate that the relevant condition code is 33 in the floating-point condition code register. One for comparisons which 34 will generate an exception if the result is unordered (CCFPEmode) and 35 one for comparisons which will never trap (CCFPmode). 36 37 CCXmode and CCX_NOOVmode are only used by v9. */ 38 39CC_MODE (CCX); 40CC_MODE (CC_NOOV); 41CC_MODE (CCX_NOOV); 42CC_MODE (CCFP); 43CC_MODE (CCFPE); 44 45/* Vector modes. */ 46VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ 47VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */ 48VECTOR_MODES (INT, 4); /* V4QI V2HI */ 49VECTOR_MODE (INT, DI, 1); /* V1DI */ 50VECTOR_MODE (INT, SI, 1); /* V1SI */ 51