1/* Definitions of target machine for GNU compiler, for IBM S/390 2 Copyright (C) 2002-2020 Free Software Foundation, Inc. 3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and 4 Ulrich Weigand (uweigand@de.ibm.com). 5 6This file is part of GCC. 7 8GCC is free software; you can redistribute it and/or modify it under 9the terms of the GNU General Public License as published by the Free 10Software Foundation; either version 3, or (at your option) any later 11version. 12 13GCC is distributed in the hope that it will be useful, but WITHOUT ANY 14WARRANTY; without even the implied warranty of MERCHANTABILITY or 15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16for more details. 17 18You should have received a copy of the GNU General Public License 19along with GCC; see the file COPYING3. If not see 20<http://www.gnu.org/licenses/>. */ 21 22/* 256-bit integer mode is needed for STACK_SAVEAREA_MODE. */ 23INT_MODE (OI, 32); 24 25/* Define TFmode to work around reload problem PR 20927. */ 26FLOAT_MODE (TF, 16, ieee_quad_format); 27 28/* Add any extra modes needed to represent the condition code. */ 29 30/* 31 32Condition Codes 33 34 CC0 CC1 CC2 CC3 35 36Check for zero 37 38CCZ: EQ NE NE NE 39CCZ1: EQ NE (CS) 40 41Unsigned compares 42 43CCU: EQ LTU GTU NE (CLG/R, CL/R/Y, CLM/Y, CLI/Y) 44CCUR: EQ GTU LTU NE (CLGF/R) 45 46Signed compares 47 48CCS: EQ LT GT UNORDERED (LTGFR, LTGR, LTR, ICM/Y, 49 LTDBR, LTDR, LTEBR, LTER, 50 CG/R, C/R/Y, CGHI, CHI, 51 CDB/R, CD/R, CEB/R, CE/R, 52 ADB/R, AEB/R, SDB/R, SEB/R, 53 SRAG, SRA, SRDA) 54CCSR: EQ GT LT UNORDERED (CGF/R, CH/Y) 55CCSFPS: EQ LT GT UNORDERED (KEB/R, KDB/R, KXBR, KDTR, 56 KXTR, WFK) 57 58Condition codes resulting from add with overflow 59 60CCA: EQ LT GT Overflow 61CCAP: EQ LT GT LT (AGHI, AHI) 62CCAN: EQ LT GT GT (AGHI, AHI) 63 64Condition codes for overflow checking resulting from signed adds/subs/mults 65 66CCO: EQ EQ EQ NE (AGR, AGHI, SGR, MSC, ...) 67 68Condition codes of unsigned adds and subs 69 70CCL: EQ NE EQ NE (ALGF/R, ALG/R, AL/R/Y, 71 ALCG/R, ALC/R, 72 SLGF/R, SLG/R, SL/R/Y, 73 SLBG/R, SLB/R) 74CCL1: GEU GEU LTU LTU (ALG/R, AL/R/Y) 75CCL2: GTU GTU LEU LEU (SLG/R, SL/R/Y) 76CCL3: EQ LTU EQ GTU (SLG/R, SL/R/Y) 77 78Test under mask checks 79 80CCT: EQ NE NE NE (ICM/Y, TML, CG/R, CGHI, 81 C/R/Y, CHI, NG/R, N/R/Y, 82 OG/R, O/R/Y, XG/R, X/R/Y) 83CCT1: NE EQ NE NE (TMH, TML) 84CCT2: NE NE EQ NE (TMH, TML) 85CCT3: NE NE NE EQ (TMH, TML) 86 87CCA and CCT modes are request only modes. These modes are never returned by 88s390_select_cc_mode. They are only intended to match other modes. 89 90Requested mode -> Destination CC register mode 91 92CCS, CCU, CCT, CCSR, CCUR -> CCZ 93CCA -> CCAP, CCAN 94 95 96 97*** Comments *** 98 99CCAP, CCAN 100 101The CC obtained from add instruction usually can't be used for comparisons 102because its coupling with overflow flag. In case of an overflow the 103less than/greater than data are lost. Nevertheless a comparison can be done 104whenever immediate values are involved because they are known at compile time. 105If you know whether the used constant is positive or negative you can predict 106the sign of the result even in case of an overflow. 107 108 109CCO 110 111This mode is used to check whether there was an overflow condition in 112a signed add, sub, or mul operation. See (addv<mode>4, subv<mode>4, 113mulv<mode>4 patterns). 114 115 116CCT, CCT1, CCT2, CCT3 117 118If bits of an integer masked with an AND instruction are checked, the test under 119mask instructions turn out to be very handy for a set of special cases. 120The simple cases are checks whether all masked bits are zero or ones: 121 122 int a; 123 if ((a & (16 + 128)) == 0) -> CCT/CCZ 124 if ((a & (16 + 128)) == 16 + 128) -> CCT3 125 126Using two extra modes makes it possible to do complete checks on two bits of an 127integer (This is possible on register operands only. TM does not provide the 128information necessary for CCT1 and CCT2 modes.): 129 130 int a; 131 if ((a & (16 + 128)) == 16) -> CCT1 132 if ((a & (16 + 128)) == 128) -> CCT2 133 134 135CCSR, CCUR 136 137There are several instructions comparing 32 bit with 64-bit unsigned/signed 138values. Such instructions can be considered to have a builtin zero/sign_extend. 139The problem is that in the RTL (to be canonical) the zero/sign extended operand 140has to be the first one but the machine instructions like it the other way 141around. The following both modes can be considered as CCS and CCU modes with 142exchanged operands. 143 144 145CCSFPS 146 147This mode is used for signaling rtxes: LT, LE, GT, GE and LTGT. 148 149 150CCL1, CCL2 151 152These modes represent the result of overflow checks. 153 154if (a + b < a) -> CCL1 state of the carry bit (CC2 | CC3) 155if (a - b > a) -> CCL2 state of the borrow bit (CC0 | CC1) 156 157They are used when multi word numbers are computed dealing one SImode part after 158another or whenever manual overflow checks like the examples above are 159compiled. 160 161 162CCL3 163 164A logical subtract instruction sets the borrow bit in case of an overflow. 165The resulting condition code of those instructions is represented by the 166CCL3 mode. Together with the CCU mode this mode is used for jumpless 167implementations of several if-constructs - see s390_expand_addcc for more 168details. 169 170CCZ1 171 172The compare and swap instructions sets the condition code to 0/1 if the 173operands were equal/unequal. The CCZ1 mode ensures the result can be 174effectively placed into a register. 175 176CCVIH, CCVIHU, CCVFH, CCVFHE 177 178These are condition code modes used in instructions setting the 179condition code. The mode determines which comparison to perform (H - 180high, HU - high unsigned, HE - high or equal) and whether it is a 181floating point comparison or not (I - int, F - float). 182 183The comparison operation to be performed needs to be encoded into the 184condition code mode since the comparison operator is not available in 185compare style patterns (set cc (compare (op0) (op1))). So the 186condition code mode is the only information to determine the 187instruction to be used. 188 189CCVIALL, CCVIANY, CCVFALL, CCVFANY 190 191These modes are used in instructions reading the condition code. 192Opposed to the CC producer patterns the comparison operator is 193available. Hence the comparison operation does not need to be part of 194the CC mode. However, we still need to know whether CC has been 195generated by a float or an integer comparison in order to be able to 196invert the condition correctly (int: GT -> LE, float: GT -> UNLE). 197 198The ALL and ANY variants differ only in the usage of CC1 which 199indicates a mixed result across the vector elements. Be aware that 200depending on the comparison code the ALL and ANY variants might 201actually refer to their opposite meaning. I.e. while inverting the 202comparison in (EQ (reg:CCVIALL 33) (const_int 0)) results in (NE 203(reg:CCVIALL 33) (const_int 0)) it in fact describes an ANY comparison 204(inverting "all equal" should be "any not equal") However, the 205middle-end does invert only the comparison operator without touching 206the mode. 207Hence, the ALL/ANY in the mode names refer to the meaning in the 208context of EQ, GT, GE while for the inverted codes it actually means 209ANY/ALL. 210 211CCRAW 212 213The cc mode generated by a non-compare instruction. The condition 214code mask for the CC consumer is determined by the comparison operator 215(only EQ and NE allowed) and the immediate value given as second 216operand to the operator. For the other CC modes this value used to be 2170. 218 219*/ 220 221 222CC_MODE (CCZ); 223CC_MODE (CCZ1); 224CC_MODE (CCA); 225CC_MODE (CCAP); 226CC_MODE (CCAN); 227CC_MODE (CCO); 228CC_MODE (CCL); 229CC_MODE (CCL1); 230CC_MODE (CCL2); 231CC_MODE (CCL3); 232CC_MODE (CCU); 233CC_MODE (CCUR); 234CC_MODE (CCS); 235CC_MODE (CCSR); 236CC_MODE (CCSFPS); 237CC_MODE (CCT); 238CC_MODE (CCT1); 239CC_MODE (CCT2); 240CC_MODE (CCT3); 241CC_MODE (CCRAW); 242 243CC_MODE (CCVEQ); 244 245CC_MODE (CCVIH); 246CC_MODE (CCVIHU); 247 248CC_MODE (CCVFH); 249CC_MODE (CCVFHE); 250 251CC_MODE (CCVIALL); 252CC_MODE (CCVIANY); 253 254CC_MODE (CCVFALL); 255CC_MODE (CCVFANY); 256 257/* Vector modes. */ 258 259VECTOR_MODES (INT, 2); /* V2QI */ 260VECTOR_MODES (INT, 4); /* V4QI V2HI */ 261VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */ 262VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ 263 264VECTOR_MODE (FLOAT, SF, 2); /* V2SF */ 265VECTOR_MODE (FLOAT, SF, 4); /* V4SF */ 266VECTOR_MODE (FLOAT, DF, 2); /* V2DF */ 267 268VECTOR_MODE (INT, QI, 1); /* V1QI */ 269VECTOR_MODE (INT, HI, 1); /* V1HI */ 270VECTOR_MODE (INT, SI, 1); /* V1SI */ 271VECTOR_MODE (INT, DI, 1); /* V1DI */ 272VECTOR_MODE (INT, TI, 1); /* V1TI */ 273 274VECTOR_MODE (FLOAT, SF, 1); /* V1SF */ 275VECTOR_MODE (FLOAT, DF, 1); /* V1DF */ 276VECTOR_MODE (FLOAT, TF, 1); /* V1TF */ 277