1 /* Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2 2008 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify it under 7 the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 3, or (at your option) any later 9 version. 10 11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 12 WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 for more details. 15 16 Under Section 7 of GPL version 3, you are granted additional 17 permissions described in the GCC Runtime Library Exception, version 18 3.1, as published by the Free Software Foundation. 19 20 You should have received a copy of the GNU General Public License and 21 a copy of the GCC Runtime Library Exception along with this program; 22 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 23 <http://www.gnu.org/licenses/>. */ 24 25 /* Standard register usage. */ 26 27 /* Number of actual hardware registers. 28 The hardware registers are assigned numbers for the compiler 29 from 0 to just below FIRST_PSEUDO_REGISTER. 30 All registers that the compiler knows about must be given numbers, 31 even those that are not normally considered general registers. 32 33 HP-PA 1.0 has 32 fullword registers and 16 floating point 34 registers. The floating point registers hold either word or double 35 word values. 36 37 16 additional registers are reserved. 38 39 HP-PA 1.1 has 32 fullword registers and 32 floating point 40 registers. However, the floating point registers behave 41 differently: the left and right halves of registers are addressable 42 as 32-bit registers. So, we will set things up like the 68k which 43 has different fp units: define separate register sets for the 1.0 44 and 1.1 fp units. */ 45 46 #define FIRST_PSEUDO_REGISTER 89 /* 32 general regs + 56 fp regs + 47 + 1 shift reg */ 48 49 /* 1 for registers that have pervasive standard uses 50 and are not available for the register allocator. 51 52 On the HP-PA, these are: 53 Reg 0 = 0 (hardware). However, 0 is used for condition code, 54 so is not fixed. 55 Reg 1 = ADDIL target/Temporary (hardware). 56 Reg 2 = Return Pointer 57 Reg 3 = Frame Pointer 58 Reg 4 = Frame Pointer (>8k varying frame with HP compilers only) 59 Reg 4-18 = Preserved Registers 60 Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme. 61 Reg 20-22 = Temporary Registers 62 Reg 23-26 = Temporary/Parameter Registers 63 Reg 27 = Global Data Pointer (hp) 64 Reg 28 = Temporary/Return Value register 65 Reg 29 = Temporary/Static Chain/Return Value register #2 66 Reg 30 = stack pointer 67 Reg 31 = Temporary/Millicode Return Pointer (hp) 68 69 Freg 0-3 = Status Registers -- Not known to the compiler. 70 Freg 4-7 = Arguments/Return Value 71 Freg 8-11 = Temporary Registers 72 Freg 12-15 = Preserved Registers 73 74 Freg 16-31 = Reserved 75 76 On the Snake, fp regs are 77 78 Freg 0-3 = Status Registers -- Not known to the compiler. 79 Freg 4L-7R = Arguments/Return Value 80 Freg 8L-11R = Temporary Registers 81 Freg 12L-21R = Preserved Registers 82 Freg 22L-31R = Temporary Registers 83 84 */ 85 86 #define FIXED_REGISTERS \ 87 {0, 0, 0, 0, 0, 0, 0, 0, \ 88 0, 0, 0, 0, 0, 0, 0, 0, \ 89 0, 0, 0, 0, 0, 0, 0, 0, \ 90 0, 0, 0, 1, 0, 0, 1, 0, \ 91 /* fp registers */ \ 92 0, 0, 0, 0, 0, 0, 0, 0, \ 93 0, 0, 0, 0, 0, 0, 0, 0, \ 94 0, 0, 0, 0, 0, 0, 0, 0, \ 95 0, 0, 0, 0, 0, 0, 0, 0, \ 96 0, 0, 0, 0, 0, 0, 0, 0, \ 97 0, 0, 0, 0, 0, 0, 0, 0, \ 98 0, 0, 0, 0, 0, 0, 0, 0, \ 99 0} 100 101 /* 1 for registers not available across function calls. 102 These must include the FIXED_REGISTERS and also any 103 registers that can be used without being saved. 104 The latter must include the registers where values are returned 105 and the register where structure-value addresses are passed. 106 Aside from that, you can include as many other registers as you like. */ 107 #define CALL_USED_REGISTERS \ 108 {1, 1, 1, 0, 0, 0, 0, 0, \ 109 0, 0, 0, 0, 0, 0, 0, 0, \ 110 0, 0, 0, 1, 1, 1, 1, 1, \ 111 1, 1, 1, 1, 1, 1, 1, 1, \ 112 /* fp registers */ \ 113 1, 1, 1, 1, 1, 1, 1, 1, \ 114 1, 1, 1, 1, 1, 1, 1, 1, \ 115 0, 0, 0, 0, 0, 0, 0, 0, \ 116 0, 0, 0, 0, 0, 0, 0, 0, \ 117 0, 0, 0, 0, 1, 1, 1, 1, \ 118 1, 1, 1, 1, 1, 1, 1, 1, \ 119 1, 1, 1, 1, 1, 1, 1, 1, \ 120 1} 121 122 #define CONDITIONAL_REGISTER_USAGE \ 123 { \ 124 int i; \ 125 if (!TARGET_PA_11) \ 126 { \ 127 for (i = 56; i < 88; i++) \ 128 fixed_regs[i] = call_used_regs[i] = 1; \ 129 for (i = 33; i < 88; i += 2) \ 130 fixed_regs[i] = call_used_regs[i] = 1; \ 131 } \ 132 if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\ 133 { \ 134 for (i = 32; i < 88; i++) \ 135 fixed_regs[i] = call_used_regs[i] = 1; \ 136 } \ 137 if (flag_pic) \ 138 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 139 } 140 141 /* Allocate the call used registers first. This should minimize 142 the number of registers that need to be saved (as call used 143 registers will generally not be allocated across a call). 144 145 Experimentation has shown slightly better results by allocating 146 FP registers first. We allocate the caller-saved registers more 147 or less in reverse order to their allocation as arguments. 148 149 FP registers are ordered so that all L registers are selected before 150 R registers. This works around a false dependency interlock on the 151 PA8000 when accessing the high and low parts of an FP register 152 independently. */ 153 154 #define REG_ALLOC_ORDER \ 155 { \ 156 /* caller-saved fp regs. */ \ 157 68, 70, 72, 74, 76, 78, 80, 82, \ 158 84, 86, 40, 42, 44, 46, 38, 36, \ 159 34, 32, \ 160 69, 71, 73, 75, 77, 79, 81, 83, \ 161 85, 87, 41, 43, 45, 47, 39, 37, \ 162 35, 33, \ 163 /* caller-saved general regs. */ \ 164 28, 19, 20, 21, 22, 31, 27, 29, \ 165 23, 24, 25, 26, 2, \ 166 /* callee-saved fp regs. */ \ 167 48, 50, 52, 54, 56, 58, 60, 62, \ 168 64, 66, \ 169 49, 51, 53, 55, 57, 59, 61, 63, \ 170 65, 67, \ 171 /* callee-saved general regs. */ \ 172 3, 4, 5, 6, 7, 8, 9, 10, \ 173 11, 12, 13, 14, 15, 16, 17, 18, \ 174 /* special registers. */ \ 175 1, 30, 0, 88} 176 177 178 /* Return number of consecutive hard regs needed starting at reg REGNO 179 to hold something of mode MODE. 180 This is ordinarily the length in words of a value of mode MODE 181 but can be less for certain modes in special long registers. 182 183 On the HP-PA, general registers are 32 bits wide. The floating 184 point registers are 64 bits wide. Snake fp regs are treated as 185 32 bits wide since the left and right parts are independently 186 accessible. */ 187 #define HARD_REGNO_NREGS(REGNO, MODE) \ 188 (FP_REGNO_P (REGNO) \ 189 ? (!TARGET_PA_11 \ 190 ? COMPLEX_MODE_P (MODE) ? 2 : 1 \ 191 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \ 192 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 193 194 /* There are no instructions that use DImode in PA 1.0, so we only 195 allow it in PA 1.1 and later. */ 196 #define VALID_FP_MODE_P(MODE) \ 197 ((MODE) == SFmode || (MODE) == DFmode \ 198 || (MODE) == SCmode || (MODE) == DCmode \ 199 || (MODE) == SImode || (TARGET_PA_11 && (MODE) == DImode)) 200 201 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 202 203 On the HP-PA, the cpu registers can hold any mode that fits in 32 bits. 204 For the 64-bit modes, we choose a set of non-overlapping general registers 205 that includes the incoming arguments and the return value. We specify a 206 set with no overlaps so that we don't have to specify that the destination 207 register is an early clobber in patterns using this mode. Except for the 208 return value, the starting registers are odd. For 128 and 256 bit modes, 209 we similarly specify non-overlapping sets of cpu registers. However, 210 there aren't any patterns defined for modes larger than 64 bits at the 211 moment. 212 213 We limit the modes allowed in the floating point registers to the 214 set of modes used in the machine definition. In addition, we allow 215 the complex modes SCmode and DCmode. The real and imaginary parts 216 of complex modes are allocated to separate registers. This might 217 allow patterns to be defined in the future to operate on these values. 218 219 The PA 2.0 architecture specifies that quad-precision floating-point 220 values should start on an even floating point register. Thus, we 221 choose non-overlapping sets of registers starting on even register 222 boundaries for large modes. However, there is currently no support 223 in the machine definition for modes larger than 64 bits. TFmode is 224 supported under HP-UX using libcalls. Since TFmode values are passed 225 by reference, they never need to be loaded into the floating-point 226 registers. */ 227 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 228 ((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode \ 229 : (REGNO) == 88 ? SCALAR_INT_MODE_P (MODE) \ 230 : !TARGET_PA_11 && FP_REGNO_P (REGNO) \ 231 ? (VALID_FP_MODE_P (MODE) \ 232 && (GET_MODE_SIZE (MODE) <= 8 \ 233 || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0))) \ 234 : FP_REGNO_P (REGNO) \ 235 ? (VALID_FP_MODE_P (MODE) \ 236 && (GET_MODE_SIZE (MODE) <= 4 \ 237 || (GET_MODE_SIZE (MODE) == 8 && ((REGNO) & 1) == 0) \ 238 || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0) \ 239 || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 7) == 0))) \ 240 : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \ 241 || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD \ 242 && ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28)) \ 243 || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD \ 244 && ((REGNO) & 3) == 3 && (REGNO) <= 23) \ 245 || (GET_MODE_SIZE (MODE) == 8 * UNITS_PER_WORD \ 246 && ((REGNO) & 7) == 3 && (REGNO) <= 19))) 247 248 /* How to renumber registers for dbx and gdb. 249 250 Registers 0 - 31 remain unchanged. 251 252 Registers 32 - 87 are mapped to 72 - 127 253 254 Register 88 is mapped to 32. */ 255 256 #define DBX_REGISTER_NUMBER(REGNO) \ 257 ((REGNO) <= 31 ? (REGNO) : \ 258 ((REGNO) <= 87 ? (REGNO) + 40 : 32)) 259 260 /* We must not use the DBX register numbers for the DWARF 2 CFA column 261 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. 262 Instead use the identity mapping. */ 263 #define DWARF_FRAME_REGNUM(REG) REG 264 265 /* Define the classes of registers for register constraints in the 266 machine description. Also define ranges of constants. 267 268 One of the classes must always be named ALL_REGS and include all hard regs. 269 If there is more than one class, another class must be named NO_REGS 270 and contain no registers. 271 272 The name GENERAL_REGS must be the name of a class (or an alias for 273 another name such as ALL_REGS). This is the class of registers 274 that is allowed by "g" or "r" in a register constraint. 275 Also, registers outside this class are allocated only when 276 instructions express preferences for them. 277 278 The classes must be numbered in nondecreasing order; that is, 279 a larger-numbered class must never be contained completely 280 in a smaller-numbered class. 281 282 For any two classes, it is very desirable that there be another 283 class that represents their union. */ 284 285 /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs, 286 1.1 fp regs, and the high 1.1 fp regs, to which the operands of 287 fmpyadd and fmpysub are restricted. */ 288 289 enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, 290 GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES}; 291 292 #define N_REG_CLASSES (int) LIM_REG_CLASSES 293 294 /* Give names of register classes as strings for dump file. */ 295 296 #define REG_CLASS_NAMES \ 297 {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \ 298 "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"} 299 300 /* Define which registers fit in which classes. 301 This is an initializer for a vector of HARD_REG_SET 302 of length N_REG_CLASSES. Register 0, the "condition code" register, 303 is in no class. */ 304 305 #define REG_CLASS_CONTENTS \ 306 {{0x00000000, 0x00000000, 0x00000000}, /* NO_REGS */ \ 307 {0x00000002, 0x00000000, 0x00000000}, /* R1_REGS */ \ 308 {0xfffffffe, 0x00000000, 0x00000000}, /* GENERAL_REGS */ \ 309 {0x00000000, 0xff000000, 0x00ffffff}, /* FPUPPER_REGS */ \ 310 {0x00000000, 0xffffffff, 0x00ffffff}, /* FP_REGS */ \ 311 {0xfffffffe, 0xffffffff, 0x00ffffff}, /* GENERAL_OR_FP_REGS */ \ 312 {0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \ 313 {0xfffffffe, 0xffffffff, 0x01ffffff}} /* ALL_REGS */ 314 315 /* The following macro defines cover classes for Integrated Register 316 Allocator. Cover classes is a set of non-intersected register 317 classes covering all hard registers used for register allocation 318 purpose. Any move between two registers of a cover class should be 319 cheaper than load or store of the registers. The macro value is 320 array of register classes with LIM_REG_CLASSES used as the end 321 marker. */ 322 323 #define IRA_COVER_CLASSES \ 324 { \ 325 GENERAL_REGS, FP_REGS, SHIFT_REGS, LIM_REG_CLASSES \ 326 } 327 328 /* Defines invalid mode changes. */ 329 330 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 331 pa_cannot_change_mode_class (FROM, TO, CLASS) 332 333 /* Return the class number of the smallest class containing 334 reg number REGNO. This could be a conditional expression 335 or could index an array. */ 336 337 #define REGNO_REG_CLASS(REGNO) \ 338 ((REGNO) == 0 ? NO_REGS \ 339 : (REGNO) == 1 ? R1_REGS \ 340 : (REGNO) < 32 ? GENERAL_REGS \ 341 : (REGNO) < 56 ? FP_REGS \ 342 : (REGNO) < 88 ? FPUPPER_REGS \ 343 : SHIFT_REGS) 344 345 /* Return the maximum number of consecutive registers 346 needed to represent mode MODE in a register of class CLASS. */ 347 #define CLASS_MAX_NREGS(CLASS, MODE) \ 348 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS \ 349 ? (!TARGET_PA_11 \ 350 ? COMPLEX_MODE_P (MODE) ? 2 : 1 \ 351 : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \ 352 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 353 354 /* 1 if N is a possible register number for function argument passing. */ 355 356 #define FUNCTION_ARG_REGNO_P(N) \ 357 (((N) >= 23 && (N) <= 26) || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39)) 358 359 /* How to refer to registers in assembler output. 360 This sequence is indexed by compiler's hard-register-number (see above). */ 361 362 #define REGISTER_NAMES \ 363 {"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ 364 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ 365 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \ 366 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \ 367 "%fr4", "%fr4R", "%fr5", "%fr5R", "%fr6", "%fr6R", "%fr7", "%fr7R", \ 368 "%fr8", "%fr8R", "%fr9", "%fr9R", "%fr10", "%fr10R", "%fr11", "%fr11R", \ 369 "%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R", \ 370 "%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R", \ 371 "%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R", \ 372 "%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R", \ 373 "%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R", \ 374 "SAR"} 375 376 #define ADDITIONAL_REGISTER_NAMES \ 377 {{"%fr4L",32}, {"%fr5L",34}, {"%fr6L",36}, {"%fr7L",38}, \ 378 {"%fr8L",40}, {"%fr9L",42}, {"%fr10L",44}, {"%fr11L",46}, \ 379 {"%fr12L",48}, {"%fr13L",50}, {"%fr14L",52}, {"%fr15L",54}, \ 380 {"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62}, \ 381 {"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70}, \ 382 {"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78}, \ 383 {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86}, \ 384 {"%cr11",88}} 385 386 #define FP_SAVED_REG_LAST 66 387 #define FP_SAVED_REG_FIRST 48 388 #define FP_REG_STEP 2 389 #define FP_REG_FIRST 32 390 #define FP_REG_LAST 87 391