1;; Machine Description for MIPS MSA ASE 2;; Based on the MIPS MSA spec Revision 1.11 8/4/2014 3;; 4;; Copyright (C) 2015-2020 Free Software Foundation, Inc. 5;; 6;; This file is part of GCC. 7;; 8;; GCC is free software; you can redistribute it and/or modify 9;; it under the terms of the GNU General Public License as published by 10;; the Free Software Foundation; either version 3, or (at your option) 11;; any later version. 12;; 13;; GCC is distributed in the hope that it will be useful, 14;; but WITHOUT ANY WARRANTY; without even the implied warranty of 15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16;; GNU General Public License for more details. 17;; 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING3. If not see 20;; <http://www.gnu.org/licenses/>. 21;; 22 23(define_c_enum "unspec" [ 24 UNSPEC_MSA_ASUB_S 25 UNSPEC_MSA_ASUB_U 26 UNSPEC_MSA_AVE_S 27 UNSPEC_MSA_AVE_U 28 UNSPEC_MSA_AVER_S 29 UNSPEC_MSA_AVER_U 30 UNSPEC_MSA_BCLR 31 UNSPEC_MSA_BCLRI 32 UNSPEC_MSA_BINSL 33 UNSPEC_MSA_BINSLI 34 UNSPEC_MSA_BINSR 35 UNSPEC_MSA_BINSRI 36 UNSPEC_MSA_BNEG 37 UNSPEC_MSA_BNEGI 38 UNSPEC_MSA_BSET 39 UNSPEC_MSA_BSETI 40 UNSPEC_MSA_BRANCH_V 41 UNSPEC_MSA_BRANCH 42 UNSPEC_MSA_CFCMSA 43 UNSPEC_MSA_CTCMSA 44 UNSPEC_MSA_FCAF 45 UNSPEC_MSA_FCLASS 46 UNSPEC_MSA_FCUNE 47 UNSPEC_MSA_FEXDO 48 UNSPEC_MSA_FEXP2 49 UNSPEC_MSA_FEXUPL 50 UNSPEC_MSA_FEXUPR 51 UNSPEC_MSA_FFQL 52 UNSPEC_MSA_FFQR 53 UNSPEC_MSA_FLOG2 54 UNSPEC_MSA_FRCP 55 UNSPEC_MSA_FRINT 56 UNSPEC_MSA_FRSQRT 57 UNSPEC_MSA_FSAF 58 UNSPEC_MSA_FSEQ 59 UNSPEC_MSA_FSLE 60 UNSPEC_MSA_FSLT 61 UNSPEC_MSA_FSNE 62 UNSPEC_MSA_FSOR 63 UNSPEC_MSA_FSUEQ 64 UNSPEC_MSA_FSULE 65 UNSPEC_MSA_FSULT 66 UNSPEC_MSA_FSUN 67 UNSPEC_MSA_FSUNE 68 UNSPEC_MSA_FTINT_S 69 UNSPEC_MSA_FTINT_U 70 UNSPEC_MSA_FTQ 71 UNSPEC_MSA_MADD_Q 72 UNSPEC_MSA_MADDR_Q 73 UNSPEC_MSA_MSUB_Q 74 UNSPEC_MSA_MSUBR_Q 75 UNSPEC_MSA_MUL_Q 76 UNSPEC_MSA_MULR_Q 77 UNSPEC_MSA_NLOC 78 UNSPEC_MSA_SAT_S 79 UNSPEC_MSA_SAT_U 80 UNSPEC_MSA_SLD 81 UNSPEC_MSA_SLDI 82 UNSPEC_MSA_SPLAT 83 UNSPEC_MSA_SPLATI 84 UNSPEC_MSA_SRAR 85 UNSPEC_MSA_SRARI 86 UNSPEC_MSA_SRLR 87 UNSPEC_MSA_SRLRI 88 UNSPEC_MSA_SUBS_S 89 UNSPEC_MSA_SUBS_U 90 UNSPEC_MSA_SUBSUU_S 91 UNSPEC_MSA_SUBSUS_U 92 UNSPEC_MSA_VSHF 93]) 94 95;; All vector modes with 128 bits. 96(define_mode_iterator MSA [V2DF V4SF V2DI V4SI V8HI V16QI]) 97 98;; Same as MSA. Used by vcond to iterate two modes. 99(define_mode_iterator MSA_2 [V2DF V4SF V2DI V4SI V8HI V16QI]) 100 101;; Only used for splitting insert_d and copy_{u,s}.d. 102(define_mode_iterator MSA_D [V2DI V2DF]) 103 104;; Only used for copy_{u,s}.w. 105(define_mode_iterator MSA_W [V4SI V4SF]) 106 107;; Only integer modes. 108(define_mode_iterator IMSA [V2DI V4SI V8HI V16QI]) 109 110;; As IMSA but excludes V16QI. 111(define_mode_iterator IMSA_DWH [V2DI V4SI V8HI]) 112 113;; As IMSA but excludes V2DI. 114(define_mode_iterator IMSA_WHB [V4SI V8HI V16QI]) 115 116;; Only integer modes equal or larger than a word. 117(define_mode_iterator IMSA_DW [V2DI V4SI]) 118 119;; Only integer modes smaller than a word. 120(define_mode_iterator IMSA_HB [V8HI V16QI]) 121 122;; Only integer modes for fixed-point madd_q/maddr_q. 123(define_mode_iterator IMSA_WH [V4SI V8HI]) 124 125;; Only floating-point modes. 126(define_mode_iterator FMSA [V2DF V4SF]) 127 128;; Only used for immediate set shuffle elements instruction. 129(define_mode_iterator MSA_WHB_W [V4SI V8HI V16QI V4SF]) 130 131;; The attribute gives the integer vector mode with same size. 132(define_mode_attr VIMODE 133 [(V2DF "V2DI") 134 (V4SF "V4SI") 135 (V2DI "V2DI") 136 (V4SI "V4SI") 137 (V8HI "V8HI") 138 (V16QI "V16QI")]) 139 140;; The attribute gives half modes for vector modes. 141(define_mode_attr VHMODE 142 [(V8HI "V16QI") 143 (V4SI "V8HI") 144 (V2DI "V4SI")]) 145 146;; The attribute gives double modes for vector modes. 147(define_mode_attr VDMODE 148 [(V4SI "V2DI") 149 (V8HI "V4SI") 150 (V16QI "V8HI")]) 151 152;; The attribute gives half modes with same number of elements for vector modes. 153(define_mode_attr VTRUNCMODE 154 [(V8HI "V8QI") 155 (V4SI "V4HI") 156 (V2DI "V2SI")]) 157 158;; This attribute gives the mode of the result for "copy_s_b, copy_u_b" etc. 159(define_mode_attr VRES 160 [(V2DF "DF") 161 (V4SF "SF") 162 (V2DI "DI") 163 (V4SI "SI") 164 (V8HI "SI") 165 (V16QI "SI")]) 166 167;; Only used with MSA_D iterator. 168(define_mode_attr msa_d 169 [(V2DI "reg_or_0") 170 (V2DF "register")]) 171 172;; This attribute gives the integer vector mode with same size. 173(define_mode_attr mode_i 174 [(V2DF "v2di") 175 (V4SF "v4si") 176 (V2DI "v2di") 177 (V4SI "v4si") 178 (V8HI "v8hi") 179 (V16QI "v16qi")]) 180 181;; This attribute gives suffix for MSA instructions. 182(define_mode_attr msafmt 183 [(V2DF "d") 184 (V4SF "w") 185 (V2DI "d") 186 (V4SI "w") 187 (V8HI "h") 188 (V16QI "b")]) 189 190;; This attribute gives suffix for integers in VHMODE. 191(define_mode_attr hmsafmt 192 [(V2DI "w") 193 (V4SI "h") 194 (V8HI "b")]) 195 196;; This attribute gives define_insn suffix for MSA instructions that need 197;; distinction between integer and floating point. 198(define_mode_attr msafmt_f 199 [(V2DF "d_f") 200 (V4SF "w_f") 201 (V2DI "d") 202 (V4SI "w") 203 (V8HI "h") 204 (V16QI "b")]) 205 206;; This is used to form an immediate operand constraint using 207;; "const_<indeximm>_operand". 208(define_mode_attr indeximm 209 [(V2DF "0_or_1") 210 (V4SF "0_to_3") 211 (V2DI "0_or_1") 212 (V4SI "0_to_3") 213 (V8HI "uimm3") 214 (V16QI "uimm4")]) 215 216;; This attribute represents bitmask needed for vec_merge using 217;; "const_<bitmask>_operand". 218(define_mode_attr bitmask 219 [(V2DF "exp_2") 220 (V4SF "exp_4") 221 (V2DI "exp_2") 222 (V4SI "exp_4") 223 (V8HI "exp_8") 224 (V16QI "exp_16")]) 225 226;; This attribute is used to form an immediate operand constraint using 227;; "const_<bitimm>_operand". 228(define_mode_attr bitimm 229 [(V16QI "uimm3") 230 (V8HI "uimm4") 231 (V4SI "uimm5") 232 (V2DI "uimm6")]) 233 234(define_expand "vec_init<mode><unitmode>" 235 [(match_operand:MSA 0 "register_operand") 236 (match_operand:MSA 1 "")] 237 "ISA_HAS_MSA" 238{ 239 mips_expand_vector_init (operands[0], operands[1]); 240 DONE; 241}) 242 243;; pckev pattern with implicit type conversion. 244(define_insn "vec_pack_trunc_<mode>" 245 [(set (match_operand:<VHMODE> 0 "register_operand" "=f") 246 (vec_concat:<VHMODE> 247 (truncate:<VTRUNCMODE> 248 (match_operand:IMSA_DWH 1 "register_operand" "f")) 249 (truncate:<VTRUNCMODE> 250 (match_operand:IMSA_DWH 2 "register_operand" "f"))))] 251 "ISA_HAS_MSA" 252 "pckev.<hmsafmt>\t%w0,%w2,%w1" 253 [(set_attr "type" "simd_permute") 254 (set_attr "mode" "<MODE>")]) 255 256(define_expand "vec_unpacks_hi_v4sf" 257 [(set (match_operand:V2DF 0 "register_operand" "=f") 258 (float_extend:V2DF 259 (vec_select:V2SF 260 (match_operand:V4SF 1 "register_operand" "f") 261 (match_dup 2))))] 262 "ISA_HAS_MSA" 263{ 264 operands[2] = mips_msa_vec_parallel_const_half (V4SFmode, true/*high_p*/); 265}) 266 267(define_expand "vec_unpacks_lo_v4sf" 268 [(set (match_operand:V2DF 0 "register_operand" "=f") 269 (float_extend:V2DF 270 (vec_select:V2SF 271 (match_operand:V4SF 1 "register_operand" "f") 272 (match_dup 2))))] 273 "ISA_HAS_MSA" 274{ 275 operands[2] = mips_msa_vec_parallel_const_half (V4SFmode, false/*high_p*/); 276}) 277 278(define_expand "vec_unpacks_hi_<mode>" 279 [(match_operand:<VDMODE> 0 "register_operand") 280 (match_operand:IMSA_WHB 1 "register_operand")] 281 "ISA_HAS_MSA" 282{ 283 mips_expand_vec_unpack (operands, false/*unsigned_p*/, true/*high_p*/); 284 DONE; 285}) 286 287(define_expand "vec_unpacks_lo_<mode>" 288 [(match_operand:<VDMODE> 0 "register_operand") 289 (match_operand:IMSA_WHB 1 "register_operand")] 290 "ISA_HAS_MSA" 291{ 292 mips_expand_vec_unpack (operands, false/*unsigned_p*/, false/*high_p*/); 293 DONE; 294}) 295 296(define_expand "vec_unpacku_hi_<mode>" 297 [(match_operand:<VDMODE> 0 "register_operand") 298 (match_operand:IMSA_WHB 1 "register_operand")] 299 "ISA_HAS_MSA" 300{ 301 mips_expand_vec_unpack (operands, true/*unsigned_p*/, true/*high_p*/); 302 DONE; 303}) 304 305(define_expand "vec_unpacku_lo_<mode>" 306 [(match_operand:<VDMODE> 0 "register_operand") 307 (match_operand:IMSA_WHB 1 "register_operand")] 308 "ISA_HAS_MSA" 309{ 310 mips_expand_vec_unpack (operands, true/*unsigned_p*/, false/*high_p*/); 311 DONE; 312}) 313 314(define_expand "vec_extract<mode><unitmode>" 315 [(match_operand:<UNITMODE> 0 "register_operand") 316 (match_operand:IMSA 1 "register_operand") 317 (match_operand 2 "const_<indeximm>_operand")] 318 "ISA_HAS_MSA" 319{ 320 if (<UNITMODE>mode == QImode || <UNITMODE>mode == HImode) 321 { 322 rtx dest1 = gen_reg_rtx (SImode); 323 emit_insn (gen_msa_copy_s_<msafmt> (dest1, operands[1], operands[2])); 324 emit_move_insn (operands[0], 325 gen_lowpart (<UNITMODE>mode, dest1)); 326 } 327 else 328 emit_insn (gen_msa_copy_s_<msafmt> (operands[0], operands[1], operands[2])); 329 DONE; 330}) 331 332(define_expand "vec_extract<mode><unitmode>" 333 [(match_operand:<UNITMODE> 0 "register_operand") 334 (match_operand:FMSA 1 "register_operand") 335 (match_operand 2 "const_<indeximm>_operand")] 336 "ISA_HAS_MSA" 337{ 338 rtx temp; 339 HOST_WIDE_INT val = INTVAL (operands[2]); 340 341 if (val == 0) 342 temp = operands[1]; 343 else 344 { 345 /* We need to do the SLDI operation in V16QImode and adjust 346 operands[2] accordingly. */ 347 rtx wd = gen_reg_rtx (V16QImode); 348 rtx ws = gen_reg_rtx (V16QImode); 349 emit_move_insn (ws, gen_lowpart (V16QImode, operands[1])); 350 rtx n = GEN_INT (val * GET_MODE_SIZE (<UNITMODE>mode)); 351 gcc_assert (INTVAL (n) < GET_MODE_NUNITS (V16QImode)); 352 emit_insn (gen_msa_sldi_b (wd, ws, ws, n)); 353 temp = gen_reg_rtx (<MODE>mode); 354 emit_move_insn (temp, gen_lowpart (<MODE>mode, wd)); 355 } 356 emit_insn (gen_msa_vec_extract_<msafmt_f> (operands[0], temp)); 357 DONE; 358}) 359 360(define_insn_and_split "msa_vec_extract_<msafmt_f>" 361 [(set (match_operand:<UNITMODE> 0 "register_operand" "=f") 362 (vec_select:<UNITMODE> 363 (match_operand:FMSA 1 "register_operand" "f") 364 (parallel [(const_int 0)])))] 365 "ISA_HAS_MSA" 366 "#" 367 "&& reload_completed" 368 [(set (match_dup 0) (match_dup 1))] 369{ 370 /* An MSA register cannot be reinterpreted as a single precision 371 register when using -mno-odd-spreg and the MSA register is 372 an odd number. */ 373 if (<UNITMODE>mode == SFmode && !TARGET_ODD_SPREG 374 && (REGNO (operands[1]) & 1)) 375 { 376 emit_move_insn (gen_rtx_REG (<MODE>mode, REGNO (operands[0])), 377 operands[1]); 378 operands[1] = operands[0]; 379 } 380 else 381 operands[1] = gen_rtx_REG (<UNITMODE>mode, REGNO (operands[1])); 382} 383 [(set_attr "move_type" "fmove") 384 (set_attr "mode" "<UNITMODE>")]) 385 386(define_expand "vec_set<mode>" 387 [(match_operand:IMSA 0 "register_operand") 388 (match_operand:<UNITMODE> 1 "reg_or_0_operand") 389 (match_operand 2 "const_<indeximm>_operand")] 390 "ISA_HAS_MSA" 391{ 392 rtx index = GEN_INT (1 << INTVAL (operands[2])); 393 emit_insn (gen_msa_insert_<msafmt> (operands[0], operands[1], 394 operands[0], index)); 395 DONE; 396}) 397 398(define_expand "vec_set<mode>" 399 [(match_operand:FMSA 0 "register_operand") 400 (match_operand:<UNITMODE> 1 "register_operand") 401 (match_operand 2 "const_<indeximm>_operand")] 402 "ISA_HAS_MSA" 403{ 404 rtx index = GEN_INT (1 << INTVAL (operands[2])); 405 emit_insn (gen_msa_insve_<msafmt_f>_scalar (operands[0], operands[1], 406 operands[0], index)); 407 DONE; 408}) 409 410(define_expand "vcondu<MSA:mode><IMSA:mode>" 411 [(match_operand:MSA 0 "register_operand") 412 (match_operand:MSA 1 "reg_or_m1_operand") 413 (match_operand:MSA 2 "reg_or_0_operand") 414 (match_operator 3 "" 415 [(match_operand:IMSA 4 "register_operand") 416 (match_operand:IMSA 5 "register_operand")])] 417 "ISA_HAS_MSA 418 && (GET_MODE_NUNITS (<MSA:MODE>mode) == GET_MODE_NUNITS (<IMSA:MODE>mode))" 419{ 420 mips_expand_vec_cond_expr (<MSA:MODE>mode, <MSA:VIMODE>mode, operands); 421 DONE; 422}) 423 424(define_expand "vcond<MSA:mode><MSA_2:mode>" 425 [(match_operand:MSA 0 "register_operand") 426 (match_operand:MSA 1 "reg_or_m1_operand") 427 (match_operand:MSA 2 "reg_or_0_operand") 428 (match_operator 3 "" 429 [(match_operand:MSA_2 4 "register_operand") 430 (match_operand:MSA_2 5 "register_operand")])] 431 "ISA_HAS_MSA 432 && (GET_MODE_NUNITS (<MSA:MODE>mode) == GET_MODE_NUNITS (<MSA_2:MODE>mode))" 433{ 434 mips_expand_vec_cond_expr (<MSA:MODE>mode, <MSA:VIMODE>mode, operands); 435 DONE; 436}) 437 438(define_insn "msa_insert_<msafmt_f>" 439 [(set (match_operand:MSA 0 "register_operand" "=f,f") 440 (vec_merge:MSA 441 (vec_duplicate:MSA 442 (match_operand:<UNITMODE> 1 "reg_or_0_operand" "dJ,f")) 443 (match_operand:MSA 2 "register_operand" "0,0") 444 (match_operand 3 "const_<bitmask>_operand" "")))] 445 "ISA_HAS_MSA" 446{ 447 if (which_alternative == 1) 448 return "insve.<msafmt>\t%w0[%y3],%w1[0]"; 449 450 if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode)) 451 return "#"; 452 else 453 return "insert.<msafmt>\t%w0[%y3],%z1"; 454} 455 [(set_attr "type" "simd_insert") 456 (set_attr "mode" "<MODE>")]) 457 458(define_split 459 [(set (match_operand:MSA_D 0 "register_operand") 460 (vec_merge:MSA_D 461 (vec_duplicate:MSA_D 462 (match_operand:<UNITMODE> 1 "<MSA_D:msa_d>_operand")) 463 (match_operand:MSA_D 2 "register_operand") 464 (match_operand 3 "const_<bitmask>_operand")))] 465 "reload_completed && ISA_HAS_MSA && !TARGET_64BIT" 466 [(const_int 0)] 467{ 468 if (REG_P (operands[1]) && FP_REG_P (REGNO (operands[1]))) 469 FAIL; 470 mips_split_msa_insert_d (operands[0], operands[2], operands[3], operands[1]); 471 DONE; 472}) 473 474(define_insn "msa_insve_<msafmt_f>" 475 [(set (match_operand:MSA 0 "register_operand" "=f") 476 (vec_merge:MSA 477 (vec_duplicate:MSA 478 (vec_select:<UNITMODE> 479 (match_operand:MSA 1 "register_operand" "f") 480 (parallel [(const_int 0)]))) 481 (match_operand:MSA 2 "register_operand" "0") 482 (match_operand 3 "const_<bitmask>_operand" "")))] 483 "ISA_HAS_MSA" 484 "insve.<msafmt>\t%w0[%y3],%w1[0]" 485 [(set_attr "type" "simd_insert") 486 (set_attr "mode" "<MODE>")]) 487 488;; Operand 3 is a scalar. 489(define_insn "msa_insve_<msafmt_f>_scalar" 490 [(set (match_operand:FMSA 0 "register_operand" "=f") 491 (vec_merge:FMSA 492 (vec_duplicate:FMSA 493 (match_operand:<UNITMODE> 1 "register_operand" "f")) 494 (match_operand:FMSA 2 "register_operand" "0") 495 (match_operand 3 "const_<bitmask>_operand" "")))] 496 "ISA_HAS_MSA" 497 "insve.<msafmt>\t%w0[%y3],%w1[0]" 498 [(set_attr "type" "simd_insert") 499 (set_attr "mode" "<MODE>")]) 500 501(define_insn "msa_copy_<su>_<msafmt>" 502 [(set (match_operand:<VRES> 0 "register_operand" "=d") 503 (any_extend:<VRES> 504 (vec_select:<UNITMODE> 505 (match_operand:IMSA_HB 1 "register_operand" "f") 506 (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))] 507 "ISA_HAS_MSA" 508 "copy_<su>.<msafmt>\t%0,%w1[%2]" 509 [(set_attr "type" "simd_copy") 510 (set_attr "mode" "<MODE>")]) 511 512(define_insn "msa_copy_u_w" 513 [(set (match_operand:DI 0 "register_operand" "=d") 514 (zero_extend:DI 515 (vec_select:SI 516 (match_operand:V4SI 1 "register_operand" "f") 517 (parallel [(match_operand 2 "const_0_to_3_operand" "")]))))] 518 "ISA_HAS_MSA && TARGET_64BIT" 519 "copy_u.w\t%0,%w1[%2]" 520 [(set_attr "type" "simd_copy") 521 (set_attr "mode" "V4SI")]) 522 523(define_insn "msa_copy_s_<msafmt_f>_64bit" 524 [(set (match_operand:DI 0 "register_operand" "=d") 525 (sign_extend:DI 526 (vec_select:<UNITMODE> 527 (match_operand:MSA_W 1 "register_operand" "f") 528 (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))] 529 "ISA_HAS_MSA && TARGET_64BIT" 530 "copy_s.<msafmt>\t%0,%w1[%2]" 531 [(set_attr "type" "simd_copy") 532 (set_attr "mode" "<MODE>")]) 533 534(define_insn "msa_copy_s_<msafmt_f>" 535 [(set (match_operand:<UNITMODE> 0 "register_operand" "=d") 536 (vec_select:<UNITMODE> 537 (match_operand:MSA_W 1 "register_operand" "f") 538 (parallel [(match_operand 2 "const_<indeximm>_operand" "")])))] 539 "ISA_HAS_MSA" 540 "copy_s.<msafmt>\t%0,%w1[%2]" 541 [(set_attr "type" "simd_copy") 542 (set_attr "mode" "<MODE>")]) 543 544(define_insn_and_split "msa_copy_s_<msafmt_f>" 545 [(set (match_operand:<UNITMODE> 0 "register_operand" "=d") 546 (vec_select:<UNITMODE> 547 (match_operand:MSA_D 1 "register_operand" "f") 548 (parallel [(match_operand 2 "const_<indeximm>_operand" "")])))] 549 "ISA_HAS_MSA" 550{ 551 if (TARGET_64BIT) 552 return "copy_s.<msafmt>\t%0,%w1[%2]"; 553 else 554 return "#"; 555} 556 "reload_completed && ISA_HAS_MSA && !TARGET_64BIT" 557 [(const_int 0)] 558{ 559 mips_split_msa_copy_d (operands[0], operands[1], operands[2], 560 gen_msa_copy_s_w); 561 DONE; 562} 563 [(set_attr "type" "simd_copy") 564 (set_attr "mode" "<MODE>")]) 565 566(define_expand "abs<mode>2" 567 [(match_operand:IMSA 0 "register_operand" "=f") 568 (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))] 569 "ISA_HAS_MSA" 570{ 571 rtx reg = gen_reg_rtx (<MODE>mode); 572 emit_move_insn (reg, CONST0_RTX (<MODE>mode)); 573 emit_insn (gen_msa_add_a_<msafmt> (operands[0], operands[1], reg)); 574 DONE; 575}) 576 577(define_expand "neg<mode>2" 578 [(set (match_operand:MSA 0 "register_operand") 579 (minus:MSA (match_dup 2) 580 (match_operand:MSA 1 "register_operand")))] 581 "ISA_HAS_MSA" 582{ 583 rtx reg = gen_reg_rtx (<MODE>mode); 584 emit_move_insn (reg, CONST0_RTX (<MODE>mode)); 585 operands[2] = reg; 586}) 587 588(define_expand "msa_ldi<mode>" 589 [(match_operand:IMSA 0 "register_operand") 590 (match_operand 1 "const_imm10_operand")] 591 "ISA_HAS_MSA" 592{ 593 if (<MODE>mode == V16QImode) 594 operands[1] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]), 595 <UNITMODE>mode)); 596 emit_move_insn (operands[0], 597 mips_gen_const_int_vector (<MODE>mode, INTVAL (operands[1]))); 598 DONE; 599}) 600 601(define_insn "vec_perm<mode>" 602 [(set (match_operand:MSA 0 "register_operand" "=f") 603 (unspec:MSA [(match_operand:MSA 1 "register_operand" "f") 604 (match_operand:MSA 2 "register_operand" "f") 605 (match_operand:<VIMODE> 3 "register_operand" "0")] 606 UNSPEC_MSA_VSHF))] 607 "ISA_HAS_MSA" 608 "vshf.<msafmt>\t%w0,%w2,%w1" 609 [(set_attr "type" "simd_sld") 610 (set_attr "mode" "<MODE>")]) 611 612(define_expand "mov<mode>" 613 [(set (match_operand:MSA 0) 614 (match_operand:MSA 1))] 615 "ISA_HAS_MSA" 616{ 617 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1])) 618 DONE; 619}) 620 621(define_expand "movmisalign<mode>" 622 [(set (match_operand:MSA 0) 623 (match_operand:MSA 1))] 624 "ISA_HAS_MSA" 625{ 626 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1])) 627 DONE; 628}) 629 630;; 128-bit MSA modes can only exist in MSA registers or memory. An exception 631;; is allowing MSA modes for GP registers for arguments and return values. 632(define_insn "mov<mode>_msa" 633 [(set (match_operand:MSA 0 "nonimmediate_operand" "=f,f,R,*d,*f") 634 (match_operand:MSA 1 "move_operand" "fYGYI,R,f,*f,*d"))] 635 "ISA_HAS_MSA" 636 { return mips_output_move (operands[0], operands[1]); } 637 [(set_attr "type" "simd_move,simd_load,simd_store,simd_copy,simd_insert") 638 (set_attr "mode" "<MODE>")]) 639 640(define_split 641 [(set (match_operand:MSA 0 "nonimmediate_operand") 642 (match_operand:MSA 1 "move_operand"))] 643 "reload_completed && ISA_HAS_MSA 644 && mips_split_move_insn_p (operands[0], operands[1], insn)" 645 [(const_int 0)] 646{ 647 mips_split_move_insn (operands[0], operands[1], curr_insn); 648 DONE; 649}) 650 651;; Offset load 652(define_expand "msa_ld_<msafmt_f>" 653 [(match_operand:MSA 0 "register_operand") 654 (match_operand 1 "pmode_register_operand") 655 (match_operand 2 "aq10<msafmt>_operand")] 656 "ISA_HAS_MSA" 657{ 658 rtx addr = plus_constant (GET_MODE (operands[1]), operands[1], 659 INTVAL (operands[2])); 660 mips_emit_move (operands[0], gen_rtx_MEM (<MODE>mode, addr)); 661 DONE; 662}) 663 664;; Offset store 665(define_expand "msa_st_<msafmt_f>" 666 [(match_operand:MSA 0 "register_operand") 667 (match_operand 1 "pmode_register_operand") 668 (match_operand 2 "aq10<msafmt>_operand")] 669 "ISA_HAS_MSA" 670{ 671 rtx addr = plus_constant (GET_MODE (operands[1]), operands[1], 672 INTVAL (operands[2])); 673 mips_emit_move (gen_rtx_MEM (<MODE>mode, addr), operands[0]); 674 DONE; 675}) 676 677;; Integer operations 678(define_insn "add<mode>3" 679 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f") 680 (plus:IMSA 681 (match_operand:IMSA 1 "register_operand" "f,f,f") 682 (match_operand:IMSA 2 "reg_or_vector_same_ximm5_operand" "f,Unv5,Uuv5")))] 683 "ISA_HAS_MSA" 684{ 685 switch (which_alternative) 686 { 687 case 0: 688 return "addv.<msafmt>\t%w0,%w1,%w2"; 689 case 1: 690 { 691 HOST_WIDE_INT val = INTVAL (CONST_VECTOR_ELT (operands[2], 0)); 692 693 operands[2] = GEN_INT (-val); 694 return "subvi.<msafmt>\t%w0,%w1,%d2"; 695 } 696 case 2: 697 return "addvi.<msafmt>\t%w0,%w1,%E2"; 698 default: 699 gcc_unreachable (); 700 } 701} 702 [(set_attr "alu_type" "simd_add") 703 (set_attr "type" "simd_int_arith") 704 (set_attr "mode" "<MODE>")]) 705 706(define_insn "sub<mode>3" 707 [(set (match_operand:IMSA 0 "register_operand" "=f,f") 708 (minus:IMSA 709 (match_operand:IMSA 1 "register_operand" "f,f") 710 (match_operand:IMSA 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))] 711 "ISA_HAS_MSA" 712 "@ 713 subv.<msafmt>\t%w0,%w1,%w2 714 subvi.<msafmt>\t%w0,%w1,%E2" 715 [(set_attr "alu_type" "simd_add") 716 (set_attr "type" "simd_int_arith") 717 (set_attr "mode" "<MODE>")]) 718 719(define_insn "mul<mode>3" 720 [(set (match_operand:IMSA 0 "register_operand" "=f") 721 (mult:IMSA (match_operand:IMSA 1 "register_operand" "f") 722 (match_operand:IMSA 2 "register_operand" "f")))] 723 "ISA_HAS_MSA" 724 "mulv.<msafmt>\t%w0,%w1,%w2" 725 [(set_attr "type" "simd_mul") 726 (set_attr "mode" "<MODE>")]) 727 728(define_insn "msa_maddv_<msafmt>" 729 [(set (match_operand:IMSA 0 "register_operand" "=f") 730 (plus:IMSA (mult:IMSA (match_operand:IMSA 1 "register_operand" "f") 731 (match_operand:IMSA 2 "register_operand" "f")) 732 (match_operand:IMSA 3 "register_operand" "0")))] 733 "ISA_HAS_MSA" 734 "maddv.<msafmt>\t%w0,%w1,%w2" 735 [(set_attr "type" "simd_mul") 736 (set_attr "mode" "<MODE>")]) 737 738(define_insn "msa_msubv_<msafmt>" 739 [(set (match_operand:IMSA 0 "register_operand" "=f") 740 (minus:IMSA (match_operand:IMSA 1 "register_operand" "0") 741 (mult:IMSA (match_operand:IMSA 2 "register_operand" "f") 742 (match_operand:IMSA 3 "register_operand" "f"))))] 743 "ISA_HAS_MSA" 744 "msubv.<msafmt>\t%w0,%w2,%w3" 745 [(set_attr "type" "simd_mul") 746 (set_attr "mode" "<MODE>")]) 747 748(define_insn "div<mode>3" 749 [(set (match_operand:IMSA 0 "register_operand" "=f") 750 (div:IMSA (match_operand:IMSA 1 "register_operand" "f") 751 (match_operand:IMSA 2 "register_operand" "f")))] 752 "ISA_HAS_MSA" 753 { return mips_msa_output_division ("div_s.<msafmt>\t%w0,%w1,%w2", operands); } 754 [(set_attr "type" "simd_div") 755 (set_attr "mode" "<MODE>")]) 756 757(define_insn "udiv<mode>3" 758 [(set (match_operand:IMSA 0 "register_operand" "=f") 759 (udiv:IMSA (match_operand:IMSA 1 "register_operand" "f") 760 (match_operand:IMSA 2 "register_operand" "f")))] 761 "ISA_HAS_MSA" 762 { return mips_msa_output_division ("div_u.<msafmt>\t%w0,%w1,%w2", operands); } 763 [(set_attr "type" "simd_div") 764 (set_attr "mode" "<MODE>")]) 765 766(define_insn "mod<mode>3" 767 [(set (match_operand:IMSA 0 "register_operand" "=f") 768 (mod:IMSA (match_operand:IMSA 1 "register_operand" "f") 769 (match_operand:IMSA 2 "register_operand" "f")))] 770 "ISA_HAS_MSA" 771 { return mips_msa_output_division ("mod_s.<msafmt>\t%w0,%w1,%w2", operands); } 772 [(set_attr "type" "simd_div") 773 (set_attr "mode" "<MODE>")]) 774 775(define_insn "umod<mode>3" 776 [(set (match_operand:IMSA 0 "register_operand" "=f") 777 (umod:IMSA (match_operand:IMSA 1 "register_operand" "f") 778 (match_operand:IMSA 2 "register_operand" "f")))] 779 "ISA_HAS_MSA" 780 { return mips_msa_output_division ("mod_u.<msafmt>\t%w0,%w1,%w2", operands); } 781 [(set_attr "type" "simd_div") 782 (set_attr "mode" "<MODE>")]) 783 784(define_insn "xor<mode>3" 785 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f") 786 (xor:IMSA 787 (match_operand:IMSA 1 "register_operand" "f,f,f") 788 (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))] 789 "ISA_HAS_MSA" 790 "@ 791 xor.v\t%w0,%w1,%w2 792 bnegi.%v0\t%w0,%w1,%V2 793 xori.b\t%w0,%w1,%B2" 794 [(set_attr "type" "simd_logic,simd_bit,simd_logic") 795 (set_attr "mode" "<MODE>")]) 796 797(define_insn "ior<mode>3" 798 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f") 799 (ior:IMSA 800 (match_operand:IMSA 1 "register_operand" "f,f,f") 801 (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))] 802 "ISA_HAS_MSA" 803 "@ 804 or.v\t%w0,%w1,%w2 805 bseti.%v0\t%w0,%w1,%V2 806 ori.b\t%w0,%w1,%B2" 807 [(set_attr "type" "simd_logic,simd_bit,simd_logic") 808 (set_attr "mode" "<MODE>")]) 809 810(define_insn "and<mode>3" 811 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f") 812 (and:IMSA 813 (match_operand:IMSA 1 "register_operand" "f,f,f") 814 (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,YZ,Urv8")))] 815 "ISA_HAS_MSA" 816{ 817 switch (which_alternative) 818 { 819 case 0: 820 return "and.v\t%w0,%w1,%w2"; 821 case 1: 822 { 823 rtx elt0 = CONST_VECTOR_ELT (operands[2], 0); 824 unsigned HOST_WIDE_INT val = ~UINTVAL (elt0); 825 operands[2] = mips_gen_const_int_vector (<MODE>mode, val & (-val)); 826 return "bclri.%v0\t%w0,%w1,%V2"; 827 } 828 case 2: 829 return "andi.b\t%w0,%w1,%B2"; 830 default: 831 gcc_unreachable (); 832 } 833} 834 [(set_attr "type" "simd_logic,simd_bit,simd_logic") 835 (set_attr "mode" "<MODE>")]) 836 837(define_insn "one_cmpl<mode>2" 838 [(set (match_operand:IMSA 0 "register_operand" "=f") 839 (not:IMSA (match_operand:IMSA 1 "register_operand" "f")))] 840 "ISA_HAS_MSA" 841 "nor.v\t%w0,%w1,%w1" 842 [(set_attr "type" "simd_logic") 843 (set_attr "mode" "TI")]) 844 845(define_insn "vlshr<mode>3" 846 [(set (match_operand:IMSA 0 "register_operand" "=f,f") 847 (lshiftrt:IMSA 848 (match_operand:IMSA 1 "register_operand" "f,f") 849 (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] 850 "ISA_HAS_MSA" 851 "@ 852 srl.<msafmt>\t%w0,%w1,%w2 853 srli.<msafmt>\t%w0,%w1,%E2" 854 [(set_attr "type" "simd_shift") 855 (set_attr "mode" "<MODE>")]) 856 857(define_insn "vashr<mode>3" 858 [(set (match_operand:IMSA 0 "register_operand" "=f,f") 859 (ashiftrt:IMSA 860 (match_operand:IMSA 1 "register_operand" "f,f") 861 (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] 862 "ISA_HAS_MSA" 863 "@ 864 sra.<msafmt>\t%w0,%w1,%w2 865 srai.<msafmt>\t%w0,%w1,%E2" 866 [(set_attr "type" "simd_shift") 867 (set_attr "mode" "<MODE>")]) 868 869(define_insn "vashl<mode>3" 870 [(set (match_operand:IMSA 0 "register_operand" "=f,f") 871 (ashift:IMSA 872 (match_operand:IMSA 1 "register_operand" "f,f") 873 (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] 874 "ISA_HAS_MSA" 875 "@ 876 sll.<msafmt>\t%w0,%w1,%w2 877 slli.<msafmt>\t%w0,%w1,%E2" 878 [(set_attr "type" "simd_shift") 879 (set_attr "mode" "<MODE>")]) 880 881;; Floating-point operations 882(define_insn "add<mode>3" 883 [(set (match_operand:FMSA 0 "register_operand" "=f") 884 (plus:FMSA (match_operand:FMSA 1 "register_operand" "f") 885 (match_operand:FMSA 2 "register_operand" "f")))] 886 "ISA_HAS_MSA" 887 "fadd.<msafmt>\t%w0,%w1,%w2" 888 [(set_attr "type" "simd_fadd") 889 (set_attr "mode" "<MODE>")]) 890 891(define_insn "sub<mode>3" 892 [(set (match_operand:FMSA 0 "register_operand" "=f") 893 (minus:FMSA (match_operand:FMSA 1 "register_operand" "f") 894 (match_operand:FMSA 2 "register_operand" "f")))] 895 "ISA_HAS_MSA" 896 "fsub.<msafmt>\t%w0,%w1,%w2" 897 [(set_attr "type" "simd_fadd") 898 (set_attr "mode" "<MODE>")]) 899 900(define_insn "mul<mode>3" 901 [(set (match_operand:FMSA 0 "register_operand" "=f") 902 (mult:FMSA (match_operand:FMSA 1 "register_operand" "f") 903 (match_operand:FMSA 2 "register_operand" "f")))] 904 "ISA_HAS_MSA" 905 "fmul.<msafmt>\t%w0,%w1,%w2" 906 [(set_attr "type" "simd_fmul") 907 (set_attr "mode" "<MODE>")]) 908 909(define_insn "div<mode>3" 910 [(set (match_operand:FMSA 0 "register_operand" "=f") 911 (div:FMSA (match_operand:FMSA 1 "register_operand" "f") 912 (match_operand:FMSA 2 "register_operand" "f")))] 913 "ISA_HAS_MSA" 914 "fdiv.<msafmt>\t%w0,%w1,%w2" 915 [(set_attr "type" "simd_fdiv") 916 (set_attr "mode" "<MODE>")]) 917 918(define_insn "fma<mode>4" 919 [(set (match_operand:FMSA 0 "register_operand" "=f") 920 (fma:FMSA (match_operand:FMSA 1 "register_operand" "f") 921 (match_operand:FMSA 2 "register_operand" "f") 922 (match_operand:FMSA 3 "register_operand" "0")))] 923 "ISA_HAS_MSA" 924 "fmadd.<msafmt>\t%w0,%w1,%w2" 925 [(set_attr "type" "simd_fmadd") 926 (set_attr "mode" "<MODE>")]) 927 928(define_insn "fnma<mode>4" 929 [(set (match_operand:FMSA 0 "register_operand" "=f") 930 (fma:FMSA (neg:FMSA (match_operand:FMSA 1 "register_operand" "f")) 931 (match_operand:FMSA 2 "register_operand" "f") 932 (match_operand:FMSA 3 "register_operand" "0")))] 933 "ISA_HAS_MSA" 934 "fmsub.<msafmt>\t%w0,%w1,%w2" 935 [(set_attr "type" "simd_fmadd") 936 (set_attr "mode" "<MODE>")]) 937 938(define_insn "sqrt<mode>2" 939 [(set (match_operand:FMSA 0 "register_operand" "=f") 940 (sqrt:FMSA (match_operand:FMSA 1 "register_operand" "f")))] 941 "ISA_HAS_MSA" 942 "fsqrt.<msafmt>\t%w0,%w1" 943 [(set_attr "type" "simd_fdiv") 944 (set_attr "mode" "<MODE>")]) 945 946;; Built-in functions 947(define_insn "msa_add_a_<msafmt>" 948 [(set (match_operand:IMSA 0 "register_operand" "=f") 949 (plus:IMSA (abs:IMSA (match_operand:IMSA 1 "register_operand" "f")) 950 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))))] 951 "ISA_HAS_MSA" 952 "add_a.<msafmt>\t%w0,%w1,%w2" 953 [(set_attr "type" "simd_int_arith") 954 (set_attr "mode" "<MODE>")]) 955 956(define_insn "msa_adds_a_<msafmt>" 957 [(set (match_operand:IMSA 0 "register_operand" "=f") 958 (ss_plus:IMSA 959 (abs:IMSA (match_operand:IMSA 1 "register_operand" "f")) 960 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))))] 961 "ISA_HAS_MSA" 962 "adds_a.<msafmt>\t%w0,%w1,%w2" 963 [(set_attr "type" "simd_int_arith") 964 (set_attr "mode" "<MODE>")]) 965 966(define_insn "ssadd<mode>3" 967 [(set (match_operand:IMSA 0 "register_operand" "=f") 968 (ss_plus:IMSA (match_operand:IMSA 1 "register_operand" "f") 969 (match_operand:IMSA 2 "register_operand" "f")))] 970 "ISA_HAS_MSA" 971 "adds_s.<msafmt>\t%w0,%w1,%w2" 972 [(set_attr "type" "simd_int_arith") 973 (set_attr "mode" "<MODE>")]) 974 975(define_insn "usadd<mode>3" 976 [(set (match_operand:IMSA 0 "register_operand" "=f") 977 (us_plus:IMSA (match_operand:IMSA 1 "register_operand" "f") 978 (match_operand:IMSA 2 "register_operand" "f")))] 979 "ISA_HAS_MSA" 980 "adds_u.<msafmt>\t%w0,%w1,%w2" 981 [(set_attr "type" "simd_int_arith") 982 (set_attr "mode" "<MODE>")]) 983 984(define_insn "msa_asub_s_<msafmt>" 985 [(set (match_operand:IMSA 0 "register_operand" "=f") 986 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 987 (match_operand:IMSA 2 "register_operand" "f")] 988 UNSPEC_MSA_ASUB_S))] 989 "ISA_HAS_MSA" 990 "asub_s.<msafmt>\t%w0,%w1,%w2" 991 [(set_attr "type" "simd_int_arith") 992 (set_attr "mode" "<MODE>")]) 993 994(define_insn "msa_asub_u_<msafmt>" 995 [(set (match_operand:IMSA 0 "register_operand" "=f") 996 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 997 (match_operand:IMSA 2 "register_operand" "f")] 998 UNSPEC_MSA_ASUB_U))] 999 "ISA_HAS_MSA" 1000 "asub_u.<msafmt>\t%w0,%w1,%w2" 1001 [(set_attr "type" "simd_int_arith") 1002 (set_attr "mode" "<MODE>")]) 1003 1004(define_insn "msa_ave_s_<msafmt>" 1005 [(set (match_operand:IMSA 0 "register_operand" "=f") 1006 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 1007 (match_operand:IMSA 2 "register_operand" "f")] 1008 UNSPEC_MSA_AVE_S))] 1009 "ISA_HAS_MSA" 1010 "ave_s.<msafmt>\t%w0,%w1,%w2" 1011 [(set_attr "type" "simd_int_arith") 1012 (set_attr "mode" "<MODE>")]) 1013 1014(define_insn "msa_ave_u_<msafmt>" 1015 [(set (match_operand:IMSA 0 "register_operand" "=f") 1016 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 1017 (match_operand:IMSA 2 "register_operand" "f")] 1018 UNSPEC_MSA_AVE_U))] 1019 "ISA_HAS_MSA" 1020 "ave_u.<msafmt>\t%w0,%w1,%w2" 1021 [(set_attr "type" "simd_int_arith") 1022 (set_attr "mode" "<MODE>")]) 1023 1024(define_insn "msa_aver_s_<msafmt>" 1025 [(set (match_operand:IMSA 0 "register_operand" "=f") 1026 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 1027 (match_operand:IMSA 2 "register_operand" "f")] 1028 UNSPEC_MSA_AVER_S))] 1029 "ISA_HAS_MSA" 1030 "aver_s.<msafmt>\t%w0,%w1,%w2" 1031 [(set_attr "type" "simd_int_arith") 1032 (set_attr "mode" "<MODE>")]) 1033 1034(define_insn "msa_aver_u_<msafmt>" 1035 [(set (match_operand:IMSA 0 "register_operand" "=f") 1036 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 1037 (match_operand:IMSA 2 "register_operand" "f")] 1038 UNSPEC_MSA_AVER_U))] 1039 "ISA_HAS_MSA" 1040 "aver_u.<msafmt>\t%w0,%w1,%w2" 1041 [(set_attr "type" "simd_int_arith") 1042 (set_attr "mode" "<MODE>")]) 1043 1044(define_insn "msa_bclr_<msafmt>" 1045 [(set (match_operand:IMSA 0 "register_operand" "=f") 1046 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 1047 (match_operand:IMSA 2 "register_operand" "f")] 1048 UNSPEC_MSA_BCLR))] 1049 "ISA_HAS_MSA" 1050 "bclr.<msafmt>\t%w0,%w1,%w2" 1051 [(set_attr "type" "simd_bit") 1052 (set_attr "mode" "<MODE>")]) 1053 1054(define_insn "msa_bclri_<msafmt>" 1055 [(set (match_operand:IMSA 0 "register_operand" "=f") 1056 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 1057 (match_operand 2 "const_<bitimm>_operand" "")] 1058 UNSPEC_MSA_BCLRI))] 1059 "ISA_HAS_MSA" 1060 "bclri.<msafmt>\t%w0,%w1,%2" 1061 [(set_attr "type" "simd_bit") 1062 (set_attr "mode" "<MODE>")]) 1063 1064(define_insn "msa_binsl_<msafmt>" 1065 [(set (match_operand:IMSA 0 "register_operand" "=f") 1066 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0") 1067 (match_operand:IMSA 2 "register_operand" "f") 1068 (match_operand:IMSA 3 "register_operand" "f")] 1069 UNSPEC_MSA_BINSL))] 1070 "ISA_HAS_MSA" 1071 "binsl.<msafmt>\t%w0,%w2,%w3" 1072 [(set_attr "type" "simd_bitins") 1073 (set_attr "mode" "<MODE>")]) 1074 1075(define_insn "msa_binsli_<msafmt>" 1076 [(set (match_operand:IMSA 0 "register_operand" "=f") 1077 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0") 1078 (match_operand:IMSA 2 "register_operand" "f") 1079 (match_operand 3 "const_<bitimm>_operand" "")] 1080 UNSPEC_MSA_BINSLI))] 1081 "ISA_HAS_MSA" 1082 "binsli.<msafmt>\t%w0,%w2,%3" 1083 [(set_attr "type" "simd_bitins") 1084 (set_attr "mode" "<MODE>")]) 1085 1086(define_insn "msa_binsr_<msafmt>" 1087 [(set (match_operand:IMSA 0 "register_operand" "=f") 1088 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0") 1089 (match_operand:IMSA 2 "register_operand" "f") 1090 (match_operand:IMSA 3 "register_operand" "f")] 1091 UNSPEC_MSA_BINSR))] 1092 "ISA_HAS_MSA" 1093 "binsr.<msafmt>\t%w0,%w2,%w3" 1094 [(set_attr "type" "simd_bitins") 1095 (set_attr "mode" "<MODE>")]) 1096 1097(define_insn "msa_binsri_<msafmt>" 1098 [(set (match_operand:IMSA 0 "register_operand" "=f") 1099 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0") 1100 (match_operand:IMSA 2 "register_operand" "f") 1101 (match_operand 3 "const_<bitimm>_operand" "")] 1102 UNSPEC_MSA_BINSRI))] 1103 "ISA_HAS_MSA" 1104 "binsri.<msafmt>\t%w0,%w2,%3" 1105 [(set_attr "type" "simd_bitins") 1106 (set_attr "mode" "<MODE>")]) 1107 1108(define_insn "msa_bmnz_<msafmt>" 1109 [(set (match_operand:IMSA 0 "register_operand" "=f,f") 1110 (ior:IMSA (and:IMSA (match_operand:IMSA 2 "register_operand" "f,f") 1111 (match_operand:IMSA 3 "reg_or_vector_same_val_operand" "f,Urv8")) 1112 (and:IMSA (not:IMSA (match_dup 3)) 1113 (match_operand:IMSA 1 "register_operand" "0,0"))))] 1114 "ISA_HAS_MSA" 1115 "@ 1116 bmnz.v\t%w0,%w2,%w3 1117 bmnzi.b\t%w0,%w2,%B3" 1118 [(set_attr "type" "simd_bitmov") 1119 (set_attr "mode" "<MODE>")]) 1120 1121(define_insn "msa_bmz_<msafmt>" 1122 [(set (match_operand:IMSA 0 "register_operand" "=f,f") 1123 (ior:IMSA (and:IMSA (not:IMSA 1124 (match_operand:IMSA 3 "reg_or_vector_same_val_operand" "f,Urv8")) 1125 (match_operand:IMSA 2 "register_operand" "f,f")) 1126 (and:IMSA (match_operand:IMSA 1 "register_operand" "0,0") 1127 (match_dup 3))))] 1128 "ISA_HAS_MSA" 1129 "@ 1130 bmz.v\t%w0,%w2,%w3 1131 bmzi.b\t%w0,%w2,%B3" 1132 [(set_attr "type" "simd_bitmov") 1133 (set_attr "mode" "<MODE>")]) 1134 1135(define_insn "msa_bneg_<msafmt>" 1136 [(set (match_operand:IMSA 0 "register_operand" "=f") 1137 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 1138 (match_operand:IMSA 2 "register_operand" "f")] 1139 UNSPEC_MSA_BNEG))] 1140 "ISA_HAS_MSA" 1141 "bneg.<msafmt>\t%w0,%w1,%w2" 1142 [(set_attr "type" "simd_bit") 1143 (set_attr "mode" "<MODE>")]) 1144 1145(define_insn "msa_bnegi_<msafmt>" 1146 [(set (match_operand:IMSA 0 "register_operand" "=f") 1147 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 1148 (match_operand 2 "const_msa_branch_operand" "")] 1149 UNSPEC_MSA_BNEGI))] 1150 "ISA_HAS_MSA" 1151 "bnegi.<msafmt>\t%w0,%w1,%2" 1152 [(set_attr "type" "simd_bit") 1153 (set_attr "mode" "<MODE>")]) 1154 1155(define_insn "msa_bsel_<msafmt>" 1156 [(set (match_operand:IMSA 0 "register_operand" "=f,f") 1157 (ior:IMSA (and:IMSA (not:IMSA 1158 (match_operand:IMSA 1 "register_operand" "0,0")) 1159 (match_operand:IMSA 2 "register_operand" "f,f")) 1160 (and:IMSA (match_dup 1) 1161 (match_operand:IMSA 3 "reg_or_vector_same_val_operand" "f,Urv8"))))] 1162 "ISA_HAS_MSA" 1163 "@ 1164 bsel.v\t%w0,%w2,%w3 1165 bseli.b\t%w0,%w2,%B3" 1166 [(set_attr "type" "simd_bitmov") 1167 (set_attr "mode" "<MODE>")]) 1168 1169(define_insn "msa_bset_<msafmt>" 1170 [(set (match_operand:IMSA 0 "register_operand" "=f") 1171 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 1172 (match_operand:IMSA 2 "register_operand" "f")] 1173 UNSPEC_MSA_BSET))] 1174 "ISA_HAS_MSA" 1175 "bset.<msafmt>\t%w0,%w1,%w2" 1176 [(set_attr "type" "simd_bit") 1177 (set_attr "mode" "<MODE>")]) 1178 1179(define_insn "msa_bseti_<msafmt>" 1180 [(set (match_operand:IMSA 0 "register_operand" "=f") 1181 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 1182 (match_operand 2 "const_<bitimm>_operand" "")] 1183 UNSPEC_MSA_BSETI))] 1184 "ISA_HAS_MSA" 1185 "bseti.<msafmt>\t%w0,%w1,%2" 1186 [(set_attr "type" "simd_bit") 1187 (set_attr "mode" "<MODE>")]) 1188 1189(define_code_iterator ICC [eq le leu lt ltu]) 1190 1191(define_code_attr icc 1192 [(eq "eq") 1193 (le "le_s") 1194 (leu "le_u") 1195 (lt "lt_s") 1196 (ltu "lt_u")]) 1197 1198(define_code_attr icci 1199 [(eq "eqi") 1200 (le "lei_s") 1201 (leu "lei_u") 1202 (lt "lti_s") 1203 (ltu "lti_u")]) 1204 1205(define_code_attr cmpi 1206 [(eq "s") 1207 (le "s") 1208 (leu "u") 1209 (lt "s") 1210 (ltu "u")]) 1211 1212(define_insn "msa_c<ICC:icc>_<IMSA:msafmt>" 1213 [(set (match_operand:IMSA 0 "register_operand" "=f,f") 1214 (ICC:IMSA 1215 (match_operand:IMSA 1 "register_operand" "f,f") 1216 (match_operand:IMSA 2 "reg_or_vector_same_<ICC:cmpi>imm5_operand" "f,U<ICC:cmpi>v5")))] 1217 "ISA_HAS_MSA" 1218 "@ 1219 c<ICC:icc>.<IMSA:msafmt>\t%w0,%w1,%w2 1220 c<ICC:icci>.<IMSA:msafmt>\t%w0,%w1,%E2" 1221 [(set_attr "type" "simd_int_arith") 1222 (set_attr "mode" "<MODE>")]) 1223 1224(define_insn "msa_dotp_<su>_d" 1225 [(set (match_operand:V2DI 0 "register_operand" "=f") 1226 (plus:V2DI 1227 (mult:V2DI 1228 (any_extend:V2DI 1229 (vec_select:V2SI 1230 (match_operand:V4SI 1 "register_operand" "%f") 1231 (parallel [(const_int 0) (const_int 2)]))) 1232 (any_extend:V2DI 1233 (vec_select:V2SI 1234 (match_operand:V4SI 2 "register_operand" "f") 1235 (parallel [(const_int 0) (const_int 2)])))) 1236 (mult:V2DI 1237 (any_extend:V2DI 1238 (vec_select:V2SI (match_dup 1) 1239 (parallel [(const_int 1) (const_int 3)]))) 1240 (any_extend:V2DI 1241 (vec_select:V2SI (match_dup 2) 1242 (parallel [(const_int 1) (const_int 3)]))))))] 1243 "ISA_HAS_MSA" 1244 "dotp_<su>.d\t%w0,%w1,%w2" 1245 [(set_attr "type" "simd_mul") 1246 (set_attr "mode" "V2DI")]) 1247 1248(define_insn "msa_dotp_<su>_w" 1249 [(set (match_operand:V4SI 0 "register_operand" "=f") 1250 (plus:V4SI 1251 (mult:V4SI 1252 (any_extend:V4SI 1253 (vec_select:V4HI 1254 (match_operand:V8HI 1 "register_operand" "%f") 1255 (parallel [(const_int 0) (const_int 2) 1256 (const_int 4) (const_int 6)]))) 1257 (any_extend:V4SI 1258 (vec_select:V4HI 1259 (match_operand:V8HI 2 "register_operand" "f") 1260 (parallel [(const_int 0) (const_int 2) 1261 (const_int 4) (const_int 6)])))) 1262 (mult:V4SI 1263 (any_extend:V4SI 1264 (vec_select:V4HI (match_dup 1) 1265 (parallel [(const_int 1) (const_int 3) 1266 (const_int 5) (const_int 7)]))) 1267 (any_extend:V4SI 1268 (vec_select:V4HI (match_dup 2) 1269 (parallel [(const_int 1) (const_int 3) 1270 (const_int 5) (const_int 7)]))))))] 1271 "ISA_HAS_MSA" 1272 "dotp_<su>.w\t%w0,%w1,%w2" 1273 [(set_attr "type" "simd_mul") 1274 (set_attr "mode" "V4SI")]) 1275 1276(define_insn "msa_dotp_<su>_h" 1277 [(set (match_operand:V8HI 0 "register_operand" "=f") 1278 (plus:V8HI 1279 (mult:V8HI 1280 (any_extend:V8HI 1281 (vec_select:V8QI 1282 (match_operand:V16QI 1 "register_operand" "%f") 1283 (parallel [(const_int 0) (const_int 2) 1284 (const_int 4) (const_int 6) 1285 (const_int 8) (const_int 10) 1286 (const_int 12) (const_int 14)]))) 1287 (any_extend:V8HI 1288 (vec_select:V8QI 1289 (match_operand:V16QI 2 "register_operand" "f") 1290 (parallel [(const_int 0) (const_int 2) 1291 (const_int 4) (const_int 6) 1292 (const_int 8) (const_int 10) 1293 (const_int 12) (const_int 14)])))) 1294 (mult:V8HI 1295 (any_extend:V8HI 1296 (vec_select:V8QI (match_dup 1) 1297 (parallel [(const_int 1) (const_int 3) 1298 (const_int 5) (const_int 7) 1299 (const_int 9) (const_int 11) 1300 (const_int 13) (const_int 15)]))) 1301 (any_extend:V8HI 1302 (vec_select:V8QI (match_dup 2) 1303 (parallel [(const_int 1) (const_int 3) 1304 (const_int 5) (const_int 7) 1305 (const_int 9) (const_int 11) 1306 (const_int 13) (const_int 15)]))))))] 1307 "ISA_HAS_MSA" 1308 "dotp_<su>.h\t%w0,%w1,%w2" 1309 [(set_attr "type" "simd_mul") 1310 (set_attr "mode" "V8HI")]) 1311 1312(define_insn "msa_dpadd_<su>_d" 1313 [(set (match_operand:V2DI 0 "register_operand" "=f") 1314 (plus:V2DI 1315 (plus:V2DI 1316 (mult:V2DI 1317 (any_extend:V2DI 1318 (vec_select:V2SI 1319 (match_operand:V4SI 2 "register_operand" "%f") 1320 (parallel [(const_int 0) (const_int 2)]))) 1321 (any_extend:V2DI 1322 (vec_select:V2SI 1323 (match_operand:V4SI 3 "register_operand" "f") 1324 (parallel [(const_int 0) (const_int 2)])))) 1325 (mult:V2DI 1326 (any_extend:V2DI 1327 (vec_select:V2SI (match_dup 2) 1328 (parallel [(const_int 1) (const_int 3)]))) 1329 (any_extend:V2DI 1330 (vec_select:V2SI (match_dup 3) 1331 (parallel [(const_int 1) (const_int 3)]))))) 1332 (match_operand:V2DI 1 "register_operand" "0")))] 1333 "ISA_HAS_MSA" 1334 "dpadd_<su>.d\t%w0,%w2,%w3" 1335 [(set_attr "type" "simd_mul") 1336 (set_attr "mode" "V2DI")]) 1337 1338(define_insn "msa_dpadd_<su>_w" 1339 [(set (match_operand:V4SI 0 "register_operand" "=f") 1340 (plus:V4SI 1341 (plus:V4SI 1342 (mult:V4SI 1343 (any_extend:V4SI 1344 (vec_select:V4HI 1345 (match_operand:V8HI 2 "register_operand" "%f") 1346 (parallel [(const_int 0) (const_int 2) 1347 (const_int 4) (const_int 6)]))) 1348 (any_extend:V4SI 1349 (vec_select:V4HI 1350 (match_operand:V8HI 3 "register_operand" "f") 1351 (parallel [(const_int 0) (const_int 2) 1352 (const_int 4) (const_int 6)])))) 1353 (mult:V4SI 1354 (any_extend:V4SI 1355 (vec_select:V4HI (match_dup 2) 1356 (parallel [(const_int 1) (const_int 3) 1357 (const_int 5) (const_int 7)]))) 1358 (any_extend:V4SI 1359 (vec_select:V4HI (match_dup 3) 1360 (parallel [(const_int 1) (const_int 3) 1361 (const_int 5) (const_int 7)]))))) 1362 (match_operand:V4SI 1 "register_operand" "0")))] 1363 "ISA_HAS_MSA" 1364 "dpadd_<su>.w\t%w0,%w2,%w3" 1365 [(set_attr "type" "simd_mul") 1366 (set_attr "mode" "V4SI")]) 1367 1368(define_insn "msa_dpadd_<su>_h" 1369 [(set (match_operand:V8HI 0 "register_operand" "=f") 1370 (plus:V8HI 1371 (plus:V8HI 1372 (mult:V8HI 1373 (any_extend:V8HI 1374 (vec_select:V8QI 1375 (match_operand:V16QI 2 "register_operand" "%f") 1376 (parallel [(const_int 0) (const_int 2) 1377 (const_int 4) (const_int 6) 1378 (const_int 8) (const_int 10) 1379 (const_int 12) (const_int 14)]))) 1380 (any_extend:V8HI 1381 (vec_select:V8QI 1382 (match_operand:V16QI 3 "register_operand" "f") 1383 (parallel [(const_int 0) (const_int 2) 1384 (const_int 4) (const_int 6) 1385 (const_int 8) (const_int 10) 1386 (const_int 12) (const_int 14)])))) 1387 (mult:V8HI 1388 (any_extend:V8HI 1389 (vec_select:V8QI (match_dup 2) 1390 (parallel [(const_int 1) (const_int 3) 1391 (const_int 5) (const_int 7) 1392 (const_int 9) (const_int 11) 1393 (const_int 13) (const_int 15)]))) 1394 (any_extend:V8HI 1395 (vec_select:V8QI (match_dup 3) 1396 (parallel [(const_int 1) (const_int 3) 1397 (const_int 5) (const_int 7) 1398 (const_int 9) (const_int 11) 1399 (const_int 13) (const_int 15)]))))) 1400 (match_operand:V8HI 1 "register_operand" "0")))] 1401 "ISA_HAS_MSA" 1402 "dpadd_<su>.h\t%w0,%w2,%w3" 1403 [(set_attr "type" "simd_mul") 1404 (set_attr "mode" "V8HI")]) 1405 1406(define_insn "msa_dpsub_<su>_d" 1407 [(set (match_operand:V2DI 0 "register_operand" "=f") 1408 (minus:V2DI 1409 (match_operand:V2DI 1 "register_operand" "0") 1410 (plus:V2DI 1411 (mult:V2DI 1412 (any_extend:V2DI 1413 (vec_select:V2SI 1414 (match_operand:V4SI 2 "register_operand" "%f") 1415 (parallel [(const_int 0) (const_int 2)]))) 1416 (any_extend:V2DI 1417 (vec_select:V2SI 1418 (match_operand:V4SI 3 "register_operand" "f") 1419 (parallel [(const_int 0) (const_int 2)])))) 1420 (mult:V2DI 1421 (any_extend:V2DI 1422 (vec_select:V2SI (match_dup 2) 1423 (parallel [(const_int 1) (const_int 3)]))) 1424 (any_extend:V2DI 1425 (vec_select:V2SI (match_dup 3) 1426 (parallel [(const_int 1) (const_int 3)])))))))] 1427 "ISA_HAS_MSA" 1428 "dpsub_<su>.d\t%w0,%w2,%w3" 1429 [(set_attr "type" "simd_mul") 1430 (set_attr "mode" "V2DI")]) 1431 1432(define_insn "msa_dpsub_<su>_w" 1433 [(set (match_operand:V4SI 0 "register_operand" "=f") 1434 (minus:V4SI 1435 (match_operand:V4SI 1 "register_operand" "0") 1436 (plus:V4SI 1437 (mult:V4SI 1438 (any_extend:V4SI 1439 (vec_select:V4HI 1440 (match_operand:V8HI 2 "register_operand" "%f") 1441 (parallel [(const_int 0) (const_int 2) 1442 (const_int 4) (const_int 6)]))) 1443 (any_extend:V4SI 1444 (vec_select:V4HI 1445 (match_operand:V8HI 3 "register_operand" "f") 1446 (parallel [(const_int 0) (const_int 2) 1447 (const_int 4) (const_int 6)])))) 1448 (mult:V4SI 1449 (any_extend:V4SI 1450 (vec_select:V4HI (match_dup 2) 1451 (parallel [(const_int 1) (const_int 3) 1452 (const_int 5) (const_int 7)]))) 1453 (any_extend:V4SI 1454 (vec_select:V4HI (match_dup 3) 1455 (parallel [(const_int 1) (const_int 3) 1456 (const_int 5) (const_int 7)])))))))] 1457 "ISA_HAS_MSA" 1458 "dpsub_<su>.w\t%w0,%w2,%w3" 1459 [(set_attr "type" "simd_mul") 1460 (set_attr "mode" "V4SI")]) 1461 1462(define_insn "msa_dpsub_<su>_h" 1463 [(set (match_operand:V8HI 0 "register_operand" "=f") 1464 (minus:V8HI 1465 (match_operand:V8HI 1 "register_operand" "0") 1466 (plus:V8HI 1467 (mult:V8HI 1468 (any_extend:V8HI 1469 (vec_select:V8QI 1470 (match_operand:V16QI 2 "register_operand" "%f") 1471 (parallel [(const_int 0) (const_int 2) 1472 (const_int 4) (const_int 6) 1473 (const_int 8) (const_int 10) 1474 (const_int 12) (const_int 14)]))) 1475 (any_extend:V8HI 1476 (vec_select:V8QI 1477 (match_operand:V16QI 3 "register_operand" "f") 1478 (parallel [(const_int 0) (const_int 2) 1479 (const_int 4) (const_int 6) 1480 (const_int 8) (const_int 10) 1481 (const_int 12) (const_int 14)])))) 1482 (mult:V8HI 1483 (any_extend:V8HI 1484 (vec_select:V8QI (match_dup 2) 1485 (parallel [(const_int 1) (const_int 3) 1486 (const_int 5) (const_int 7) 1487 (const_int 9) (const_int 11) 1488 (const_int 13) (const_int 15)]))) 1489 (any_extend:V8HI 1490 (vec_select:V8QI (match_dup 3) 1491 (parallel [(const_int 1) (const_int 3) 1492 (const_int 5) (const_int 7) 1493 (const_int 9) (const_int 11) 1494 (const_int 13) (const_int 15)])))))))] 1495 "ISA_HAS_MSA" 1496 "dpsub_<su>.h\t%w0,%w2,%w3" 1497 [(set_attr "type" "simd_mul") 1498 (set_attr "mode" "V8HI")]) 1499 1500(define_insn "msa_fclass_<msafmt>" 1501 [(set (match_operand:<VIMODE> 0 "register_operand" "=f") 1502 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")] 1503 UNSPEC_MSA_FCLASS))] 1504 "ISA_HAS_MSA" 1505 "fclass.<msafmt>\t%w0,%w1" 1506 [(set_attr "type" "simd_fclass") 1507 (set_attr "mode" "<MODE>")]) 1508 1509(define_insn "msa_fcaf_<msafmt>" 1510 [(set (match_operand:<VIMODE> 0 "register_operand" "=f") 1511 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f") 1512 (match_operand:FMSA 2 "register_operand" "f")] 1513 UNSPEC_MSA_FCAF))] 1514 "ISA_HAS_MSA" 1515 "fcaf.<msafmt>\t%w0,%w1,%w2" 1516 [(set_attr "type" "simd_fcmp") 1517 (set_attr "mode" "<MODE>")]) 1518 1519(define_insn "msa_fcune_<FMSA:msafmt>" 1520 [(set (match_operand:<VIMODE> 0 "register_operand" "=f") 1521 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f") 1522 (match_operand:FMSA 2 "register_operand" "f")] 1523 UNSPEC_MSA_FCUNE))] 1524 "ISA_HAS_MSA" 1525 "fcune.<FMSA:msafmt>\t%w0,%w1,%w2" 1526 [(set_attr "type" "simd_fcmp") 1527 (set_attr "mode" "<MODE>")]) 1528 1529(define_code_iterator FCC [unordered ordered eq ne le lt uneq unle unlt]) 1530 1531(define_code_attr fcc 1532 [(unordered "fcun") 1533 (ordered "fcor") 1534 (eq "fceq") 1535 (ne "fcne") 1536 (uneq "fcueq") 1537 (unle "fcule") 1538 (unlt "fcult") 1539 (le "fcle") 1540 (lt "fclt")]) 1541 1542(define_int_iterator FSC_UNS [UNSPEC_MSA_FSAF UNSPEC_MSA_FSUN UNSPEC_MSA_FSOR 1543 UNSPEC_MSA_FSEQ UNSPEC_MSA_FSNE UNSPEC_MSA_FSUEQ 1544 UNSPEC_MSA_FSUNE UNSPEC_MSA_FSULE UNSPEC_MSA_FSULT 1545 UNSPEC_MSA_FSLE UNSPEC_MSA_FSLT]) 1546 1547(define_int_attr fsc 1548 [(UNSPEC_MSA_FSAF "fsaf") 1549 (UNSPEC_MSA_FSUN "fsun") 1550 (UNSPEC_MSA_FSOR "fsor") 1551 (UNSPEC_MSA_FSEQ "fseq") 1552 (UNSPEC_MSA_FSNE "fsne") 1553 (UNSPEC_MSA_FSUEQ "fsueq") 1554 (UNSPEC_MSA_FSUNE "fsune") 1555 (UNSPEC_MSA_FSULE "fsule") 1556 (UNSPEC_MSA_FSULT "fsult") 1557 (UNSPEC_MSA_FSLE "fsle") 1558 (UNSPEC_MSA_FSLT "fslt")]) 1559 1560(define_insn "msa_<FCC:fcc>_<FMSA:msafmt>" 1561 [(set (match_operand:<VIMODE> 0 "register_operand" "=f") 1562 (FCC:<VIMODE> (match_operand:FMSA 1 "register_operand" "f") 1563 (match_operand:FMSA 2 "register_operand" "f")))] 1564 "ISA_HAS_MSA" 1565 "<FCC:fcc>.<FMSA:msafmt>\t%w0,%w1,%w2" 1566 [(set_attr "type" "simd_fcmp") 1567 (set_attr "mode" "<MODE>")]) 1568 1569(define_insn "msa_<fsc>_<FMSA:msafmt>" 1570 [(set (match_operand:<VIMODE> 0 "register_operand" "=f") 1571 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f") 1572 (match_operand:FMSA 2 "register_operand" "f")] 1573 FSC_UNS))] 1574 "ISA_HAS_MSA" 1575 "<fsc>.<FMSA:msafmt>\t%w0,%w1,%w2" 1576 [(set_attr "type" "simd_fcmp") 1577 (set_attr "mode" "<MODE>")]) 1578 1579(define_insn "msa_fexp2_<msafmt>" 1580 [(set (match_operand:FMSA 0 "register_operand" "=f") 1581 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f") 1582 (match_operand:<VIMODE> 2 "register_operand" "f")] 1583 UNSPEC_MSA_FEXP2))] 1584 "ISA_HAS_MSA" 1585 "fexp2.<msafmt>\t%w0,%w1,%w2" 1586 [(set_attr "type" "simd_fexp2") 1587 (set_attr "mode" "<MODE>")]) 1588 1589(define_mode_attr fint 1590 [(V4SF "v4si") 1591 (V2DF "v2di")]) 1592 1593(define_mode_attr FQ 1594 [(V4SF "V8HI") 1595 (V2DF "V4SI")]) 1596 1597(define_mode_attr FINTCNV 1598 [(V4SF "I2S") 1599 (V2DF "I2D")]) 1600 1601(define_mode_attr FINTCNV_2 1602 [(V4SF "S2I") 1603 (V2DF "D2I")]) 1604 1605(define_insn "float<fint><FMSA:mode>2" 1606 [(set (match_operand:FMSA 0 "register_operand" "=f") 1607 (float:FMSA (match_operand:<VIMODE> 1 "register_operand" "f")))] 1608 "ISA_HAS_MSA" 1609 "ffint_s.<msafmt>\t%w0,%w1" 1610 [(set_attr "type" "simd_fcvt") 1611 (set_attr "cnv_mode" "<FINTCNV>") 1612 (set_attr "mode" "<MODE>")]) 1613 1614(define_insn "floatuns<fint><FMSA:mode>2" 1615 [(set (match_operand:FMSA 0 "register_operand" "=f") 1616 (unsigned_float:FMSA 1617 (match_operand:<VIMODE> 1 "register_operand" "f")))] 1618 "ISA_HAS_MSA" 1619 "ffint_u.<msafmt>\t%w0,%w1" 1620 [(set_attr "type" "simd_fcvt") 1621 (set_attr "cnv_mode" "<FINTCNV>") 1622 (set_attr "mode" "<MODE>")]) 1623 1624(define_mode_attr FFQ 1625 [(V4SF "V8HI") 1626 (V2DF "V4SI")]) 1627 1628(define_insn "msa_ffql_<msafmt>" 1629 [(set (match_operand:FMSA 0 "register_operand" "=f") 1630 (unspec:FMSA [(match_operand:<FQ> 1 "register_operand" "f")] 1631 UNSPEC_MSA_FFQL))] 1632 "ISA_HAS_MSA" 1633 "ffql.<msafmt>\t%w0,%w1" 1634 [(set_attr "type" "simd_fcvt") 1635 (set_attr "cnv_mode" "<FINTCNV>") 1636 (set_attr "mode" "<MODE>")]) 1637 1638(define_insn "msa_ffqr_<msafmt>" 1639 [(set (match_operand:FMSA 0 "register_operand" "=f") 1640 (unspec:FMSA [(match_operand:<FQ> 1 "register_operand" "f")] 1641 UNSPEC_MSA_FFQR))] 1642 "ISA_HAS_MSA" 1643 "ffqr.<msafmt>\t%w0,%w1" 1644 [(set_attr "type" "simd_fcvt") 1645 (set_attr "cnv_mode" "<FINTCNV>") 1646 (set_attr "mode" "<MODE>")]) 1647 1648(define_insn "msa_fill_<msafmt_f>" 1649 [(set (match_operand:MSA 0 "register_operand" "=f,f") 1650 (vec_duplicate:MSA 1651 (match_operand:<UNITMODE> 1 "reg_or_0_operand" "d,J")))] 1652 "ISA_HAS_MSA" 1653{ 1654 if (which_alternative == 1) 1655 return "ldi.<msafmt>\t%w0,0"; 1656 1657 if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode)) 1658 return "#"; 1659 else 1660 return "fill.<msafmt>\t%w0,%z1"; 1661} 1662 [(set_attr "type" "simd_fill") 1663 (set_attr "mode" "<MODE>")]) 1664 1665(define_split 1666 [(set (match_operand:MSA_D 0 "register_operand") 1667 (vec_duplicate:MSA_D 1668 (match_operand:<UNITMODE> 1 "register_operand")))] 1669 "reload_completed && ISA_HAS_MSA && !TARGET_64BIT" 1670 [(const_int 0)] 1671{ 1672 mips_split_msa_fill_d (operands[0], operands[1]); 1673 DONE; 1674}) 1675 1676(define_insn "msa_flog2_<msafmt>" 1677 [(set (match_operand:FMSA 0 "register_operand" "=f") 1678 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")] 1679 UNSPEC_MSA_FLOG2))] 1680 "ISA_HAS_MSA" 1681 "flog2.<msafmt>\t%w0,%w1" 1682 [(set_attr "type" "simd_flog2") 1683 (set_attr "mode" "<MODE>")]) 1684 1685(define_insn "smax<mode>3" 1686 [(set (match_operand:FMSA 0 "register_operand" "=f") 1687 (smax:FMSA (match_operand:FMSA 1 "register_operand" "f") 1688 (match_operand:FMSA 2 "register_operand" "f")))] 1689 "ISA_HAS_MSA" 1690 "fmax.<msafmt>\t%w0,%w1,%w2" 1691 [(set_attr "type" "simd_fminmax") 1692 (set_attr "mode" "<MODE>")]) 1693 1694(define_insn "msa_fmax_a_<msafmt>" 1695 [(set (match_operand:FMSA 0 "register_operand" "=f") 1696 (if_then_else:FMSA 1697 (gt (abs:FMSA (match_operand:FMSA 1 "register_operand" "f")) 1698 (abs:FMSA (match_operand:FMSA 2 "register_operand" "f"))) 1699 (match_dup 1) 1700 (match_dup 2)))] 1701 "ISA_HAS_MSA" 1702 "fmax_a.<msafmt>\t%w0,%w1,%w2" 1703 [(set_attr "type" "simd_fminmax") 1704 (set_attr "mode" "<MODE>")]) 1705 1706(define_insn "smin<mode>3" 1707 [(set (match_operand:FMSA 0 "register_operand" "=f") 1708 (smin:FMSA (match_operand:FMSA 1 "register_operand" "f") 1709 (match_operand:FMSA 2 "register_operand" "f")))] 1710 "ISA_HAS_MSA" 1711 "fmin.<msafmt>\t%w0,%w1,%w2" 1712 [(set_attr "type" "simd_fminmax") 1713 (set_attr "mode" "<MODE>")]) 1714 1715(define_insn "msa_fmin_a_<msafmt>" 1716 [(set (match_operand:FMSA 0 "register_operand" "=f") 1717 (if_then_else:FMSA 1718 (lt (abs:FMSA (match_operand:FMSA 1 "register_operand" "f")) 1719 (abs:FMSA (match_operand:FMSA 2 "register_operand" "f"))) 1720 (match_dup 1) 1721 (match_dup 2)))] 1722 "ISA_HAS_MSA" 1723 "fmin_a.<msafmt>\t%w0,%w1,%w2" 1724 [(set_attr "type" "simd_fminmax") 1725 (set_attr "mode" "<MODE>")]) 1726 1727(define_insn "msa_frcp_<msafmt>" 1728 [(set (match_operand:FMSA 0 "register_operand" "=f") 1729 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")] 1730 UNSPEC_MSA_FRCP))] 1731 "ISA_HAS_MSA" 1732 "frcp.<msafmt>\t%w0,%w1" 1733 [(set_attr "type" "simd_fdiv") 1734 (set_attr "mode" "<MODE>")]) 1735 1736(define_insn "msa_frint_<msafmt>" 1737 [(set (match_operand:FMSA 0 "register_operand" "=f") 1738 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")] 1739 UNSPEC_MSA_FRINT))] 1740 "ISA_HAS_MSA" 1741 "frint.<msafmt>\t%w0,%w1" 1742 [(set_attr "type" "simd_fcvt") 1743 (set_attr "mode" "<MODE>")]) 1744 1745(define_insn "msa_frsqrt_<msafmt>" 1746 [(set (match_operand:FMSA 0 "register_operand" "=f") 1747 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")] 1748 UNSPEC_MSA_FRSQRT))] 1749 "ISA_HAS_MSA" 1750 "frsqrt.<msafmt>\t%w0,%w1" 1751 [(set_attr "type" "simd_fdiv") 1752 (set_attr "mode" "<MODE>")]) 1753 1754(define_insn "msa_ftint_s_<msafmt>" 1755 [(set (match_operand:<VIMODE> 0 "register_operand" "=f") 1756 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")] 1757 UNSPEC_MSA_FTINT_S))] 1758 "ISA_HAS_MSA" 1759 "ftint_s.<msafmt>\t%w0,%w1" 1760 [(set_attr "type" "simd_fcvt") 1761 (set_attr "cnv_mode" "<FINTCNV_2>") 1762 (set_attr "mode" "<MODE>")]) 1763 1764(define_insn "msa_ftint_u_<msafmt>" 1765 [(set (match_operand:<VIMODE> 0 "register_operand" "=f") 1766 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")] 1767 UNSPEC_MSA_FTINT_U))] 1768 "ISA_HAS_MSA" 1769 "ftint_u.<msafmt>\t%w0,%w1" 1770 [(set_attr "type" "simd_fcvt") 1771 (set_attr "cnv_mode" "<FINTCNV_2>") 1772 (set_attr "mode" "<MODE>")]) 1773 1774(define_insn "fix_trunc<FMSA:mode><mode_i>2" 1775 [(set (match_operand:<VIMODE> 0 "register_operand" "=f") 1776 (fix:<VIMODE> (match_operand:FMSA 1 "register_operand" "f")))] 1777 "ISA_HAS_MSA" 1778 "ftrunc_s.<msafmt>\t%w0,%w1" 1779 [(set_attr "type" "simd_fcvt") 1780 (set_attr "cnv_mode" "<FINTCNV_2>") 1781 (set_attr "mode" "<MODE>")]) 1782 1783(define_insn "fixuns_trunc<FMSA:mode><mode_i>2" 1784 [(set (match_operand:<VIMODE> 0 "register_operand" "=f") 1785 (unsigned_fix:<VIMODE> (match_operand:FMSA 1 "register_operand" "f")))] 1786 "ISA_HAS_MSA" 1787 "ftrunc_u.<msafmt>\t%w0,%w1" 1788 [(set_attr "type" "simd_fcvt") 1789 (set_attr "cnv_mode" "<FINTCNV_2>") 1790 (set_attr "mode" "<MODE>")]) 1791 1792(define_insn "msa_ftq_h" 1793 [(set (match_operand:V8HI 0 "register_operand" "=f") 1794 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "f") 1795 (match_operand:V4SF 2 "register_operand" "f")] 1796 UNSPEC_MSA_FTQ))] 1797 "ISA_HAS_MSA" 1798 "ftq.h\t%w0,%w1,%w2" 1799 [(set_attr "type" "simd_fcvt") 1800 (set_attr "cnv_mode" "S2I") 1801 (set_attr "mode" "V4SF")]) 1802 1803(define_insn "msa_ftq_w" 1804 [(set (match_operand:V4SI 0 "register_operand" "=f") 1805 (unspec:V4SI [(match_operand:V2DF 1 "register_operand" "f") 1806 (match_operand:V2DF 2 "register_operand" "f")] 1807 UNSPEC_MSA_FTQ))] 1808 "ISA_HAS_MSA" 1809 "ftq.w\t%w0,%w1,%w2" 1810 [(set_attr "type" "simd_fcvt") 1811 (set_attr "cnv_mode" "D2I") 1812 (set_attr "mode" "V2DF")]) 1813 1814(define_insn "msa_h<optab>_<su>_h" 1815 [(set (match_operand:V8HI 0 "register_operand" "=f") 1816 (addsub:V8HI 1817 (any_extend:V8HI 1818 (vec_select:V8QI 1819 (match_operand:V16QI 1 "register_operand" "f") 1820 (parallel [(const_int 1) (const_int 3) 1821 (const_int 5) (const_int 7) 1822 (const_int 9) (const_int 11) 1823 (const_int 13) (const_int 15)]))) 1824 (any_extend:V8HI 1825 (vec_select:V8QI 1826 (match_operand:V16QI 2 "register_operand" "f") 1827 (parallel [(const_int 0) (const_int 2) 1828 (const_int 4) (const_int 6) 1829 (const_int 8) (const_int 10) 1830 (const_int 12) (const_int 14)])))))] 1831 "ISA_HAS_MSA" 1832 "h<optab>_<su>.h\t%w0,%w1,%w2" 1833 [(set_attr "type" "simd_int_arith") 1834 (set_attr "mode" "V8HI")]) 1835 1836(define_insn "msa_h<optab>_<su>_w" 1837 [(set (match_operand:V4SI 0 "register_operand" "=f") 1838 (addsub:V4SI 1839 (any_extend:V4SI 1840 (vec_select:V4HI 1841 (match_operand:V8HI 1 "register_operand" "f") 1842 (parallel [(const_int 1) (const_int 3) 1843 (const_int 5) (const_int 7)]))) 1844 (any_extend:V4SI 1845 (vec_select:V4HI 1846 (match_operand:V8HI 2 "register_operand" "f") 1847 (parallel [(const_int 0) (const_int 2) 1848 (const_int 4) (const_int 6)])))))] 1849 "ISA_HAS_MSA" 1850 "h<optab>_<su>.w\t%w0,%w1,%w2" 1851 [(set_attr "type" "simd_int_arith") 1852 (set_attr "mode" "V4SI")]) 1853 1854(define_insn "msa_h<optab>_<su>_d" 1855 [(set (match_operand:V2DI 0 "register_operand" "=f") 1856 (addsub:V2DI 1857 (any_extend:V2DI 1858 (vec_select:V2SI 1859 (match_operand:V4SI 1 "register_operand" "f") 1860 (parallel [(const_int 1) (const_int 3)]))) 1861 (any_extend:V2DI 1862 (vec_select:V2SI 1863 (match_operand:V4SI 2 "register_operand" "f") 1864 (parallel [(const_int 0) (const_int 2)])))))] 1865 "ISA_HAS_MSA" 1866 "h<optab>_<su>.d\t%w0,%w1,%w2" 1867 [(set_attr "type" "simd_int_arith") 1868 (set_attr "mode" "V2DI")]) 1869 1870(define_insn "msa_ilvev_b" 1871 [(set (match_operand:V16QI 0 "register_operand" "=f") 1872 (vec_select:V16QI 1873 (vec_concat:V32QI 1874 (match_operand:V16QI 1 "register_operand" "f") 1875 (match_operand:V16QI 2 "register_operand" "f")) 1876 (parallel [(const_int 0) (const_int 16) 1877 (const_int 2) (const_int 18) 1878 (const_int 4) (const_int 20) 1879 (const_int 6) (const_int 22) 1880 (const_int 8) (const_int 24) 1881 (const_int 10) (const_int 26) 1882 (const_int 12) (const_int 28) 1883 (const_int 14) (const_int 30)])))] 1884 "ISA_HAS_MSA" 1885 "ilvev.b\t%w0,%w2,%w1" 1886 [(set_attr "type" "simd_permute") 1887 (set_attr "mode" "V16QI")]) 1888 1889(define_insn "msa_ilvev_h" 1890 [(set (match_operand:V8HI 0 "register_operand" "=f") 1891 (vec_select:V8HI 1892 (vec_concat:V16HI 1893 (match_operand:V8HI 1 "register_operand" "f") 1894 (match_operand:V8HI 2 "register_operand" "f")) 1895 (parallel [(const_int 0) (const_int 8) 1896 (const_int 2) (const_int 10) 1897 (const_int 4) (const_int 12) 1898 (const_int 6) (const_int 14)])))] 1899 "ISA_HAS_MSA" 1900 "ilvev.h\t%w0,%w2,%w1" 1901 [(set_attr "type" "simd_permute") 1902 (set_attr "mode" "V8HI")]) 1903 1904(define_insn "msa_ilvev_w" 1905 [(set (match_operand:V4SI 0 "register_operand" "=f") 1906 (vec_select:V4SI 1907 (vec_concat:V8SI 1908 (match_operand:V4SI 1 "register_operand" "f") 1909 (match_operand:V4SI 2 "register_operand" "f")) 1910 (parallel [(const_int 0) (const_int 4) 1911 (const_int 2) (const_int 6)])))] 1912 "ISA_HAS_MSA" 1913 "ilvev.w\t%w0,%w2,%w1" 1914 [(set_attr "type" "simd_permute") 1915 (set_attr "mode" "V4SI")]) 1916 1917(define_insn "msa_ilvev_w_f" 1918 [(set (match_operand:V4SF 0 "register_operand" "=f") 1919 (vec_select:V4SF 1920 (vec_concat:V8SF 1921 (match_operand:V4SF 1 "register_operand" "f") 1922 (match_operand:V4SF 2 "register_operand" "f")) 1923 (parallel [(const_int 0) (const_int 4) 1924 (const_int 2) (const_int 6)])))] 1925 "ISA_HAS_MSA" 1926 "ilvev.w\t%w0,%w2,%w1" 1927 [(set_attr "type" "simd_permute") 1928 (set_attr "mode" "V4SF")]) 1929 1930(define_insn "msa_ilvl_b" 1931 [(set (match_operand:V16QI 0 "register_operand" "=f") 1932 (vec_select:V16QI 1933 (vec_concat:V32QI 1934 (match_operand:V16QI 1 "register_operand" "f") 1935 (match_operand:V16QI 2 "register_operand" "f")) 1936 (parallel [(const_int 8) (const_int 24) 1937 (const_int 9) (const_int 25) 1938 (const_int 10) (const_int 26) 1939 (const_int 11) (const_int 27) 1940 (const_int 12) (const_int 28) 1941 (const_int 13) (const_int 29) 1942 (const_int 14) (const_int 30) 1943 (const_int 15) (const_int 31)])))] 1944 "ISA_HAS_MSA" 1945 "ilvl.b\t%w0,%w2,%w1" 1946 [(set_attr "type" "simd_permute") 1947 (set_attr "mode" "V16QI")]) 1948 1949(define_insn "msa_ilvl_h" 1950 [(set (match_operand:V8HI 0 "register_operand" "=f") 1951 (vec_select:V8HI 1952 (vec_concat:V16HI 1953 (match_operand:V8HI 1 "register_operand" "f") 1954 (match_operand:V8HI 2 "register_operand" "f")) 1955 (parallel [(const_int 4) (const_int 12) 1956 (const_int 5) (const_int 13) 1957 (const_int 6) (const_int 14) 1958 (const_int 7) (const_int 15)])))] 1959 "ISA_HAS_MSA" 1960 "ilvl.h\t%w0,%w2,%w1" 1961 [(set_attr "type" "simd_permute") 1962 (set_attr "mode" "V8HI")]) 1963 1964(define_insn "msa_ilvl_w" 1965 [(set (match_operand:V4SI 0 "register_operand" "=f") 1966 (vec_select:V4SI 1967 (vec_concat:V8SI 1968 (match_operand:V4SI 1 "register_operand" "f") 1969 (match_operand:V4SI 2 "register_operand" "f")) 1970 (parallel [(const_int 2) (const_int 6) 1971 (const_int 3) (const_int 7)])))] 1972 "ISA_HAS_MSA" 1973 "ilvl.w\t%w0,%w2,%w1" 1974 [(set_attr "type" "simd_permute") 1975 (set_attr "mode" "V4SI")]) 1976 1977(define_insn "msa_ilvl_w_f" 1978 [(set (match_operand:V4SF 0 "register_operand" "=f") 1979 (vec_select:V4SF 1980 (vec_concat:V8SF 1981 (match_operand:V4SF 1 "register_operand" "f") 1982 (match_operand:V4SF 2 "register_operand" "f")) 1983 (parallel [(const_int 2) (const_int 6) 1984 (const_int 3) (const_int 7)])))] 1985 "ISA_HAS_MSA" 1986 "ilvl.w\t%w0,%w2,%w1" 1987 [(set_attr "type" "simd_permute") 1988 (set_attr "mode" "V4SF")]) 1989 1990(define_insn "msa_ilvl_d" 1991 [(set (match_operand:V2DI 0 "register_operand" "=f") 1992 (vec_select:V2DI 1993 (vec_concat:V4DI 1994 (match_operand:V2DI 1 "register_operand" "f") 1995 (match_operand:V2DI 2 "register_operand" "f")) 1996 (parallel [(const_int 1) (const_int 3)])))] 1997 "ISA_HAS_MSA" 1998 "ilvl.d\t%w0,%w2,%w1" 1999 [(set_attr "type" "simd_permute") 2000 (set_attr "mode" "V2DI")]) 2001 2002(define_insn "msa_ilvl_d_f" 2003 [(set (match_operand:V2DF 0 "register_operand" "=f") 2004 (vec_select:V2DF 2005 (vec_concat:V4DF 2006 (match_operand:V2DF 1 "register_operand" "f") 2007 (match_operand:V2DF 2 "register_operand" "f")) 2008 (parallel [(const_int 1) (const_int 3)])))] 2009 "ISA_HAS_MSA" 2010 "ilvl.d\t%w0,%w2,%w1" 2011 [(set_attr "type" "simd_permute") 2012 (set_attr "mode" "V2DF")]) 2013 2014(define_insn "msa_ilvod_b" 2015 [(set (match_operand:V16QI 0 "register_operand" "=f") 2016 (vec_select:V16QI 2017 (vec_concat:V32QI 2018 (match_operand:V16QI 1 "register_operand" "f") 2019 (match_operand:V16QI 2 "register_operand" "f")) 2020 (parallel [(const_int 1) (const_int 17) 2021 (const_int 3) (const_int 19) 2022 (const_int 5) (const_int 21) 2023 (const_int 7) (const_int 23) 2024 (const_int 9) (const_int 25) 2025 (const_int 11) (const_int 27) 2026 (const_int 13) (const_int 29) 2027 (const_int 15) (const_int 31)])))] 2028 "ISA_HAS_MSA" 2029 "ilvod.b\t%w0,%w2,%w1" 2030 [(set_attr "type" "simd_permute") 2031 (set_attr "mode" "V16QI")]) 2032 2033(define_insn "msa_ilvod_h" 2034 [(set (match_operand:V8HI 0 "register_operand" "=f") 2035 (vec_select:V8HI 2036 (vec_concat:V16HI 2037 (match_operand:V8HI 1 "register_operand" "f") 2038 (match_operand:V8HI 2 "register_operand" "f")) 2039 (parallel [(const_int 1) (const_int 9) 2040 (const_int 3) (const_int 11) 2041 (const_int 5) (const_int 13) 2042 (const_int 7) (const_int 15)])))] 2043 "ISA_HAS_MSA" 2044 "ilvod.h\t%w0,%w2,%w1" 2045 [(set_attr "type" "simd_permute") 2046 (set_attr "mode" "V8HI")]) 2047 2048(define_insn "msa_ilvod_w" 2049 [(set (match_operand:V4SI 0 "register_operand" "=f") 2050 (vec_select:V4SI 2051 (vec_concat:V8SI 2052 (match_operand:V4SI 1 "register_operand" "f") 2053 (match_operand:V4SI 2 "register_operand" "f")) 2054 (parallel [(const_int 1) (const_int 5) 2055 (const_int 3) (const_int 7)])))] 2056 "ISA_HAS_MSA" 2057 "ilvod.w\t%w0,%w2,%w1" 2058 [(set_attr "type" "simd_permute") 2059 (set_attr "mode" "V4SI")]) 2060 2061(define_insn "msa_ilvod_w_f" 2062 [(set (match_operand:V4SF 0 "register_operand" "=f") 2063 (vec_select:V4SF 2064 (vec_concat:V8SF 2065 (match_operand:V4SF 1 "register_operand" "f") 2066 (match_operand:V4SF 2 "register_operand" "f")) 2067 (parallel [(const_int 1) (const_int 5) 2068 (const_int 3) (const_int 7)])))] 2069 "ISA_HAS_MSA" 2070 "ilvod.w\t%w0,%w2,%w1" 2071 [(set_attr "type" "simd_permute") 2072 (set_attr "mode" "V4SF")]) 2073 2074(define_insn "msa_ilvr_b" 2075 [(set (match_operand:V16QI 0 "register_operand" "=f") 2076 (vec_select:V16QI 2077 (vec_concat:V32QI 2078 (match_operand:V16QI 1 "register_operand" "f") 2079 (match_operand:V16QI 2 "register_operand" "f")) 2080 (parallel [(const_int 0) (const_int 16) 2081 (const_int 1) (const_int 17) 2082 (const_int 2) (const_int 18) 2083 (const_int 3) (const_int 19) 2084 (const_int 4) (const_int 20) 2085 (const_int 5) (const_int 21) 2086 (const_int 6) (const_int 22) 2087 (const_int 7) (const_int 23)])))] 2088 "ISA_HAS_MSA" 2089 "ilvr.b\t%w0,%w2,%w1" 2090 [(set_attr "type" "simd_permute") 2091 (set_attr "mode" "V16QI")]) 2092 2093(define_insn "msa_ilvr_h" 2094 [(set (match_operand:V8HI 0 "register_operand" "=f") 2095 (vec_select:V8HI 2096 (vec_concat:V16HI 2097 (match_operand:V8HI 1 "register_operand" "f") 2098 (match_operand:V8HI 2 "register_operand" "f")) 2099 (parallel [(const_int 0) (const_int 8) 2100 (const_int 1) (const_int 9) 2101 (const_int 2) (const_int 10) 2102 (const_int 3) (const_int 11)])))] 2103 "ISA_HAS_MSA" 2104 "ilvr.h\t%w0,%w2,%w1" 2105 [(set_attr "type" "simd_permute") 2106 (set_attr "mode" "V8HI")]) 2107 2108(define_insn "msa_ilvr_w" 2109 [(set (match_operand:V4SI 0 "register_operand" "=f") 2110 (vec_select:V4SI 2111 (vec_concat:V8SI 2112 (match_operand:V4SI 1 "register_operand" "f") 2113 (match_operand:V4SI 2 "register_operand" "f")) 2114 (parallel [(const_int 0) (const_int 4) 2115 (const_int 1) (const_int 5)])))] 2116 "ISA_HAS_MSA" 2117 "ilvr.w\t%w0,%w2,%w1" 2118 [(set_attr "type" "simd_permute") 2119 (set_attr "mode" "V4SI")]) 2120 2121(define_insn "msa_ilvr_w_f" 2122 [(set (match_operand:V4SF 0 "register_operand" "=f") 2123 (vec_select:V4SF 2124 (vec_concat:V8SF 2125 (match_operand:V4SF 1 "register_operand" "f") 2126 (match_operand:V4SF 2 "register_operand" "f")) 2127 (parallel [(const_int 0) (const_int 4) 2128 (const_int 1) (const_int 5)])))] 2129 "ISA_HAS_MSA" 2130 "ilvr.w\t%w0,%w2,%w1" 2131 [(set_attr "type" "simd_permute") 2132 (set_attr "mode" "V4SF")]) 2133 2134(define_insn "msa_ilvr_d" 2135 [(set (match_operand:V2DI 0 "register_operand" "=f") 2136 (vec_select:V2DI 2137 (vec_concat:V4DI 2138 (match_operand:V2DI 1 "register_operand" "f") 2139 (match_operand:V2DI 2 "register_operand" "f")) 2140 (parallel [(const_int 0) (const_int 2)])))] 2141 "ISA_HAS_MSA" 2142 "ilvr.d\t%w0,%w2,%w1" 2143 [(set_attr "type" "simd_permute") 2144 (set_attr "mode" "V2DI")]) 2145 2146(define_insn "msa_ilvr_d_f" 2147 [(set (match_operand:V2DF 0 "register_operand" "=f") 2148 (vec_select:V2DF 2149 (vec_concat:V4DF 2150 (match_operand:V2DF 1 "register_operand" "f") 2151 (match_operand:V2DF 2 "register_operand" "f")) 2152 (parallel [(const_int 0) (const_int 2)])))] 2153 "ISA_HAS_MSA" 2154 "ilvr.d\t%w0,%w2,%w1" 2155 [(set_attr "type" "simd_permute") 2156 (set_attr "mode" "V2DF")]) 2157 2158(define_insn "msa_madd_q_<msafmt>" 2159 [(set (match_operand:IMSA_WH 0 "register_operand" "=f") 2160 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0") 2161 (match_operand:IMSA_WH 2 "register_operand" "f") 2162 (match_operand:IMSA_WH 3 "register_operand" "f")] 2163 UNSPEC_MSA_MADD_Q))] 2164 "ISA_HAS_MSA" 2165 "madd_q.<msafmt>\t%w0,%w2,%w3" 2166 [(set_attr "type" "simd_mul") 2167 (set_attr "mode" "<MODE>")]) 2168 2169(define_insn "msa_maddr_q_<msafmt>" 2170 [(set (match_operand:IMSA_WH 0 "register_operand" "=f") 2171 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0") 2172 (match_operand:IMSA_WH 2 "register_operand" "f") 2173 (match_operand:IMSA_WH 3 "register_operand" "f")] 2174 UNSPEC_MSA_MADDR_Q))] 2175 "ISA_HAS_MSA" 2176 "maddr_q.<msafmt>\t%w0,%w2,%w3" 2177 [(set_attr "type" "simd_mul") 2178 (set_attr "mode" "<MODE>")]) 2179 2180(define_insn "msa_max_a_<msafmt>" 2181 [(set (match_operand:IMSA 0 "register_operand" "=f") 2182 (if_then_else:IMSA 2183 (gt (abs:IMSA (match_operand:IMSA 1 "register_operand" "f")) 2184 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))) 2185 (match_dup 1) 2186 (match_dup 2)))] 2187 "ISA_HAS_MSA" 2188 "max_a.<msafmt>\t%w0,%w1,%w2" 2189 [(set_attr "type" "simd_int_arith") 2190 (set_attr "mode" "<MODE>")]) 2191 2192(define_insn "smax<mode>3" 2193 [(set (match_operand:IMSA 0 "register_operand" "=f,f") 2194 (smax:IMSA (match_operand:IMSA 1 "register_operand" "f,f") 2195 (match_operand:IMSA 2 "reg_or_vector_same_simm5_operand" "f,Usv5")))] 2196 "ISA_HAS_MSA" 2197 "@ 2198 max_s.<msafmt>\t%w0,%w1,%w2 2199 maxi_s.<msafmt>\t%w0,%w1,%E2" 2200 [(set_attr "type" "simd_int_arith") 2201 (set_attr "mode" "<MODE>")]) 2202 2203(define_insn "umax<mode>3" 2204 [(set (match_operand:IMSA 0 "register_operand" "=f,f") 2205 (umax:IMSA (match_operand:IMSA 1 "register_operand" "f,f") 2206 (match_operand:IMSA 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))] 2207 "ISA_HAS_MSA" 2208 "@ 2209 max_u.<msafmt>\t%w0,%w1,%w2 2210 maxi_u.<msafmt>\t%w0,%w1,%B2" 2211 [(set_attr "type" "simd_int_arith") 2212 (set_attr "mode" "<MODE>")]) 2213 2214(define_insn "msa_min_a_<msafmt>" 2215 [(set (match_operand:IMSA 0 "register_operand" "=f") 2216 (if_then_else:IMSA 2217 (lt (abs:IMSA (match_operand:IMSA 1 "register_operand" "f")) 2218 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))) 2219 (match_dup 1) 2220 (match_dup 2)))] 2221 "ISA_HAS_MSA" 2222 "min_a.<msafmt>\t%w0,%w1,%w2" 2223 [(set_attr "type" "simd_int_arith") 2224 (set_attr "mode" "<MODE>")]) 2225 2226(define_insn "smin<mode>3" 2227 [(set (match_operand:IMSA 0 "register_operand" "=f,f") 2228 (smin:IMSA (match_operand:IMSA 1 "register_operand" "f,f") 2229 (match_operand:IMSA 2 "reg_or_vector_same_simm5_operand" "f,Usv5")))] 2230 "ISA_HAS_MSA" 2231 "@ 2232 min_s.<msafmt>\t%w0,%w1,%w2 2233 mini_s.<msafmt>\t%w0,%w1,%E2" 2234 [(set_attr "type" "simd_int_arith") 2235 (set_attr "mode" "<MODE>")]) 2236 2237(define_insn "umin<mode>3" 2238 [(set (match_operand:IMSA 0 "register_operand" "=f,f") 2239 (umin:IMSA (match_operand:IMSA 1 "register_operand" "f,f") 2240 (match_operand:IMSA 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))] 2241 "ISA_HAS_MSA" 2242 "@ 2243 min_u.<msafmt>\t%w0,%w1,%w2 2244 mini_u.<msafmt>\t%w0,%w1,%B2" 2245 [(set_attr "type" "simd_int_arith") 2246 (set_attr "mode" "<MODE>")]) 2247 2248(define_insn "msa_msub_q_<msafmt>" 2249 [(set (match_operand:IMSA_WH 0 "register_operand" "=f") 2250 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0") 2251 (match_operand:IMSA_WH 2 "register_operand" "f") 2252 (match_operand:IMSA_WH 3 "register_operand" "f")] 2253 UNSPEC_MSA_MSUB_Q))] 2254 "ISA_HAS_MSA" 2255 "msub_q.<msafmt>\t%w0,%w2,%w3" 2256 [(set_attr "type" "simd_mul") 2257 (set_attr "mode" "<MODE>")]) 2258 2259(define_insn "msa_msubr_q_<msafmt>" 2260 [(set (match_operand:IMSA_WH 0 "register_operand" "=f") 2261 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0") 2262 (match_operand:IMSA_WH 2 "register_operand" "f") 2263 (match_operand:IMSA_WH 3 "register_operand" "f")] 2264 UNSPEC_MSA_MSUBR_Q))] 2265 "ISA_HAS_MSA" 2266 "msubr_q.<msafmt>\t%w0,%w2,%w3" 2267 [(set_attr "type" "simd_mul") 2268 (set_attr "mode" "<MODE>")]) 2269 2270(define_insn "msa_mul_q_<msafmt>" 2271 [(set (match_operand:IMSA_WH 0 "register_operand" "=f") 2272 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "f") 2273 (match_operand:IMSA_WH 2 "register_operand" "f")] 2274 UNSPEC_MSA_MUL_Q))] 2275 "ISA_HAS_MSA" 2276 "mul_q.<msafmt>\t%w0,%w1,%w2" 2277 [(set_attr "type" "simd_mul") 2278 (set_attr "mode" "<MODE>")]) 2279 2280(define_insn "msa_mulr_q_<msafmt>" 2281 [(set (match_operand:IMSA_WH 0 "register_operand" "=f") 2282 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "f") 2283 (match_operand:IMSA_WH 2 "register_operand" "f")] 2284 UNSPEC_MSA_MULR_Q))] 2285 "ISA_HAS_MSA" 2286 "mulr_q.<msafmt>\t%w0,%w1,%w2" 2287 [(set_attr "type" "simd_mul") 2288 (set_attr "mode" "<MODE>")]) 2289 2290(define_insn "msa_nloc_<msafmt>" 2291 [(set (match_operand:IMSA 0 "register_operand" "=f") 2292 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")] 2293 UNSPEC_MSA_NLOC))] 2294 "ISA_HAS_MSA" 2295 "nloc.<msafmt>\t%w0,%w1" 2296 [(set_attr "type" "simd_bit") 2297 (set_attr "mode" "<MODE>")]) 2298 2299(define_insn "clz<mode>2" 2300 [(set (match_operand:IMSA 0 "register_operand" "=f") 2301 (clz:IMSA (match_operand:IMSA 1 "register_operand" "f")))] 2302 "ISA_HAS_MSA" 2303 "nlzc.<msafmt>\t%w0,%w1" 2304 [(set_attr "type" "simd_bit") 2305 (set_attr "mode" "<MODE>")]) 2306 2307(define_insn "msa_nor_<msafmt>" 2308 [(set (match_operand:IMSA 0 "register_operand" "=f,f") 2309 (and:IMSA (not:IMSA (match_operand:IMSA 1 "register_operand" "f,f")) 2310 (not:IMSA (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,Urv8"))))] 2311 "ISA_HAS_MSA" 2312 "@ 2313 nor.v\t%w0,%w1,%w2 2314 nori.b\t%w0,%w1,%B2" 2315 [(set_attr "type" "simd_logic") 2316 (set_attr "mode" "<MODE>")]) 2317 2318(define_insn "msa_pckev_b" 2319[(set (match_operand:V16QI 0 "register_operand" "=f") 2320 (vec_select:V16QI 2321 (vec_concat:V32QI 2322 (match_operand:V16QI 1 "register_operand" "f") 2323 (match_operand:V16QI 2 "register_operand" "f")) 2324 (parallel [(const_int 0) (const_int 2) 2325 (const_int 4) (const_int 6) 2326 (const_int 8) (const_int 10) 2327 (const_int 12) (const_int 14) 2328 (const_int 16) (const_int 18) 2329 (const_int 20) (const_int 22) 2330 (const_int 24) (const_int 26) 2331 (const_int 28) (const_int 30)])))] 2332 "ISA_HAS_MSA" 2333 "pckev.b\t%w0,%w2,%w1" 2334 [(set_attr "type" "simd_permute") 2335 (set_attr "mode" "V16QI")]) 2336 2337(define_insn "msa_pckev_h" 2338[(set (match_operand:V8HI 0 "register_operand" "=f") 2339 (vec_select:V8HI 2340 (vec_concat:V16HI 2341 (match_operand:V8HI 1 "register_operand" "f") 2342 (match_operand:V8HI 2 "register_operand" "f")) 2343 (parallel [(const_int 0) (const_int 2) 2344 (const_int 4) (const_int 6) 2345 (const_int 8) (const_int 10) 2346 (const_int 12) (const_int 14)])))] 2347 "ISA_HAS_MSA" 2348 "pckev.h\t%w0,%w2,%w1" 2349 [(set_attr "type" "simd_permute") 2350 (set_attr "mode" "V8HI")]) 2351 2352(define_insn "msa_pckev_w" 2353[(set (match_operand:V4SI 0 "register_operand" "=f") 2354 (vec_select:V4SI 2355 (vec_concat:V8SI 2356 (match_operand:V4SI 1 "register_operand" "f") 2357 (match_operand:V4SI 2 "register_operand" "f")) 2358 (parallel [(const_int 0) (const_int 2) 2359 (const_int 4) (const_int 6)])))] 2360 "ISA_HAS_MSA" 2361 "pckev.w\t%w0,%w2,%w1" 2362 [(set_attr "type" "simd_permute") 2363 (set_attr "mode" "V4SI")]) 2364 2365(define_insn "msa_pckev_w_f" 2366[(set (match_operand:V4SF 0 "register_operand" "=f") 2367 (vec_select:V4SF 2368 (vec_concat:V8SF 2369 (match_operand:V4SF 1 "register_operand" "f") 2370 (match_operand:V4SF 2 "register_operand" "f")) 2371 (parallel [(const_int 0) (const_int 2) 2372 (const_int 4) (const_int 6)])))] 2373 "ISA_HAS_MSA" 2374 "pckev.w\t%w0,%w2,%w1" 2375 [(set_attr "type" "simd_permute") 2376 (set_attr "mode" "V4SF")]) 2377 2378(define_insn "msa_pckod_b" 2379[(set (match_operand:V16QI 0 "register_operand" "=f") 2380 (vec_select:V16QI 2381 (vec_concat:V32QI 2382 (match_operand:V16QI 1 "register_operand" "f") 2383 (match_operand:V16QI 2 "register_operand" "f")) 2384 (parallel [(const_int 1) (const_int 3) 2385 (const_int 5) (const_int 7) 2386 (const_int 9) (const_int 11) 2387 (const_int 13) (const_int 15) 2388 (const_int 17) (const_int 19) 2389 (const_int 21) (const_int 23) 2390 (const_int 25) (const_int 27) 2391 (const_int 29) (const_int 31)])))] 2392 "ISA_HAS_MSA" 2393 "pckod.b\t%w0,%w2,%w1" 2394 [(set_attr "type" "simd_permute") 2395 (set_attr "mode" "V16QI")]) 2396 2397(define_insn "msa_pckod_h" 2398[(set (match_operand:V8HI 0 "register_operand" "=f") 2399 (vec_select:V8HI 2400 (vec_concat:V16HI 2401 (match_operand:V8HI 1 "register_operand" "f") 2402 (match_operand:V8HI 2 "register_operand" "f")) 2403 (parallel [(const_int 1) (const_int 3) 2404 (const_int 5) (const_int 7) 2405 (const_int 9) (const_int 11) 2406 (const_int 13) (const_int 15)])))] 2407 "ISA_HAS_MSA" 2408 "pckod.h\t%w0,%w2,%w1" 2409 [(set_attr "type" "simd_permute") 2410 (set_attr "mode" "V8HI")]) 2411 2412(define_insn "msa_pckod_w" 2413[(set (match_operand:V4SI 0 "register_operand" "=f") 2414 (vec_select:V4SI 2415 (vec_concat:V8SI 2416 (match_operand:V4SI 1 "register_operand" "f") 2417 (match_operand:V4SI 2 "register_operand" "f")) 2418 (parallel [(const_int 1) (const_int 3) 2419 (const_int 5) (const_int 7)])))] 2420 "ISA_HAS_MSA" 2421 "pckod.w\t%w0,%w2,%w1" 2422 [(set_attr "type" "simd_permute") 2423 (set_attr "mode" "V4SI")]) 2424 2425(define_insn "msa_pckod_w_f" 2426[(set (match_operand:V4SF 0 "register_operand" "=f") 2427 (vec_select:V4SF 2428 (vec_concat:V8SF 2429 (match_operand:V4SF 1 "register_operand" "f") 2430 (match_operand:V4SF 2 "register_operand" "f")) 2431 (parallel [(const_int 1) (const_int 3) 2432 (const_int 5) (const_int 7)])))] 2433 "ISA_HAS_MSA" 2434 "pckod.w\t%w0,%w2,%w1" 2435 [(set_attr "type" "simd_permute") 2436 (set_attr "mode" "V4SF")]) 2437 2438(define_insn "popcount<mode>2" 2439 [(set (match_operand:IMSA 0 "register_operand" "=f") 2440 (popcount:IMSA (match_operand:IMSA 1 "register_operand" "f")))] 2441 "ISA_HAS_MSA" 2442 "pcnt.<msafmt>\t%w0,%w1" 2443 [(set_attr "type" "simd_pcnt") 2444 (set_attr "mode" "<MODE>")]) 2445 2446(define_insn "msa_sat_s_<msafmt>" 2447 [(set (match_operand:IMSA 0 "register_operand" "=f") 2448 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 2449 (match_operand 2 "const_<bitimm>_operand" "")] 2450 UNSPEC_MSA_SAT_S))] 2451 "ISA_HAS_MSA" 2452 "sat_s.<msafmt>\t%w0,%w1,%2" 2453 [(set_attr "type" "simd_sat") 2454 (set_attr "mode" "<MODE>")]) 2455 2456(define_insn "msa_sat_u_<msafmt>" 2457 [(set (match_operand:IMSA 0 "register_operand" "=f") 2458 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 2459 (match_operand 2 "const_<bitimm>_operand" "")] 2460 UNSPEC_MSA_SAT_U))] 2461 "ISA_HAS_MSA" 2462 "sat_u.<msafmt>\t%w0,%w1,%2" 2463 [(set_attr "type" "simd_sat") 2464 (set_attr "mode" "<MODE>")]) 2465 2466(define_insn "msa_shf_<msafmt_f>" 2467 [(set (match_operand:MSA_WHB_W 0 "register_operand" "=f") 2468 (vec_select:MSA_WHB_W 2469 (match_operand:MSA_WHB_W 1 "register_operand" "f") 2470 (match_operand 2 "par_const_vector_shf_set_operand" "")))] 2471 "ISA_HAS_MSA" 2472{ 2473 HOST_WIDE_INT val = 0; 2474 unsigned int i; 2475 2476 /* We convert the selection to an immediate. */ 2477 for (i = 0; i < 4; i++) 2478 val |= INTVAL (XVECEXP (operands[2], 0, i)) << (2 * i); 2479 2480 operands[2] = GEN_INT (val); 2481 return "shf.<msafmt>\t%w0,%w1,%X2"; 2482} 2483 [(set_attr "type" "simd_shf") 2484 (set_attr "mode" "<MODE>")]) 2485 2486(define_insn "msa_srar_<msafmt>" 2487 [(set (match_operand:IMSA 0 "register_operand" "=f") 2488 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 2489 (match_operand:IMSA 2 "register_operand" "f")] 2490 UNSPEC_MSA_SRAR))] 2491 "ISA_HAS_MSA" 2492 "srar.<msafmt>\t%w0,%w1,%w2" 2493 [(set_attr "type" "simd_shift") 2494 (set_attr "mode" "<MODE>")]) 2495 2496(define_insn "msa_srari_<msafmt>" 2497 [(set (match_operand:IMSA 0 "register_operand" "=f") 2498 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 2499 (match_operand 2 "const_<bitimm>_operand" "")] 2500 UNSPEC_MSA_SRARI))] 2501 "ISA_HAS_MSA" 2502 "srari.<msafmt>\t%w0,%w1,%2" 2503 [(set_attr "type" "simd_shift") 2504 (set_attr "mode" "<MODE>")]) 2505 2506(define_insn "msa_srlr_<msafmt>" 2507 [(set (match_operand:IMSA 0 "register_operand" "=f") 2508 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 2509 (match_operand:IMSA 2 "register_operand" "f")] 2510 UNSPEC_MSA_SRLR))] 2511 "ISA_HAS_MSA" 2512 "srlr.<msafmt>\t%w0,%w1,%w2" 2513 [(set_attr "type" "simd_shift") 2514 (set_attr "mode" "<MODE>")]) 2515 2516(define_insn "msa_srlri_<msafmt>" 2517 [(set (match_operand:IMSA 0 "register_operand" "=f") 2518 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 2519 (match_operand 2 "const_<bitimm>_operand" "")] 2520 UNSPEC_MSA_SRLRI))] 2521 "ISA_HAS_MSA" 2522 "srlri.<msafmt>\t%w0,%w1,%2" 2523 [(set_attr "type" "simd_shift") 2524 (set_attr "mode" "<MODE>")]) 2525 2526(define_insn "msa_subs_s_<msafmt>" 2527 [(set (match_operand:IMSA 0 "register_operand" "=f") 2528 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 2529 (match_operand:IMSA 2 "register_operand" "f")] 2530 UNSPEC_MSA_SUBS_S))] 2531 "ISA_HAS_MSA" 2532 "subs_s.<msafmt>\t%w0,%w1,%w2" 2533 [(set_attr "type" "simd_int_arith") 2534 (set_attr "mode" "<MODE>")]) 2535 2536(define_insn "msa_subs_u_<msafmt>" 2537 [(set (match_operand:IMSA 0 "register_operand" "=f") 2538 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 2539 (match_operand:IMSA 2 "register_operand" "f")] 2540 UNSPEC_MSA_SUBS_U))] 2541 "ISA_HAS_MSA" 2542 "subs_u.<msafmt>\t%w0,%w1,%w2" 2543 [(set_attr "type" "simd_int_arith") 2544 (set_attr "mode" "<MODE>")]) 2545 2546(define_insn "msa_subsuu_s_<msafmt>" 2547 [(set (match_operand:IMSA 0 "register_operand" "=f") 2548 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 2549 (match_operand:IMSA 2 "register_operand" "f")] 2550 UNSPEC_MSA_SUBSUU_S))] 2551 "ISA_HAS_MSA" 2552 "subsuu_s.<msafmt>\t%w0,%w1,%w2" 2553 [(set_attr "type" "simd_int_arith") 2554 (set_attr "mode" "<MODE>")]) 2555 2556(define_insn "msa_subsus_u_<msafmt>" 2557 [(set (match_operand:IMSA 0 "register_operand" "=f") 2558 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f") 2559 (match_operand:IMSA 2 "register_operand" "f")] 2560 UNSPEC_MSA_SUBSUS_U))] 2561 "ISA_HAS_MSA" 2562 "subsus_u.<msafmt>\t%w0,%w1,%w2" 2563 [(set_attr "type" "simd_int_arith") 2564 (set_attr "mode" "<MODE>")]) 2565 2566(define_insn "msa_sld_<msafmt_f>" 2567 [(set (match_operand:MSA 0 "register_operand" "=f") 2568 (unspec:MSA [(match_operand:MSA 1 "register_operand" "0") 2569 (match_operand:MSA 2 "register_operand" "f") 2570 (match_operand:SI 3 "reg_or_0_operand" "dJ")] 2571 UNSPEC_MSA_SLD))] 2572 "ISA_HAS_MSA" 2573 "sld.<msafmt>\t%w0,%w2[%z3]" 2574 [(set_attr "type" "simd_sld") 2575 (set_attr "mode" "<MODE>")]) 2576 2577(define_insn "msa_sldi_<msafmt_f>" 2578 [(set (match_operand:MSA 0 "register_operand" "=f") 2579 (unspec:MSA [(match_operand:MSA 1 "register_operand" "0") 2580 (match_operand:MSA 2 "register_operand" "f") 2581 (match_operand 3 "const_<indeximm>_operand" "")] 2582 UNSPEC_MSA_SLDI))] 2583 "ISA_HAS_MSA" 2584 "sldi.<msafmt>\t%w0,%w2[%3]" 2585 [(set_attr "type" "simd_sld") 2586 (set_attr "mode" "<MODE>")]) 2587 2588(define_insn "msa_splat_<msafmt_f>" 2589 [(set (match_operand:MSA 0 "register_operand" "=f") 2590 (unspec:MSA [(match_operand:MSA 1 "register_operand" "f") 2591 (match_operand:SI 2 "register_operand" "d")] 2592 UNSPEC_MSA_SPLAT))] 2593 "ISA_HAS_MSA" 2594 "splat.<msafmt>\t%w0,%w1[%z2]" 2595 [(set_attr "type" "simd_splat") 2596 (set_attr "mode" "<MODE>")]) 2597 2598(define_insn "msa_splati_<msafmt_f>" 2599 [(set (match_operand:MSA 0 "register_operand" "=f") 2600 (vec_duplicate:MSA 2601 (vec_select:<UNITMODE> 2602 (match_operand:MSA 1 "register_operand" "f") 2603 (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))] 2604 "ISA_HAS_MSA" 2605 "splati.<msafmt>\t%w0,%w1[%2]" 2606 [(set_attr "type" "simd_splat") 2607 (set_attr "mode" "<MODE>")]) 2608 2609(define_insn "msa_splati_<msafmt_f>_scalar" 2610 [(set (match_operand:FMSA 0 "register_operand" "=f") 2611 (unspec:FMSA [(match_operand:<UNITMODE> 1 "register_operand" "f")] 2612 UNSPEC_MSA_SPLATI))] 2613 "ISA_HAS_MSA" 2614 "splati.<msafmt>\t%w0,%w1[0]" 2615 [(set_attr "type" "simd_splat") 2616 (set_attr "mode" "<MODE>")]) 2617 2618(define_insn "msa_cfcmsa" 2619 [(set (match_operand:SI 0 "register_operand" "=d") 2620 (unspec_volatile:SI [(match_operand 1 "const_uimm5_operand" "")] 2621 UNSPEC_MSA_CFCMSA))] 2622 "ISA_HAS_MSA" 2623 "cfcmsa\t%0,$%1" 2624 [(set_attr "type" "simd_cmsa") 2625 (set_attr "mode" "SI")]) 2626 2627(define_insn "msa_ctcmsa" 2628 [(unspec_volatile [(match_operand 0 "const_uimm5_operand" "") 2629 (match_operand:SI 1 "register_operand" "d")] 2630 UNSPEC_MSA_CTCMSA)] 2631 "ISA_HAS_MSA" 2632 "ctcmsa\t$%0,%1" 2633 [(set_attr "type" "simd_cmsa") 2634 (set_attr "mode" "SI")]) 2635 2636(define_insn "msa_fexdo_h" 2637 [(set (match_operand:V8HI 0 "register_operand" "=f") 2638 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "f") 2639 (match_operand:V4SF 2 "register_operand" "f")] 2640 UNSPEC_MSA_FEXDO))] 2641 "ISA_HAS_MSA" 2642 "fexdo.h\t%w0,%w1,%w2" 2643 [(set_attr "type" "simd_fcvt") 2644 (set_attr "mode" "V8HI")]) 2645 2646(define_insn "vec_pack_trunc_v2df" 2647 [(set (match_operand:V4SF 0 "register_operand" "=f") 2648 (vec_concat:V4SF 2649 (float_truncate:V2SF (match_operand:V2DF 1 "register_operand" "f")) 2650 (float_truncate:V2SF (match_operand:V2DF 2 "register_operand" "f"))))] 2651 "ISA_HAS_MSA" 2652 "fexdo.w\t%w0,%w2,%w1" 2653 [(set_attr "type" "simd_fcvt") 2654 (set_attr "mode" "V4SF")]) 2655 2656(define_insn "msa_fexupl_w" 2657 [(set (match_operand:V4SF 0 "register_operand" "=f") 2658 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "f")] 2659 UNSPEC_MSA_FEXUPL))] 2660 "ISA_HAS_MSA" 2661 "fexupl.w\t%w0,%w1" 2662 [(set_attr "type" "simd_fcvt") 2663 (set_attr "mode" "V4SF")]) 2664 2665(define_insn "msa_fexupl_d" 2666 [(set (match_operand:V2DF 0 "register_operand" "=f") 2667 (float_extend:V2DF 2668 (vec_select:V2SF 2669 (match_operand:V4SF 1 "register_operand" "f") 2670 (parallel [(const_int 2) (const_int 3)]))))] 2671 "ISA_HAS_MSA" 2672 "fexupl.d\t%w0,%w1" 2673 [(set_attr "type" "simd_fcvt") 2674 (set_attr "mode" "V2DF")]) 2675 2676(define_insn "msa_fexupr_w" 2677 [(set (match_operand:V4SF 0 "register_operand" "=f") 2678 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "f")] 2679 UNSPEC_MSA_FEXUPR))] 2680 "ISA_HAS_MSA" 2681 "fexupr.w\t%w0,%w1" 2682 [(set_attr "type" "simd_fcvt") 2683 (set_attr "mode" "V4SF")]) 2684 2685(define_insn "msa_fexupr_d" 2686 [(set (match_operand:V2DF 0 "register_operand" "=f") 2687 (float_extend:V2DF 2688 (vec_select:V2SF 2689 (match_operand:V4SF 1 "register_operand" "f") 2690 (parallel [(const_int 0) (const_int 1)]))))] 2691 "ISA_HAS_MSA" 2692 "fexupr.d\t%w0,%w1" 2693 [(set_attr "type" "simd_fcvt") 2694 (set_attr "mode" "V2DF")]) 2695 2696(define_code_attr msabr 2697 [(eq "bz") 2698 (ne "bnz")]) 2699 2700(define_code_attr msabr_neg 2701 [(eq "bnz") 2702 (ne "bz")]) 2703 2704(define_insn "msa_<msabr>_<msafmt_f>" 2705 [(set (pc) (if_then_else 2706 (equality_op 2707 (unspec:SI [(match_operand:MSA 1 "register_operand" "f")] 2708 UNSPEC_MSA_BRANCH) 2709 (match_operand:SI 2 "const_0_operand")) 2710 (label_ref (match_operand 0)) 2711 (pc)))] 2712 "ISA_HAS_MSA" 2713{ 2714 return mips_output_conditional_branch (insn, operands, 2715 MIPS_BRANCH ("<msabr>.<msafmt>", 2716 "%w1,%0"), 2717 MIPS_BRANCH ("<msabr_neg>.<msafmt>", 2718 "%w1,%0")); 2719} 2720 [(set_attr "type" "simd_branch") 2721 (set_attr "mode" "<MODE>") 2722 (set_attr "compact_form" "never") 2723 (set_attr "branch_likely" "no")]) 2724 2725(define_insn "msa_<msabr>_v_<msafmt_f>" 2726 [(set (pc) (if_then_else 2727 (equality_op 2728 (unspec:SI [(match_operand:MSA 1 "register_operand" "f")] 2729 UNSPEC_MSA_BRANCH_V) 2730 (match_operand:SI 2 "const_0_operand")) 2731 (label_ref (match_operand 0)) 2732 (pc)))] 2733 "ISA_HAS_MSA" 2734{ 2735 return mips_output_conditional_branch (insn, operands, 2736 MIPS_BRANCH ("<msabr>.v", "%w1,%0"), 2737 MIPS_BRANCH ("<msabr_neg>.v", 2738 "%w1,%0")); 2739} 2740 [(set_attr "type" "simd_branch") 2741 (set_attr "mode" "TI") 2742 (set_attr "compact_form" "never") 2743 (set_attr "branch_likely" "no")]) 2744