1;; DFA-based pipeline description for MIPS32 models M5100. 2;; 3;; Copyright (C) 2015-2020 Free Software Foundation, Inc. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_automaton "m51_alu_pipe, m51_mdu_pipe, m51_fpu_pipe") 22(define_cpu_unit "m51_mul" "m51_mdu_pipe") 23(define_cpu_unit "m51_alu" "m51_alu_pipe") 24(define_cpu_unit "m51_fpu" "m51_fpu_pipe") 25 26;; -------------------------------------------------------------- 27;; ALU Instructions 28;; -------------------------------------------------------------- 29 30;; ALU: Logicals 31(define_insn_reservation "m51_int_logical" 1 32 (and (eq_attr "cpu" "m5100") 33 (eq_attr "type" "logical,move,signext,slt")) 34 "m51_alu") 35 36;; Arithmetics 37(define_insn_reservation "m51_int" 1 38 (and (eq_attr "cpu" "m5100") 39 (eq_attr "type" "arith,const,shift,clz")) 40 "m51_alu") 41 42(define_insn_reservation "m51_int_nop" 0 43 (and (eq_attr "cpu" "m5100") 44 (eq_attr "type" "nop")) 45 "nothing") 46 47;; Conditional move 48(define_insn_reservation "m51_int_cmove" 1 49 (and (eq_attr "cpu" "m5100") 50 (and (eq_attr "type" "condmove") 51 (eq_attr "mode" "SI,DI"))) 52 "m51_alu") 53 54;; Call 55(define_insn_reservation "m51_int_call" 1 56 (and (eq_attr "cpu" "m5100") 57 (eq_attr "type" "call")) 58 "m51_alu") 59 60;; branch/jump 61(define_insn_reservation "m51_int_jump" 1 62 (and (eq_attr "cpu" "m5100") 63 (eq_attr "type" "branch,jump")) 64 "m51_alu") 65 66;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs 67;; prefetch: prefetch, prefetchx 68(define_insn_reservation "m51_int_load" 2 69 (and (eq_attr "cpu" "m5100") 70 (eq_attr "type" "load,prefetch,prefetchx")) 71 "m51_alu") 72 73;; stores 74(define_insn_reservation "m51_int_store" 1 75 (and (eq_attr "cpu" "m5100") 76 (eq_attr "type" "store")) 77 "m51_alu") 78 79;; -------------------------------------------------------------- 80;; MDU Instructions 81;; -------------------------------------------------------------- 82 83;; High performance fully pipelined multiplier 84;; MULT to HI/LO 85(define_insn_reservation "m51_int_mult" 2 86 (and (eq_attr "cpu" "m5100") 87 (eq_attr "type" "imul,imadd")) 88 "m51_alu+m51_mul*2") 89 90;; MUL to GPR 91(define_insn_reservation "m51_int_mul3" 2 92 (and (eq_attr "cpu" "m5100") 93 (eq_attr "type" "imul3")) 94 "(m51_alu*2)+(m51_mul*2)") 95 96;; mfhi, mflo 97(define_insn_reservation "m51_int_mfhilo" 1 98 (and (eq_attr "cpu" "m5100") 99 (eq_attr "type" "mfhi,mflo")) 100 "m51_mul") 101 102;; mthi, mtlo 103(define_insn_reservation "m51_int_mthilo" 1 104 (and (eq_attr "cpu" "m5100") 105 (eq_attr "type" "mthi,mtlo")) 106 "m51_mul") 107 108;; div 109(define_insn_reservation "m51_int_div_si" 34 110 (and (eq_attr "cpu" "m5100") 111 (eq_attr "type" "idiv")) 112 "m51_alu+m51_mul*34") 113 114;; -------------------------------------------------------------- 115;; Floating Point Instructions 116;; -------------------------------------------------------------- 117 118;; fadd, fabs, fneg 119(define_insn_reservation "m51_fadd" 4 120 (and (eq_attr "cpu" "m5100") 121 (eq_attr "type" "fadd,fabs,fneg")) 122 "m51_fpu") 123 124;; fmove 125(define_insn_reservation "m51_fmove" 4 126 (and (eq_attr "cpu" "m5100") 127 (eq_attr "type" "fmove")) 128 "m51_fpu") 129 130;; conditional move 131(define_insn_reservation "m51_fp_cmove" 4 132 (and (eq_attr "cpu" "m5100") 133 (and (eq_attr "type" "condmove") 134 (eq_attr "mode" "SF,DF"))) 135 "m51_fpu") 136 137;; fload 138(define_insn_reservation "m51_fload" 3 139 (and (eq_attr "cpu" "m5100") 140 (eq_attr "type" "fpload,fpidxload")) 141 "m51_fpu") 142 143;; fstore 144(define_insn_reservation "m51_fstore" 1 145 (and (eq_attr "cpu" "m5100") 146 (eq_attr "type" "fpstore,fpidxstore")) 147 "m51_fpu") 148 149;; fmul, fmadd 150(define_insn_reservation "m51_fmul_sf" 4 151 (and (eq_attr "cpu" "m5100") 152 (and (eq_attr "type" "fmul,fmadd") 153 (eq_attr "mode" "SF"))) 154 "m51_fpu") 155 156(define_insn_reservation "m51_fmul_df" 5 157 (and (eq_attr "cpu" "m5100") 158 (and (eq_attr "type" "fmul,fmadd") 159 (eq_attr "mode" "DF"))) 160 "m51_fpu*2") 161 162;; fdiv, fsqrt 163(define_insn_reservation "m51_fdiv_sf" 17 164 (and (eq_attr "cpu" "m5100") 165 (and (eq_attr "type" "fdiv,fsqrt") 166 (eq_attr "mode" "SF"))) 167 "m51_fpu*14") 168 169(define_insn_reservation "m51_fdiv_df" 32 170 (and (eq_attr "cpu" "m5100") 171 (and (eq_attr "type" "fdiv,fsqrt") 172 (eq_attr "mode" "DF"))) 173 "m51_fpu*29") 174 175;; frsqrt 176(define_insn_reservation "m51_frsqrt_sf" 17 177 (and (eq_attr "cpu" "m5100") 178 (and (eq_attr "type" "frsqrt") 179 (eq_attr "mode" "SF"))) 180 "m51_fpu*14") 181 182(define_insn_reservation "m51_frsqrt_df" 35 183 (and (eq_attr "cpu" "m5100") 184 (and (eq_attr "type" "frsqrt") 185 (eq_attr "mode" "DF"))) 186 "m51_fpu*31") 187 188;; fcmp 189(define_insn_reservation "m51_fcmp" 4 190 (and (eq_attr "cpu" "m5100") 191 (eq_attr "type" "fcmp")) 192 "m51_fpu") 193 194;; fcvt 195;; cvt.s.d 196(define_insn_reservation "m51_fcvt_6" 6 197 (and (eq_attr "cpu" "m5100") 198 (and (eq_attr "type" "fcvt") 199 (eq_attr "cnv_mode" "D2S"))) 200 "m51_fpu") 201 202;; trunc 203(define_insn_reservation "m51_fcvt_5" 5 204 (and (eq_attr "cpu" "m5100") 205 (and (eq_attr "type" "fcvt") 206 (eq_attr "cnv_mode" "D2I,S2I"))) 207 "m51_fpu") 208 209;; cvt 210(define_insn_reservation "m51_fcvt_4" 4 211 (and (eq_attr "cpu" "m5100") 212 (and (eq_attr "type" "fcvt") 213 (eq_attr "cnv_mode" "S2D,I2D,I2S"))) 214 "m51_fpu") 215 216;; mtc, mfc 217(define_insn_reservation "m51_move_to_from_c1" 2 218 (and (eq_attr "cpu" "m5100") 219 (eq_attr "type" "mtc, mfc")) 220 "m51_fpu") 221