1 /* Definitions of target machine for GNU compiler for Xilinx MicroBlaze. 2 Copyright (C) 2009-2017 Free Software Foundation, Inc. 3 4 Contributed by Michael Eager <eager@eagercon.com>. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify it 9 under the terms of the GNU General Public License as published 10 by the Free Software Foundation; either version 3, or (at your 11 option) any later version. 12 13 GCC is distributed in the hope that it will be useful, but WITHOUT 14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 /* Standard GCC variables that we reference. */ 23 24 /* MicroBlaze external variables defined in microblaze.c. */ 25 26 /* Which pipeline to schedule for. */ 27 enum pipeline_type 28 { 29 MICROBLAZE_PIPE_3 = 0, 30 MICROBLAZE_PIPE_5 = 1 31 }; 32 33 #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001 34 35 /* print_operand punctuation chars */ 36 extern char microblaze_print_operand_punct[]; 37 38 /* # bytes of data/sdata cutoff */ 39 extern int microblaze_section_threshold; 40 41 /* Map register # to debug register # */ 42 extern int microblaze_dbx_regno[]; 43 44 extern int microblaze_no_unsafe_delay; 45 extern int microblaze_has_clz; 46 extern enum pipeline_type microblaze_pipe; 47 48 #define OBJECT_FORMAT_ELF 49 50 #if TARGET_BIG_ENDIAN_DEFAULT 51 #define TARGET_ENDIAN_DEFAULT 0 52 #define TARGET_ENDIAN_OPTION "mbig-endian" 53 #else 54 #define TARGET_ENDIAN_DEFAULT MASK_LITTLE_ENDIAN 55 #define TARGET_ENDIAN_OPTION "mlittle-endian" 56 #endif 57 58 /* Default target_flags if no switches are specified */ 59 #define TARGET_DEFAULT (MASK_SOFT_MUL | MASK_SOFT_DIV | MASK_SOFT_FLOAT \ 60 | TARGET_ENDIAN_DEFAULT) 61 62 /* Do we have CLZ? */ 63 #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz) 64 65 /* The default is to support PIC. */ 66 #define TARGET_SUPPORTS_PIC 1 67 68 /* The default is to not need GOT for TLS. */ 69 #define TLS_NEEDS_GOT 0 70 71 /* What is the default setting for -mcpu= . We set it to v4.00.a even though 72 we are actually ahead. This is safest version that has generate code 73 compatible for the original ISA */ 74 #define MICROBLAZE_DEFAULT_CPU "v4.00.a" 75 76 /* Macros to decide whether certain features are available or not, 77 depending on the instruction set architecture level. */ 78 79 #define DRIVER_SELF_SPECS \ 80 "%{mxl-soft-mul:%<mno-xl-soft-mul}", \ 81 "%{mno-xl-barrel-shift:%<mxl-barrel-shift}", \ 82 "%{mno-xl-pattern-compare:%<mxl-pattern-compare}", \ 83 "%{mxl-soft-div:%<mno-xl-soft-div}", \ 84 "%{mxl-reorder:%<mno-xl-reorder}", \ 85 "%{msoft-float:%<mhard-float}" 86 87 /* Tell collect what flags to pass to nm. */ 88 #ifndef NM_FLAGS 89 #define NM_FLAGS "-Bn" 90 #endif 91 92 /* Names to predefine in the preprocessor for this target machine. */ 93 #define TARGET_CPU_CPP_BUILTINS() microblaze_cpp_define (pfile) 94 95 /* Assembler specs. */ 96 97 #define TARGET_ASM_SPEC "" 98 99 #define ASM_SPEC "\ 100 %(target_asm_spec) \ 101 %{mbig-endian:-EB} \ 102 %{mlittle-endian:-EL}" 103 104 /* Extra switches sometimes passed to the linker. */ 105 /* -xl-mode-xmdstub translated to -Zxl-mode-xmdstub -- deprecated. */ 106 107 #define LINK_SPEC "%{shared:-shared} -N -relax \ 108 %{mbig-endian:-EB --oformat=elf32-microblaze} \ 109 %{mlittle-endian:-EL --oformat=elf32-microblazeel} \ 110 %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ 111 %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ 112 %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \ 113 %{!T*: -dT xilinx.ld%s}" 114 115 /* Specs for the compiler proper */ 116 117 #ifndef CC1_SPEC 118 #define CC1_SPEC " \ 119 %{G*} \ 120 %(subtarget_cc1_spec) \ 121 %{mxl-multiply-high:-mcpu=v6.00.a} \ 122 " 123 #endif 124 125 #define EXTRA_SPECS \ 126 { "target_asm_spec", TARGET_ASM_SPEC }, \ 127 SUBTARGET_EXTRA_SPECS 128 129 /* Local compiler-generated symbols must have a prefix that the assembler 130 understands. */ 131 132 #ifndef LOCAL_LABEL_PREFIX 133 #define LOCAL_LABEL_PREFIX "$" 134 #endif 135 136 /* fixed registers. */ 137 #define MB_ABI_BASE_REGNUM 0 138 #define MB_ABI_STACK_POINTER_REGNUM 1 139 #define MB_ABI_GPRO_REGNUM 2 140 #define MB_ABI_GPRW_REGNUM 13 141 #define MB_ABI_INTR_RETURN_ADDR_REGNUM 14 142 #define MB_ABI_SUB_RETURN_ADDR_REGNUM 15 143 #define MB_ABI_DEBUG_RETURN_ADDR_REGNUM 16 144 #define MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM 17 145 #define MB_ABI_ASM_TEMP_REGNUM 18 146 /* This is our temp register. */ 147 #define MB_ABI_FRAME_POINTER_REGNUM 19 148 #define MB_ABI_PIC_ADDR_REGNUM 20 149 #define MB_ABI_PIC_FUNC_REGNUM 21 150 /* Volatile registers. */ 151 #define MB_ABI_INT_RETURN_VAL_REGNUM 3 152 #define MB_ABI_INT_RETURN_VAL2_REGNUM 4 153 #define MB_ABI_FIRST_ARG_REGNUM 5 154 #define MB_ABI_LAST_ARG_REGNUM 10 155 #define MB_ABI_MAX_ARG_REGS (MB_ABI_LAST_ARG_REGNUM \ 156 - MB_ABI_FIRST_ARG_REGNUM + 1) 157 #define MB_ABI_STATIC_CHAIN_REGNUM 3 158 #define MB_ABI_TEMP1_REGNUM 11 159 #define MB_ABI_TEMP2_REGNUM 12 160 #define MB_ABI_MSR_SAVE_REG 11 161 /* Volatile register used to save MSR in interrupt handlers. */ 162 163 164 /* Debug stuff. */ 165 166 /* How to renumber registers for dbx and gdb. */ 167 #define DBX_REGISTER_NUMBER(REGNO) microblaze_dbx_regno[(REGNO)] 168 169 /* Generate DWARF exception handling info. */ 170 #define DWARF2_UNWIND_INFO 1 171 172 /* Don't generate .loc operations. */ 173 #define DWARF2_ASM_LINE_DEBUG_INFO 0 174 175 /* The DWARF 2 CFA column which tracks the return address. */ 176 #define DWARF_FRAME_RETURN_COLUMN \ 177 (GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM) 178 179 /* Initial state of return address on entry to func = R15. 180 Actually, the RA is at R15+8, but gcc doesn't know how 181 to generate this. 182 NOTE: GDB has a workaround and expects this incorrect value. 183 If this is fixed, a corresponding fix to GDB is needed. */ 184 #define INCOMING_RETURN_ADDR_RTX \ 185 gen_rtx_REG (Pmode, GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM) 186 187 /* Specifies the offset from INCOMING_RETURN_ADDR_RTX and the actual return PC. */ 188 #define RETURN_ADDR_OFFSET (8) 189 190 /* Describe how we implement __builtin_eh_return. */ 191 #define EH_RETURN_DATA_REGNO(N) \ 192 (((N) < 2) ? MB_ABI_FIRST_ARG_REGNUM + (N) : INVALID_REGNUM) 193 194 #define MB_EH_STACKADJ_REGNUM MB_ABI_INT_RETURN_VAL2_REGNUM 195 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, MB_EH_STACKADJ_REGNUM) 196 197 /* Select a format to encode pointers in exception handling data. CODE 198 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 199 true if the symbol may be affected by dynamic relocations. */ 200 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 201 ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr) 202 203 /* Use DWARF 2 debugging information by default. */ 204 #define DWARF2_DEBUGGING_INFO 205 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 206 207 /* Target machine storage layout */ 208 209 #define BITS_BIG_ENDIAN 0 210 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) 211 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 212 #define BITS_PER_WORD 32 213 #define UNITS_PER_WORD 4 214 #define MIN_UNITS_PER_WORD 4 215 #define INT_TYPE_SIZE 32 216 #define SHORT_TYPE_SIZE 16 217 #define LONG_TYPE_SIZE 32 218 #define LONG_LONG_TYPE_SIZE 64 219 #define FLOAT_TYPE_SIZE 32 220 #define DOUBLE_TYPE_SIZE 64 221 #define LONG_DOUBLE_TYPE_SIZE 64 222 #define POINTER_SIZE 32 223 #define PARM_BOUNDARY 32 224 #define FUNCTION_BOUNDARY 32 225 #define EMPTY_FIELD_BOUNDARY 32 226 #define STRUCTURE_SIZE_BOUNDARY 8 227 #define BIGGEST_ALIGNMENT 32 228 #define STRICT_ALIGNMENT 1 229 #define PCC_BITFIELD_TYPE_MATTERS 1 230 231 #undef SIZE_TYPE 232 #define SIZE_TYPE "unsigned int" 233 234 #undef PTRDIFF_TYPE 235 #define PTRDIFF_TYPE "int" 236 237 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 238 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ 239 && (ALIGN) < BITS_PER_WORD \ 240 ? BITS_PER_WORD \ 241 : (ALIGN)) 242 243 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 244 ((((ALIGN) < BITS_PER_WORD) \ 245 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 246 || TREE_CODE (TYPE) == UNION_TYPE \ 247 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 248 249 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 250 (((TREE_CODE (TYPE) == ARRAY_TYPE \ 251 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \ 252 && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN)) 253 254 #define WORD_REGISTER_OPERATIONS 1 255 256 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 257 258 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 259 if (GET_MODE_CLASS (MODE) == MODE_INT \ 260 && GET_MODE_SIZE (MODE) < 4) \ 261 (MODE) = SImode; 262 263 /* Standard register usage. */ 264 265 /* On the MicroBlaze, we have 32 integer registers */ 266 267 #define FIRST_PSEUDO_REGISTER 36 268 269 #define FIXED_REGISTERS \ 270 { \ 271 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ 272 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 273 1, 1, 1, 1 \ 274 } 275 276 #define CALL_USED_REGISTERS \ 277 { \ 278 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 279 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 280 1, 1, 1, 1 \ 281 } 282 #define GP_REG_FIRST 0 283 #define GP_REG_LAST 31 284 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 285 #define GP_DBX_FIRST 0 286 287 #define ST_REG 32 288 #define AP_REG_NUM 33 289 #define RAP_REG_NUM 34 290 #define FRP_REG_NUM 35 291 292 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM) 293 #define ST_REG_P(REGNO) ((REGNO) == ST_REG) 294 295 #define HARD_REGNO_NREGS(REGNO, MODE) \ 296 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 297 298 /* Value is 1 if hard register REGNO can hold a value of machine-mode 299 MODE. In 32 bit mode, require that DImode and DFmode be in even 300 registers. For DImode, this makes some of the insns easier to 301 write, since you don't have to worry about a DImode value in 302 registers 3 & 4, producing a result in 4 & 5. 303 304 To make the code simpler HARD_REGNO_MODE_OK now just references an 305 array built in override_options. Because machmodes.h is not yet 306 included before this file is processed, the MODE bound can't be 307 expressed here. */ 308 extern char microblaze_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; 309 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 310 microblaze_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO)] 311 312 #define MODES_TIEABLE_P(MODE1, MODE2) \ 313 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ 314 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 315 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \ 316 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) 317 318 #define STACK_POINTER_REGNUM (GP_REG_FIRST + MB_ABI_STACK_POINTER_REGNUM) 319 320 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(FNDECL) 321 322 /* Base register for access to local variables of the function. We 323 pretend that the frame pointer is 324 MB_ABI_INTR_RETURN_ADDR_REGNUM, and then eliminate it 325 to HARD_FRAME_POINTER_REGNUM. We can get away with this because 326 rMB_ABI_INTR_RETUREN_ADDR_REGNUM is a fixed 327 register(return address for interrupt), and will not be used for 328 anything else. */ 329 330 #define FRAME_POINTER_REGNUM FRP_REG_NUM 331 #define HARD_FRAME_POINTER_REGNUM \ 332 (GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM) 333 #define ARG_POINTER_REGNUM AP_REG_NUM 334 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM 335 #define STATIC_CHAIN_REGNUM \ 336 (GP_REG_FIRST + MB_ABI_STATIC_CHAIN_REGNUM) 337 338 /* registers used in prologue/epilogue code when the stack frame 339 is larger than 32K bytes. These registers must come from the 340 scratch register set, and not used for passing and returning 341 arguments and any other information used in the calling sequence 342 (such as pic). */ 343 344 #define MICROBLAZE_TEMP1_REGNUM \ 345 (GP_REG_FIRST + MB_ABI_TEMP1_REGNUM) 346 347 #define MICROBLAZE_TEMP2_REGNUM \ 348 (GP_REG_FIRST + MB_ABI_TEMP2_REGNUM) 349 350 #define NO_FUNCTION_CSE 1 351 352 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + MB_ABI_PIC_ADDR_REGNUM) 353 354 enum reg_class 355 { 356 NO_REGS, /* no registers in set. */ 357 GR_REGS, /* integer registers. */ 358 ST_REGS, /* status register. */ 359 ALL_REGS, /* all registers. */ 360 LIM_REG_CLASSES /* max value + 1. */ 361 }; 362 363 #define N_REG_CLASSES (int) LIM_REG_CLASSES 364 365 #define GENERAL_REGS GR_REGS 366 367 #define REG_CLASS_NAMES \ 368 { \ 369 "NO_REGS", \ 370 "GR_REGS", \ 371 "ST_REGS", \ 372 "ALL_REGS" \ 373 } 374 375 #define REG_CLASS_CONTENTS \ 376 { \ 377 { 0x00000000, 0x00000000 }, /* no registers. */ \ 378 { 0xffffffff, 0x00000000 }, /* integer registers. */ \ 379 { 0x00000000, 0x00000001 }, /* status registers. */ \ 380 { 0xffffffff, 0x0000000f } /* all registers. */ \ 381 } 382 383 extern enum reg_class microblaze_regno_to_class[]; 384 385 #define REGNO_REG_CLASS(REGNO) microblaze_regno_to_class[ (REGNO) ] 386 387 #define BASE_REG_CLASS GR_REGS 388 389 #define INDEX_REG_CLASS GR_REGS 390 391 #define GR_REG_CLASS_P(CLASS) ((CLASS) == GR_REGS) 392 393 /* REGISTER AND CONSTANT CLASSES */ 394 395 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000) 396 #define LARGE_INT(X) \ 397 (INTVAL (X) > 0 && UINTVAL (X) >= 0x80000000 && UINTVAL (X) <= 0xffffffff) 398 #define PLT_ADDR_P(X) (GET_CODE (X) == UNSPEC && XINT (X,1) == UNSPEC_PLT) 399 /* Test for a valid operand for a call instruction. 400 Don't allow the arg pointer register or virtual regs 401 since they may change into reg + const, which the patterns 402 can't handle yet. */ 403 #define CALL_INSN_OP(X) (CONSTANT_ADDRESS_P (X) \ 404 || (GET_CODE (X) == REG && X != arg_pointer_rtx\ 405 && ! (REGNO (X) >= FIRST_PSEUDO_REGISTER \ 406 && REGNO (X) <= LAST_VIRTUAL_REGISTER))) 407 408 /* True if VALUE is a signed 16-bit number. */ 409 #define SMALL_OPERAND(VALUE) \ 410 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000) 411 412 /* Constant which cannot be loaded in one instruction. */ 413 #define LARGE_OPERAND(VALUE) \ 414 ((((VALUE) & ~0x0000ffff) != 0) \ 415 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \ 416 && (((VALUE) & 0x0000ffff) != 0 \ 417 || (((VALUE) & ~2147483647) != 0 \ 418 && ((VALUE) & ~2147483647) != ~2147483647))) 419 420 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 421 ((CLASS) != ALL_REGS \ 422 ? (CLASS) \ 423 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ 424 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \ 425 ? (GR_REGS) \ 426 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ 427 || GET_MODE (X) == VOIDmode) \ 428 ? (GR_REGS) : (CLASS)))) 429 430 /* Stack layout; function entry, exit and calling. */ 431 432 #define STACK_GROWS_DOWNWARD 1 433 434 /* Changed the starting frame offset to including the new link stuff */ 435 #define STARTING_FRAME_OFFSET \ 436 (crtl->outgoing_args_size + FIRST_PARM_OFFSET(FNDECL)) 437 438 /* The return address for the current frame is in r31 if this is a leaf 439 function. Otherwise, it is on the stack. It is at a variable offset 440 from sp/fp/ap, so we define a fake hard register rap which is a 441 poiner to the return address on the stack. This always gets eliminated 442 during reload to be either the frame pointer or the stack pointer plus 443 an offset. */ 444 445 #define RETURN_ADDR_RTX(count, frame) \ 446 microblaze_return_addr(count,frame) 447 448 extern struct microblaze_frame_info current_frame_info; 449 450 #define ELIMINABLE_REGS \ 451 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 452 { ARG_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \ 453 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 454 { RETURN_ADDRESS_POINTER_REGNUM, \ 455 GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \ 456 { RETURN_ADDRESS_POINTER_REGNUM, \ 457 GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM}, \ 458 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 459 { FRAME_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}} 460 461 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 462 (OFFSET) = microblaze_initial_elimination_offset ((FROM), (TO)) 463 464 #define ACCUMULATE_OUTGOING_ARGS 1 465 466 #define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD) 467 468 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 469 470 #define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) 471 472 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 473 474 #define STACK_BOUNDARY 32 475 476 #define NUM_OF_ARGS 6 477 478 #define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM) 479 480 #define GP_ARG_FIRST (GP_REG_FIRST + MB_ABI_FIRST_ARG_REGNUM) 481 #define GP_ARG_LAST (GP_REG_FIRST + MB_ABI_LAST_ARG_REGNUM) 482 483 #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS 484 485 #define LIBCALL_VALUE(MODE) \ 486 gen_rtx_REG ( \ 487 ((GET_MODE_CLASS (MODE) != MODE_INT \ 488 || GET_MODE_SIZE (MODE) >= 4) \ 489 ? (MODE) \ 490 : SImode), GP_RETURN) 491 492 /* 1 if N is a possible register number for a function value. 493 On the MicroBlaze, R2 R3 are the only register thus used. 494 Currently, R2 are only implemented here (C has no complex type) */ 495 496 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN) 497 498 #define FUNCTION_ARG_REGNO_P(N) (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST)) 499 500 typedef struct microblaze_args 501 { 502 int gp_reg_found; /* whether a gp register was found yet */ 503 int arg_number; /* argument number */ 504 int arg_words; /* # total words the arguments take */ 505 int fp_arg_words; /* # words for FP args */ 506 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */ 507 int fp_code; /* Mode of FP arguments */ 508 int num_adjusts; /* number of adjustments made */ 509 /* Adjustments made to args pass in regs. */ 510 /* ??? The size is doubled to work around a bug in the code that sets the 511 adjustments in function_arg. */ 512 rtx adjust[MAX_ARGS_IN_REGISTERS * 2]; 513 } CUMULATIVE_ARGS; 514 515 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \ 516 init_cumulative_args (&CUM, FNTYPE, LIBNAME) 517 518 #define NO_PROFILE_COUNTERS 1 519 520 #define FUNCTION_PROFILER(FILE, LABELNO) { \ 521 { \ 522 fprintf (FILE, "\tbrki\tr16,_mcount\n"); \ 523 } \ 524 } 525 526 #define EXIT_IGNORE_STACK 1 527 528 /* 4 insns + 2 words of data. */ 529 #define TRAMPOLINE_SIZE (6 * 4) 530 531 #define TRAMPOLINE_ALIGNMENT 32 532 533 #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) 534 535 #define REGNO_OK_FOR_INDEX_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) 536 537 #ifndef REG_OK_STRICT 538 #define REG_STRICT_FLAG 0 539 #else 540 #define REG_STRICT_FLAG 1 541 #endif 542 543 #define REG_OK_FOR_BASE_P(X) \ 544 microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG) 545 546 #define REG_OK_FOR_INDEX_P(X) \ 547 microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG) 548 549 #define MAX_REGS_PER_ADDRESS 2 550 551 552 /* Identify valid constant addresses. Exclude if PIC addr which 553 needs scratch register. */ 554 #define CONSTANT_ADDRESS_P(X) \ 555 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 556 || GET_CODE (X) == CONST_INT \ 557 || (GET_CODE (X) == CONST \ 558 && ! (flag_pic && pic_address_needs_scratch (X)))) 559 560 /* Define this, so that when PIC, reload won't try to reload invalid 561 addresses which require two reload registers. */ 562 #define LEGITIMATE_PIC_OPERAND_P(X) microblaze_legitimate_pic_operand (X) 563 564 #define CASE_VECTOR_MODE (SImode) 565 566 #ifndef DEFAULT_SIGNED_CHAR 567 #define DEFAULT_SIGNED_CHAR 1 568 #endif 569 570 #define MOVE_MAX 4 571 #define MAX_MOVE_MAX 8 572 573 #define SLOW_BYTE_ACCESS 1 574 575 /* sCOND operations return 1. */ 576 #define STORE_FLAG_VALUE 1 577 578 #define SHIFT_COUNT_TRUNCATED 1 579 580 /* This results in inefficient code for 64 bit to 32 conversions. 581 Something needs to be done about this. Perhaps not use any 32 bit 582 instructions? Perhaps use PROMOTE_MODE? */ 583 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 584 585 #define Pmode SImode 586 587 #define FUNCTION_MODE SImode 588 589 /* Mode should always be SImode */ 590 #define REGISTER_MOVE_COST(MODE, FROM, TO) \ 591 ( GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? 2 \ 592 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \ 593 : 12) 594 595 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \ 596 (4 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P))) 597 598 #define BRANCH_COST(speed_p, predictable_p) 2 599 600 /* Control the assembler format that we output. */ 601 #define ASM_APP_ON " #APP\n" 602 #define ASM_APP_OFF " #NO_APP\n" 603 604 #define REGISTER_NAMES { \ 605 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 606 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 607 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ 608 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ 609 "rmsr", "$ap", "$rap", "$frp" } 610 611 #define ADDITIONAL_REGISTER_NAMES \ 612 { \ 613 { "r0", 0 + GP_REG_FIRST }, \ 614 { "r1", 1 + GP_REG_FIRST }, \ 615 { "r2", 2 + GP_REG_FIRST }, \ 616 { "r3", 3 + GP_REG_FIRST }, \ 617 { "r4", 4 + GP_REG_FIRST }, \ 618 { "r5", 5 + GP_REG_FIRST }, \ 619 { "r6", 6 + GP_REG_FIRST }, \ 620 { "r7", 7 + GP_REG_FIRST }, \ 621 { "r8", 8 + GP_REG_FIRST }, \ 622 { "r9", 9 + GP_REG_FIRST }, \ 623 { "r10", 10 + GP_REG_FIRST }, \ 624 { "r11", 11 + GP_REG_FIRST }, \ 625 { "r12", 12 + GP_REG_FIRST }, \ 626 { "r13", 13 + GP_REG_FIRST }, \ 627 { "r14", 14 + GP_REG_FIRST }, \ 628 { "r15", 15 + GP_REG_FIRST }, \ 629 { "r16", 16 + GP_REG_FIRST }, \ 630 { "r17", 17 + GP_REG_FIRST }, \ 631 { "r18", 18 + GP_REG_FIRST }, \ 632 { "r19", 19 + GP_REG_FIRST }, \ 633 { "r20", 20 + GP_REG_FIRST }, \ 634 { "r21", 21 + GP_REG_FIRST }, \ 635 { "r22", 22 + GP_REG_FIRST }, \ 636 { "r23", 23 + GP_REG_FIRST }, \ 637 { "r24", 24 + GP_REG_FIRST }, \ 638 { "r25", 25 + GP_REG_FIRST }, \ 639 { "r26", 26 + GP_REG_FIRST }, \ 640 { "r27", 27 + GP_REG_FIRST }, \ 641 { "r28", 28 + GP_REG_FIRST }, \ 642 { "r29", 29 + GP_REG_FIRST }, \ 643 { "r30", 30 + GP_REG_FIRST }, \ 644 { "r31", 31 + GP_REG_FIRST }, \ 645 { "rmsr", ST_REG} \ 646 } 647 648 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 649 650 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) microblaze_print_operand_punct[CODE] 651 652 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 653 654 /* ASM_OUTPUT_ALIGNED_COMMON and ASM_OUTPUT_ALIGNED_LOCAL 655 656 Unfortunately, we still need to set the section explicitly. Somehow, 657 our binutils assign .comm and .lcomm variables to the "current" section 658 in the assembly file, rather than where they implicitly belong. We need to 659 remove this explicit setting in GCC when binutils can understand sections 660 better. */ 661 #undef ASM_OUTPUT_ALIGNED_COMMON 662 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ 663 do { \ 664 if ((SIZE) > 0 && (SIZE) <= INT_MAX \ 665 && (int) (SIZE) <= microblaze_section_threshold \ 666 && TARGET_XLGPOPT) \ 667 { \ 668 switch_to_section (sbss_section); \ 669 } \ 670 else \ 671 { \ 672 switch_to_section (bss_section); \ 673 } \ 674 fprintf (FILE, "%s", COMMON_ASM_OP); \ 675 assemble_name ((FILE), (NAME)); \ 676 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \ 677 (SIZE), (ALIGN) / BITS_PER_UNIT); \ 678 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \ 679 } while (0) 680 681 #undef ASM_OUTPUT_ALIGNED_LOCAL 682 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ 683 do { \ 684 if ((SIZE) > 0 && (SIZE) <= INT_MAX \ 685 && (int) (SIZE) <= microblaze_section_threshold \ 686 && TARGET_XLGPOPT) \ 687 { \ 688 switch_to_section (sbss_section); \ 689 } \ 690 else \ 691 { \ 692 switch_to_section (bss_section); \ 693 } \ 694 fprintf (FILE, "%s", LCOMMON_ASM_OP); \ 695 assemble_name ((FILE), (NAME)); \ 696 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \ 697 (SIZE), (ALIGN) / BITS_PER_UNIT); \ 698 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \ 699 } while (0) 700 701 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 702 do { \ 703 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ 704 } while (0) 705 706 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ 707 { \ 708 } 709 710 #undef TARGET_ASM_CONSTRUCTOR 711 #define TARGET_ASM_CONSTRUCTOR microblaze_elf_asm_constructor 712 713 #undef TARGET_ASM_DESTRUCTOR 714 #define TARGET_ASM_DESTRUCTOR microblaze_elf_asm_destructor 715 716 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 717 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) 718 719 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 720 fprintf (STREAM, "\t%s\t%sL%d\n", \ 721 ".gpword", \ 722 LOCAL_LABEL_PREFIX, VALUE) 723 724 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 725 do { \ 726 if (flag_pic == 2) \ 727 fprintf (STREAM, "\t%s\t%sL%d@GOTOFF\n", \ 728 ".gpword", \ 729 LOCAL_LABEL_PREFIX, VALUE); \ 730 else \ 731 fprintf (STREAM, "\t%s\t%sL%d\n", \ 732 ".gpword", \ 733 LOCAL_LABEL_PREFIX, VALUE); \ 734 } while (0) 735 736 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ 737 fprintf (STREAM, "\t.align\t%d\n", (LOG)) 738 739 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \ 740 fprintf (STREAM, "\t.space\t%lu\n", (SIZE)) 741 742 #define ASCII_DATA_ASM_OP "\t.ascii\t" 743 #define STRING_ASM_OP "\t.asciz\t" 744 745 #undef TARGET_ASM_OUTPUT_IDENT 746 #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident 747 748 /* Default to -G 8 */ 749 #ifndef MICROBLAZE_DEFAULT_GVALUE 750 #define MICROBLAZE_DEFAULT_GVALUE 8 751 #endif 752 753 /* Given a decl node or constant node, choose the section to output it in 754 and select that section. */ 755 756 /* Store in OUTPUT a string (made with alloca) containing 757 an assembler-name for a local static variable named NAME. 758 LABELNO is an integer which is different for each call. */ 759 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 760 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 13), \ 761 sprintf ((OUTPUT), "%s.%lu", (NAME), (unsigned long)(LABELNO))) 762 763 /* How to start an assembler comment. 764 The leading space is important (the microblaze assembler requires it). */ 765 #ifndef ASM_COMMENT_START 766 #define ASM_COMMENT_START " #" 767 #endif 768 769 #define BSS_VAR 1 770 #define SBSS_VAR 2 771 #define DATA_VAR 4 772 #define SDATA_VAR 5 773 #define RODATA_VAR 6 774 #define SDATA2_VAR 7 775 776 /* These definitions are used in with the shift_type flag in the rtl. */ 777 #define SHIFT_CONST 1 778 #define SHIFT_REG 2 779 #define USE_ADDK 3 780 781 /* Handle interrupt attribute. */ 782 extern int interrupt_handler; 783 extern int fast_interrupt; 784 extern int save_volatiles; 785 786 #define INTERRUPT_HANDLER_NAME "_interrupt_handler" 787 /* The function name for the function tagged with attribute break_handler 788 has been set in the RTL as _break_handler. This function name is used 789 in the generation of directives .ent .end and .global. */ 790 #define BREAK_HANDLER_NAME "_break_handler" 791 #define FAST_INTERRUPT_NAME "_fast_interrupt" 792 793 /* The following #defines are used in the headers files. Always retain these. */ 794 795 /* Added for declaring size at the end of the function. */ 796 #undef ASM_DECLARE_FUNCTION_SIZE 797 #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ 798 do { \ 799 if (!flag_inhibit_size_directive) \ 800 { \ 801 char label[256]; \ 802 static int labelno; \ 803 labelno++; \ 804 ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \ 805 (*targetm.asm_out.internal_label) (FILE, "Lfe", labelno); \ 806 fprintf (FILE, "%s", SIZE_ASM_OP); \ 807 assemble_name (FILE, (FNAME)); \ 808 fprintf (FILE, ","); \ 809 assemble_name (FILE, label); \ 810 fprintf (FILE, "-"); \ 811 assemble_name (FILE, (FNAME)); \ 812 putc ('\n', FILE); \ 813 } \ 814 } while (0) 815 816 #define GLOBAL_ASM_OP "\t.globl\t" 817 #define TYPE_ASM_OP "\t.type\t" 818 #define SIZE_ASM_OP "\t.size\t" 819 #define COMMON_ASM_OP "\t.comm\t" 820 #define LCOMMON_ASM_OP "\t.lcomm\t" 821 822 #define MAX_OFILE_ALIGNMENT (32768*8) 823 824 #define TYPE_OPERAND_FMT "@%s" 825 826 /* Write the extra assembler code needed to declare an object properly. */ 827 #undef ASM_DECLARE_OBJECT_NAME 828 #define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \ 829 do { \ 830 fprintf (FILE, "%s", TYPE_ASM_OP); \ 831 assemble_name (FILE, NAME); \ 832 putc (',', FILE); \ 833 fprintf (FILE, TYPE_OPERAND_FMT, "object"); \ 834 putc ('\n', FILE); \ 835 size_directive_output = 0; \ 836 if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \ 837 { \ 838 size_directive_output = 1; \ 839 fprintf (FILE, "%s", SIZE_ASM_OP); \ 840 assemble_name (FILE, NAME); \ 841 fprintf (FILE, "," HOST_WIDE_INT_PRINT_DEC "\n", \ 842 int_size_in_bytes (TREE_TYPE (DECL))); \ 843 } \ 844 microblaze_declare_object (FILE, NAME, "", ":\n", 0); \ 845 } while (0) 846 847 #undef ASM_FINISH_DECLARE_OBJECT 848 #define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ 849 do { \ 850 const char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ 851 if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \ 852 && ! AT_END && TOP_LEVEL \ 853 && DECL_INITIAL (DECL) == error_mark_node \ 854 && !size_directive_output) \ 855 { \ 856 size_directive_output = 1; \ 857 fprintf (FILE, "%s", SIZE_ASM_OP); \ 858 assemble_name (FILE, name); \ 859 fprintf (FILE, "," HOST_WIDE_INT_PRINT_DEC "\n", \ 860 int_size_in_bytes (TREE_TYPE (DECL))); \ 861 } \ 862 } while (0) 863 864 #define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ 865 do { fputc ( '\t', FILE); \ 866 assemble_name (FILE, LABEL1); \ 867 fputs ( " = ", FILE); \ 868 assemble_name (FILE, LABEL2); \ 869 fputc ( '\n', FILE); \ 870 } while (0) 871 872 #define ASM_WEAKEN_LABEL(FILE,NAME) \ 873 do { fputs ("\t.weakext\t", FILE); \ 874 assemble_name (FILE, NAME); \ 875 fputc ('\n', FILE); \ 876 } while (0) 877 878 #define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1) 879 #undef UNIQUE_SECTION_P 880 #define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL)) 881 882 #undef TARGET_ASM_NAMED_SECTION 883 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section 884 885 /* Define the strings to put out for each section in the object file. 886 887 Note: For ctors/dtors, we want to give these sections the SHF_WRITE 888 attribute to allow shared libraries to patch/resolve addresses into 889 these locations. On Microblaze, there is no concept of shared libraries 890 yet, so this is for future use. */ 891 #define TEXT_SECTION_ASM_OP "\t.text" 892 #define DATA_SECTION_ASM_OP "\t.data" 893 #define READONLY_DATA_SECTION_ASM_OP \ 894 "\t.rodata" 895 #define BSS_SECTION_ASM_OP "\t.bss" 896 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\"" 897 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\"" 898 #define INIT_SECTION_ASM_OP "\t.section\t.init,\"ax\"" 899 #define FINI_SECTION_ASM_OP "\t.section\t.fini,\"ax\"" 900 901 #define SDATA_SECTION_ASM_OP "\t.sdata" /* Small RW initialized data */ 902 #define SDATA2_SECTION_ASM_OP "\t.sdata2" /* Small RO initialized data */ 903 #define SBSS_SECTION_ASM_OP "\t.sbss" /* Small RW uninitialized data */ 904 #define SBSS2_SECTION_ASM_OP "\t.sbss2" /* Small RO uninitialized data */ 905 906 /* We do this to save a few 10s of code space that would be taken up 907 by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION 908 definition in crtstuff.c. */ 909 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 910 asm ( SECTION_OP "\n" \ 911 "\tbrlid r15, " #FUNC "\n\t nop\n" \ 912 TEXT_SECTION_ASM_OP); 913 914 /* We need to group -lm as well, since some Newlib math functions 915 reference __errno! */ 916 #undef LIB_SPEC 917 #define LIB_SPEC \ 918 "%{!nostdlib: \ 919 %{pg:-start-group -lxilprofile -lgloss -lxil -lc -lm -end-group } \ 920 %{!pg:-start-group -lgloss -lxil -lc -lm -end-group }} " 921 922 /* microblaze-unknown-elf target has no support of C99 runtime */ 923 #undef TARGET_LIBC_HAS_FUNCTION 924 #define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function 925 926 #undef ENDFILE_SPEC 927 #define ENDFILE_SPEC "crtend.o%s crtn.o%s" 928 929 #define STARTFILE_EXECUTABLE_SPEC "crt0.o%s crti.o%s crtbegin.o%s" 930 #define STARTFILE_XMDSTUB_SPEC "crt1.o%s crti.o%s crtbegin.o%s" 931 #define STARTFILE_BOOTSTRAP_SPEC "crt2.o%s crti.o%s crtbegin.o%s" 932 #define STARTFILE_NOVECTORS_SPEC "crt3.o%s crti.o%s crtbegin.o%s" 933 #define STARTFILE_CRTINIT_SPEC "%{!pg: %{!mno-clearbss: crtinit.o%s} \ 934 %{mno-clearbss: sim-crtinit.o%s}} \ 935 %{pg: %{!mno-clearbss: pgcrtinit.o%s} %{mno-clearbss: sim-pgcrtinit.o%s}}" 936 937 #define STARTFILE_DEFAULT_SPEC STARTFILE_EXECUTABLE_SPEC 938 939 #undef SUBTARGET_EXTRA_SPECS 940 #define SUBTARGET_EXTRA_SPECS \ 941 { "startfile_executable", STARTFILE_EXECUTABLE_SPEC }, \ 942 { "startfile_xmdstub", STARTFILE_XMDSTUB_SPEC }, \ 943 { "startfile_bootstrap", STARTFILE_BOOTSTRAP_SPEC }, \ 944 { "startfile_novectors", STARTFILE_NOVECTORS_SPEC }, \ 945 { "startfile_crtinit", STARTFILE_CRTINIT_SPEC }, \ 946 { "startfile_default", STARTFILE_DEFAULT_SPEC }, 947 948 #undef STARTFILE_SPEC 949 #define STARTFILE_SPEC "\ 950 %{Zxl-mode-executable : %(startfile_executable) ; \ 951 mxl-mode-executable : %(startfile_executable) ; \ 952 Zxl-mode-xmdstub : %(startfile_xmdstub) ; \ 953 mxl-mode-xmdstub : %(startfile_xmdstub) ; \ 954 Zxl-mode-bootstrap : %(startfile_bootstrap) ; \ 955 mxl-mode-bootstrap : %(startfile_bootstrap) ; \ 956 Zxl-mode-novectors : %(startfile_novectors) ; \ 957 mxl-mode-novectors : %(startfile_novectors) ; \ 958 Zxl-mode-xilkernel : %(startfile_xilkernel) ; \ 959 mxl-mode-xilkernel : %(startfile_xilkernel) ; \ 960 : %(startfile_default) \ 961 } \ 962 %(startfile_crtinit)" 963