1;; Machine Descriptions for R8C/M16C/M32C 2;; Copyright (C) 2005-2020 Free Software Foundation, Inc. 3;; Contributed by Red Hat. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;; Predicates 22 23; TRUE for any valid operand. We do this because general_operand 24; refuses to match volatile memory refs. 25 26(define_predicate "m32c_any_operand" 27 (ior (match_operand 0 "general_operand") 28 (match_code "mem,const_int,const_double")) 29 { 30 return ! m32c_illegal_subreg_p (op); 31 } 32) 33 34; Likewise for nonimmediate_operand. 35 36(define_predicate "m32c_nonimmediate_operand" 37 (ior (match_operand 0 "nonimmediate_operand") 38 (match_code "mem")) 39 { 40 return ! m32c_illegal_subreg_p (op); 41 } 42) 43 44; TRUE if the operand is a pseudo-register. 45(define_predicate "m32c_pseudo" 46 (ior (and (match_code "reg") 47 (match_test "REGNO(op) >= FIRST_PSEUDO_REGISTER")) 48 (and (match_code "subreg") 49 (and (match_test "GET_CODE (XEXP (op, 0)) == REG") 50 (match_test "REGNO(XEXP (op,0)) >= FIRST_PSEUDO_REGISTER"))))) 51 52 53; Returning true causes many predicates to NOT match. We allow 54; subregs for type changing, but not for size changing. 55(define_predicate "m32c_wide_subreg" 56 (and (match_code "subreg") 57 (not (match_operand 0 "m32c_pseudo"))) 58 { 59 unsigned int sizeo = GET_MODE_SIZE (GET_MODE (op)); 60 unsigned int sizei = GET_MODE_SIZE (GET_MODE (XEXP (op, 0))); 61 sizeo = (sizeo + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 62 sizei = (sizei + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 63 return sizeo != sizei; 64 }) 65 66; TRUE for r0 through r3, or a pseudo that reload could put in r0 67; through r3 (likewise for the next couple too) 68(define_predicate "r0123_operand" 69 (ior (match_operand 0 "m32c_pseudo" "") 70 (and (match_code "reg") 71 (match_test "REGNO(op) <= R3_REGNO")))) 72 73; TRUE for r0 74(define_predicate "m32c_r0_operand" 75 (ior (match_operand 0 "m32c_pseudo" "") 76 (and (match_code "reg") 77 (match_test "REGNO(op) == R0_REGNO")))) 78 79; TRUE for r1 80(define_predicate "m32c_r1_operand" 81 (ior (match_operand 0 "m32c_pseudo" "") 82 (and (match_code "reg") 83 (match_test "REGNO(op) == R1_REGNO")))) 84 85; TRUE for HL_CLASS (r0 or r1) 86(define_predicate "m32c_hl_operand" 87 (ior (match_operand 0 "m32c_pseudo" "") 88 (and (match_code "reg") 89 (match_test "REGNO(op) == R0_REGNO || REGNO(op) == R1_REGNO")))) 90 91 92; TRUE for r2 93(define_predicate "m32c_r2_operand" 94 (ior (match_operand 0 "m32c_pseudo" "") 95 (and (match_code "reg") 96 (match_test "REGNO(op) == R2_REGNO")))) 97 98; TRUE for r3 99(define_predicate "m32c_r3_operand" 100 (ior (match_operand 0 "m32c_pseudo" "") 101 (and (match_code "reg") 102 (match_test "REGNO(op) == R3_REGNO")))) 103 104; TRUE for any general operand except r2. 105(define_predicate "m32c_notr2_operand" 106 (and (match_operand 0 "general_operand") 107 (ior (not (match_code "reg")) 108 (match_test "REGNO(op) != R2_REGNO")))) 109 110; TRUE for the stack pointer. 111(define_predicate "m32c_sp_operand" 112 (ior (match_operand 0 "m32c_pseudo" "") 113 (and (match_code "reg") 114 (match_test "REGNO(op) == SP_REGNO")))) 115 116; TRUE for control registers. 117(define_predicate "cr_operand" 118 (match_code "reg") 119 "return (REGNO (op) >= SB_REGNO 120 && REGNO (op) <= FLG_REGNO);") 121 122; TRUE for $a0 or $a1. 123(define_predicate "a_operand" 124 (and (match_code "reg") 125 (match_test "REGNO (op) == A0_REGNO || REGNO (op) == A1_REGNO"))) 126 127; TRUE for $a0 or $a1 or a pseudo 128(define_predicate "ap_operand" 129 (ior (match_operand 0 "m32c_pseudo" "") 130 (and (match_code "reg") 131 (match_test "REGNO (op) == A0_REGNO || REGNO (op) == A1_REGNO")))) 132 133; TRUE for r0 through r3, or a0 or a1. 134(define_predicate "ra_operand" 135 (and (and (match_operand 0 "register_operand" "") 136 (not (match_operand 1 "cr_operand" ""))) 137 (not (match_operand 2 "m32c_wide_subreg" "")))) 138 139; Likewise, plus TRUE for memory references. 140(define_predicate "mra_operand" 141 (and (and (match_operand 0 "m32c_nonimmediate_operand" "") 142 (not (match_operand 1 "cr_operand" ""))) 143 (not (match_operand 2 "m32c_wide_subreg" "")))) 144 145; Likewise, plus TRUE for subregs. 146(define_predicate "mras_operand" 147 (and (match_operand 0 "nonimmediate_operand" "") 148 (not (match_operand 1 "cr_operand" "")))) 149 150; As above, but no push/pop operations 151(define_predicate "mra_nopp_operand" 152 (match_operand 0 "mra_operand" "") 153{ 154 if (GET_CODE (op) == MEM 155 && (GET_CODE (XEXP (op, 0)) == PRE_DEC 156 || (GET_CODE (XEXP (op, 0)) == POST_INC))) 157 return 0; 158 return 1; 159}) 160 161; TRUE for memory, r0..r3, a0..a1, or immediates. 162(define_predicate "mrai_operand" 163 (and (and (match_operand 0 "m32c_any_operand" "") 164 (not (match_operand 1 "cr_operand" ""))) 165 (not (match_operand 2 "m32c_wide_subreg" "")))) 166 167; Likewise, plus true for subregs. 168(define_predicate "mrasi_operand" 169 (and (match_operand 0 "general_operand" "") 170 (not (match_operand 1 "cr_operand" "")))) 171 172; TRUE for r0..r3 or memory. 173(define_predicate "mr_operand" 174 (and (match_operand 0 "mra_operand" "") 175 (not (match_operand 1 "a_operand" "")))) 176 177; TRUE for a0..a1 or memory. 178(define_predicate "ma_operand" 179 (ior (match_operand 0 "a_operand" "") 180 (match_operand 1 "memory_operand" ""))) 181 182; TRUE for memory operands that are not indexed 183(define_predicate "memsym_operand" 184 (and (match_operand 0 "memory_operand" "") 185 (match_test "satisfies_constraint_Si (op)"))) 186 187; TRUE for memory operands with small integer addresses 188(define_predicate "memimmed_operand" 189 (and (match_operand 0 "memory_operand" "") 190 (match_test "satisfies_constraint_Sp (op)"))) 191 192; TRUE for r1h. This is complicated since r1h isn't a register GCC 193; normally knows about. 194(define_predicate "r1h_operand" 195 (match_code "zero_extract") 196 { 197 rtx reg = XEXP (op, 0); 198 rtx size = XEXP (op, 1); 199 rtx pos = XEXP (op, 2); 200 return (GET_CODE (reg) == REG 201 && REGNO (reg) == R1_REGNO 202 && GET_CODE (size) == CONST_INT 203 && INTVAL (size) == 8 204 && GET_CODE (pos) == CONST_INT 205 && INTVAL (pos) == 8); 206 }) 207 208; TRUE if we can shift by this amount. Constant shift counts have a 209; limited range. 210(define_predicate "shiftcount_operand" 211 (ior (match_operand 0 "mra_operand" "") 212 (and (match_operand 2 "const_int_operand" "") 213 (match_test "INTVAL (op) >= -8 && INTVAL (op) && INTVAL (op) <= 8")))) 214(define_predicate "longshiftcount_operand" 215 (ior (match_operand 0 "mra_operand" "") 216 (and (match_operand 2 "const_int_operand" "") 217 (match_test "INTVAL (op) >= -32 && INTVAL (op) && INTVAL (op) <= 32")))) 218 219; TRUE for r0..r3, a0..a1, or sp. 220(define_predicate "mra_or_sp_operand" 221 (and (ior (match_operand 0 "mra_operand") 222 (match_operand 1 "m32c_sp_operand")) 223 (not (match_operand 2 "m32c_wide_subreg" "")))) 224 225 226; TRUE for r2 or r3. 227(define_predicate "m32c_r2r3_operand" 228 (ior (and (match_code "reg") 229 (ior (match_test "REGNO(op) == R2_REGNO") 230 (match_test "REGNO(op) == R3_REGNO"))) 231 (and (match_code "subreg") 232 (match_test "GET_CODE (XEXP (op, 0)) == REG && (REGNO (XEXP (op, 0)) == R2_REGNO || REGNO (XEXP (op, 0)) == R3_REGNO)")))) 233 234; Likewise, plus TRUE for a0..a1. 235(define_predicate "m32c_r2r3a_operand" 236 (ior (match_operand 0 "m32c_r2r3_operand" "") 237 (match_operand 0 "a_operand" ""))) 238 239; These two are only for movqi - no subreg limit 240(define_predicate "mra_qi_operand" 241 (and (and (match_operand 0 "m32c_nonimmediate_operand" "") 242 (not (match_operand 1 "cr_operand" ""))) 243 (not (match_operand 1 "m32c_r2r3a_operand" "")))) 244 245(define_predicate "mrai_qi_operand" 246 (and (and (match_operand 0 "m32c_any_operand" "") 247 (not (match_operand 1 "cr_operand" ""))) 248 (not (match_operand 1 "m32c_r2r3a_operand" "")))) 249 250(define_predicate "a_qi_operand" 251 (ior (match_operand 0 "m32c_pseudo" "") 252 (match_operand 1 "a_operand" ""))) 253 254; TRUE for comparisons we support. 255(define_predicate "m32c_cmp_operator" 256 (match_code "eq,ne,gt,gtu,lt,ltu,ge,geu,le,leu")) 257 258(define_predicate "m32c_eqne_operator" 259 (match_code "eq,ne")) 260 261; TRUE for mem0 262(define_predicate "m32c_mem0_operand" 263 (ior (match_operand 0 "m32c_pseudo" "") 264 (and (match_code "reg") 265 (match_test "REGNO(op) == MEM0_REGNO")))) 266 267; TRUE for things the call patterns can return. 268(define_predicate "m32c_return_operand" 269 (ior (match_operand 0 "m32c_r0_operand") 270 (ior (match_operand 0 "m32c_mem0_operand") 271 (match_code "parallel")))) 272 273; TRUE for constants we can multiply pointers by 274(define_predicate "m32c_psi_scale" 275 (and (match_operand 0 "const_int_operand") 276 (match_test "satisfies_constraint_Ilb (op)"))) 277 278; TRUE for one bit set (bit) or clear (mask) out of N bits. 279 280(define_predicate "m32c_1bit8_operand" 281 (and (match_operand 0 "const_int_operand") 282 (match_test "satisfies_constraint_Ilb (op)"))) 283 284(define_predicate "m32c_1bit16_operand" 285 (and (match_operand 0 "const_int_operand") 286 (match_test "satisfies_constraint_Ilw (op)"))) 287 288(define_predicate "m32c_1mask8_operand" 289 (and (match_operand 0 "const_int_operand") 290 (match_test "satisfies_constraint_ImB (op)"))) 291 292(define_predicate "m32c_1mask16_operand" 293 (and (match_operand 0 "const_int_operand") 294 (match_test "satisfies_constraint_Imw (op)"))) 295