1;; Itanium2 DFA descriptions for insn scheduling and bundling. 2;; Copyright (C) 2002-2020 Free Software Foundation, Inc. 3;; Contributed by Vladimir Makarov <vmakarov@redhat.com>. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. */ 20;; 21 22/* This is description of pipeline hazards based on DFA. The 23 following constructions can be used for this: 24 25 o define_cpu_unit string [string]) describes a cpu functional unit 26 (separated by comma). 27 28 1st operand: Names of cpu function units. 29 2nd operand: Name of automaton (see comments for 30 DEFINE_AUTOMATON). 31 32 All define_reservations and define_cpu_units should have unique 33 names which cannot be "nothing". 34 35 o (exclusion_set string string) means that each CPU function unit 36 in the first string cannot be reserved simultaneously with each 37 unit whose name is in the second string and vise versa. CPU 38 units in the string are separated by commas. For example, it is 39 useful for description CPU with fully pipelined floating point 40 functional unit which can execute simultaneously only single 41 floating point insns or only double floating point insns. 42 43 o (presence_set string string) means that each CPU function unit in 44 the first string cannot be reserved unless at least one of 45 pattern of units whose names are in the second string is 46 reserved. This is an asymmetric relation. CPU units or unit 47 patterns in the strings are separated by commas. Pattern is one 48 unit name or unit names separated by white-spaces. 49 50 For example, it is useful for description that slot1 is reserved 51 after slot0 reservation for a VLIW processor. We could describe 52 it by the following construction 53 54 (presence_set "slot1" "slot0") 55 56 Or slot1 is reserved only after slot0 and unit b0 reservation. 57 In this case we could write 58 59 (presence_set "slot1" "slot0 b0") 60 61 All CPU functional units in a set should belong to the same 62 automaton. 63 64 o (final_presence_set string string) is analogous to 65 `presence_set'. The difference between them is when checking is 66 done. When an instruction is issued in given automaton state 67 reflecting all current and planned unit reservations, the 68 automaton state is changed. The first state is a source state, 69 the second one is a result state. Checking for `presence_set' is 70 done on the source state reservation, checking for 71 `final_presence_set' is done on the result reservation. This 72 construction is useful to describe a reservation which is 73 actually two subsequent reservations. For example, if we use 74 75 (presence_set "slot1" "slot0") 76 77 the following insn will be never issued (because slot1 requires 78 slot0 which is absent in the source state). 79 80 (define_reservation "insn_and_nop" "slot0 + slot1") 81 82 but it can be issued if we use analogous `final_presence_set'. 83 84 o (absence_set string string) means that each CPU function unit in 85 the first string can be reserved only if each pattern of units 86 whose names are in the second string is not reserved. This is an 87 asymmetric relation (actually exclusion set is analogous to this 88 one but it is symmetric). CPU units or unit patterns in the 89 string are separated by commas. Pattern is one unit name or unit 90 names separated by white-spaces. 91 92 For example, it is useful for description that slot0 cannot be 93 reserved after slot1 or slot2 reservation for a VLIW processor. 94 We could describe it by the following construction 95 96 (absence_set "slot2" "slot0, slot1") 97 98 Or slot2 cannot be reserved if slot0 and unit b0 are reserved or 99 slot1 and unit b1 are reserved . In this case we could write 100 101 (absence_set "slot2" "slot0 b0, slot1 b1") 102 103 All CPU functional units in a set should to belong the same 104 automaton. 105 106 o (final_absence_set string string) is analogous to `absence_set' but 107 checking is done on the result (state) reservation. See comments 108 for final_presence_set. 109 110 o (define_bypass number out_insn_names in_insn_names) names bypass with 111 given latency (the first number) from insns given by the first 112 string (see define_insn_reservation) into insns given by the 113 second string. Insn names in the strings are separated by 114 commas. 115 116 o (define_automaton string) describes names of an automaton 117 generated and used for pipeline hazards recognition. The names 118 are separated by comma. Actually it is possibly to generate the 119 single automaton but unfortunately it can be very large. If we 120 use more one automata, the summary size of the automata usually 121 is less than the single one. The automaton name is used in 122 define_cpu_unit. All automata should have unique names. 123 124 o (automata_option string) describes option for generation of 125 automata. Currently there are the following options: 126 127 o "no-minimization" which makes no minimization of automata. 128 This is only worth to do when we are debugging the description 129 and need to look more accurately at reservations of states. 130 131 o "ndfa" which makes automata with nondeterministic reservation 132 by insns. 133 134 o (define_reservation string string) names reservation (the first 135 string) of cpu functional units (the 2nd string). Sometimes unit 136 reservations for different insns contain common parts. In such 137 case, you describe common part and use one its name (the 1st 138 parameter) in regular expression in define_insn_reservation. All 139 define_reservations, define results and define_cpu_units should 140 have unique names which cannot be "nothing". 141 142 o (define_insn_reservation name default_latency condition regexpr) 143 describes reservation of cpu functional units (the 3nd operand) 144 for instruction which is selected by the condition (the 2nd 145 parameter). The first parameter is used for output of debugging 146 information. The reservations are described by a regular 147 expression according the following syntax: 148 149 regexp = regexp "," oneof 150 | oneof 151 152 oneof = oneof "|" allof 153 | allof 154 155 allof = allof "+" repeat 156 | repeat 157 158 repeat = element "*" number 159 | element 160 161 element = cpu_function_name 162 | reservation_name 163 | result_name 164 | "nothing" 165 | "(" regexp ")" 166 167 1. "," is used for describing start of the next cycle in 168 reservation. 169 170 2. "|" is used for describing the reservation described by the 171 first regular expression *or* the reservation described by 172 the second regular expression *or* etc. 173 174 3. "+" is used for describing the reservation described by the 175 first regular expression *and* the reservation described by 176 the second regular expression *and* etc. 177 178 4. "*" is used for convenience and simply means sequence in 179 which the regular expression are repeated NUMBER times with 180 cycle advancing (see ","). 181 182 5. cpu function unit name which means reservation. 183 184 6. reservation name -- see define_reservation. 185 186 7. string "nothing" means no units reservation. 187 188*/ 189 190(define_automaton "two") 191 192;; All possible combinations of bundles/syllables 193(define_cpu_unit "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ 194 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx" "two") 195(define_cpu_unit "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\ 196 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx." "two") 197(define_cpu_unit "2_0mii., 2_0mmi., 2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\ 198 2_0mib., 2_0mmb., 2_0mfb." "two") 199 200(define_cpu_unit "2_1m.ii, 2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\ 201 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx" "two") 202(define_cpu_unit "2_1mi.i, 2_1mm.i, 2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\ 203 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx." "two") 204(define_cpu_unit "2_1mii., 2_1mmi., 2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\ 205 2_1mib., 2_1mmb., 2_1mfb." "two") 206 207;; Slot 1 208(exclusion_set "2_0m.ii" "2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ 209 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") 210(exclusion_set "2_0m.mi" "2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb, 2_0m.ib,\ 211 2_0m.mb, 2_0m.fb, 2_0m.lx") 212(exclusion_set "2_0m.fi" "2_0m.mf, 2_0b.bb, 2_0m.bb, 2_0m.ib, 2_0m.mb,\ 213 2_0m.fb, 2_0m.lx") 214(exclusion_set "2_0m.mf" "2_0b.bb, 2_0m.bb, 2_0m.ib, 2_0m.mb, 2_0m.fb,\ 215 2_0m.lx") 216(exclusion_set "2_0b.bb" "2_0m.bb, 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") 217(exclusion_set "2_0m.bb" "2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") 218(exclusion_set "2_0m.ib" "2_0m.mb, 2_0m.fb, 2_0m.lx") 219(exclusion_set "2_0m.mb" "2_0m.fb, 2_0m.lx") 220(exclusion_set "2_0m.fb" "2_0m.lx") 221 222;; Slot 2 223(exclusion_set "2_0mi.i" "2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\ 224 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") 225(exclusion_set "2_0mm.i" "2_0mf.i, 2_0mm.f, 2_0bb.b, 2_0mb.b,\ 226 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") 227(exclusion_set "2_0mf.i" "2_0mm.f, 2_0bb.b, 2_0mb.b, 2_0mi.b, 2_0mm.b,\ 228 2_0mf.b, 2_0mlx.") 229(exclusion_set "2_0mm.f" "2_0bb.b, 2_0mb.b, 2_0mi.b, 2_0mm.b, 2_0mf.b,\ 230 2_0mlx.") 231(exclusion_set "2_0bb.b" "2_0mb.b, 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") 232(exclusion_set "2_0mb.b" "2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") 233(exclusion_set "2_0mi.b" "2_0mm.b, 2_0mf.b, 2_0mlx.") 234(exclusion_set "2_0mm.b" "2_0mf.b, 2_0mlx.") 235(exclusion_set "2_0mf.b" "2_0mlx.") 236 237;; Slot 3 238(exclusion_set "2_0mii." "2_0mmi., 2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\ 239 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") 240(exclusion_set "2_0mmi." "2_0mfi., 2_0mmf., 2_0bbb., 2_0mbb.,\ 241 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") 242(exclusion_set "2_0mfi." "2_0mmf., 2_0bbb., 2_0mbb., 2_0mib., 2_0mmb.,\ 243 2_0mfb., 2_0mlx.") 244(exclusion_set "2_0mmf." "2_0bbb., 2_0mbb., 2_0mib., 2_0mmb., 2_0mfb.,\ 245 2_0mlx.") 246(exclusion_set "2_0bbb." "2_0mbb., 2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") 247(exclusion_set "2_0mbb." "2_0mib., 2_0mmb., 2_0mfb., 2_0mlx.") 248(exclusion_set "2_0mib." "2_0mmb., 2_0mfb., 2_0mlx.") 249(exclusion_set "2_0mmb." "2_0mfb., 2_0mlx.") 250(exclusion_set "2_0mfb." "2_0mlx.") 251 252;; Slot 4 253(exclusion_set "2_1m.ii" "2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\ 254 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx") 255(exclusion_set "2_1m.mi" "2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb, 2_1m.ib,\ 256 2_1m.mb, 2_1m.fb, 2_1m.lx") 257(exclusion_set "2_1m.fi" "2_1m.mf, 2_1b.bb, 2_1m.bb, 2_1m.ib, 2_1m.mb,\ 258 2_1m.fb, 2_1m.lx") 259(exclusion_set "2_1m.mf" "2_1b.bb, 2_1m.bb, 2_1m.ib, 2_1m.mb, 2_1m.fb,\ 260 2_1m.lx") 261(exclusion_set "2_1b.bb" "2_1m.bb, 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx") 262(exclusion_set "2_1m.bb" "2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx") 263(exclusion_set "2_1m.ib" "2_1m.mb, 2_1m.fb, 2_1m.lx") 264(exclusion_set "2_1m.mb" "2_1m.fb, 2_1m.lx") 265(exclusion_set "2_1m.fb" "2_1m.lx") 266 267;; Slot 5 268(exclusion_set "2_1mi.i" "2_1mm.i, 2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\ 269 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") 270(exclusion_set "2_1mm.i" "2_1mf.i, 2_1mm.f, 2_1bb.b, 2_1mb.b,\ 271 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") 272(exclusion_set "2_1mf.i" "2_1mm.f, 2_1bb.b, 2_1mb.b, 2_1mi.b, 2_1mm.b,\ 273 2_1mf.b, 2_1mlx.") 274(exclusion_set "2_1mm.f" "2_1bb.b, 2_1mb.b, 2_1mi.b, 2_1mm.b, 2_1mf.b,\ 275 2_1mlx.") 276(exclusion_set "2_1bb.b" "2_1mb.b, 2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") 277(exclusion_set "2_1mb.b" "2_1mi.b, 2_1mm.b, 2_1mf.b, 2_1mlx.") 278(exclusion_set "2_1mi.b" "2_1mm.b, 2_1mf.b, 2_1mlx.") 279(exclusion_set "2_1mm.b" "2_1mf.b, 2_1mlx.") 280(exclusion_set "2_1mf.b" "2_1mlx.") 281 282;; Slot 6 283(exclusion_set "2_1mii." "2_1mmi., 2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\ 284 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") 285(exclusion_set "2_1mmi." "2_1mfi., 2_1mmf., 2_1bbb., 2_1mbb.,\ 286 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") 287(exclusion_set "2_1mfi." "2_1mmf., 2_1bbb., 2_1mbb., 2_1mib., 2_1mmb.,\ 288 2_1mfb., 2_1mlx.") 289(exclusion_set "2_1mmf." "2_1bbb., 2_1mbb., 2_1mib., 2_1mmb., 2_1mfb.,\ 290 2_1mlx.") 291(exclusion_set "2_1bbb." "2_1mbb., 2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") 292(exclusion_set "2_1mbb." "2_1mib., 2_1mmb., 2_1mfb., 2_1mlx.") 293(exclusion_set "2_1mib." "2_1mmb., 2_1mfb., 2_1mlx.") 294(exclusion_set "2_1mmb." "2_1mfb., 2_1mlx.") 295(exclusion_set "2_1mfb." "2_1mlx.") 296 297(final_presence_set "2_0mi.i" "2_0m.ii") 298(final_presence_set "2_0mii." "2_0mi.i") 299(final_presence_set "2_1mi.i" "2_1m.ii") 300(final_presence_set "2_1mii." "2_1mi.i") 301 302(final_presence_set "2_0mm.i" "2_0m.mi") 303(final_presence_set "2_0mmi." "2_0mm.i") 304(final_presence_set "2_1mm.i" "2_1m.mi") 305(final_presence_set "2_1mmi." "2_1mm.i") 306 307(final_presence_set "2_0mf.i" "2_0m.fi") 308(final_presence_set "2_0mfi." "2_0mf.i") 309(final_presence_set "2_1mf.i" "2_1m.fi") 310(final_presence_set "2_1mfi." "2_1mf.i") 311 312(final_presence_set "2_0mm.f" "2_0m.mf") 313(final_presence_set "2_0mmf." "2_0mm.f") 314(final_presence_set "2_1mm.f" "2_1m.mf") 315(final_presence_set "2_1mmf." "2_1mm.f") 316 317(final_presence_set "2_0bb.b" "2_0b.bb") 318(final_presence_set "2_0bbb." "2_0bb.b") 319(final_presence_set "2_1bb.b" "2_1b.bb") 320(final_presence_set "2_1bbb." "2_1bb.b") 321 322(final_presence_set "2_0mb.b" "2_0m.bb") 323(final_presence_set "2_0mbb." "2_0mb.b") 324(final_presence_set "2_1mb.b" "2_1m.bb") 325(final_presence_set "2_1mbb." "2_1mb.b") 326 327(final_presence_set "2_0mi.b" "2_0m.ib") 328(final_presence_set "2_0mib." "2_0mi.b") 329(final_presence_set "2_1mi.b" "2_1m.ib") 330(final_presence_set "2_1mib." "2_1mi.b") 331 332(final_presence_set "2_0mm.b" "2_0m.mb") 333(final_presence_set "2_0mmb." "2_0mm.b") 334(final_presence_set "2_1mm.b" "2_1m.mb") 335(final_presence_set "2_1mmb." "2_1mm.b") 336 337(final_presence_set "2_0mf.b" "2_0m.fb") 338(final_presence_set "2_0mfb." "2_0mf.b") 339(final_presence_set "2_1mf.b" "2_1m.fb") 340(final_presence_set "2_1mfb." "2_1mf.b") 341 342(final_presence_set "2_0mlx." "2_0m.lx") 343(final_presence_set "2_1mlx." "2_1m.lx") 344 345;; The following reflects the dual issue bundle types table. 346;; We could place all possible combinations here because impossible 347;; combinations would go away by the subsequent constrains. 348(final_presence_set 349 "2_1m.lx" 350 "2_0mmi.,2_0mfi.,2_0mmf.,2_0mib.,2_0mmb.,2_0mfb.,2_0mlx.") 351(final_presence_set "2_1b.bb" "2_0mii.,2_0mmi.,2_0mfi.,2_0mmf.,2_0mlx.") 352(final_presence_set 353 "2_1m.ii,2_1m.mi,2_1m.fi,2_1m.mf,2_1m.bb,2_1m.ib,2_1m.mb,2_1m.fb" 354 "2_0mii.,2_0mmi.,2_0mfi.,2_0mmf.,2_0mib.,2_0mmb.,2_0mfb.,2_0mlx.") 355 356;; Ports/units (nb means nop.b insn issued into given port): 357(define_cpu_unit 358 "2_um0, 2_um1, 2_um2, 2_um3, 2_ui0, 2_ui1, 2_uf0, 2_uf1,\ 359 2_ub0, 2_ub1, 2_ub2, 2_unb0, 2_unb1, 2_unb2" "two") 360 361(exclusion_set "2_ub0" "2_unb0") 362(exclusion_set "2_ub1" "2_unb1") 363(exclusion_set "2_ub2" "2_unb2") 364 365;; The following rules are used to decrease number of alternatives. 366;; They are consequences of Itanium2 microarchitecture. They also 367;; describe the following rules mentioned in Itanium2 368;; microarchitecture: rules mentioned in Itanium2 microarchitecture: 369;; o "BBB/MBB: Always splits issue after either of these bundles". 370;; o "MIB BBB: Split issue after the first bundle in this pair". 371(exclusion_set 372 "2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb." 373 "2_1m.ii,2_1m.mi,2_1m.fi,2_1m.mf,2_1b.bb,2_1m.bb,\ 374 2_1m.ib,2_1m.mb,2_1m.fb,2_1m.lx") 375(exclusion_set "2_0m.ib,2_0mi.b,2_0mib." "2_1b.bb") 376 377;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the 378;;; B-slot contains a nop.b or a brp instruction". 379;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or 380;;; nop.b, otherwise it disperses to B2". 381(final_absence_set 382 "2_1m.ii, 2_1m.mi, 2_1m.fi, 2_1m.mf, 2_1b.bb, 2_1m.bb,\ 383 2_1m.ib, 2_1m.mb, 2_1m.fb, 2_1m.lx" 384 "2_0mib. 2_ub2, 2_0mfb. 2_ub2, 2_0mmb. 2_ub2") 385 386;; This is necessary to start new processor cycle when we meet stop bit. 387(define_cpu_unit "2_stop" "two") 388(final_absence_set 389 "2_0m.ii,2_0mi.i,2_0mii.,2_0m.mi,2_0mm.i,2_0mmi.,2_0m.fi,2_0mf.i,2_0mfi.,\ 390 2_0m.mf,2_0mm.f,2_0mmf.,2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb.,\ 391 2_0m.ib,2_0mi.b,2_0mib.,2_0m.mb,2_0mm.b,2_0mmb.,2_0m.fb,2_0mf.b,2_0mfb.,\ 392 2_0m.lx,2_0mlx., \ 393 2_1m.ii,2_1mi.i,2_1mii.,2_1m.mi,2_1mm.i,2_1mmi.,2_1m.fi,2_1mf.i,2_1mfi.,\ 394 2_1m.mf,2_1mm.f,2_1mmf.,2_1b.bb,2_1bb.b,2_1bbb.,2_1m.bb,2_1mb.b,2_1mbb.,\ 395 2_1m.ib,2_1mi.b,2_1mib.,2_1m.mb,2_1mm.b,2_1mmb.,2_1m.fb,2_1mf.b,2_1mfb.,\ 396 2_1m.lx,2_1mlx." 397 "2_stop") 398 399;; The issue logic can reorder M slot insns between different subtypes 400;; but cannot reorder insn within the same subtypes. The following 401;; constraint is enough to describe this. 402(final_presence_set "2_um1" "2_um0") 403(final_presence_set "2_um3" "2_um2") 404 405;; The insn in the 1st I slot of the two bundle issue group will issue 406;; to I0. The second I slot insn will issue to I1. 407(final_presence_set "2_ui1" "2_ui0") 408 409;; For exceptions of I insns: 410(define_cpu_unit "2_only_ui0" "two") 411(final_absence_set "2_only_ui0" "2_ui1") 412 413;; Insns 414 415(define_reservation "2_M0" 416 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ 417 |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ 418 |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ 419 +(2_um0|2_um1|2_um2|2_um3)") 420 421(define_reservation "2_M1" 422 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ 423 |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ 424 +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ 425 +(2_um0|2_um1|2_um2|2_um3)") 426 427(define_reservation "2_M" "2_M0|2_M1") 428 429(define_reservation "2_M0_only_um0" 430 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ 431 |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ 432 |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ 433 +2_um0") 434 435(define_reservation "2_M1_only_um0" 436 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ 437 |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ 438 +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ 439 +2_um0") 440 441(define_reservation "2_M_only_um0" "2_M0_only_um0|2_M1_only_um0") 442 443(define_reservation "2_M0_only_um2" 444 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ 445 |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ 446 |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ 447 +2_um2") 448 449(define_reservation "2_M1_only_um2" 450 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ 451 |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ 452 +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ 453 +2_um2") 454 455(define_reservation "2_M_only_um2" "2_M0_only_um2|2_M1_only_um2") 456 457(define_reservation "2_M0_only_um23" 458 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ 459 |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ 460 |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ 461 +(2_um2|2_um3)") 462 463(define_reservation "2_M1_only_um23" 464 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ 465 |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ 466 +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ 467 +(2_um2|2_um3)") 468 469(define_reservation "2_M_only_um23" "2_M0_only_um23|2_M1_only_um23") 470 471(define_reservation "2_M0_only_um01" 472 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb|2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx\ 473 |2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx\ 474 |2_0mm.i|2_0mm.f|2_0mm.b|2_1mm.i|2_1mm.f|2_1mm.b)\ 475 +(2_um0|2_um1)") 476 477(define_reservation "2_M1_only_um01" 478 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ 479 |2_0mib.+2_unb0|2_0mfb.+2_unb0|2_0mmb.+2_unb0)\ 480 +(2_1m.ii|2_1m.mi|2_1m.fi|2_1m.mf|2_1m.bb|2_1m.ib|2_1m.mb|2_1m.fb|2_1m.lx)\ 481 +(2_um0|2_um1)") 482 483(define_reservation "2_M_only_um01" "2_M0_only_um01|2_M1_only_um01") 484 485;; I instruction is dispersed to the lowest numbered I unit 486;; not already in use. Remember about possible splitting. 487(define_reservation "2_I0" 488 "2_0mi.i+2_ui0|2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0\ 489 |2_0mfi.+2_ui0|2_0mi.b+2_ui0|(2_1mi.i|2_1mi.b)+(2_ui0|2_ui1)\ 490 |(2_1mii.|2_1mmi.|2_1mfi.)+(2_ui0|2_ui1)") 491 492(define_reservation "2_I1" 493 "2_0m.ii+(2_um0|2_um1|2_um2|2_um3)+2_0mi.i+2_ui0\ 494 |2_0mm.i+(2_um0|2_um1|2_um2|2_um3)+2_0mmi.+2_ui0\ 495 |2_0mf.i+2_uf0+2_0mfi.+2_ui0\ 496 |2_0m.ib+(2_um0|2_um1|2_um2|2_um3)+2_0mi.b+2_ui0\ 497 |(2_1m.ii+2_1mi.i|2_1m.ib+2_1mi.b)+(2_um0|2_um1|2_um2|2_um3)+(2_ui0|2_ui1)\ 498 |2_1mm.i+(2_um0|2_um1|2_um2|2_um3)+2_1mmi.+(2_ui0|2_ui1)\ 499 |2_1mf.i+2_uf1+2_1mfi.+(2_ui0|2_ui1)") 500 501(define_reservation "2_I" "2_I0|2_I1") 502 503;; "An F slot in the 1st bundle disperses to F0". 504;; "An F slot in the 2st bundle disperses to F1". 505(define_reservation "2_F0" 506 "2_0mf.i+2_uf0|2_0mmf.+2_uf0|2_0mf.b+2_uf0\ 507 |2_1mf.i+2_uf1|2_1mmf.+2_uf1|2_1mf.b+2_uf1") 508 509(define_reservation "2_F1" 510 "(2_0m.fi+2_0mf.i|2_0mm.f+2_0mmf.|2_0m.fb+2_0mf.b)\ 511 +(2_um0|2_um1|2_um2|2_um3)+2_uf0\ 512 |(2_1m.fi+2_1mf.i|2_1mm.f+2_1mmf.|2_1m.fb+2_1mf.b)\ 513 +(2_um0|2_um1|2_um2|2_um3)+2_uf1") 514 515(define_reservation "2_F2" 516 "(2_0m.mf+2_0mm.f+2_0mmf.+2_uf0|2_1m.mf+2_1mm.f+2_1mmf.+2_uf1)\ 517 +(2_um0|2_um1|2_um2|2_um3)+(2_um0|2_um1|2_um2|2_um3)\ 518 |(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0\ 519 |2_0mmf.+(2_um0|2_um1|2_um2|2_um3)\ 520 |2_0mib.+2_unb0|2_0mmb.+2_unb0|2_0mfb.+2_unb0)\ 521 +(2_1m.fi+2_1mf.i|2_1m.fb+2_1mf.b)+(2_um0|2_um1|2_um2|2_um3)+2_uf1") 522 523(define_reservation "2_F" "2_F0|2_F1|2_F2") 524 525;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B 526;;; unit. That is, a B slot in 1st position is dispersed to B0. In the 527;;; 2nd position it is dispersed to B2". 528(define_reservation "2_NB" 529 "2_0b.bb+2_unb0|2_0bb.b+2_unb1|2_0bbb.+2_unb2\ 530 |2_0mb.b+2_unb1|2_0mbb.+2_unb2|2_0mib.+2_unb0\ 531 |2_0mmb.+2_unb0|2_0mfb.+2_unb0\ 532 |2_1b.bb+2_unb0|2_1bb.b+2_unb1 533 |2_1bbb.+2_unb2|2_1mb.b+2_unb1|2_1mbb.+2_unb2\ 534 |2_1mib.+2_unb0|2_1mmb.+2_unb0|2_1mfb.+2_unb0") 535 536(define_reservation "2_B0" 537 "2_0b.bb+2_ub0|2_0bb.b+2_ub1|2_0bbb.+2_ub2\ 538 |2_0mb.b+2_ub1|2_0mbb.+2_ub2|2_0mib.+2_ub2\ 539 |2_0mfb.+2_ub2|2_1b.bb+2_ub0|2_1bb.b+2_ub1\ 540 |2_1bbb.+2_ub2|2_1mb.b+2_ub1\ 541 |2_1mib.+2_ub2|2_1mmb.+2_ub2|2_1mfb.+2_ub2") 542 543(define_reservation "2_B1" 544 "2_0m.bb+(2_um0|2_um1|2_um2|2_um3)+2_0mb.b+2_ub1\ 545 |2_0mi.b+2_ui0+2_0mib.+2_ub2\ 546 |2_0mm.b+(2_um0|2_um1|2_um2|2_um3)+2_0mmb.+2_ub2\ 547 |2_0mf.b+2_uf0+2_0mfb.+2_ub2\ 548 |(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0)\ 549 +2_1b.bb+2_ub0\ 550 |2_1m.bb+(2_um0|2_um1|2_um2|2_um3)+2_1mb.b+2_ub1\ 551 |2_1mi.b+(2_ui0|2_ui1)+2_1mib.+2_ub2\ 552 |2_1mm.b+(2_um0|2_um1|2_um2|2_um3)+2_1mmb.+2_ub2\ 553 |2_1mf.b+2_uf1+2_1mfb.+2_ub2") 554 555(define_reservation "2_B" "2_B0|2_B1") 556 557;; MLX bunlde uses ports equivalent to MFI bundles. 558 559;; For the MLI template, the I slot insn is always assigned to port I0 560;; if it is in the first bundle or it is assigned to port I1 if it is in 561;; the second bundle. 562(define_reservation "2_L0" "2_0mlx.+2_ui0+2_uf0|2_1mlx.+2_ui1+2_uf1") 563 564(define_reservation "2_L1" 565 "2_0m.lx+(2_um0|2_um1|2_um2|2_um3)+2_0mlx.+2_ui0+2_uf0\ 566 |2_1m.lx+(2_um0|2_um1|2_um2|2_um3)+2_1mlx.+2_ui1+2_uf1") 567 568(define_reservation "2_L2" 569 "(2_0mii.+(2_ui0|2_ui1)|2_0mmi.+2_ui0|2_0mfi.+2_ui0|2_0mmf.+2_uf0\ 570 |2_0mib.+2_unb0|2_0mmb.+2_unb0|2_0mfb.+2_unb0) 571 +2_1m.lx+(2_um0|2_um1|2_um2|2_um3)+2_1mlx.+2_ui1+2_uf1") 572 573(define_reservation "2_L" "2_L0|2_L1|2_L2") 574 575;; Should we describe that A insn in I slot can be issued into M 576;; ports? I think it is not necessary because of multipass 577;; scheduling. For example, the multipass scheduling could use 578;; MMI-MMI instead of MII-MII where the two last I slots contain A 579;; insns (even if the case is complicated by use-def conflicts). 580;; 581;; In any case we could describe it as 582;; (define_cpu_unit "2_ui1_0pres,2_ui1_1pres,2_ui1_2pres,2_ui1_3pres" "two") 583;; (final_presence_set "2_ui1_0pres,2_ui1_1pres,2_ui1_2pres,2_ui1_3pres" 584;; "2_ui1") 585;; (define_reservation "b_A" 586;; "b_M|b_I\ 587;; |(2_1mi.i|2_1mii.|2_1mmi.|2_1mfi.|2_1mi.b)+(2_um0|2_um1|2_um2|2_um3)\ 588;; +(2_ui1_0pres|2_ui1_1pres|2_ui1_2pres|2_ui1_3pres)") 589 590(define_reservation "2_A" "2_M|2_I") 591 592;; We assume that there is no insn issued on the same cycle as the 593;; unknown insn. 594(define_cpu_unit "2_empty" "two") 595(exclusion_set "2_empty" 596 "2_0m.ii,2_0m.mi,2_0m.fi,2_0m.mf,2_0b.bb,2_0m.bb,2_0m.ib,2_0m.mb,2_0m.fb,\ 597 2_0m.lx") 598 599(define_cpu_unit 600 "2_0m_bs, 2_0mi_bs, 2_0mm_bs, 2_0mf_bs, 2_0b_bs, 2_0bb_bs, 2_0mb_bs" 601 "two") 602(define_cpu_unit 603 "2_1m_bs, 2_1mi_bs, 2_1mm_bs, 2_1mf_bs, 2_1b_bs, 2_1bb_bs, 2_1mb_bs" 604 "two") 605 606(define_cpu_unit "2_m_cont, 2_mi_cont, 2_mm_cont, 2_mf_cont, 2_mb_cont,\ 607 2_b_cont, 2_bb_cont" "two") 608 609;; For stop in the middle of the bundles. 610(define_cpu_unit "2_m_stop, 2_m0_stop, 2_m1_stop, 2_0mmi_cont" "two") 611(define_cpu_unit "2_mi_stop, 2_mi0_stop, 2_mi1_stop, 2_0mii_cont" "two") 612 613(final_presence_set "2_0m_bs" 614 "2_0m.ii, 2_0m.mi, 2_0m.mf, 2_0m.fi, 2_0m.bb,\ 615 2_0m.ib, 2_0m.fb, 2_0m.mb, 2_0m.lx") 616(final_presence_set "2_1m_bs" 617 "2_1m.ii, 2_1m.mi, 2_1m.mf, 2_1m.fi, 2_1m.bb,\ 618 2_1m.ib, 2_1m.fb, 2_1m.mb, 2_1m.lx") 619(final_presence_set "2_0mi_bs" "2_0mi.i, 2_0mi.i") 620(final_presence_set "2_1mi_bs" "2_1mi.i, 2_1mi.i") 621(final_presence_set "2_0mm_bs" "2_0mm.i, 2_0mm.f, 2_0mm.b") 622(final_presence_set "2_1mm_bs" "2_1mm.i, 2_1mm.f, 2_1mm.b") 623(final_presence_set "2_0mf_bs" "2_0mf.i, 2_0mf.b") 624(final_presence_set "2_1mf_bs" "2_1mf.i, 2_1mf.b") 625(final_presence_set "2_0b_bs" "2_0b.bb") 626(final_presence_set "2_1b_bs" "2_1b.bb") 627(final_presence_set "2_0bb_bs" "2_0bb.b") 628(final_presence_set "2_1bb_bs" "2_1bb.b") 629(final_presence_set "2_0mb_bs" "2_0mb.b") 630(final_presence_set "2_1mb_bs" "2_1mb.b") 631 632(exclusion_set "2_0m_bs" 633 "2_0mi.i, 2_0mm.i, 2_0mm.f, 2_0mf.i, 2_0mb.b,\ 634 2_0mi.b, 2_0mf.b, 2_0mm.b, 2_0mlx., 2_m0_stop") 635(exclusion_set "2_1m_bs" 636 "2_1mi.i, 2_1mm.i, 2_1mm.f, 2_1mf.i, 2_1mb.b,\ 637 2_1mi.b, 2_1mf.b, 2_1mm.b, 2_1mlx., 2_m1_stop") 638(exclusion_set "2_0mi_bs" "2_0mii., 2_0mib., 2_mi0_stop") 639(exclusion_set "2_1mi_bs" "2_1mii., 2_1mib., 2_mi1_stop") 640(exclusion_set "2_0mm_bs" "2_0mmi., 2_0mmf., 2_0mmb.") 641(exclusion_set "2_1mm_bs" "2_1mmi., 2_1mmf., 2_1mmb.") 642(exclusion_set "2_0mf_bs" "2_0mfi., 2_0mfb.") 643(exclusion_set "2_1mf_bs" "2_1mfi., 2_1mfb.") 644(exclusion_set "2_0b_bs" "2_0bb.b") 645(exclusion_set "2_1b_bs" "2_1bb.b") 646(exclusion_set "2_0bb_bs" "2_0bbb.") 647(exclusion_set "2_1bb_bs" "2_1bbb.") 648(exclusion_set "2_0mb_bs" "2_0mbb.") 649(exclusion_set "2_1mb_bs" "2_1mbb.") 650 651(exclusion_set 652 "2_0m_bs, 2_0mi_bs, 2_0mm_bs, 2_0mf_bs, 2_0b_bs, 2_0bb_bs, 2_0mb_bs, 653 2_1m_bs, 2_1mi_bs, 2_1mm_bs, 2_1mf_bs, 2_1b_bs, 2_1bb_bs, 2_1mb_bs" 654 "2_stop") 655 656(final_presence_set 657 "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0mb.b,\ 658 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx." 659 "2_m_cont") 660(final_presence_set "2_0mii., 2_0mib." "2_mi_cont") 661(final_presence_set "2_0mmi., 2_0mmf., 2_0mmb." "2_mm_cont") 662(final_presence_set "2_0mfi., 2_0mfb." "2_mf_cont") 663(final_presence_set "2_0bb.b" "2_b_cont") 664(final_presence_set "2_0bbb." "2_bb_cont") 665(final_presence_set "2_0mbb." "2_mb_cont") 666 667(exclusion_set 668 "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ 669 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx" 670 "2_m_cont, 2_mi_cont, 2_mm_cont, 2_mf_cont,\ 671 2_mb_cont, 2_b_cont, 2_bb_cont") 672 673(exclusion_set "2_empty" 674 "2_m_cont,2_mi_cont,2_mm_cont,2_mf_cont,\ 675 2_mb_cont,2_b_cont,2_bb_cont") 676 677;; For m;mi bundle 678(final_presence_set "2_m0_stop" "2_0m.mi") 679(final_presence_set "2_0mm.i" "2_0mmi_cont") 680(exclusion_set "2_0mmi_cont" 681 "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ 682 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") 683(exclusion_set "2_m0_stop" "2_0mm.i") 684(final_presence_set "2_m1_stop" "2_1m.mi") 685(exclusion_set "2_m1_stop" "2_1mm.i") 686(final_presence_set "2_m_stop" "2_m0_stop, 2_m1_stop") 687 688;; For mi;i bundle 689(final_presence_set "2_mi0_stop" "2_0mi.i") 690(final_presence_set "2_0mii." "2_0mii_cont") 691(exclusion_set "2_0mii_cont" 692 "2_0m.ii, 2_0m.mi, 2_0m.fi, 2_0m.mf, 2_0b.bb, 2_0m.bb,\ 693 2_0m.ib, 2_0m.mb, 2_0m.fb, 2_0m.lx") 694(exclusion_set "2_mi0_stop" "2_0mii.") 695(final_presence_set "2_mi1_stop" "2_1mi.i") 696(exclusion_set "2_mi1_stop" "2_1mii.") 697(final_presence_set "2_mi_stop" "2_mi0_stop, 2_mi1_stop") 698 699(final_absence_set 700 "2_0m.ii,2_0mi.i,2_0mii.,2_0m.mi,2_0mm.i,2_0mmi.,2_0m.fi,2_0mf.i,2_0mfi.,\ 701 2_0m.mf,2_0mm.f,2_0mmf.,2_0b.bb,2_0bb.b,2_0bbb.,2_0m.bb,2_0mb.b,2_0mbb.,\ 702 2_0m.ib,2_0mi.b,2_0mib.,2_0m.mb,2_0mm.b,2_0mmb.,2_0m.fb,2_0mf.b,2_0mfb.,\ 703 2_0m.lx,2_0mlx., \ 704 2_1m.ii,2_1mi.i,2_1mii.,2_1m.mi,2_1mm.i,2_1mmi.,2_1m.fi,2_1mf.i,2_1mfi.,\ 705 2_1m.mf,2_1mm.f,2_1mmf.,2_1b.bb,2_1bb.b,2_1bbb.,2_1m.bb,2_1mb.b,2_1mbb.,\ 706 2_1m.ib,2_1mi.b,2_1mib.,2_1m.mb,2_1mm.b,2_1mmb.,2_1m.fb,2_1mf.b,2_1mfb.,\ 707 2_1m.lx,2_1mlx." 708 "2_m0_stop,2_m1_stop,2_mi0_stop,2_mi1_stop") 709 710(define_insn_reservation "2_stop_bit" 0 711 (and (and (eq_attr "cpu" "itanium2") 712 (eq_attr "itanium_class" "stop_bit")) 713 (not (match_test "bundling_p"))) 714 "2_stop|2_m0_stop|2_m1_stop|2_mi0_stop|2_mi1_stop") 715 716(define_insn_reservation "2_br" 0 717 (and (and (eq_attr "cpu" "itanium2") 718 (eq_attr "itanium_class" "br")) 719 (not (match_test "bundling_p"))) "2_B") 720(define_insn_reservation "2_scall" 0 721 (and (and (eq_attr "cpu" "itanium2") 722 (eq_attr "itanium_class" "scall")) 723 (not (match_test "bundling_p"))) "2_B") 724(define_insn_reservation "2_fcmp" 2 725 (and (and (eq_attr "cpu" "itanium2") 726 (eq_attr "itanium_class" "fcmp")) 727 (not (match_test "bundling_p"))) "2_F") 728(define_insn_reservation "2_fcvtfx" 4 729 (and (and (eq_attr "cpu" "itanium2") 730 (eq_attr "itanium_class" "fcvtfx")) 731 (not (match_test "bundling_p"))) "2_F") 732(define_insn_reservation "2_fld" 6 733 (and (and (and (and (eq_attr "cpu" "itanium2") 734 (eq_attr "itanium_class" "fld")) 735 (eq_attr "data_speculative" "no")) 736 (eq_attr "check_load" "no")) 737 (not (match_test "bundling_p"))) 738 "2_M") 739(define_insn_reservation "2_flda" 6 740 (and (and (and (eq_attr "cpu" "itanium2") 741 (eq_attr "itanium_class" "fld")) 742 (eq_attr "data_speculative" "yes")) 743 (not (match_test "bundling_p"))) 744 "2_M_only_um01") 745(define_insn_reservation "2_fldc" 0 746 (and (and (and (eq_attr "cpu" "itanium2") 747 (eq_attr "itanium_class" "fld")) 748 (eq_attr "check_load" "yes")) 749 (not (match_test "bundling_p"))) 750 "2_M_only_um01") 751 752(define_insn_reservation "2_fldp" 6 753 (and (and (and (eq_attr "cpu" "itanium2") 754 (eq_attr "itanium_class" "fldp")) 755 (eq_attr "check_load" "no")) 756 (not (match_test "bundling_p"))) 757 "2_M_only_um01") 758(define_insn_reservation "2_fldpc" 0 759 (and (and (and (eq_attr "cpu" "itanium2") 760 (eq_attr "itanium_class" "fldp")) 761 (eq_attr "check_load" "yes")) 762 (not (match_test "bundling_p"))) 763 "2_M_only_um01") 764 765(define_insn_reservation "2_fmac" 4 766 (and (and (eq_attr "cpu" "itanium2") 767 (eq_attr "itanium_class" "fmac")) 768 (not (match_test "bundling_p"))) "2_F") 769(define_insn_reservation "2_fmisc" 4 770 (and (and (eq_attr "cpu" "itanium2") 771 (eq_attr "itanium_class" "fmisc")) 772 (not (match_test "bundling_p"))) "2_F") 773 774;; There is only one insn `mov = ar.bsp' for frar_i: 775;; Latency time ??? 776(define_insn_reservation "2_frar_i" 13 777 (and (and (eq_attr "cpu" "itanium2") 778 (eq_attr "itanium_class" "frar_i")) 779 (not (match_test "bundling_p"))) 780 "2_I+2_only_ui0") 781;; There is only two insns `mov = ar.unat' or `mov = ar.ccv' for frar_m: 782;; Latency time ??? 783(define_insn_reservation "2_frar_m" 6 784 (and (and (eq_attr "cpu" "itanium2") 785 (eq_attr "itanium_class" "frar_m")) 786 (not (match_test "bundling_p"))) 787 "2_M_only_um2") 788(define_insn_reservation "2_frbr" 2 789 (and (and (eq_attr "cpu" "itanium2") 790 (eq_attr "itanium_class" "frbr")) 791 (not (match_test "bundling_p"))) 792 "2_I+2_only_ui0") 793(define_insn_reservation "2_frfr" 5 794 (and (and (eq_attr "cpu" "itanium2") 795 (eq_attr "itanium_class" "frfr")) 796 (not (match_test "bundling_p"))) 797 "2_M_only_um2") 798(define_insn_reservation "2_frpr" 2 799 (and (and (eq_attr "cpu" "itanium2") 800 (eq_attr "itanium_class" "frpr")) 801 (not (match_test "bundling_p"))) 802 "2_I+2_only_ui0") 803 804(define_insn_reservation "2_ialu" 1 805 (and (and (eq_attr "cpu" "itanium2") 806 (eq_attr "itanium_class" "ialu")) 807 (not (match_test "bundling_p"))) 808 "2_A") 809(define_insn_reservation "2_icmp" 1 810 (and (and (eq_attr "cpu" "itanium2") 811 (eq_attr "itanium_class" "icmp")) 812 (not (match_test "bundling_p"))) "2_A") 813(define_insn_reservation "2_ilog" 1 814 (and (and (eq_attr "cpu" "itanium2") 815 (eq_attr "itanium_class" "ilog")) 816 (not (match_test "bundling_p"))) "2_A") 817(define_insn_reservation "2_mmalua" 2 818 (and (and (eq_attr "cpu" "itanium2") 819 (eq_attr "itanium_class" "mmalua")) 820 (not (match_test "bundling_p"))) "2_A") 821;; Latency time ??? 822(define_insn_reservation "2_ishf" 1 823 (and (and (eq_attr "cpu" "itanium2") 824 (eq_attr "itanium_class" "ishf")) 825 (not (match_test "bundling_p"))) 826 "2_I+2_only_ui0") 827 828(define_insn_reservation "2_ld" 1 829 (and (and (and (eq_attr "cpu" "itanium2") 830 (eq_attr "itanium_class" "ld")) 831 (eq_attr "check_load" "no")) 832 (not (match_test "bundling_p"))) 833 "2_M_only_um01") 834(define_insn_reservation "2_ldc" 0 835 (and (and (eq_attr "cpu" "itanium2") 836 (eq_attr "check_load" "yes")) 837 (not (match_test "bundling_p"))) 838 "2_M_only_um01") 839 840(define_insn_reservation "2_long_i" 1 841 (and (and (eq_attr "cpu" "itanium2") 842 (eq_attr "itanium_class" "long_i")) 843 (not (match_test "bundling_p"))) "2_L") 844 845(define_insn_reservation "2_mmmul" 2 846 (and (and (eq_attr "cpu" "itanium2") 847 (eq_attr "itanium_class" "mmmul")) 848 (not (match_test "bundling_p"))) 849 "2_I+2_only_ui0") 850;; Latency time ??? 851(define_insn_reservation "2_mmshf" 2 852 (and (and (eq_attr "cpu" "itanium2") 853 (eq_attr "itanium_class" "mmshf")) 854 (not (match_test "bundling_p"))) "2_I") 855;; Latency time ??? 856(define_insn_reservation "2_mmshfi" 1 857 (and (and (eq_attr "cpu" "itanium2") 858 (eq_attr "itanium_class" "mmshfi")) 859 (not (match_test "bundling_p"))) "2_I") 860 861;; Now we have only one insn (flushrs) of such class. We assume that flushrs 862;; is the 1st syllable of the bundle after stop bit. 863(define_insn_reservation "2_rse_m" 0 864 (and (and (eq_attr "cpu" "itanium2") 865 (eq_attr "itanium_class" "rse_m")) 866 (not (match_test "bundling_p"))) 867 "(2_0m.ii|2_0m.mi|2_0m.fi|2_0m.mf|2_0m.bb\ 868 |2_0m.ib|2_0m.mb|2_0m.fb|2_0m.lx)+2_um0") 869(define_insn_reservation "2_sem" 0 870 (and (and (eq_attr "cpu" "itanium2") 871 (eq_attr "itanium_class" "sem")) 872 (not (match_test "bundling_p"))) 873 "2_M_only_um23") 874 875(define_insn_reservation "2_stf" 1 876 (and (and (eq_attr "cpu" "itanium2") 877 (eq_attr "itanium_class" "stf")) 878 (not (match_test "bundling_p"))) 879 "2_M_only_um23") 880(define_insn_reservation "2_st" 1 881 (and (and (eq_attr "cpu" "itanium2") 882 (eq_attr "itanium_class" "st")) 883 (not (match_test "bundling_p"))) 884 "2_M_only_um23") 885(define_insn_reservation "2_syst_m0" 0 886 (and (and (eq_attr "cpu" "itanium2") 887 (eq_attr "itanium_class" "syst_m0")) 888 (not (match_test "bundling_p"))) 889 "2_M_only_um2") 890(define_insn_reservation "2_syst_m" 0 891 (and (and (eq_attr "cpu" "itanium2") 892 (eq_attr "itanium_class" "syst_m")) 893 (not (match_test "bundling_p"))) 894 "2_M_only_um0") 895;; Reservation??? 896(define_insn_reservation "2_tbit" 1 897 (and (and (eq_attr "cpu" "itanium2") 898 (eq_attr "itanium_class" "tbit")) 899 (not (match_test "bundling_p"))) 900 "2_I+2_only_ui0") 901 902;; There is only ony insn `mov ar.pfs =' for toar_i: 903(define_insn_reservation "2_toar_i" 0 904 (and (and (eq_attr "cpu" "itanium2") 905 (eq_attr "itanium_class" "toar_i")) 906 (not (match_test "bundling_p"))) 907 "2_I+2_only_ui0") 908;; There are only ony 2 insns `mov ar.ccv =' and `mov ar.unat =' for toar_m: 909;; Latency time ??? 910(define_insn_reservation "2_toar_m" 5 911 (and (and (eq_attr "cpu" "itanium2") 912 (eq_attr "itanium_class" "toar_m")) 913 (not (match_test "bundling_p"))) 914 "2_M_only_um2") 915;; Latency time ??? 916(define_insn_reservation "2_tobr" 1 917 (and (and (eq_attr "cpu" "itanium2") 918 (eq_attr "itanium_class" "tobr")) 919 (not (match_test "bundling_p"))) 920 "2_I+2_only_ui0") 921(define_insn_reservation "2_tofr" 5 922 (and (and (eq_attr "cpu" "itanium2") 923 (eq_attr "itanium_class" "tofr")) 924 (not (match_test "bundling_p"))) 925 "2_M_only_um23") 926;; Latency time ??? 927(define_insn_reservation "2_topr" 1 928 (and (and (eq_attr "cpu" "itanium2") 929 (eq_attr "itanium_class" "topr")) 930 (not (match_test "bundling_p"))) 931 "2_I+2_only_ui0") 932 933(define_insn_reservation "2_xmpy" 4 934 (and (and (eq_attr "cpu" "itanium2") 935 (eq_attr "itanium_class" "xmpy")) 936 (not (match_test "bundling_p"))) "2_F") 937;; Latency time ??? 938(define_insn_reservation "2_xtd" 1 939 (and (and (eq_attr "cpu" "itanium2") 940 (eq_attr "itanium_class" "xtd")) 941 (not (match_test "bundling_p"))) "2_I") 942 943(define_insn_reservation "2_chk_s_i" 0 944 (and (and (eq_attr "cpu" "itanium2") 945 (eq_attr "itanium_class" "chk_s_i")) 946 (not (match_test "bundling_p"))) 947 "2_I|2_M_only_um23") 948(define_insn_reservation "2_chk_s_f" 0 949 (and (and (eq_attr "cpu" "itanium2") 950 (eq_attr "itanium_class" "chk_s_f")) 951 (not (match_test "bundling_p"))) 952 "2_M_only_um23") 953(define_insn_reservation "2_chk_a" 0 954 (and (and (eq_attr "cpu" "itanium2") 955 (eq_attr "itanium_class" "chk_a")) 956 (not (match_test "bundling_p"))) 957 "2_M_only_um01") 958 959(define_insn_reservation "2_lfetch" 0 960 (and (and (eq_attr "cpu" "itanium2") 961 (eq_attr "itanium_class" "lfetch")) 962 (not (match_test "bundling_p"))) 963 "2_M_only_um01") 964 965(define_insn_reservation "2_nop_m" 0 966 (and (and (eq_attr "cpu" "itanium2") 967 (eq_attr "itanium_class" "nop_m")) 968 (not (match_test "bundling_p"))) "2_M0") 969(define_insn_reservation "2_nop_b" 0 970 (and (and (eq_attr "cpu" "itanium2") 971 (eq_attr "itanium_class" "nop_b")) 972 (not (match_test "bundling_p"))) "2_NB") 973(define_insn_reservation "2_nop_i" 0 974 (and (and (eq_attr "cpu" "itanium2") 975 (eq_attr "itanium_class" "nop_i")) 976 (not (match_test "bundling_p"))) "2_I0") 977(define_insn_reservation "2_nop_f" 0 978 (and (and (eq_attr "cpu" "itanium2") 979 (eq_attr "itanium_class" "nop_f")) 980 (not (match_test "bundling_p"))) "2_F0") 981(define_insn_reservation "2_nop_x" 0 982 (and (and (eq_attr "cpu" "itanium2") 983 (eq_attr "itanium_class" "nop_x")) 984 (not (match_test "bundling_p"))) "2_L0") 985 986(define_insn_reservation "2_unknown" 1 987 (and (and (eq_attr "cpu" "itanium2") 988 (eq_attr "itanium_class" "unknown")) 989 (not (match_test "bundling_p"))) "2_empty") 990 991(define_insn_reservation "2_nop" 0 992 (and (and (eq_attr "cpu" "itanium2") 993 (eq_attr "itanium_class" "nop")) 994 (not (match_test "bundling_p"))) 995 "2_M0|2_NB|2_I0|2_F0") 996 997(define_insn_reservation "2_ignore" 0 998 (and (and (eq_attr "cpu" "itanium2") 999 (eq_attr "itanium_class" "ignore")) 1000 (not (match_test "bundling_p"))) "nothing") 1001 1002(define_cpu_unit "2_m_cont_only, 2_b_cont_only" "two") 1003(define_cpu_unit "2_mi_cont_only, 2_mm_cont_only, 2_mf_cont_only" "two") 1004(define_cpu_unit "2_mb_cont_only, 2_bb_cont_only" "two") 1005 1006(final_presence_set "2_m_cont_only" "2_m_cont") 1007(exclusion_set "2_m_cont_only" 1008 "2_0mi.i, 2_0mm.i, 2_0mf.i, 2_0mm.f, 2_0mb.b,\ 1009 2_0mi.b, 2_0mm.b, 2_0mf.b, 2_0mlx.") 1010 1011(final_presence_set "2_b_cont_only" "2_b_cont") 1012(exclusion_set "2_b_cont_only" "2_0bb.b") 1013 1014(final_presence_set "2_mi_cont_only" "2_mi_cont") 1015(exclusion_set "2_mi_cont_only" "2_0mii., 2_0mib.") 1016 1017(final_presence_set "2_mm_cont_only" "2_mm_cont") 1018(exclusion_set "2_mm_cont_only" "2_0mmi., 2_0mmf., 2_0mmb.") 1019 1020(final_presence_set "2_mf_cont_only" "2_mf_cont") 1021(exclusion_set "2_mf_cont_only" "2_0mfi., 2_0mfb.") 1022 1023(final_presence_set "2_mb_cont_only" "2_mb_cont") 1024(exclusion_set "2_mb_cont_only" "2_0mbb.") 1025 1026(final_presence_set "2_bb_cont_only" "2_bb_cont") 1027(exclusion_set "2_bb_cont_only" "2_0bbb.") 1028 1029(define_insn_reservation "2_pre_cycle" 0 1030 (and (and (eq_attr "cpu" "itanium2") 1031 (eq_attr "itanium_class" "pre_cycle")) 1032 (not (match_test "bundling_p"))) 1033 "nothing") 1034 1035;;(define_insn_reservation "2_pre_cycle" 0 1036;; (and (and (eq_attr "cpu" "itanium2") 1037;; (eq_attr "itanium_class" "pre_cycle")) 1038;; (not (match_test "bundling_p"))) 1039;; "(2_0m_bs, 2_m_cont) \ 1040;; | (2_0mi_bs, (2_mi_cont|nothing)) \ 1041;; | (2_0mm_bs, 2_mm_cont) \ 1042;; | (2_0mf_bs, (2_mf_cont|nothing)) \ 1043;; | (2_0b_bs, (2_b_cont|nothing)) \ 1044;; | (2_0bb_bs, (2_bb_cont|nothing)) \ 1045;; | (2_0mb_bs, (2_mb_cont|nothing)) \ 1046;; | (2_1m_bs, 2_m_cont) \ 1047;; | (2_1mi_bs, (2_mi_cont|nothing)) \ 1048;; | (2_1mm_bs, 2_mm_cont) \ 1049;; | (2_1mf_bs, (2_mf_cont|nothing)) \ 1050;; | (2_1b_bs, (2_b_cont|nothing)) \ 1051;; | (2_1bb_bs, (2_bb_cont|nothing)) \ 1052;; | (2_1mb_bs, (2_mb_cont|nothing)) \ 1053;; | (2_m_cont_only, (2_m_cont|nothing)) \ 1054;; | (2_b_cont_only, (2_b_cont|nothing)) \ 1055;; | (2_mi_cont_only, (2_mi_cont|nothing)) \ 1056;; | (2_mm_cont_only, (2_mm_cont|nothing)) \ 1057;; | (2_mf_cont_only, (2_mf_cont|nothing)) \ 1058;; | (2_mb_cont_only, (2_mb_cont|nothing)) \ 1059;; | (2_bb_cont_only, (2_bb_cont|nothing)) \ 1060;; | (2_m_stop, (2_0mmi_cont|nothing)) \ 1061;; | (2_mi_stop, (2_0mii_cont|nothing))") 1062 1063;; Bypasses: 1064 1065(define_bypass 1 "2_fcmp" "2_br,2_scall") 1066(define_bypass 0 "2_icmp" "2_br,2_scall") 1067(define_bypass 0 "2_tbit" "2_br,2_scall") 1068(define_bypass 2 "2_ld" "2_ld" "ia64_ld_address_bypass_p") 1069(define_bypass 2 "2_ld" "2_st" "ia64_st_address_bypass_p") 1070(define_bypass 2 "2_ld,2_ldc" "2_mmalua,2_mmmul,2_mmshf") 1071(define_bypass 3 "2_ilog" "2_mmalua,2_mmmul,2_mmshf") 1072(define_bypass 3 "2_ialu" "2_mmalua,2_mmmul,2_mmshf") 1073(define_bypass 3 "2_mmalua,2_mmmul,2_mmshf" "2_ialu,2_ilog,2_ishf,2_st,2_ld,2_ldc") 1074(define_bypass 6 "2_tofr" "2_frfr,2_stf") 1075 1076;; We don't use here fcmp because scall may be predicated. 1077(define_bypass 0 "2_fcvtfx,2_fld,2_flda,2_fldc,2_fmac,2_fmisc,2_frar_i,2_frar_m,\ 1078 2_frbr,2_frfr,2_frpr,2_ialu,2_ilog,2_ishf,2_ld,2_ldc,2_long_i,\ 1079 2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_toar_m,2_tobr,2_tofr,\ 1080 2_xmpy,2_xtd" 1081 "2_br,2_scall") 1082 1083(define_bypass 0 "2_unknown,2_ignore,2_stop_bit,2_br,2_fcmp,2_fcvtfx,2_fld,2_flda,2_fldc,\ 1084 2_fmac,2_fmisc,2_frar_i,2_frar_m,2_frbr,2_frfr,2_frpr,\ 1085 2_ialu,2_icmp,2_ilog,2_ishf,2_ld,2_ldc,2_chk_s_i,2_chk_s_f,2_chk_a,2_long_i,\ 1086 2_mmalua,2_mmmul,2_mmshf,2_mmshfi,2_nop,2_nop_b,2_nop_f,\ 1087 2_nop_i,2_nop_m,2_nop_x,2_rse_m,2_scall,2_sem,2_stf,2_st,\ 1088 2_syst_m0,2_syst_m,2_tbit,2_toar_i,2_toar_m,2_tobr,2_tofr,\ 1089 2_topr,2_xmpy,2_xtd,2_lfetch" "2_ignore") 1090 1091 1092 1093;; Bundling 1094 1095(define_automaton "twob") 1096 1097;; Pseudo units for quicker searching for position in two packet window. */ 1098(define_query_cpu_unit "2_1,2_2,2_3,2_4,2_5,2_6" "twob") 1099 1100;; All possible combinations of bundles/syllables 1101(define_cpu_unit 1102 "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ 1103 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx" "twob") 1104(define_cpu_unit 1105 "2b_0mi.i, 2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\ 1106 2b_0mi.b, 2b_0mm.b, 2b_0mf.b" "twob") 1107(define_query_cpu_unit 1108 "2b_0mii., 2b_0mmi., 2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\ 1109 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx." "twob") 1110 1111(define_cpu_unit 1112 "2b_1m.ii, 2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\ 1113 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx" "twob") 1114(define_cpu_unit 1115 "2b_1mi.i, 2b_1mm.i, 2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\ 1116 2b_1mi.b, 2b_1mm.b, 2b_1mf.b" "twob") 1117(define_query_cpu_unit 1118 "2b_1mii., 2b_1mmi., 2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\ 1119 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx." "twob") 1120 1121;; Slot 1 1122(exclusion_set "2b_0m.ii" 1123 "2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ 1124 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1125(exclusion_set "2b_0m.mi" 1126 "2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb, 2b_0m.ib,\ 1127 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1128(exclusion_set "2b_0m.fi" 1129 "2b_0m.mf, 2b_0b.bb, 2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1130(exclusion_set "2b_0m.mf" 1131 "2b_0b.bb, 2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1132(exclusion_set "2b_0b.bb" "2b_0m.bb, 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1133(exclusion_set "2b_0m.bb" "2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1134(exclusion_set "2b_0m.ib" "2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1135(exclusion_set "2b_0m.mb" "2b_0m.fb, 2b_0m.lx") 1136(exclusion_set "2b_0m.fb" "2b_0m.lx") 1137 1138;; Slot 2 1139(exclusion_set "2b_0mi.i" 1140 "2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\ 1141 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") 1142(exclusion_set "2b_0mm.i" 1143 "2b_0mf.i, 2b_0mm.f, 2b_0bb.b, 2b_0mb.b,\ 1144 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") 1145(exclusion_set "2b_0mf.i" 1146 "2b_0mm.f, 2b_0bb.b, 2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") 1147(exclusion_set "2b_0mm.f" 1148 "2b_0bb.b, 2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") 1149(exclusion_set "2b_0bb.b" "2b_0mb.b, 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") 1150(exclusion_set "2b_0mb.b" "2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx.") 1151(exclusion_set "2b_0mi.b" "2b_0mm.b, 2b_0mf.b, 2b_0mlx.") 1152(exclusion_set "2b_0mm.b" "2b_0mf.b, 2b_0mlx.") 1153(exclusion_set "2b_0mf.b" "2b_0mlx.") 1154 1155;; Slot 3 1156(exclusion_set "2b_0mii." 1157 "2b_0mmi., 2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\ 1158 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") 1159(exclusion_set "2b_0mmi." 1160 "2b_0mfi., 2b_0mmf., 2b_0bbb., 2b_0mbb.,\ 1161 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") 1162(exclusion_set "2b_0mfi." 1163 "2b_0mmf., 2b_0bbb., 2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") 1164(exclusion_set "2b_0mmf." 1165 "2b_0bbb., 2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") 1166(exclusion_set "2b_0bbb." "2b_0mbb., 2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") 1167(exclusion_set "2b_0mbb." "2b_0mib., 2b_0mmb., 2b_0mfb., 2b_0mlx.") 1168(exclusion_set "2b_0mib." "2b_0mmb., 2b_0mfb., 2b_0mlx.") 1169(exclusion_set "2b_0mmb." "2b_0mfb., 2b_0mlx.") 1170(exclusion_set "2b_0mfb." "2b_0mlx.") 1171 1172;; Slot 4 1173(exclusion_set "2b_1m.ii" 1174 "2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\ 1175 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") 1176(exclusion_set "2b_1m.mi" 1177 "2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb, 2b_1m.ib,\ 1178 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") 1179(exclusion_set "2b_1m.fi" 1180 "2b_1m.mf, 2b_1b.bb, 2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") 1181(exclusion_set "2b_1m.mf" 1182 "2b_1b.bb, 2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") 1183(exclusion_set "2b_1b.bb" "2b_1m.bb, 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") 1184(exclusion_set "2b_1m.bb" "2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx") 1185(exclusion_set "2b_1m.ib" "2b_1m.mb, 2b_1m.fb, 2b_1m.lx") 1186(exclusion_set "2b_1m.mb" "2b_1m.fb, 2b_1m.lx") 1187(exclusion_set "2b_1m.fb" "2b_1m.lx") 1188 1189;; Slot 5 1190(exclusion_set "2b_1mi.i" 1191 "2b_1mm.i, 2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\ 1192 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") 1193(exclusion_set "2b_1mm.i" 1194 "2b_1mf.i, 2b_1mm.f, 2b_1bb.b, 2b_1mb.b,\ 1195 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") 1196(exclusion_set "2b_1mf.i" 1197 "2b_1mm.f, 2b_1bb.b, 2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") 1198(exclusion_set "2b_1mm.f" 1199 "2b_1bb.b, 2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") 1200(exclusion_set "2b_1bb.b" "2b_1mb.b, 2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") 1201(exclusion_set "2b_1mb.b" "2b_1mi.b, 2b_1mm.b, 2b_1mf.b, 2b_1mlx.") 1202(exclusion_set "2b_1mi.b" "2b_1mm.b, 2b_1mf.b, 2b_1mlx.") 1203(exclusion_set "2b_1mm.b" "2b_1mf.b, 2b_1mlx.") 1204(exclusion_set "2b_1mf.b" "2b_1mlx.") 1205 1206;; Slot 6 1207(exclusion_set "2b_1mii." 1208 "2b_1mmi., 2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\ 1209 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") 1210(exclusion_set "2b_1mmi." 1211 "2b_1mfi., 2b_1mmf., 2b_1bbb., 2b_1mbb.,\ 1212 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") 1213(exclusion_set "2b_1mfi." 1214 "2b_1mmf., 2b_1bbb., 2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") 1215(exclusion_set "2b_1mmf." 1216 "2b_1bbb., 2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") 1217(exclusion_set "2b_1bbb." "2b_1mbb., 2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") 1218(exclusion_set "2b_1mbb." "2b_1mib., 2b_1mmb., 2b_1mfb., 2b_1mlx.") 1219(exclusion_set "2b_1mib." "2b_1mmb., 2b_1mfb., 2b_1mlx.") 1220(exclusion_set "2b_1mmb." "2b_1mfb., 2b_1mlx.") 1221(exclusion_set "2b_1mfb." "2b_1mlx.") 1222 1223(final_presence_set "2b_0mi.i" "2b_0m.ii") 1224(final_presence_set "2b_0mii." "2b_0mi.i") 1225(final_presence_set "2b_1mi.i" "2b_1m.ii") 1226(final_presence_set "2b_1mii." "2b_1mi.i") 1227 1228(final_presence_set "2b_0mm.i" "2b_0m.mi") 1229(final_presence_set "2b_0mmi." "2b_0mm.i") 1230(final_presence_set "2b_1mm.i" "2b_1m.mi") 1231(final_presence_set "2b_1mmi." "2b_1mm.i") 1232 1233(final_presence_set "2b_0mf.i" "2b_0m.fi") 1234(final_presence_set "2b_0mfi." "2b_0mf.i") 1235(final_presence_set "2b_1mf.i" "2b_1m.fi") 1236(final_presence_set "2b_1mfi." "2b_1mf.i") 1237 1238(final_presence_set "2b_0mm.f" "2b_0m.mf") 1239(final_presence_set "2b_0mmf." "2b_0mm.f") 1240(final_presence_set "2b_1mm.f" "2b_1m.mf") 1241(final_presence_set "2b_1mmf." "2b_1mm.f") 1242 1243(final_presence_set "2b_0bb.b" "2b_0b.bb") 1244(final_presence_set "2b_0bbb." "2b_0bb.b") 1245(final_presence_set "2b_1bb.b" "2b_1b.bb") 1246(final_presence_set "2b_1bbb." "2b_1bb.b") 1247 1248(final_presence_set "2b_0mb.b" "2b_0m.bb") 1249(final_presence_set "2b_0mbb." "2b_0mb.b") 1250(final_presence_set "2b_1mb.b" "2b_1m.bb") 1251(final_presence_set "2b_1mbb." "2b_1mb.b") 1252 1253(final_presence_set "2b_0mi.b" "2b_0m.ib") 1254(final_presence_set "2b_0mib." "2b_0mi.b") 1255(final_presence_set "2b_1mi.b" "2b_1m.ib") 1256(final_presence_set "2b_1mib." "2b_1mi.b") 1257 1258(final_presence_set "2b_0mm.b" "2b_0m.mb") 1259(final_presence_set "2b_0mmb." "2b_0mm.b") 1260(final_presence_set "2b_1mm.b" "2b_1m.mb") 1261(final_presence_set "2b_1mmb." "2b_1mm.b") 1262 1263(final_presence_set "2b_0mf.b" "2b_0m.fb") 1264(final_presence_set "2b_0mfb." "2b_0mf.b") 1265(final_presence_set "2b_1mf.b" "2b_1m.fb") 1266(final_presence_set "2b_1mfb." "2b_1mf.b") 1267 1268(final_presence_set "2b_0mlx." "2b_0m.lx") 1269(final_presence_set "2b_1mlx." "2b_1m.lx") 1270 1271;; See the corresponding comment in non-bundling section above. 1272(final_presence_set 1273 "2b_1m.lx" 1274 "2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mib.,2b_0mmb.,2b_0mfb.,2b_0mlx.") 1275(final_presence_set "2b_1b.bb" "2b_0mii.,2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mlx.") 1276(final_presence_set 1277 "2b_1m.ii,2b_1m.mi,2b_1m.fi,2b_1m.mf,2b_1m.bb,2b_1m.ib,2b_1m.mb,2b_1m.fb" 1278 "2b_0mii.,2b_0mmi.,2b_0mfi.,2b_0mmf.,2b_0mib.,2b_0mmb.,2b_0mfb.,2b_0mlx.") 1279 1280;; Ports/units (nb means nop.b insn issued into given port): 1281(define_cpu_unit 1282 "2b_um0, 2b_um1, 2b_um2, 2b_um3, 2b_ui0, 2b_ui1, 2b_uf0, 2b_uf1,\ 1283 2b_ub0, 2b_ub1, 2b_ub2, 2b_unb0, 2b_unb1, 2b_unb2" "twob") 1284 1285(exclusion_set "2b_ub0" "2b_unb0") 1286(exclusion_set "2b_ub1" "2b_unb1") 1287(exclusion_set "2b_ub2" "2b_unb2") 1288 1289;; The following rules are used to decrease number of alternatives. 1290;; They are consequences of Itanium2 microarchitecture. They also 1291;; describe the following rules mentioned in Itanium2 1292;; microarchitecture: rules mentioned in Itanium2 microarchitecture: 1293;; o "BBB/MBB: Always splits issue after either of these bundles". 1294;; o "MIB BBB: Split issue after the first bundle in this pair". 1295(exclusion_set 1296 "2b_0b.bb,2b_0bb.b,2b_0bbb.,2b_0m.bb,2b_0mb.b,2b_0mbb." 1297 "2b_1m.ii,2b_1m.mi,2b_1m.fi,2b_1m.mf,2b_1b.bb,2b_1m.bb,\ 1298 2b_1m.ib,2b_1m.mb,2b_1m.fb,2b_1m.lx") 1299(exclusion_set "2b_0m.ib,2b_0mi.b,2b_0mib." "2b_1b.bb") 1300 1301;;; "MIB/MFB/MMB: Splits issue after any of these bundles unless the 1302;;; B-slot contains a nop.b or a brp instruction". 1303;;; "The B in an MIB/MFB/MMB bundle disperses to B0 if it is a brp or 1304;;; nop.b, otherwise it disperses to B2". 1305(final_absence_set 1306 "2b_1m.ii, 2b_1m.mi, 2b_1m.fi, 2b_1m.mf, 2b_1b.bb, 2b_1m.bb,\ 1307 2b_1m.ib, 2b_1m.mb, 2b_1m.fb, 2b_1m.lx" 1308 "2b_0mib. 2b_ub2, 2b_0mfb. 2b_ub2, 2b_0mmb. 2b_ub2") 1309 1310;; This is necessary to start new processor cycle when we meet stop bit. 1311(define_cpu_unit "2b_stop" "twob") 1312(final_absence_set 1313 "2b_0m.ii,2b_0mi.i,2b_0mii.,2b_0m.mi,2b_0mm.i,2b_0mmi.,\ 1314 2b_0m.fi,2b_0mf.i,2b_0mfi.,\ 1315 2b_0m.mf,2b_0mm.f,2b_0mmf.,2b_0b.bb,2b_0bb.b,2b_0bbb.,\ 1316 2b_0m.bb,2b_0mb.b,2b_0mbb.,\ 1317 2b_0m.ib,2b_0mi.b,2b_0mib.,2b_0m.mb,2b_0mm.b,2b_0mmb.,\ 1318 2b_0m.fb,2b_0mf.b,2b_0mfb.,2b_0m.lx,2b_0mlx., \ 1319 2b_1m.ii,2b_1mi.i,2b_1mii.,2b_1m.mi,2b_1mm.i,2b_1mmi.,\ 1320 2b_1m.fi,2b_1mf.i,2b_1mfi.,\ 1321 2b_1m.mf,2b_1mm.f,2b_1mmf.,2b_1b.bb,2b_1bb.b,2b_1bbb.,\ 1322 2b_1m.bb,2b_1mb.b,2b_1mbb.,\ 1323 2b_1m.ib,2b_1mi.b,2b_1mib.,2b_1m.mb,2b_1mm.b,2b_1mmb.,\ 1324 2b_1m.fb,2b_1mf.b,2b_1mfb.,2b_1m.lx,2b_1mlx." 1325 "2b_stop") 1326 1327;; The issue logic can reorder M slot insns between different subtypes 1328;; but cannot reorder insn within the same subtypes. The following 1329;; constraint is enough to describe this. 1330(final_presence_set "2b_um1" "2b_um0") 1331(final_presence_set "2b_um3" "2b_um2") 1332 1333;; The insn in the 1st I slot of the two bundle issue group will issue 1334;; to I0. The second I slot insn will issue to I1. 1335(final_presence_set "2b_ui1" "2b_ui0") 1336 1337;; For exceptions of I insns: 1338(define_cpu_unit "2b_only_ui0" "twob") 1339(final_absence_set "2b_only_ui0" "2b_ui1") 1340 1341;; Insns 1342 1343(define_reservation "2b_M" 1344 "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ 1345 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ 1346 |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ 1347 |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ 1348 |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ 1349 |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ 1350 +(2b_um0|2b_um1|2b_um2|2b_um3)") 1351 1352(define_reservation "2b_M_only_um0" 1353 "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ 1354 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ 1355 |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ 1356 |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ 1357 |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ 1358 |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ 1359 +2b_um0") 1360 1361(define_reservation "2b_M_only_um2" 1362 "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ 1363 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ 1364 |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ 1365 |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ 1366 |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ 1367 |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ 1368 +2b_um2") 1369 1370(define_reservation "2b_M_only_um01" 1371 "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ 1372 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ 1373 |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ 1374 |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ 1375 |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ 1376 |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ 1377 +(2b_um0|2b_um1)") 1378 1379(define_reservation "2b_M_only_um23" 1380 "((2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ 1381 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1\ 1382 |(2b_1m.ii|2b_1m.mi|2b_1m.fi|2b_1m.mf|2b_1m.bb\ 1383 |2b_1m.ib|2b_1m.mb|2b_1m.fb|2b_1m.lx)+2_4\ 1384 |(2b_0mm.i|2b_0mm.f|2b_0mm.b)+2_2\ 1385 |(2b_1mm.i|2b_1mm.f|2b_1mm.b)+2_5)\ 1386 +(2b_um2|2b_um3)") 1387 1388;; I instruction is dispersed to the lowest numbered I unit 1389;; not already in use. Remember about possible splitting. 1390(define_reservation "2b_I" 1391 "2b_0mi.i+2_2+2b_ui0|2b_0mii.+2_3+(2b_ui0|2b_ui1)|2b_0mmi.+2_3+2b_ui0\ 1392 |2b_0mfi.+2_3+2b_ui0|2b_0mi.b+2_2+2b_ui0\ 1393 |(2b_1mi.i+2_5|2b_1mi.b+2_5)+(2b_ui0|2b_ui1)\ 1394 |(2b_1mii.|2b_1mmi.|2b_1mfi.)+2_6+(2b_ui0|2b_ui1)") 1395 1396;; "An F slot in the 1st bundle disperses to F0". 1397;; "An F slot in the 2st bundle disperses to F1". 1398(define_reservation "2b_F" 1399 "2b_0mf.i+2_2+2b_uf0|2b_0mmf.+2_3+2b_uf0|2b_0mf.b+2_2+2b_uf0\ 1400 |2b_1mf.i+2_5+2b_uf1|2b_1mmf.+2_6+2b_uf1|2b_1mf.b+2_5+2b_uf1") 1401 1402;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B 1403;;; unit. That is, a B slot in 1st position is dispersed to B0. In the 1404;;; 2nd position it is dispersed to B2". 1405(define_reservation "2b_NB" 1406 "2b_0b.bb+2_1+2b_unb0|2b_0bb.b+2_2+2b_unb1|2b_0bbb.+2_3+2b_unb2\ 1407 |2b_0mb.b+2_2+2b_unb1|2b_0mbb.+2_3+2b_unb2\ 1408 |2b_0mib.+2_3+2b_unb0|2b_0mmb.+2_3+2b_unb0|2b_0mfb.+2_3+2b_unb0\ 1409 |2b_1b.bb+2_4+2b_unb0|2b_1bb.b+2_5+2b_unb1\ 1410 |2b_1bbb.+2_6+2b_unb2|2b_1mb.b+2_5+2b_unb1|2b_1mbb.+2_6+2b_unb2\ 1411 |2b_1mib.+2_6+2b_unb0|2b_1mmb.+2_6+2b_unb0|2b_1mfb.+2_6+2b_unb0") 1412 1413(define_reservation "2b_B" 1414 "2b_0b.bb+2_1+2b_ub0|2b_0bb.b+2_2+2b_ub1|2b_0bbb.+2_3+2b_ub2\ 1415 |2b_0mb.b+2_2+2b_ub1|2b_0mbb.+2_3+2b_ub2|2b_0mib.+2_3+2b_ub2\ 1416 |2b_0mfb.+2_3+2b_ub2|2b_1b.bb+2_4+2b_ub0|2b_1bb.b+2_5+2b_ub1\ 1417 |2b_1bbb.+2_6+2b_ub2|2b_1mb.b+2_5+2b_ub1\ 1418 |2b_1mib.+2_6+2b_ub2|2b_1mmb.+2_6+2b_ub2|2b_1mfb.+2_6+2b_ub2") 1419 1420;; For the MLI template, the I slot insn is always assigned to port I0 1421;; if it is in the first bundle or it is assigned to port I1 if it is in 1422;; the second bundle. 1423(define_reservation "2b_L" 1424 "2b_0mlx.+2_3+2b_ui0+2b_uf0|2b_1mlx.+2_6+2b_ui1+2b_uf1") 1425 1426;; Should we describe that A insn in I slot can be issued into M 1427;; ports? I think it is not necessary because of multipass 1428;; scheduling. For example, the multipass scheduling could use 1429;; MMI-MMI instead of MII-MII where the two last I slots contain A 1430;; insns (even if the case is complicated by use-def conflicts). 1431;; 1432;; In any case we could describe it as 1433;; (define_cpu_unit "2b_ui1_0pres,2b_ui1_1pres,2b_ui1_2pres,2b_ui1_3pres" 1434;; "twob") 1435;; (final_presence_set "2b_ui1_0pres,2b_ui1_1pres,2b_ui1_2pres,2b_ui1_3pres" 1436;; "2b_ui1") 1437;; (define_reservation "b_A" 1438;; "b_M|b_I\ 1439;; |(2b_1mi.i+2_5|2b_1mii.+2_6|2b_1mmi.+2_6|2b_1mfi.+2_6|2b_1mi.b+2_5)\ 1440;; +(2b_um0|2b_um1|2b_um2|2b_um3)\ 1441;; +(2b_ui1_0pres|2b_ui1_1pres|2b_ui1_2pres|2b_ui1_3pres)") 1442 1443(define_reservation "2b_A" "2b_M|2b_I") 1444 1445;; We assume that there is no insn issued on the same cycle as the 1446;; unknown insn. 1447(define_cpu_unit "2b_empty" "twob") 1448(exclusion_set "2b_empty" 1449 "2b_0m.ii,2b_0m.mi,2b_0m.fi,2b_0m.mf,2b_0b.bb,2b_0m.bb,\ 1450 2b_0m.ib,2b_0m.mb,2b_0m.fb,2b_0m.lx,2b_0mm.i") 1451 1452(define_cpu_unit 1453 "2b_0m_bs, 2b_0mi_bs, 2b_0mm_bs, 2b_0mf_bs, 2b_0b_bs, 2b_0bb_bs, 2b_0mb_bs" 1454 "twob") 1455(define_cpu_unit 1456 "2b_1m_bs, 2b_1mi_bs, 2b_1mm_bs, 2b_1mf_bs, 2b_1b_bs, 2b_1bb_bs, 2b_1mb_bs" 1457 "twob") 1458 1459(define_cpu_unit "2b_m_cont, 2b_mi_cont, 2b_mm_cont, 2b_mf_cont, 2b_mb_cont,\ 1460 2b_b_cont, 2b_bb_cont" "twob") 1461 1462;; For stop in the middle of the bundles. 1463(define_cpu_unit "2b_m_stop, 2b_m0_stop, 2b_m1_stop, 2b_0mmi_cont" "twob") 1464(define_cpu_unit "2b_mi_stop, 2b_mi0_stop, 2b_mi1_stop, 2b_0mii_cont" "twob") 1465 1466(final_presence_set "2b_0m_bs" 1467 "2b_0m.ii, 2b_0m.mi, 2b_0m.mf, 2b_0m.fi, 2b_0m.bb,\ 1468 2b_0m.ib, 2b_0m.fb, 2b_0m.mb, 2b_0m.lx") 1469(final_presence_set "2b_1m_bs" 1470 "2b_1m.ii, 2b_1m.mi, 2b_1m.mf, 2b_1m.fi, 2b_1m.bb,\ 1471 2b_1m.ib, 2b_1m.fb, 2b_1m.mb, 2b_1m.lx") 1472(final_presence_set "2b_0mi_bs" "2b_0mi.i, 2b_0mi.i") 1473(final_presence_set "2b_1mi_bs" "2b_1mi.i, 2b_1mi.i") 1474(final_presence_set "2b_0mm_bs" "2b_0mm.i, 2b_0mm.f, 2b_0mm.b") 1475(final_presence_set "2b_1mm_bs" "2b_1mm.i, 2b_1mm.f, 2b_1mm.b") 1476(final_presence_set "2b_0mf_bs" "2b_0mf.i, 2b_0mf.b") 1477(final_presence_set "2b_1mf_bs" "2b_1mf.i, 2b_1mf.b") 1478(final_presence_set "2b_0b_bs" "2b_0b.bb") 1479(final_presence_set "2b_1b_bs" "2b_1b.bb") 1480(final_presence_set "2b_0bb_bs" "2b_0bb.b") 1481(final_presence_set "2b_1bb_bs" "2b_1bb.b") 1482(final_presence_set "2b_0mb_bs" "2b_0mb.b") 1483(final_presence_set "2b_1mb_bs" "2b_1mb.b") 1484 1485(exclusion_set "2b_0m_bs" 1486 "2b_0mi.i, 2b_0mm.i, 2b_0mm.f, 2b_0mf.i, 2b_0mb.b,\ 1487 2b_0mi.b, 2b_0mf.b, 2b_0mm.b, 2b_0mlx., 2b_m0_stop") 1488(exclusion_set "2b_1m_bs" 1489 "2b_1mi.i, 2b_1mm.i, 2b_1mm.f, 2b_1mf.i, 2b_1mb.b,\ 1490 2b_1mi.b, 2b_1mf.b, 2b_1mm.b, 2b_1mlx., 2b_m1_stop") 1491(exclusion_set "2b_0mi_bs" "2b_0mii., 2b_0mib., 2b_mi0_stop") 1492(exclusion_set "2b_1mi_bs" "2b_1mii., 2b_1mib., 2b_mi1_stop") 1493(exclusion_set "2b_0mm_bs" "2b_0mmi., 2b_0mmf., 2b_0mmb.") 1494(exclusion_set "2b_1mm_bs" "2b_1mmi., 2b_1mmf., 2b_1mmb.") 1495(exclusion_set "2b_0mf_bs" "2b_0mfi., 2b_0mfb.") 1496(exclusion_set "2b_1mf_bs" "2b_1mfi., 2b_1mfb.") 1497(exclusion_set "2b_0b_bs" "2b_0bb.b") 1498(exclusion_set "2b_1b_bs" "2b_1bb.b") 1499(exclusion_set "2b_0bb_bs" "2b_0bbb.") 1500(exclusion_set "2b_1bb_bs" "2b_1bbb.") 1501(exclusion_set "2b_0mb_bs" "2b_0mbb.") 1502(exclusion_set "2b_1mb_bs" "2b_1mbb.") 1503 1504(exclusion_set 1505 "2b_0m_bs, 2b_0mi_bs, 2b_0mm_bs, 2b_0mf_bs, 2b_0b_bs, 2b_0bb_bs, 2b_0mb_bs, 1506 2b_1m_bs, 2b_1mi_bs, 2b_1mm_bs, 2b_1mf_bs, 2b_1b_bs, 2b_1bb_bs, 2b_1mb_bs" 1507 "2b_stop") 1508 1509(final_presence_set 1510 "2b_0mi.i, 2b_0mm.i, 2b_0mf.i, 2b_0mm.f, 2b_0mb.b,\ 1511 2b_0mi.b, 2b_0mm.b, 2b_0mf.b, 2b_0mlx." 1512 "2b_m_cont") 1513(final_presence_set "2b_0mii., 2b_0mib." "2b_mi_cont") 1514(final_presence_set "2b_0mmi., 2b_0mmf., 2b_0mmb." "2b_mm_cont") 1515(final_presence_set "2b_0mfi., 2b_0mfb." "2b_mf_cont") 1516(final_presence_set "2b_0bb.b" "2b_b_cont") 1517(final_presence_set "2b_0bbb." "2b_bb_cont") 1518(final_presence_set "2b_0mbb." "2b_mb_cont") 1519 1520(exclusion_set 1521 "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ 1522 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx" 1523 "2b_m_cont, 2b_mi_cont, 2b_mm_cont, 2b_mf_cont,\ 1524 2b_mb_cont, 2b_b_cont, 2b_bb_cont") 1525 1526(exclusion_set "2b_empty" 1527 "2b_m_cont,2b_mi_cont,2b_mm_cont,2b_mf_cont,\ 1528 2b_mb_cont,2b_b_cont,2b_bb_cont") 1529 1530;; For m;mi bundle 1531(final_presence_set "2b_m0_stop" "2b_0m.mi") 1532(final_presence_set "2b_0mm.i" "2b_0mmi_cont") 1533(exclusion_set "2b_0mmi_cont" 1534 "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ 1535 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1536(exclusion_set "2b_m0_stop" "2b_0mm.i") 1537(final_presence_set "2b_m1_stop" "2b_1m.mi") 1538(exclusion_set "2b_m1_stop" "2b_1mm.i") 1539(final_presence_set "2b_m_stop" "2b_m0_stop, 2b_m1_stop") 1540 1541;; For mi;i bundle 1542(final_presence_set "2b_mi0_stop" "2b_0mi.i") 1543(final_presence_set "2b_0mii." "2b_0mii_cont") 1544(exclusion_set "2b_0mii_cont" 1545 "2b_0m.ii, 2b_0m.mi, 2b_0m.fi, 2b_0m.mf, 2b_0b.bb, 2b_0m.bb,\ 1546 2b_0m.ib, 2b_0m.mb, 2b_0m.fb, 2b_0m.lx") 1547(exclusion_set "2b_mi0_stop" "2b_0mii.") 1548(final_presence_set "2b_mi1_stop" "2b_1mi.i") 1549(exclusion_set "2b_mi1_stop" "2b_1mii.") 1550(final_presence_set "2b_mi_stop" "2b_mi0_stop, 2b_mi1_stop") 1551 1552(final_absence_set 1553 "2b_0m.ii,2b_0mi.i,2b_0mii.,2b_0m.mi,2b_0mm.i,2b_0mmi.,\ 1554 2b_0m.fi,2b_0mf.i,2b_0mfi.,2b_0m.mf,2b_0mm.f,2b_0mmf.,\ 1555 2b_0b.bb,2b_0bb.b,2b_0bbb.,2b_0m.bb,2b_0mb.b,2b_0mbb.,\ 1556 2b_0m.ib,2b_0mi.b,2b_0mib.,2b_0m.mb,2b_0mm.b,2b_0mmb.,\ 1557 2b_0m.fb,2b_0mf.b,2b_0mfb.,2b_0m.lx,2b_0mlx., \ 1558 2b_1m.ii,2b_1mi.i,2b_1mii.,2b_1m.mi,2b_1mm.i,2b_1mmi.,\ 1559 2b_1m.fi,2b_1mf.i,2b_1mfi.,2b_1m.mf,2b_1mm.f,2b_1mmf.,\ 1560 2b_1b.bb,2b_1bb.b,2b_1bbb.,2b_1m.bb,2b_1mb.b,2b_1mbb.,\ 1561 2b_1m.ib,2b_1mi.b,2b_1mib.,2b_1m.mb,2b_1mm.b,2b_1mmb.,\ 1562 2b_1m.fb,2b_1mf.b,2b_1mfb.,2b_1m.lx,2b_1mlx." 1563 "2b_m0_stop,2b_m1_stop,2b_mi0_stop,2b_mi1_stop") 1564 1565(define_insn_reservation "2b_stop_bit" 0 1566 (and (and (eq_attr "cpu" "itanium2") 1567 (eq_attr "itanium_class" "stop_bit")) 1568 (match_test "bundling_p")) 1569 "2b_stop|2b_m0_stop|2b_m1_stop|2b_mi0_stop|2b_mi1_stop") 1570(define_insn_reservation "2b_br" 0 1571 (and (and (eq_attr "cpu" "itanium2") 1572 (eq_attr "itanium_class" "br")) 1573 (match_test "bundling_p")) "2b_B") 1574(define_insn_reservation "2b_scall" 0 1575 (and (and (eq_attr "cpu" "itanium2") 1576 (eq_attr "itanium_class" "scall")) 1577 (match_test "bundling_p")) "2b_B") 1578(define_insn_reservation "2b_fcmp" 2 1579 (and (and (eq_attr "cpu" "itanium2") 1580 (eq_attr "itanium_class" "fcmp")) 1581 (match_test "bundling_p")) "2b_F") 1582(define_insn_reservation "2b_fcvtfx" 4 1583 (and (and (eq_attr "cpu" "itanium2") 1584 (eq_attr "itanium_class" "fcvtfx")) 1585 (match_test "bundling_p")) "2b_F") 1586(define_insn_reservation "2b_fld" 6 1587 (and (and (and (and (eq_attr "cpu" "itanium2") 1588 (eq_attr "itanium_class" "fld")) 1589 (eq_attr "data_speculative" "no")) 1590 (eq_attr "check_load" "no")) 1591 (match_test "bundling_p")) 1592 "2b_M") 1593(define_insn_reservation "2b_flda" 6 1594 (and (and (and (eq_attr "cpu" "itanium2") 1595 (eq_attr "itanium_class" "fld")) 1596 (eq_attr "data_speculative" "yes")) 1597 (match_test "bundling_p")) 1598 "2b_M_only_um01") 1599(define_insn_reservation "2b_fldc" 0 1600 (and (and (and (eq_attr "cpu" "itanium2") 1601 (eq_attr "itanium_class" "fld")) 1602 (eq_attr "check_load" "yes")) 1603 (match_test "bundling_p")) 1604 "2b_M_only_um01") 1605 1606(define_insn_reservation "2b_fldp" 6 1607 (and (and (and (eq_attr "cpu" "itanium2") 1608 (eq_attr "itanium_class" "fldp")) 1609 (eq_attr "check_load" "no")) 1610 (match_test "bundling_p")) 1611 "2b_M_only_um01") 1612(define_insn_reservation "2b_fldpc" 0 1613 (and (and (and (eq_attr "cpu" "itanium2") 1614 (eq_attr "itanium_class" "fldp")) 1615 (eq_attr "check_load" "yes")) 1616 (match_test "bundling_p")) 1617 "2b_M_only_um01") 1618 1619(define_insn_reservation "2b_fmac" 4 1620 (and (and (eq_attr "cpu" "itanium2") 1621 (eq_attr "itanium_class" "fmac")) 1622 (match_test "bundling_p")) "2b_F") 1623(define_insn_reservation "2b_fmisc" 4 1624 (and (and (eq_attr "cpu" "itanium2") 1625 (eq_attr "itanium_class" "fmisc")) 1626 (match_test "bundling_p")) "2b_F") 1627 1628;; Latency time ??? 1629(define_insn_reservation "2b_frar_i" 13 1630 (and (and (eq_attr "cpu" "itanium2") 1631 (eq_attr "itanium_class" "frar_i")) 1632 (match_test "bundling_p")) 1633 "2b_I+2b_only_ui0") 1634;; Latency time ??? 1635(define_insn_reservation "2b_frar_m" 6 1636 (and (and (eq_attr "cpu" "itanium2") 1637 (eq_attr "itanium_class" "frar_m")) 1638 (match_test "bundling_p")) 1639 "2b_M_only_um2") 1640(define_insn_reservation "2b_frbr" 2 1641 (and (and (eq_attr "cpu" "itanium2") 1642 (eq_attr "itanium_class" "frbr")) 1643 (match_test "bundling_p")) 1644 "2b_I+2b_only_ui0") 1645(define_insn_reservation "2b_frfr" 5 1646 (and (and (eq_attr "cpu" "itanium2") 1647 (eq_attr "itanium_class" "frfr")) 1648 (match_test "bundling_p")) 1649 "2b_M_only_um2") 1650(define_insn_reservation "2b_frpr" 2 1651 (and (and (eq_attr "cpu" "itanium2") 1652 (eq_attr "itanium_class" "frpr")) 1653 (match_test "bundling_p")) 1654 "2b_I+2b_only_ui0") 1655 1656(define_insn_reservation "2b_ialu" 1 1657 (and (and (eq_attr "cpu" "itanium2") 1658 (eq_attr "itanium_class" "ialu")) 1659 (match_test "bundling_p")) 1660 "2b_A") 1661(define_insn_reservation "2b_icmp" 1 1662 (and (and (eq_attr "cpu" "itanium2") 1663 (eq_attr "itanium_class" "icmp")) 1664 (match_test "bundling_p")) "2b_A") 1665(define_insn_reservation "2b_ilog" 1 1666 (and (and (eq_attr "cpu" "itanium2") 1667 (eq_attr "itanium_class" "ilog")) 1668 (match_test "bundling_p")) "2b_A") 1669(define_insn_reservation "2b_mmalua" 2 1670 (and (and (eq_attr "cpu" "itanium2") 1671 (eq_attr "itanium_class" "mmalua")) 1672 (match_test "bundling_p")) "2b_A") 1673;; Latency time ??? 1674(define_insn_reservation "2b_ishf" 1 1675 (and (and (eq_attr "cpu" "itanium2") 1676 (eq_attr "itanium_class" "ishf")) 1677 (match_test "bundling_p")) 1678 "2b_I+2b_only_ui0") 1679 1680(define_insn_reservation "2b_ld" 1 1681 (and (and (and (eq_attr "cpu" "itanium2") 1682 (eq_attr "itanium_class" "ld")) 1683 (eq_attr "check_load" "no")) 1684 (match_test "bundling_p")) 1685 "2b_M_only_um01") 1686(define_insn_reservation "2b_ldc" 0 1687 (and (and (and (eq_attr "cpu" "itanium2") 1688 (eq_attr "itanium_class" "ld")) 1689 (eq_attr "check_load" "yes")) 1690 (match_test "bundling_p")) 1691 "2b_M_only_um01") 1692 1693(define_insn_reservation "2b_long_i" 1 1694 (and (and (eq_attr "cpu" "itanium2") 1695 (eq_attr "itanium_class" "long_i")) 1696 (match_test "bundling_p")) "2b_L") 1697 1698;; Latency time ??? 1699(define_insn_reservation "2b_mmmul" 2 1700 (and (and (eq_attr "cpu" "itanium2") 1701 (eq_attr "itanium_class" "mmmul")) 1702 (match_test "bundling_p")) 1703 "2b_I+2b_only_ui0") 1704;; Latency time ??? 1705(define_insn_reservation "2b_mmshf" 2 1706 (and (and (eq_attr "cpu" "itanium2") 1707 (eq_attr "itanium_class" "mmshf")) 1708 (match_test "bundling_p")) "2b_I") 1709;; Latency time ??? 1710(define_insn_reservation "2b_mmshfi" 1 1711 (and (and (eq_attr "cpu" "itanium2") 1712 (eq_attr "itanium_class" "mmshfi")) 1713 (match_test "bundling_p")) "2b_I") 1714 1715(define_insn_reservation "2b_rse_m" 0 1716 (and (and (eq_attr "cpu" "itanium2") 1717 (eq_attr "itanium_class" "rse_m")) 1718 (match_test "bundling_p")) 1719 "(2b_0m.ii|2b_0m.mi|2b_0m.fi|2b_0m.mf|2b_0m.bb\ 1720 |2b_0m.ib|2b_0m.mb|2b_0m.fb|2b_0m.lx)+2_1+2b_um0") 1721(define_insn_reservation "2b_sem" 0 1722 (and (and (eq_attr "cpu" "itanium2") 1723 (eq_attr "itanium_class" "sem")) 1724 (match_test "bundling_p")) 1725 "2b_M_only_um23") 1726 1727(define_insn_reservation "2b_stf" 1 1728 (and (and (eq_attr "cpu" "itanium2") 1729 (eq_attr "itanium_class" "stf")) 1730 (match_test "bundling_p")) 1731 "2b_M_only_um23") 1732(define_insn_reservation "2b_st" 1 1733 (and (and (eq_attr "cpu" "itanium2") 1734 (eq_attr "itanium_class" "st")) 1735 (match_test "bundling_p")) 1736 "2b_M_only_um23") 1737(define_insn_reservation "2b_syst_m0" 0 1738 (and (and (eq_attr "cpu" "itanium2") 1739 (eq_attr "itanium_class" "syst_m0")) 1740 (match_test "bundling_p")) 1741 "2b_M_only_um2") 1742(define_insn_reservation "2b_syst_m" 0 1743 (and (and (eq_attr "cpu" "itanium2") 1744 (eq_attr "itanium_class" "syst_m")) 1745 (match_test "bundling_p")) 1746 "2b_M_only_um0") 1747;; Reservation??? 1748(define_insn_reservation "2b_tbit" 1 1749 (and (and (eq_attr "cpu" "itanium2") 1750 (eq_attr "itanium_class" "tbit")) 1751 (match_test "bundling_p")) 1752 "2b_I+2b_only_ui0") 1753(define_insn_reservation "2b_toar_i" 0 1754 (and (and (eq_attr "cpu" "itanium2") 1755 (eq_attr "itanium_class" "toar_i")) 1756 (match_test "bundling_p")) 1757 "2b_I+2b_only_ui0") 1758;; Latency time ??? 1759(define_insn_reservation "2b_toar_m" 5 1760 (and (and (eq_attr "cpu" "itanium2") 1761 (eq_attr "itanium_class" "toar_m")) 1762 (match_test "bundling_p")) 1763 "2b_M_only_um2") 1764;; Latency time ??? 1765(define_insn_reservation "2b_tobr" 1 1766 (and (and (eq_attr "cpu" "itanium2") 1767 (eq_attr "itanium_class" "tobr")) 1768 (match_test "bundling_p")) 1769 "2b_I+2b_only_ui0") 1770(define_insn_reservation "2b_tofr" 5 1771 (and (and (eq_attr "cpu" "itanium2") 1772 (eq_attr "itanium_class" "tofr")) 1773 (match_test "bundling_p")) 1774 "2b_M_only_um23") 1775;; Latency time ??? 1776(define_insn_reservation "2b_topr" 1 1777 (and (and (eq_attr "cpu" "itanium2") 1778 (eq_attr "itanium_class" "topr")) 1779 (match_test "bundling_p")) 1780 "2b_I+2b_only_ui0") 1781 1782(define_insn_reservation "2b_xmpy" 4 1783 (and (and (eq_attr "cpu" "itanium2") 1784 (eq_attr "itanium_class" "xmpy")) 1785 (match_test "bundling_p")) "2b_F") 1786;; Latency time ??? 1787(define_insn_reservation "2b_xtd" 1 1788 (and (and (eq_attr "cpu" "itanium2") 1789 (eq_attr "itanium_class" "xtd")) 1790 (match_test "bundling_p")) "2b_I") 1791 1792(define_insn_reservation "2b_chk_s_i" 0 1793 (and (and (eq_attr "cpu" "itanium2") 1794 (eq_attr "itanium_class" "chk_s_i")) 1795 (match_test "bundling_p")) 1796 "2b_I|2b_M_only_um23") 1797(define_insn_reservation "2b_chk_s_f" 0 1798 (and (and (eq_attr "cpu" "itanium2") 1799 (eq_attr "itanium_class" "chk_s_f")) 1800 (match_test "bundling_p")) 1801 "2b_M_only_um23") 1802(define_insn_reservation "2b_chk_a" 0 1803 (and (and (eq_attr "cpu" "itanium2") 1804 (eq_attr "itanium_class" "chk_a")) 1805 (match_test "bundling_p")) 1806 "2b_M_only_um01") 1807 1808(define_insn_reservation "2b_lfetch" 0 1809 (and (and (eq_attr "cpu" "itanium2") 1810 (eq_attr "itanium_class" "lfetch")) 1811 (match_test "bundling_p")) 1812 "2b_M_only_um01") 1813(define_insn_reservation "2b_nop_m" 0 1814 (and (and (eq_attr "cpu" "itanium2") 1815 (eq_attr "itanium_class" "nop_m")) 1816 (match_test "bundling_p")) "2b_M") 1817(define_insn_reservation "2b_nop_b" 0 1818 (and (and (eq_attr "cpu" "itanium2") 1819 (eq_attr "itanium_class" "nop_b")) 1820 (match_test "bundling_p")) "2b_NB") 1821(define_insn_reservation "2b_nop_i" 0 1822 (and (and (eq_attr "cpu" "itanium2") 1823 (eq_attr "itanium_class" "nop_i")) 1824 (match_test "bundling_p")) "2b_I") 1825(define_insn_reservation "2b_nop_f" 0 1826 (and (and (eq_attr "cpu" "itanium2") 1827 (eq_attr "itanium_class" "nop_f")) 1828 (match_test "bundling_p")) "2b_F") 1829(define_insn_reservation "2b_nop_x" 0 1830 (and (and (eq_attr "cpu" "itanium2") 1831 (eq_attr "itanium_class" "nop_x")) 1832 (match_test "bundling_p")) "2b_L") 1833(define_insn_reservation "2b_unknown" 1 1834 (and (and (eq_attr "cpu" "itanium2") 1835 (eq_attr "itanium_class" "unknown")) 1836 (match_test "bundling_p")) "2b_empty") 1837(define_insn_reservation "2b_nop" 0 1838 (and (and (eq_attr "cpu" "itanium2") 1839 (eq_attr "itanium_class" "nop")) 1840 (match_test "bundling_p")) 1841 "2b_M|2b_NB|2b_I|2b_F") 1842(define_insn_reservation "2b_ignore" 0 1843 (and (and (eq_attr "cpu" "itanium2") 1844 (eq_attr "itanium_class" "ignore")) 1845 (match_test "bundling_p")) "nothing") 1846 1847(define_insn_reservation "2b_pre_cycle" 0 1848 (and (and (eq_attr "cpu" "itanium2") 1849 (eq_attr "itanium_class" "pre_cycle")) 1850 (match_test "bundling_p")) 1851 "(2b_0m_bs, 2b_m_cont) \ 1852 | (2b_0mi_bs, 2b_mi_cont) \ 1853 | (2b_0mm_bs, 2b_mm_cont) \ 1854 | (2b_0mf_bs, 2b_mf_cont) \ 1855 | (2b_0b_bs, 2b_b_cont) \ 1856 | (2b_0bb_bs, 2b_bb_cont) \ 1857 | (2b_0mb_bs, 2b_mb_cont) \ 1858 | (2b_1m_bs, 2b_m_cont) \ 1859 | (2b_1mi_bs, 2b_mi_cont) \ 1860 | (2b_1mm_bs, 2b_mm_cont) \ 1861 | (2b_1mf_bs, 2b_mf_cont) \ 1862 | (2b_1b_bs, 2b_b_cont) \ 1863 | (2b_1bb_bs, 2b_bb_cont) \ 1864 | (2b_1mb_bs, 2b_mb_cont) \ 1865 | (2b_m_stop, 2b_0mmi_cont) \ 1866 | (2b_mi_stop, 2b_0mii_cont)") 1867 1868