1/* Definitions of x86 tunable features. 2 Copyright (C) 2013-2020 Free Software Foundation, Inc. 3 4This file is part of GCC. 5 6GCC is free software; you can redistribute it and/or modify 7it under the terms of the GNU General Public License as published by 8the Free Software Foundation; either version 3, or (at your option) 9any later version. 10 11GCC is distributed in the hope that it will be useful, 12but WITHOUT ANY WARRANTY; without even the implied warranty of 13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14GNU General Public License for more details. 15 16You should have received a copy of the GNU General Public License and 17a copy of the GCC Runtime Library Exception along with this program; 18see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 19<http://www.gnu.org/licenses/>. */ 20 21/* Tuning for a given CPU XXXX consists of: 22 - adding new CPU into: 23 - adding PROCESSOR_XXX to processor_type (in i386.h) 24 - possibly adding XXX into CPU attribute in i386.md 25 - adding XXX to processor_alias_table (in i386.c) 26 - introducing ix86_XXX_cost in i386.c 27 - Stringop generation table can be build based on test_stringop 28 - script (once rest of tuning is complete) 29 - designing a scheduler model in 30 - XXXX.md file 31 - Updating ix86_issue_rate and ix86_adjust_cost in i386.md 32 - possibly updating ia32_multipass_dfa_lookahead, ix86_sched_reorder 33 and ix86_sched_init_global if those tricks are needed. 34 - Tunning the flags bellow. Those are split into sections and each 35 section is very roughly ordered by importance. */ 36 37/*****************************************************************************/ 38/* Scheduling flags. */ 39/*****************************************************************************/ 40 41/* X86_TUNE_SCHEDULE: Enable scheduling. */ 42DEF_TUNE (X86_TUNE_SCHEDULE, "schedule", 43 m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT 44 | m_INTEL | m_KNL | m_KNM | m_K6_GEODE | m_AMD_MULTIPLE | m_GOLDMONT 45 | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC) 46 47/* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming 48 on modern chips. Preffer stores affecting whole integer register 49 over partial stores. For example preffer MOVZBL or MOVQ to load 8bit 50 value over movb. */ 51DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency", 52 m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 53 | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL 54 | m_KNL | m_KNM | m_AMD_MULTIPLE | m_TREMONT 55 | m_GENERIC) 56 57/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store 58 destinations to be 128bit to allow register renaming on 128bit SSE units, 59 but usually results in one extra microop on 64bit SSE units. 60 Experimental results shows that disabling this option on P4 brings over 20% 61 SPECfp regression, while enabling it on K8 brings roughly 2.4% regression 62 that can be partly masked by careful scheduling of moves. */ 63DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency", 64 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10 65 | m_BDVER | m_ZNVER | m_GENERIC) 66 67/* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies 68 are resolved on SSE register parts instead of whole registers, so we may 69 maintain just lower part of scalar values in proper format leaving the 70 upper part undefined. */ 71DEF_TUNE (X86_TUNE_SSE_SPLIT_REGS, "sse_split_regs", m_ATHLON_K8) 72 73/* X86_TUNE_PARTIAL_FLAG_REG_STALL: this flag disables use of flags 74 set by instructions affecting just some flags (in particular shifts). 75 This is because Core2 resolves dependencies on whole flags register 76 and such sequences introduce false dependency on previous instruction 77 setting full flags. 78 79 The flags does not affect generation of INC and DEC that is controlled 80 by X86_TUNE_USE_INCDEC. */ 81 82DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall", 83 m_CORE2) 84 85/* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid 86 partial dependencies. */ 87DEF_TUNE (X86_TUNE_MOVX, "movx", 88 m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE 89 | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM | m_INTEL 90 | m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE 91 | m_CORE_AVX2 | m_TREMONT | m_GENERIC) 92 93/* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by 94 full sized loads. */ 95DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall", 96 m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL 97 | m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE 98 | m_TREMONT | m_GENERIC) 99 100/* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent 101 conditional jump instruction for 32 bit TARGET. */ 102DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, "fuse_cmp_and_branch_32", 103 m_CORE_ALL | m_BDVER | m_ZNVER | m_GENERIC) 104 105/* X86_TUNE_FUSE_CMP_AND_BRANCH_64: Fuse compare with a subsequent 106 conditional jump instruction for TARGET_64BIT. */ 107DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, "fuse_cmp_and_branch_64", 108 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER 109 | m_ZNVER | m_GENERIC) 110 111/* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a 112 subsequent conditional jump instruction when the condition jump 113 check sign flag (SF) or overflow flag (OF). */ 114DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, "fuse_cmp_and_branch_soflags", 115 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER 116 | m_ZNVER | m_GENERIC) 117 118/* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional 119 jump instruction when the alu instruction produces the CCFLAG consumed by 120 the conditional jump instruction. */ 121DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH, "fuse_alu_and_branch", 122 m_SANDYBRIDGE | m_CORE_AVX2 | m_GENERIC) 123 124 125/*****************************************************************************/ 126/* Function prologue, epilogue and function calling sequences. */ 127/*****************************************************************************/ 128 129/* X86_TUNE_ACCUMULATE_OUTGOING_ARGS: Allocate stack space for outgoing 130 arguments in prologue/epilogue instead of separately for each call 131 by push/pop instructions. 132 This increase code size by about 5% in 32bit mode, less so in 64bit mode 133 because parameters are passed in registers. It is considerable 134 win for targets without stack engine that prevents multple push operations 135 to happen in parallel. */ 136 137DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS, "accumulate_outgoing_args", 138 m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL 139 | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ATHLON_K8) 140 141/* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in prologues that are 142 considered on critical path. */ 143DEF_TUNE (X86_TUNE_PROLOGUE_USING_MOVE, "prologue_using_move", 144 m_PPRO | m_ATHLON_K8) 145 146/* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in epilogues that are 147 considered on critical path. */ 148DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE, "epilogue_using_move", 149 m_PPRO | m_ATHLON_K8) 150 151/* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits. */ 152DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave", 153 m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC) 154 155/* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions. 156 Some chips, like 486 and Pentium works faster with separate load 157 and push instructions. */ 158DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory", 159 m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE 160 | m_GENERIC) 161 162/* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred 163 over esp subtraction. */ 164DEF_TUNE (X86_TUNE_SINGLE_PUSH, "single_push", m_386 | m_486 | m_PENT 165 | m_LAKEMONT | m_K6_GEODE) 166 167/* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred 168 over esp subtraction. */ 169DEF_TUNE (X86_TUNE_DOUBLE_PUSH, "double_push", m_PENT | m_LAKEMONT 170 | m_K6_GEODE) 171 172/* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred 173 over esp addition. */ 174DEF_TUNE (X86_TUNE_SINGLE_POP, "single_pop", m_386 | m_486 | m_PENT 175 | m_LAKEMONT | m_PPRO) 176 177/* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred 178 over esp addition. */ 179DEF_TUNE (X86_TUNE_DOUBLE_POP, "double_pop", m_PENT | m_LAKEMONT) 180 181/*****************************************************************************/ 182/* Branch predictor tuning */ 183/*****************************************************************************/ 184 185/* X86_TUNE_PAD_SHORT_FUNCTION: Make every function to be at least 4 186 instructions long. */ 187DEF_TUNE (X86_TUNE_PAD_SHORT_FUNCTION, "pad_short_function", m_BONNELL) 188 189/* X86_TUNE_PAD_RETURNS: Place NOP before every RET that is a destination 190 of conditional jump or directly preceded by other jump instruction. 191 This is important for AND K8-AMDFAM10 because the branch prediction 192 architecture expect at most one jump per 2 byte window. Failing to 193 pad returns leads to misaligned return stack. */ 194DEF_TUNE (X86_TUNE_PAD_RETURNS, "pad_returns", 195 m_ATHLON_K8 | m_AMDFAM10) 196 197/* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more 198 than 4 branch instructions in the 16 byte window. */ 199DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT, "four_jump_limit", 200 m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM 201 | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL | m_ATHLON_K8 202 | m_AMDFAM10) 203 204/*****************************************************************************/ 205/* Integer instruction selection tuning */ 206/*****************************************************************************/ 207 208/* X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL: Enable software prefetching 209 at -O3. For the moment, the prefetching seems badly tuned for Intel 210 chips. */ 211DEF_TUNE (X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL, "software_prefetching_beneficial", 212 m_K6_GEODE | m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER) 213 214/* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall 215 on 16-bit immediate moves into memory on Core2 and Corei7. */ 216DEF_TUNE (X86_TUNE_LCP_STALL, "lcp_stall", m_CORE_ALL | m_GENERIC) 217 218/* X86_TUNE_READ_MODIFY: Enable use of read-modify instructions such 219 as "add mem, reg". */ 220DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMONT | m_PPRO)) 221 222/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions. 223 224 Core2 and nehalem has stall of 7 cycles for partial flag register stalls. 225 Sandy bridge and Ivy bridge generate extra uop. On Haswell this extra uop 226 is output only when the values needs to be really merged, which is not 227 done by GCC generated code. */ 228DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec", 229 ~(m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE 230 | m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_GOLDMONT 231 | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC)) 232 233/* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred 234 for DFmode copies */ 235DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves", 236 ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT 237 | m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GOLDMONT 238 | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC)) 239 240/* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag 241 will impact LEA instruction selection. */ 242DEF_TUNE (X86_TUNE_OPT_AGU, "opt_agu", m_BONNELL | m_SILVERMONT | m_KNL 243 | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL) 244 245/* X86_TUNE_AVOID_LEA_FOR_ADDR: Avoid lea for address computation. */ 246DEF_TUNE (X86_TUNE_AVOID_LEA_FOR_ADDR, "avoid_lea_for_addr", 247 m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT 248 | m_KNL | m_KNM) 249 250/* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is 251 vector path on AMD machines. 252 FIXME: Do we need to enable this for core? */ 253DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM32_MEM, "slow_imul_imm32_mem", 254 m_K8 | m_AMDFAM10) 255 256/* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD 257 machines. 258 FIXME: Do we need to enable this for core? */ 259DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8, "slow_imul_imm8", 260 m_K8 | m_AMDFAM10) 261 262/* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for 263 a conditional move. */ 264DEF_TUNE (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE, "avoid_mem_opnd_for_cmove", 265 m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_KNL 266 | m_KNM | m_TREMONT | m_INTEL) 267 268/* X86_TUNE_SINGLE_STRINGOP: Enable use of single string operations, such 269 as MOVS and STOS (without a REP prefix) to move/set sequences of bytes. */ 270DEF_TUNE (X86_TUNE_SINGLE_STRINGOP, "single_stringop", m_386 | m_P4_NOCONA) 271 272/* X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES: Enable generation of 273 compact prologues and epilogues by issuing a misaligned moves. This 274 requires target to handle misaligned moves and partial memory stalls 275 reasonably well. 276 FIXME: This may actualy be a win on more targets than listed here. */ 277DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES, 278 "misaligned_move_string_pro_epilogues", 279 m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_GENERIC) 280 281/* X86_TUNE_USE_SAHF: Controls use of SAHF. */ 282DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf", 283 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT 284 | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER 285 | m_BTVER | m_ZNVER | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT 286 | m_GENERIC) 287 288/* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */ 289DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd", 290 ~(m_PENT | m_LAKEMONT | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL 291 | m_K6 | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT)) 292 293/* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions. */ 294DEF_TUNE (X86_TUNE_USE_BT, "use_bt", 295 m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL 296 | m_LAKEMONT | m_AMD_MULTIPLE | m_GOLDMONT | m_GOLDMONT_PLUS 297 | m_TREMONT | m_GENERIC) 298 299/* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency 300 for bit-manipulation instructions. */ 301DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI, "avoid_false_dep_for_bmi", 302 m_SANDYBRIDGE | m_CORE_AVX2 | m_GENERIC) 303 304/* X86_TUNE_ADJUST_UNROLL: This enables adjusting the unroll factor based 305 on hardware capabilities. Bdver3 hardware has a loop buffer which makes 306 unrolling small loop less important. For, such architectures we adjust 307 the unroll factor so that the unrolled loop fits the loop buffer. */ 308DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4) 309 310/* X86_TUNE_ONE_IF_CONV_INSNS: Restrict a number of cmov insns in 311 if-converted sequence to one. */ 312DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn", 313 m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT 314 | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC) 315 316/* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence. */ 317DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence", 318 m_CORE_ALL | m_BDVER | m_ZNVER | m_GENERIC) 319 320/* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by 321 generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) - 322 (signed) x >> (W-1)) instead of cmove or SSE max/abs instructions. */ 323DEF_TUNE (X86_TUNE_EXPAND_ABS, "expand_abs", 324 m_CORE_ALL | m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT 325 | m_GOLDMONT_PLUS | m_TREMONT ) 326 327/*****************************************************************************/ 328/* 387 instruction selection tuning */ 329/*****************************************************************************/ 330 331/* X86_TUNE_USE_HIMODE_FIOP: Enables use of x87 instructions with 16bit 332 integer operand. 333 FIXME: Why this is disabled for modern chips? */ 334DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP, "use_himode_fiop", 335 m_386 | m_486 | m_K6_GEODE) 336 337/* X86_TUNE_USE_SIMODE_FIOP: Enables use of x87 instructions with 32bit 338 integer operand. */ 339DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop", 340 ~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL 341 | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE 342 | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC)) 343 344/* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */ 345DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE) 346 347/* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI. */ 348DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants", 349 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT 350 | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_GOLDMONT 351 | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC) 352 353/*****************************************************************************/ 354/* SSE instruction selection tuning */ 355/*****************************************************************************/ 356 357/* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE 358 regs instead of memory. */ 359DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill", 360 m_CORE_ALL) 361 362/* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL: Use movups for misaligned loads instead 363 of a sequence loading registers by parts. */ 364DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal", 365 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM 366 | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS 367 | m_TREMONT | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_GENERIC) 368 369/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores 370 instead of a sequence loading registers by parts. */ 371DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal", 372 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM 373 | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS 374 | m_TREMONT | m_BDVER | m_ZNVER | m_GENERIC) 375 376/* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single 377 precision 128bit instructions instead of double where possible. */ 378DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optimal", 379 m_BDVER | m_ZNVER) 380 381/* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores. */ 382DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores", 383 m_AMD_MULTIPLE | m_CORE_ALL | m_GENERIC) 384 385/* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to 386 xorps/xorpd and other variants. */ 387DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor", 388 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER 389 | m_GENERIC) 390 391/* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer 392 to SSE registers. If disabled, the moves will be done by storing 393 the value to memory and reloading. 394 Enable this flag for generic - the only relevant architecture preferring 395 no inter-unit moves is Buldozer. While this makes small regression on SPECfp 396 scores (sub 0.3%), disabling inter-unit moves penalizes noticeably hand 397 written vectorized code which use i.e. _mm_set_epi16. */ 398DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_TO_VEC, "inter_unit_moves_to_vec", 399 ~(m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)) 400 401/* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from SSE 402 to integer registers. If disabled, the moves will be done by storing 403 the value to memory and reloading. */ 404DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_FROM_VEC, "inter_unit_moves_from_vec", 405 ~m_ATHLON_K8) 406 407/* X86_TUNE_INTER_UNIT_CONVERSIONS: Enable float<->integer conversions 408 to use both SSE and integer registers at a same time. */ 409DEF_TUNE (X86_TUNE_INTER_UNIT_CONVERSIONS, "inter_unit_conversions", 410 ~(m_AMDFAM10 | m_BDVER)) 411 412/* X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS: Try to split memory operand for 413 fp converts to destination register. */ 414DEF_TUNE (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS, "split_mem_opnd_for_fp_converts", 415 m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS 416 | m_TREMONT | m_INTEL) 417 418/* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion 419 from FP to FP. This form of instructions avoids partial write to the 420 destination. */ 421DEF_TUNE (X86_TUNE_USE_VECTOR_FP_CONVERTS, "use_vector_fp_converts", 422 m_AMDFAM10) 423 424/* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion 425 from integer to FP. */ 426DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS, "use_vector_converts", m_AMDFAM10) 427 428/* X86_TUNE_SLOW_SHUFB: Indicates tunings with slow pshufb instruction. */ 429DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb", 430 m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT 431 | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL) 432 433/* X86_TUNE_AVOID_4BYTE_PREFIXES: Avoid instructions requiring 4+ bytes of prefixes. */ 434DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes", 435 m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL) 436 437/* X86_TUNE_USE_GATHER: Use gather instructions. */ 438DEF_TUNE (X86_TUNE_USE_GATHER, "use_gather", 439 ~(m_ZNVER | m_GENERIC)) 440 441/* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or 442 smaller FMA chain. */ 443DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER) 444 445/* X86_TUNE_AVOID_256FMA_CHAINS: Avoid creating loops with tight 256bit or 446 smaller FMA chain. */ 447DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, "avoid_fma256_chains", m_ZNVER2 | m_ZNVER3) 448 449/*****************************************************************************/ 450/* AVX instruction selection tuning (some of SSE flags affects AVX, too) */ 451/*****************************************************************************/ 452 453/* X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL: if false, unaligned loads are 454 split. */ 455DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL, "256_unaligned_load_optimal", 456 ~(m_NEHALEM | m_SANDYBRIDGE | m_GENERIC)) 457 458/* X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL: if false, unaligned stores are 459 split. */ 460DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL, "256_unaligned_store_optimal", 461 ~(m_NEHALEM | m_SANDYBRIDGE | m_BDVER | m_ZNVER1 | m_GENERIC)) 462 463/* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX256 ops are split into two AVX128 ops. */ 464DEF_TUNE (X86_TUNE_AVX256_SPLIT_REGS, "avx256_split_regs",m_BDVER | m_BTVER2 465 | m_ZNVER1) 466 467/* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for 468 the auto-vectorizer. */ 469DEF_TUNE (X86_TUNE_AVX128_OPTIMAL, "avx128_optimal", m_BDVER | m_BTVER2 470 | m_ZNVER1) 471 472/* X86_TUNE_AVX256_OPTIMAL: Use 256-bit AVX instructions instead of 512-bit AVX 473 instructions in the auto-vectorizer. */ 474DEF_TUNE (X86_TUNE_AVX256_OPTIMAL, "avx256_optimal", m_CORE_AVX512) 475 476/*****************************************************************************/ 477/* Historical relics: tuning flags that helps a specific old CPU designs */ 478/*****************************************************************************/ 479 480/* X86_TUNE_DOUBLE_WITH_ADD: Use add instead of sal to double value in 481 an integer register. */ 482DEF_TUNE (X86_TUNE_DOUBLE_WITH_ADD, "double_with_add", ~m_386) 483 484/* X86_TUNE_ALWAYS_FANCY_MATH_387: controls use of fancy 387 operations, 485 such as fsqrt, fprem, fsin, fcos, fsincos etc. 486 Should be enabled for all targets that always has coprocesor. */ 487DEF_TUNE (X86_TUNE_ALWAYS_FANCY_MATH_387, "always_fancy_math_387", 488 ~(m_386 | m_486 | m_LAKEMONT)) 489 490/* X86_TUNE_UNROLL_STRLEN: Produce (quite lame) unrolled sequence for 491 inline strlen. This affects only -minline-all-stringops mode. By 492 default we always dispatch to a library since our internal strlen 493 is bad. */ 494DEF_TUNE (X86_TUNE_UNROLL_STRLEN, "unroll_strlen", ~m_386) 495 496/* X86_TUNE_SHIFT1: Enables use of short encoding of "sal reg" instead of 497 longer "sal $1, reg". */ 498DEF_TUNE (X86_TUNE_SHIFT1, "shift1", ~m_486) 499 500/* X86_TUNE_ZERO_EXTEND_WITH_AND: Use AND instruction instead 501 of mozbl/movwl. */ 502DEF_TUNE (X86_TUNE_ZERO_EXTEND_WITH_AND, "zero_extend_with_and", 503 m_486 | m_PENT) 504 505/* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode 506 and SImode multiply, but 386 and 486 do HImode multiply faster. */ 507DEF_TUNE (X86_TUNE_PROMOTE_HIMODE_IMUL, "promote_himode_imul", 508 ~(m_386 | m_486)) 509 510/* X86_TUNE_FAST_PREFIX: Enable demoting some 32bit or 64bit arithmetic 511 into 16bit/8bit when resulting sequence is shorter. For example 512 for "and $-65536, reg" to 16bit store of 0. */ 513DEF_TUNE (X86_TUNE_FAST_PREFIX, "fast_prefix", 514 ~(m_386 | m_486 | m_PENT | m_LAKEMONT)) 515 516/* X86_TUNE_READ_MODIFY_WRITE: Enable use of read modify write instructions 517 such as "add $1, mem". */ 518DEF_TUNE (X86_TUNE_READ_MODIFY_WRITE, "read_modify_write", 519 ~(m_PENT | m_LAKEMONT)) 520 521/* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR 522 than a MOV. */ 523DEF_TUNE (X86_TUNE_MOVE_M1_VIA_OR, "move_m1_via_or", m_PENT | m_LAKEMONT) 524 525/* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is, 526 but one byte longer. */ 527DEF_TUNE (X86_TUNE_NOT_UNPAIRABLE, "not_unpairable", m_PENT | m_LAKEMONT) 528 529/* X86_TUNE_PARTIAL_REG_STALL: Pentium pro, unlike later chips, handled 530 use of partial registers by renaming. This improved performance of 16bit 531 code where upper halves of registers are not used. It also leads to 532 an penalty whenever a 16bit store is followed by 32bit use. This flag 533 disables production of such sequences in common cases. 534 See also X86_TUNE_HIMODE_MATH. 535 536 In current implementation the partial register stalls are not eliminated 537 very well - they can be introduced via subregs synthesized by combine 538 and can happen in caller/callee saving sequences. */ 539DEF_TUNE (X86_TUNE_PARTIAL_REG_STALL, "partial_reg_stall", m_PPRO) 540 541/* X86_TUNE_PROMOTE_QIMODE: When it is cheap, turn 8bit arithmetic to 542 corresponding 32bit arithmetic. */ 543DEF_TUNE (X86_TUNE_PROMOTE_QIMODE, "promote_qimode", 544 ~m_PPRO) 545 546/* X86_TUNE_PROMOTE_HI_REGS: Same, but for 16bit artihmetic. Again we avoid 547 partial register stalls on PentiumPro targets. */ 548DEF_TUNE (X86_TUNE_PROMOTE_HI_REGS, "promote_hi_regs", m_PPRO) 549 550/* X86_TUNE_HIMODE_MATH: Enable use of 16bit arithmetic. 551 On PPro this flag is meant to avoid partial register stalls. */ 552DEF_TUNE (X86_TUNE_HIMODE_MATH, "himode_math", ~m_PPRO) 553 554/* X86_TUNE_SPLIT_LONG_MOVES: Avoid instructions moving immediates 555 directly to memory. */ 556DEF_TUNE (X86_TUNE_SPLIT_LONG_MOVES, "split_long_moves", m_PPRO) 557 558/* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */ 559DEF_TUNE (X86_TUNE_USE_XCHGB, "use_xchgb", m_PENT4) 560 561/* X86_TUNE_USE_MOV0: Use "mov $0, reg" instead of "xor reg, reg" to clear 562 integer register. */ 563DEF_TUNE (X86_TUNE_USE_MOV0, "use_mov0", m_K6) 564 565/* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory 566 operand that cannot be represented using a modRM byte. The XOR 567 replacement is long decoded, so this split helps here as well. */ 568DEF_TUNE (X86_TUNE_NOT_VECTORMODE, "not_vectormode", m_K6) 569 570/* X86_TUNE_AVOID_VECTOR_DECODE: Enable splitters that avoid vector decoded 571 forms of instructions on K8 targets. */ 572DEF_TUNE (X86_TUNE_AVOID_VECTOR_DECODE, "avoid_vector_decode", 573 m_K8) 574 575/*****************************************************************************/ 576/* This never worked well before. */ 577/*****************************************************************************/ 578 579/* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based 580 on simulation result. But after P4 was made, no performance benefit 581 was observed with branch hints. It also increases the code size. 582 As a result, icc never generates branch hints. */ 583DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS, "branch_prediction_hints", 0U) 584 585/* X86_TUNE_QIMODE_MATH: Enable use of 8bit arithmetic. */ 586DEF_TUNE (X86_TUNE_QIMODE_MATH, "qimode_math", ~0U) 587 588/* X86_TUNE_PROMOTE_QI_REGS: This enables generic code that promotes all 8bit 589 arithmetic to 32bit via PROMOTE_MODE macro. This code generation scheme 590 is usually used for RISC targets. */ 591DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", 0U) 592 593/* X86_TUNE_EMIT_VZEROUPPER: This enables vzeroupper instruction insertion 594 before a transfer of control flow out of the function. */ 595DEF_TUNE (X86_TUNE_EMIT_VZEROUPPER, "emit_vzeroupper", ~m_KNL) 596