1;; Predicate definitions for Renesas H8/300. 2;; Copyright (C) 2005-2020 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Return true if OP is a valid source operand for an integer move 21;; instruction. 22 23(define_predicate "general_operand_src" 24 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem") 25{ 26 if (GET_MODE (op) == mode 27 && GET_CODE (op) == MEM 28 && GET_CODE (XEXP (op, 0)) == POST_INC) 29 return 1; 30 return general_operand (op, mode); 31}) 32 33;; Return true if OP is a valid destination operand for an integer 34;; move instruction. 35 36(define_predicate "general_operand_dst" 37 (match_code "subreg,reg,mem") 38{ 39 if (GET_MODE (op) == mode 40 && GET_CODE (op) == MEM 41 && GET_CODE (XEXP (op, 0)) == PRE_DEC) 42 return 1; 43 return general_operand (op, mode); 44}) 45 46;; Likewise the second operand. 47 48(define_predicate "h8300_src_operand" 49 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem") 50{ 51 if (TARGET_H8300SX) 52 return general_operand (op, mode); 53 return nonmemory_operand (op, mode); 54}) 55 56;; Return true if OP is a suitable first operand for a general 57;; arithmetic insn such as "add". 58 59(define_predicate "h8300_dst_operand" 60 (match_code "subreg,reg,mem") 61{ 62 if (TARGET_H8300SX) 63 return nonimmediate_operand (op, mode); 64 return register_operand (op, mode); 65}) 66 67;; Check that an operand is either a register or an unsigned 4-bit 68;; constant. 69 70(define_predicate "nibble_operand" 71 (match_code "const_int") 72{ 73 return (GET_CODE (op) == CONST_INT && TARGET_H8300SX 74 && INTVAL (op) >= 0 && INTVAL (op) <= 15); 75}) 76 77;; Check that an operand is either a register or an unsigned 4-bit 78;; constant. 79 80(define_predicate "reg_or_nibble_operand" 81 (match_code "const_int,subreg,reg") 82{ 83 return (nibble_operand (op, mode) || register_operand (op, mode)); 84}) 85 86;; Return true if X is a shift operation of type H8SX_SHIFT_UNARY. 87 88(define_predicate "h8sx_unary_shift_operator" 89 (match_code "ashiftrt,lshiftrt,ashift,rotate") 90{ 91 return (BINARY_P (op) && NON_COMMUTATIVE_P (op) 92 && (h8sx_classify_shift (GET_MODE (op), GET_CODE (op), XEXP (op, 1)) 93 == H8SX_SHIFT_UNARY)); 94}) 95 96;; Likewise H8SX_SHIFT_BINARY. 97 98(define_predicate "h8sx_binary_shift_operator" 99 (match_code "ashiftrt,lshiftrt,ashift") 100{ 101 return (BINARY_P (op) && NON_COMMUTATIVE_P (op) 102 && (h8sx_classify_shift (GET_MODE (op), GET_CODE (op), XEXP (op, 1)) 103 == H8SX_SHIFT_BINARY)); 104}) 105 106;; Return true if OP is a binary operator in which it would be safe to 107;; replace register operands with memory operands. 108 109(define_predicate "h8sx_binary_memory_operator" 110 (match_code "plus,minus,and,ior,xor,ashift,ashiftrt,lshiftrt,rotate") 111{ 112 if (!TARGET_H8300SX) 113 return false; 114 115 if (GET_MODE (op) != QImode 116 && GET_MODE (op) != HImode 117 && GET_MODE (op) != SImode) 118 return false; 119 120 switch (GET_CODE (op)) 121 { 122 case PLUS: 123 case MINUS: 124 case AND: 125 case IOR: 126 case XOR: 127 return true; 128 129 default: 130 return h8sx_unary_shift_operator (op, mode); 131 } 132}) 133 134;; Like h8sx_binary_memory_operator, but applies to unary operators. 135 136(define_predicate "h8sx_unary_memory_operator" 137 (match_code "neg,not") 138{ 139 if (!TARGET_H8300SX) 140 return false; 141 142 if (GET_MODE (op) != QImode 143 && GET_MODE (op) != HImode 144 && GET_MODE (op) != SImode) 145 return false; 146 147 switch (GET_CODE (op)) 148 { 149 case NEG: 150 case NOT: 151 return true; 152 153 default: 154 return false; 155 } 156}) 157 158;; Return true if X is an ldm.l pattern. X is known to be parallel. 159 160(define_predicate "h8300_ldm_parallel" 161 (match_code "parallel") 162{ 163 return h8300_ldm_stm_parallel (XVEC (op, 0), 1, 0); 164}) 165 166;; Likewise stm.l. 167 168(define_predicate "h8300_stm_parallel" 169 (match_code "parallel") 170{ 171 return h8300_ldm_stm_parallel (XVEC (op, 0), 0, 0); 172}) 173 174;; Likewise rts/l and rte/l. Note that the .md pattern will check for 175;; the return so there's no need to do that here. 176 177(define_predicate "h8300_return_parallel" 178 (match_code "parallel") 179{ 180 return h8300_ldm_stm_parallel (XVEC (op, 0), 1, 1); 181}) 182 183;; Return true if OP is a constant that contains only one 1 in its 184;; binary representation. 185 186(define_predicate "single_one_operand" 187 (match_code "const_int") 188{ 189 if (GET_CODE (op) == CONST_INT) 190 { 191 /* We really need to do this masking because 0x80 in QImode is 192 represented as -128 for example. */ 193 if (exact_log2 (INTVAL (op) & GET_MODE_MASK (mode)) >= 0) 194 return 1; 195 } 196 197 return 0; 198}) 199 200;; Return true if OP is a constant that contains only one 0 in its 201;; binary representation. 202 203(define_predicate "single_zero_operand" 204 (match_code "const_int") 205{ 206 if (GET_CODE (op) == CONST_INT) 207 { 208 /* We really need to do this masking because 0x80 in QImode is 209 represented as -128 for example. */ 210 if (exact_log2 (~INTVAL (op) & GET_MODE_MASK (mode)) >= 0) 211 return 1; 212 } 213 214 return 0; 215}) 216 217;; Return true if OP is a valid call operand. 218 219(define_predicate "call_expander_operand" 220 (match_code "mem") 221{ 222 if (GET_CODE (op) == MEM) 223 { 224 rtx inside = XEXP (op, 0); 225 if (register_operand (inside, Pmode)) 226 return 1; 227 if (SYMBOL_REF_P (inside)) 228 return 1; 229 } 230 return 0; 231}) 232 233(define_predicate "call_insn_operand" 234 (match_code "reg,symbol_ref") 235{ 236 if (register_operand (op, Pmode)) 237 return 1; 238 if (SYMBOL_REF_P (op)) 239 return 1; 240 return 0; 241}) 242 243;; Return true if OP is a valid call operand, and OP represents an 244;; operand for a small call (4 bytes instead of 6 bytes). 245 246(define_predicate "small_call_insn_operand" 247 (match_code "reg,symbol_ref") 248{ 249 /* Register indirect is a small call. */ 250 if (register_operand (op, Pmode)) 251 return 1; 252 253 /* A call through the function vector is a small call too. */ 254 if (GET_CODE (op) == SYMBOL_REF 255 && (SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_FUNCVEC_FUNCTION)) 256 return 1; 257 258 /* Otherwise it's a large call. */ 259 return 0; 260}) 261 262;; Return true if OP is a valid jump operand. 263 264(define_predicate "jump_address_operand" 265 (match_code "reg,mem") 266{ 267 if (GET_CODE (op) == REG) 268 return GET_MODE (op) == Pmode; 269 270 if (GET_CODE (op) == MEM) 271 { 272 rtx inside = XEXP (op, 0); 273 if (register_operand (inside, Pmode)) 274 return 1; 275 if (CONSTANT_ADDRESS_P (inside)) 276 return 1; 277 } 278 return 0; 279}) 280 281;; Return 1 if an addition/subtraction of a constant integer can be 282;; transformed into two consecutive adds/subs that are faster than the 283;; straightforward way. Otherwise, return 0. 284 285(define_predicate "two_insn_adds_subs_operand" 286 (match_code "const_int") 287{ 288 if (TARGET_H8300SX) 289 return 0; 290 291 if (GET_CODE (op) == CONST_INT) 292 { 293 HOST_WIDE_INT value = INTVAL (op); 294 295 /* Force VALUE to be positive so that we do not have to consider 296 the negative case. */ 297 if (value < 0) 298 value = -value; 299 if (TARGET_H8300H || TARGET_H8300S) 300 { 301 /* A constant addition/subtraction takes 2 states in QImode, 302 4 states in HImode, and 6 states in SImode. Thus, the 303 only case we can win is when SImode is used, in which 304 case, two adds/subs are used, taking 4 states. */ 305 if (mode == SImode 306 && (value == 2 + 1 307 || value == 4 + 1 308 || value == 4 + 2 309 || value == 4 + 4)) 310 return 1; 311 } 312 else 313 { 314 /* We do not profit directly by splitting addition or 315 subtraction of 3 and 4. However, since these are 316 implemented as a sequence of adds or subs, they do not 317 clobber (cc0) unlike a sequence of add.b and add.x. */ 318 if (mode == HImode 319 && (value == 2 + 1 320 || value == 2 + 2)) 321 return 1; 322 } 323 } 324 325 return 0; 326}) 327 328;; Recognize valid operands for bit-field instructions. 329 330(define_predicate "bit_operand" 331 (match_code "reg,subreg,mem") 332{ 333 /* We can accept any nonimmediate operand, except that MEM operands must 334 be limited to those that use addresses valid for the 'U' constraint. */ 335 if (!nonimmediate_operand (op, mode) && !satisfies_constraint_U (op)) 336 return 0; 337 338 /* H8SX accepts pretty much anything here. */ 339 if (TARGET_H8300SX) 340 return 1; 341 342 /* Accept any mem during RTL generation. Otherwise, the code that does 343 insv and extzv will think that we cannot handle memory. However, 344 to avoid reload problems, we only accept 'U' MEM operands after RTL 345 generation. This means that any named pattern which uses this predicate 346 must force its operands to match 'U' before emitting RTL. */ 347 348 if (GET_CODE (op) == REG) 349 return 1; 350 if (GET_CODE (op) == SUBREG) 351 return 1; 352 return (GET_CODE (op) == MEM 353 && satisfies_constraint_U (op)); 354}) 355 356;; Return nonzero if OP is a MEM suitable for bit manipulation insns. 357 358(define_predicate "bit_memory_operand" 359 (match_code "mem") 360{ 361 return (GET_CODE (op) == MEM 362 && satisfies_constraint_U (op)); 363}) 364 365;; Return nonzero if OP is indirect register or constant memory 366;; suitable for bit manipulation insns. 367 368(define_predicate "bit_register_indirect_operand" 369 (match_code "mem") 370{ 371 return (GET_CODE (op) == MEM 372 && (GET_CODE (XEXP (op, 0)) == REG 373 || GET_CODE (XEXP (op, 0)) == CONST_INT)); 374}) 375 376;; Return nonzero if X is a stack pointer. 377 378(define_predicate "stack_pointer_operand" 379 (match_code "reg") 380{ 381 return op == stack_pointer_rtx; 382}) 383 384;; False if X is anything that might eliminate to the stack pointer. 385 386(define_predicate "register_no_sp_elim_operand" 387 (match_operand 0 "register_operand") 388{ 389 if (GET_CODE (op) == SUBREG) 390 op = SUBREG_REG (op); 391 return !(op == stack_pointer_rtx 392 || op == arg_pointer_rtx 393 || op == frame_pointer_rtx 394 || IN_RANGE (REGNO (op), 395 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER)); 396}) 397 398;; Return nonzero if X is a constant whose absolute value is greater 399;; than 2. 400 401(define_predicate "const_int_gt_2_operand" 402 (match_code "const_int") 403{ 404 return (GET_CODE (op) == CONST_INT 405 && abs (INTVAL (op)) > 2); 406}) 407 408;; Return nonzero if X is a constant whose absolute value is no 409;; smaller than 8. 410 411(define_predicate "const_int_ge_8_operand" 412 (match_code "const_int") 413{ 414 return (GET_CODE (op) == CONST_INT 415 && abs (INTVAL (op)) >= 8); 416}) 417 418;; Return nonzero if X is a constant expressible in QImode. 419 420(define_predicate "const_int_qi_operand" 421 (match_code "const_int") 422{ 423 return (GET_CODE (op) == CONST_INT 424 && (INTVAL (op) & 0xff) == INTVAL (op)); 425}) 426 427;; Return nonzero if X is a constant expressible in HImode. 428 429(define_predicate "const_int_hi_operand" 430 (match_code "const_int") 431{ 432 return (GET_CODE (op) == CONST_INT 433 && (INTVAL (op) & 0xffff) == INTVAL (op)); 434}) 435 436;; Return nonzero if X is a constant suitable for inc/dec. 437 438(define_predicate "incdec_operand" 439 (and (match_code "const_int") 440 (ior (match_test "satisfies_constraint_M (op)") 441 (match_test "satisfies_constraint_O (op)")))) 442 443;; Recognize valid operators for bit instructions. 444 445(define_predicate "bit_operator" 446 (match_code "xor,and,ior") 447{ 448 enum rtx_code code = GET_CODE (op); 449 450 return (code == XOR 451 || code == AND 452 || code == IOR); 453}) 454 455;; Return nonzero if OP is a shift operator. 456 457(define_predicate "nshift_operator" 458 (match_code "ashiftrt,lshiftrt,ashift") 459{ 460 switch (GET_CODE (op)) 461 { 462 case ASHIFTRT: 463 case LSHIFTRT: 464 case ASHIFT: 465 return 1; 466 467 default: 468 return 0; 469 } 470}) 471 472;; Return nonzero if X is either EQ or NE. 473 474(define_predicate "eqne_operator" 475 (match_code "eq,ne") 476{ 477 enum rtx_code code = GET_CODE (op); 478 479 return (code == EQ || code == NE); 480}) 481 482;; Return nonzero if X is either GT or LE. 483 484(define_predicate "gtle_operator" 485 (match_code "gt,le,gtu,leu") 486{ 487 enum rtx_code code = GET_CODE (op); 488 489 return (code == GT || code == LE); 490}) 491 492;; Return nonzero if X is either GTU or LEU. 493 494(define_predicate "gtuleu_operator" 495 (match_code "gtu,leu") 496{ 497 enum rtx_code code = GET_CODE (op); 498 499 return (code == GTU || code == LEU); 500}) 501 502;; Return nonzero if X is either IOR or XOR. 503 504(define_predicate "iorxor_operator" 505 (match_code "ior,xor") 506{ 507 enum rtx_code code = GET_CODE (op); 508 509 return (code == IOR || code == XOR); 510}) 511