1;; ARM Cortex-M7 pipeline description 2;; Copyright (C) 2014-2020 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify it 7;; under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, but 12;; WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14;; General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20(define_automaton "cortex_m7") 21 22;; We model the dual-issue constraints of this core with 23;; following units. 24 25(define_cpu_unit "cm7_i0, cm7_i1" "cortex_m7") 26(define_cpu_unit "cm7_a0, cm7_a1" "cortex_m7") 27(define_cpu_unit "cm7_branch,cm7_wb,cm7_ext,cm7_shf" "cortex_m7") 28(define_cpu_unit "cm7_lsu" "cortex_m7") 29(define_cpu_unit "cm7_mac" "cortex_m7") 30(define_cpu_unit "cm7_fpu" "cortex_m7") 31 32(define_reservation "cm7_all_units" 33 "cm7_i0+cm7_i1+cm7_a0+cm7_a1+cm7_branch\ 34 +cm7_wb+cm7_ext+cm7_shf+cm7_lsu+cm7_mac\ 35 +cm7_fpu") 36 37;; Simple alu instruction without inline shift operation. 38(define_insn_reservation "cortex_m7_alu_simple" 2 39 (and (eq_attr "tune" "cortexm7") 40 (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ 41 alu_sreg,alus_sreg,logic_reg,logics_reg,\ 42 adc_imm,adcs_imm,adc_reg,adcs_reg,\ 43 adr,bfm,rev,\ 44 shift_imm,shift_reg,\ 45 mov_imm,mov_reg,mvn_imm,mvn_reg,\ 46 mov_shift_reg,mov_shift,\ 47 mvn_shift,mvn_shift_reg,\ 48 logic_shift_imm,logics_shift_imm,\ 49 alu_shift_reg,alus_shift_reg,\ 50 logic_shift_reg,logics_shift_reg,\ 51 mrs,clz,f_mcr,f_mrc,multiple")) 52 "cm7_i0|cm7_i1,cm7_a0|cm7_a1") 53 54;; Simple alu with inline shift operation. 55(define_insn_reservation "cortex_m7_alu_shift" 2 56 (and (eq_attr "tune" "cortexm7") 57 (eq_attr "type" "alu_shift_imm,alus_shift_imm")) 58 "cm7_i0|cm7_i1,(cm7_a0|cm7_a1)+cm7_shf+cm7_branch") 59 60;; Only one ALU can be used for DSP instructions. 61(define_insn_reservation "cortex_m7_dsp" 2 62 (and (eq_attr "tune" "cortexm7") 63 (eq_attr "type" "alu_dsp_reg,smlaxy,smlalxy,smulxy")) 64 "cm7_i0|cm7_i1,cm7_a0") 65 66;; The multiply instructions. 67(define_insn_reservation "cortex_m7_multiply" 2 68 (and (eq_attr "tune" "cortexm7") 69 (eq_attr "type" "mul,muls,umull,smull")) 70 "cm7_i0|cm7_i1,(cm7_a0|cm7_a1)+cm7_wb") 71 72(define_insn_reservation "cortex_m7_idiv" 4 73 (and (eq_attr "tune" "cortexm7") 74 (eq_attr "type" "sdiv,udiv")) 75 "cm7_all_units*4") 76 77(define_insn_reservation "cortex_m7_alu_extend" 2 78 (and (eq_attr "tune" "cortexm7") 79 (eq_attr "type" "extend")) 80 "cm7_i0|cm7_i1,(cm7_a0|cm7_a1)+cm7_ext+cm7_branch") 81 82(define_insn_reservation "cortex_m7_mac" 2 83 (and (eq_attr "tune" "cortexm7") 84 (eq_attr "type" "mla,mlas")) 85 "cm7_i0|cm7_i1,cm7_mac+cm7_wb") 86 87;; The branch instructions. 88(define_insn_reservation "cortex_m7_branch" 0 89 (and (eq_attr "tune" "cortexm7") 90 (eq_attr "type" "branch,call")) 91 "cm7_i0|cm7_i1,cm7_branch") 92 93;; The load instructions. 94(define_insn_reservation "cortex_m7_load1" 2 95 (and (eq_attr "tune" "cortexm7") 96 (eq_attr "type" "load_byte, load_4")) 97 "cm7_i0|cm7_i1,cm7_lsu") 98 99(define_insn_reservation "cortex_m7_load2" 2 100 (and (eq_attr "tune" "cortexm7") 101 (eq_attr "type" "load_8")) 102 "cm7_all_units") 103 104(define_insn_reservation "cortex_m7_loadm" 2 105 (and (eq_attr "tune" "cortexm7") 106 (eq_attr "type" "load_12,load_16")) 107 "cm7_all_units*2") 108 109;; The store instructions. 110(define_insn_reservation "cortex_m7_store1" 0 111 (and (eq_attr "tune" "cortexm7") 112 (eq_attr "type" "store_4")) 113 "cm7_i0|cm7_i1,cm7_lsu+cm7_wb") 114 115(define_insn_reservation "cortex_m7_store2" 0 116 (and (eq_attr "tune" "cortexm7") 117 (eq_attr "type" "store_8")) 118 "cm7_all_units") 119 120(define_insn_reservation "cortex_m7_storem" 0 121 (and (eq_attr "tune" "cortexm7") 122 (eq_attr "type" "store_12,store_16")) 123 "cm7_all_units*2") 124 125;; The FPU instructions. 126(define_insn_reservation "cortex_m7_fpalu" 3 127 (and (eq_attr "tune" "cortexm7") 128 (eq_attr "type" "ffariths,ffarithd,fadds,faddd,fmov,fconsts,\ 129 fconstd,fcmpd,f_cvt,f_cvtf2i,f_cvti2f, fcmps,\ 130 fmuls,f_flag")) 131 "cm7_i0|cm7_i1,cm7_fpu") 132 133(define_insn_reservation "cortex_m7_fmacs" 6 134 (and (eq_attr "tune" "cortexm7") 135 (eq_attr "type" "fmacs,ffmas")) 136 "cm7_i0|cm7_i1,cm7_fpu") 137 138(define_insn_reservation "cortex_m7_fdivs" 16 139 (and (eq_attr "tune" "cortexm7") 140 (eq_attr "type" "fdivs, fsqrts")) 141 "cm7_i0|cm7_i1, cm7_fpu*5") 142 143(define_insn_reservation "cortex_m7_f_loads" 2 144 (and (eq_attr "tune" "cortexm7") 145 (eq_attr "type" "f_loads")) 146 "cm7_i0|cm7_i1, cm7_lsu") 147 148(define_insn_reservation "cortex_m7_f_stores" 0 149 (and (eq_attr "tune" "cortexm7") 150 (eq_attr "type" "f_stores")) 151 "cm7_i0|cm7_i1, cm7_lsu+cm7_wb") 152 153(define_insn_reservation "cortex_m7_fmuld" 6 154 (and (eq_attr "tune" "cortexm7") 155 (eq_attr "type" "fmuld")) 156 "cm7_i0|cm7_i1,cm7_fpu*3") 157 158(define_insn_reservation "cortex_m7_fmacd" 10 159 (and (eq_attr "tune" "cortexm7") 160 (eq_attr "type" "fmacd,ffmad")) 161 "cm7_i0|cm7_i1,cm7_fpu*4") 162 163(define_insn_reservation "cortex_m7_fdivd" 31 164 (and (eq_attr "tune" "cortexm7") 165 (eq_attr "type" "fdivd,fsqrtd")) 166 "cm7_i0|cm7_i1,cm7_fpu*4") 167 168(define_insn_reservation "cortex_m7_f_loadd" 3 169 (and (eq_attr "tune" "cortexm7") 170 (eq_attr "type" "f_loadd")) 171 "cm7_all_units") 172 173(define_insn_reservation "cortex_m7_f_stored" 0 174 (and (eq_attr "tune" "cortexm7") 175 (eq_attr "type" "f_stored")) 176 "cm7_all_units") 177 178(define_insn_reservation "cortex_m7_f_mcr" 1 179 (and (eq_attr "tune" "cortexm7") 180 (eq_attr "type" "f_mcrr,f_mrrc")) 181 "cm7_all_units") 182