1;; DFA scheduling description of the Synopsys DesignWare ARC HS4x cpu 2;; for GNU C compiler 3;; Copyright (C) 2017-2020 Free Software Foundation, Inc. 4 5;; This file is part of GCC. 6 7;; GCC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11 12;; GCC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_automaton "ARCHS4x") 22 23(define_cpu_unit "hs4x_issue0" "ARCHS4x") 24(define_cpu_unit "hs4x_issue1" "ARCHS4x") 25(define_cpu_unit "hs4x_ld_st" "ARCHS4x") 26(define_cpu_unit "hs4x_divrem" "ARCHS4x") 27(define_cpu_unit "hs4x_mult" "ARCHS4x") 28(define_cpu_unit "hs4x_x1, hs4x_x2" "ARCHS4x") 29(define_cpu_unit "hs4x_y1, hs4x_y2" "ARCHS4x") 30 31(define_insn_reservation "hs4x_brj_op" 1 32 (and (match_test "TARGET_HS") 33 (eq_attr "tune" "archs4x, archs4xd") 34 (eq_attr "type" "call, call_no_delay_slot, uncond_branch, jump, \ 35branch, brcc,brcc_no_delay_slot, sfunc")) 36 "hs4x_issue0") 37 38(define_insn_reservation "hs4x_data_load_op" 4 39 (and (match_test "TARGET_HS") 40 (eq_attr "tune" "archs4x, archs4xd") 41 (eq_attr "type" "load")) 42 "hs4x_issue1 + hs4x_ld_st,hs4x_ld_st") 43 44(define_insn_reservation "hs4x_data_store_op" 1 45 (and (match_test "TARGET_HS") 46 (eq_attr "tune" "archs4x, archs4xd") 47 (eq_attr "type" "store")) 48 "hs4x_issue1 + hs4x_ld_st") 49 50;; Advanced ALU 51(define_insn_reservation "hs4x_adv_alue_op" 4 52 (and (match_test "TARGET_HS") 53 (eq_attr "tune" "archs4x, archs4xd") 54 (eq_attr "type" "cc_arith, two_cycle_core, shift, lr, sr")) 55 "(hs4x_issue0 | hs4x_issue1), hs4x_x1") 56 57(define_insn_reservation "hs4x_adv_alul_op" 6 58 (and (match_test "TARGET_HS") 59 (eq_attr "tune" "archs4xd") 60 (eq_attr "type" "cc_arith, two_cycle_core, shift, lr, sr")) 61 "(hs4x_issue0 | hs4x_issue1), nothing*2, hs4x_x2") 62 63;; Basic ALU 64(define_insn_reservation "hs4x_basic_alue_op" 1 65 (and (match_test "TARGET_HS") 66 (eq_attr "tune" "archs4x, archs4xd") 67 (eq_attr "type" "move, cmove, unary, binary, compare, misc")) 68 "(hs4x_issue0 | hs4x_issue1) + hs4x_y1") 69 70(define_insn_reservation "hs4x_basic_alul_op" 4 71 (and (match_test "TARGET_HS") 72 (eq_attr "tune" "archs4x, archs4xd") 73 (eq_attr "type" "move, cmove, unary, binary, compare, misc")) 74 "(hs4x_issue0 | hs4x_issue1), nothing*2, hs4x_y2") 75 76(define_insn_reservation "hs4x_divrem_op" 13 77 (and (match_test "TARGET_HS") 78 (eq_attr "tune" "archs4x, archs4xd") 79 (eq_attr "type" "div_rem")) 80 "hs4x_issue0 + hs4x_divrem, (hs4x_divrem)*12") 81 82;;Consider the DSPMPY fast here 83(define_insn_reservation "hs4x_mul_fast_op" 7 84 (and (match_test "TARGET_HS") 85 (eq_attr "tune_dspmpy" "fast") 86 (eq_attr "type" "mul16_em, multi, umulti")) 87 "hs4x_issue0 + hs4x_mult") 88 89(define_insn_reservation "hs4x_mul_slow_op" 8 90 (and (match_test "TARGET_HS") 91 (eq_attr "tune_dspmpy" "slow") 92 (eq_attr "type" "mul16_em, multi, umulti")) 93 "hs4x_issue0 + hs4x_mult") 94 95;; FPU unit 96(define_insn_reservation "hs4x_fpu_op" 8 97 (and (match_test "TARGET_HS") 98 (eq_attr "tune" "archs4x, archs4xd") 99 (eq_attr "type" "fpu")) 100 "hs4x_issue0") 101 102;; FPU FUSE unit 103(define_insn_reservation "hs4x_fpu_fuse_op" 12 104 (and (match_test "TARGET_HS") 105 (eq_attr "tune" "archs4x, archs4xd") 106 (eq_attr "type" "fpu_fuse")) 107 "hs4x_issue0") 108 109;; FPU SP SQRT/DIV unit 110(define_insn_reservation "hs4x_fpu_sdiv_op" 20 111 (and (match_test "TARGET_HS") 112 (eq_attr "tune" "archs4x, archs4xd") 113 (eq_attr "type" "fpu_sdiv")) 114 "hs4x_issue0") 115 116;; FPU DP SQRT/DIV unit 117(define_insn_reservation "hs4x_fpu_ddiv_op" 34 118 (and (match_test "TARGET_HS") 119 (eq_attr "tune" "archs4x, archs4xd") 120 (eq_attr "type" "fpu_ddiv")) 121 "hs4x_issue0") 122 123;; FPU CVT unit 124(define_insn_reservation "hs4x_fpu_cvt_op" 5 125 (and (match_test "TARGET_HS") 126 (eq_attr "tune" "archs4x, archs4xd") 127 (eq_attr "type" "fpu_cvt")) 128 "hs4x_issue0") 129 130;; BYPASS Advanced ALU -> 131(define_bypass 1 "hs4x_adv_alue_op" "hs4x_divrem_op") 132(define_bypass 1 "hs4x_adv_alue_op" "hs4x_mul_*op") 133(define_bypass 2 "hs4x_adv_alue_op" "hs4x_adv_alue_op") 134(define_bypass 1 "hs4x_adv_alue_op" "hs4x_basic_alue_op") 135(define_bypass 1 "hs4x_adv_alue_op" "hs4x_basic_alul_op") 136(define_bypass 1 "hs4x_adv_alue_op" "hs4x_data_load_op") 137(define_bypass 0 "hs4x_adv_alue_op" "hs4x_data_store_op" "store_data_bypass_p") 138(define_bypass 2 "hs4x_adv_alue_op" "hs4x_data_store_op") 139(define_bypass 1 "hs4x_adv_alue_op" "hs4x_fpu_*op") 140 141(define_bypass 2 "hs4x_adv_alul_op" "hs4x_basic_alul_op") 142(define_bypass 2 "hs4x_adv_alul_op" "hs4x_adv_alul_op") 143(define_bypass 2 "hs4x_adv_alul_op" "hs4x_mul_*op") 144(define_bypass 0 "hs4x_adv_alul_op" "hs4x_data_store_op" "store_data_bypass_p") 145(define_bypass 4 "hs4x_adv_alul_op" "hs4x_divrem_op") 146(define_bypass 5 "hs4x_adv_alul_op" "hs4x_fpu_*op") 147 148;; BYPASS Basic ALU -> 149(define_bypass 0 "hs4x_basic_alue_op" "hs4x_data_store_op" "store_data_bypass_p") 150 151(define_bypass 1 "hs4x_basic_alul_op" "hs4x_basic_alul_op") 152(define_bypass 1 "hs4x_basic_alul_op" "hs4x_adv_alul_op") 153(define_bypass 0 "hs4x_basic_alul_op" "hs4x_data_store_op" "store_data_bypass_p") 154(define_bypass 1 "hs4x_basic_alul_op" "hs4x_mul_*op") 155(define_bypass 3 "hs4x_basic_alul_op" "hs4x_divrem_op") 156(define_bypass 3 "hs4x_basic_alul_op" "hs4x_fpu_*op") 157 158;; BYPASS LD -> 159(define_bypass 1 "hs4x_data_load_op" "hs4x_basic_alul_op") 160(define_bypass 1 "hs4x_data_load_op" "hs4x_adv_alul_op") 161(define_bypass 3 "hs4x_data_load_op" "hs4x_divrem_op") 162(define_bypass 3 "hs4x_data_load_op" "hs4x_data_load_op") 163(define_bypass 3 "hs4x_data_load_op" "hs4x_mul_*op") 164(define_bypass 0 "hs4x_data_load_op" "hs4x_data_store_op" "store_data_bypass_p") 165(define_bypass 3 "hs4x_data_load_op" "hs4x_fpu_*op") 166 167;; BYPASS FAST MPY -> 168(define_bypass 4 "hs4x_mul_fast_op" "hs4x_basic_alul_op") 169(define_bypass 4 "hs4x_mul_fast_op" "hs4x_adv_alul_op") 170(define_bypass 4 "hs4x_mul_fast_op" "hs4x_mul_fast_op") 171(define_bypass 6 "hs4x_mul_fast_op" "hs4x_divrem_op") 172(define_bypass 0 "hs4x_mul_fast_op" "hs4x_data_store_op" "store_data_bypass_p") 173(define_bypass 6 "hs4x_mul_fast_op" "hs4x_fpu_*op") 174 175;; BYPASS SLOW MPY -> 176(define_bypass 5 "hs4x_mul_slow_op" "hs4x_basic_alul_op") 177(define_bypass 5 "hs4x_mul_slow_op" "hs4x_adv_alul_op") 178(define_bypass 5 "hs4x_mul_slow_op" "hs4x_mul_slow_op") 179(define_bypass 7 "hs4x_mul_slow_op" "hs4x_divrem_op") 180(define_bypass 0 "hs4x_mul_slow_op" "hs4x_data_store_op" "store_data_bypass_p") 181(define_bypass 7 "hs4x_mul_slow_op" "hs4x_fpu_*op") 182 183;;BYPASS FPU -> 184(define_bypass 5 "hs4x_fpu_op" "hs4x_basic_alul_op") 185(define_bypass 5 "hs4x_fpu_op" "hs4x_adv_alul_op") 186(define_bypass 5 "hs4x_fpu_op" "hs4x_mul_*op") 187(define_bypass 7 "hs4x_fpu_op" "hs4x_divrem_op") 188(define_bypass 5 "hs4x_fpu_op" "hs4x_fpu_*op") 189(define_bypass 0 "hs4x_fpu_op" "hs4x_data_store_op" "store_data_bypass_p") 190 191;;BYPASS FPU FUSE -> 192(define_bypass 9 "hs4x_fpu_fuse_op" "hs4x_basic_alul_op") 193(define_bypass 9 "hs4x_fpu_fuse_op" "hs4x_adv_alul_op") 194(define_bypass 9 "hs4x_fpu_fuse_op" "hs4x_mul_*op") 195(define_bypass 11 "hs4x_fpu_fuse_op" "hs4x_divrem_op") 196(define_bypass 11 "hs4x_fpu_fuse_op" "hs4x_fpu_*op") 197(define_bypass 0 "hs4x_fpu_fuse_op" "hs4x_data_store_op" "store_data_bypass_p") 198 199;;BYPASS FPU SP DIV -> 200(define_bypass 16 "hs4x_fpu_sdiv_op" "hs4x_basic_alul_op") 201(define_bypass 16 "hs4x_fpu_sdiv_op" "hs4x_adv_alul_op") 202(define_bypass 16 "hs4x_fpu_sdiv_op" "hs4x_mul_*op") 203(define_bypass 19 "hs4x_fpu_sdiv_op" "hs4x_divrem_op") 204(define_bypass 19 "hs4x_fpu_sdiv_op" "hs4x_fpu_*op") 205(define_bypass 0 "hs4x_fpu_sdiv_op" "hs4x_data_store_op" "store_data_bypass_p") 206 207;;BYPASS FPU DP DIV -> 208(define_bypass 31 "hs4x_fpu_ddiv_op" "hs4x_basic_alul_op") 209(define_bypass 31 "hs4x_fpu_ddiv_op" "hs4x_adv_alul_op") 210(define_bypass 31 "hs4x_fpu_ddiv_op" "hs4x_mul_*op") 211(define_bypass 34 "hs4x_fpu_ddiv_op" "hs4x_divrem_op") 212(define_bypass 34 "hs4x_fpu_ddiv_op" "hs4x_fpu_*op") 213(define_bypass 0 "hs4x_fpu_ddiv_op" "hs4x_data_store_op" "store_data_bypass_p") 214 215;;BYPASS FPU CVT -> 216(define_bypass 1 "hs4x_fpu_cvt_op" "hs4x_basic_alul_op") 217(define_bypass 1 "hs4x_fpu_cvt_op" "hs4x_adv_alul_op") 218(define_bypass 1 "hs4x_fpu_cvt_op" "hs4x_mul_*op") 219(define_bypass 4 "hs4x_fpu_cvt_op" "hs4x_divrem_op") 220(define_bypass 4 "hs4x_fpu_cvt_op" "hs4x_fpu_*op") 221(define_bypass 0 "hs4x_fpu_cvt_op" "hs4x_data_store_op" "store_data_bypass_p") 222