xref: /netbsd-src/external/gpl3/binutils/dist/opcodes/i386-reg.tbl (revision cb63e24e8d6aae7ddac1859a9015f48b1d8bd90e) 
1// i386 register table.
2// Copyright (C) 2007-2024 Free Software Foundation, Inc.
3//
4// This file is part of the GNU opcodes library.
5//
6// This library is free software; you can redistribute it and/or modify
7// it under the terms of the GNU General Public License as published by
8// the Free Software Foundation; either version 3, or (at your option)
9// any later version.
10//
11// It is distributed in the hope that it will be useful, but WITHOUT
12// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14// License for more details.
15//
16// You should have received a copy of the GNU General Public License
17// along with GAS; see the file COPYING.  If not, write to the Free
18// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19// 02110-1301, USA.
20
21// The code in gas backend for SCFI relies on the relative ordering
22// of 8 bit / 16 bit / 32 bit / 64 bit regs
23
24// 8 bit regs
25al, Class=Reg|Instance=Accum|Byte, 0, 0, Dw2Inval, Dw2Inval
26cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval
27dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval
28bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval
29ah, Class=Reg|Byte, 0, 4, Dw2Inval, Dw2Inval
30ch, Class=Reg|Byte, 0, 5, Dw2Inval, Dw2Inval
31dh, Class=Reg|Byte, 0, 6, Dw2Inval, Dw2Inval
32bh, Class=Reg|Byte, 0, 7, Dw2Inval, Dw2Inval
33axl, Class=Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
34cxl, Class=Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval
35dxl, Class=Reg|Byte, RegRex64, 2, Dw2Inval, Dw2Inval
36bxl, Class=Reg|Byte, RegRex64, 3, Dw2Inval, Dw2Inval
37spl, Class=Reg|Byte, RegRex64, 4, Dw2Inval, Dw2Inval
38bpl, Class=Reg|Byte, RegRex64, 5, Dw2Inval, Dw2Inval
39sil, Class=Reg|Byte, RegRex64, 6, Dw2Inval, Dw2Inval
40dil, Class=Reg|Byte, RegRex64, 7, Dw2Inval, Dw2Inval
41r8b, Class=Reg|Byte, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
42r9b, Class=Reg|Byte, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
43r10b, Class=Reg|Byte, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
44r11b, Class=Reg|Byte, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
45r12b, Class=Reg|Byte, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
46r13b, Class=Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
47r14b, Class=Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
48r15b, Class=Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
49r16b, Class=Reg|Byte, RegRex2|RegRex64, 0, Dw2Inval, Dw2Inval
50r17b, Class=Reg|Byte, RegRex2|RegRex64, 1, Dw2Inval, Dw2Inval
51r18b, Class=Reg|Byte, RegRex2|RegRex64, 2, Dw2Inval, Dw2Inval
52r19b, Class=Reg|Byte, RegRex2|RegRex64, 3, Dw2Inval, Dw2Inval
53r20b, Class=Reg|Byte, RegRex2|RegRex64, 4, Dw2Inval, Dw2Inval
54r21b, Class=Reg|Byte, RegRex2|RegRex64, 5, Dw2Inval, Dw2Inval
55r22b, Class=Reg|Byte, RegRex2|RegRex64, 6, Dw2Inval, Dw2Inval
56r23b, Class=Reg|Byte, RegRex2|RegRex64, 7, Dw2Inval, Dw2Inval
57r24b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 0, Dw2Inval, Dw2Inval
58r25b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 1, Dw2Inval, Dw2Inval
59r26b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 2, Dw2Inval, Dw2Inval
60r27b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 3, Dw2Inval, Dw2Inval
61r28b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 4, Dw2Inval, Dw2Inval
62r29b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 5, Dw2Inval, Dw2Inval
63r30b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 6, Dw2Inval, Dw2Inval
64r31b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 7, Dw2Inval, Dw2Inval
65// 16 bit regs
66ax, Class=Reg|Instance=Accum|Word, 0, 0, Dw2Inval, Dw2Inval
67cx, Class=Reg|Word, 0, 1, Dw2Inval, Dw2Inval
68dx, Class=Reg|Instance=RegD|Word, 0, 2, Dw2Inval, Dw2Inval
69bx, Class=Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
70sp, Class=Reg|Word, 0, 4, Dw2Inval, Dw2Inval
71bp, Class=Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
72si, Class=Reg|Word|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
73di, Class=Reg|Word|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
74r8w, Class=Reg|Word, RegRex, 0, Dw2Inval, Dw2Inval
75r9w, Class=Reg|Word, RegRex, 1, Dw2Inval, Dw2Inval
76r10w, Class=Reg|Word, RegRex, 2, Dw2Inval, Dw2Inval
77r11w, Class=Reg|Word, RegRex, 3, Dw2Inval, Dw2Inval
78r12w, Class=Reg|Word, RegRex, 4, Dw2Inval, Dw2Inval
79r13w, Class=Reg|Word, RegRex, 5, Dw2Inval, Dw2Inval
80r14w, Class=Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval
81r15w, Class=Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval
82r16w, Class=Reg|Word, RegRex2, 0, Dw2Inval, Dw2Inval
83r17w, Class=Reg|Word, RegRex2, 1, Dw2Inval, Dw2Inval
84r18w, Class=Reg|Word, RegRex2, 2, Dw2Inval, Dw2Inval
85r19w, Class=Reg|Word, RegRex2, 3, Dw2Inval, Dw2Inval
86r20w, Class=Reg|Word, RegRex2, 4, Dw2Inval, Dw2Inval
87r21w, Class=Reg|Word, RegRex2, 5, Dw2Inval, Dw2Inval
88r22w, Class=Reg|Word, RegRex2, 6, Dw2Inval, Dw2Inval
89r23w, Class=Reg|Word, RegRex2, 7, Dw2Inval, Dw2Inval
90r24w, Class=Reg|Word, RegRex2|RegRex, 0, Dw2Inval, Dw2Inval
91r25w, Class=Reg|Word, RegRex2|RegRex, 1, Dw2Inval, Dw2Inval
92r26w, Class=Reg|Word, RegRex2|RegRex, 2, Dw2Inval, Dw2Inval
93r27w, Class=Reg|Word, RegRex2|RegRex, 3, Dw2Inval, Dw2Inval
94r28w, Class=Reg|Word, RegRex2|RegRex, 4, Dw2Inval, Dw2Inval
95r29w, Class=Reg|Word, RegRex2|RegRex, 5, Dw2Inval, Dw2Inval
96r30w, Class=Reg|Word, RegRex2|RegRex, 6, Dw2Inval, Dw2Inval
97r31w, Class=Reg|Word, RegRex2|RegRex, 7, Dw2Inval, Dw2Inval
98// 32 bit regs
99eax, Class=Reg|Instance=Accum|Dword|BaseIndex, 0, 0, 0, Dw2Inval
100ecx, Class=Reg|Instance=RegC|Dword|BaseIndex, 0, 1, 1, Dw2Inval
101edx, Class=Reg|Instance=RegD|Dword|BaseIndex, 0, 2, 2, Dw2Inval
102ebx, Class=Reg|Instance=RegB|Dword|BaseIndex, 0, 3, 3, Dw2Inval
103esp, Class=Reg|Dword, 0, 4, 4, Dw2Inval
104ebp, Class=Reg|Dword|BaseIndex, 0, 5, 5, Dw2Inval
105esi, Class=Reg|Dword|BaseIndex, 0, 6, 6, Dw2Inval
106edi, Class=Reg|Dword|BaseIndex, 0, 7, 7, Dw2Inval
107r8d, Class=Reg|Dword|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
108r9d, Class=Reg|Dword|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
109r10d, Class=Reg|Dword|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
110r11d, Class=Reg|Dword|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
111r12d, Class=Reg|Dword|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
112r13d, Class=Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
113r14d, Class=Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
114r15d, Class=Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
115r16d, Class=Reg|Dword|BaseIndex, RegRex2, 0, Dw2Inval, Dw2Inval
116r17d, Class=Reg|Dword|BaseIndex, RegRex2, 1, Dw2Inval, Dw2Inval
117r18d, Class=Reg|Dword|BaseIndex, RegRex2, 2, Dw2Inval, Dw2Inval
118r19d, Class=Reg|Dword|BaseIndex, RegRex2, 3, Dw2Inval, Dw2Inval
119r20d, Class=Reg|Dword|BaseIndex, RegRex2, 4, Dw2Inval, Dw2Inval
120r21d, Class=Reg|Dword|BaseIndex, RegRex2, 5, Dw2Inval, Dw2Inval
121r22d, Class=Reg|Dword|BaseIndex, RegRex2, 6, Dw2Inval, Dw2Inval
122r23d, Class=Reg|Dword|BaseIndex, RegRex2, 7, Dw2Inval, Dw2Inval
123r24d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 0, Dw2Inval, Dw2Inval
124r25d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 1, Dw2Inval, Dw2Inval
125r26d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 2, Dw2Inval, Dw2Inval
126r27d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 3, Dw2Inval, Dw2Inval
127r28d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 4, Dw2Inval, Dw2Inval
128r29d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 5, Dw2Inval, Dw2Inval
129r30d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 6, Dw2Inval, Dw2Inval
130r31d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 7, Dw2Inval, Dw2Inval
131rax, Class=Reg|Instance=Accum|Qword|BaseIndex, 0, 0, Dw2Inval, 0
132rcx, Class=Reg|Instance=RegC|Qword|BaseIndex, 0, 1, Dw2Inval, 2
133rdx, Class=Reg|Instance=RegD|Qword|BaseIndex, 0, 2, Dw2Inval, 1
134rbx, Class=Reg|Instance=RegB|Qword|BaseIndex, 0, 3, Dw2Inval, 3
135rsp, Class=Reg|Qword, 0, 4, Dw2Inval, 7
136rbp, Class=Reg|Qword|BaseIndex, 0, 5, Dw2Inval, 6
137rsi, Class=Reg|Qword|BaseIndex, 0, 6, Dw2Inval, 4
138rdi, Class=Reg|Qword|BaseIndex, 0, 7, Dw2Inval, 5
139r8, Class=Reg|Qword|BaseIndex, RegRex, 0, Dw2Inval, 8
140r9, Class=Reg|Qword|BaseIndex, RegRex, 1, Dw2Inval, 9
141r10, Class=Reg|Qword|BaseIndex, RegRex, 2, Dw2Inval, 10
142r11, Class=Reg|Qword|BaseIndex, RegRex, 3, Dw2Inval, 11
143r12, Class=Reg|Qword|BaseIndex, RegRex, 4, Dw2Inval, 12
144r13, Class=Reg|Qword|BaseIndex, RegRex, 5, Dw2Inval, 13
145r14, Class=Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14
146r15, Class=Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15
147r16, Class=Reg|Qword|BaseIndex, RegRex2, 0, Dw2Inval, 130
148r17, Class=Reg|Qword|BaseIndex, RegRex2, 1, Dw2Inval, 131
149r18, Class=Reg|Qword|BaseIndex, RegRex2, 2, Dw2Inval, 132
150r19, Class=Reg|Qword|BaseIndex, RegRex2, 3, Dw2Inval, 133
151r20, Class=Reg|Qword|BaseIndex, RegRex2, 4, Dw2Inval, 134
152r21, Class=Reg|Qword|BaseIndex, RegRex2, 5, Dw2Inval, 135
153r22, Class=Reg|Qword|BaseIndex, RegRex2, 6, Dw2Inval, 136
154r23, Class=Reg|Qword|BaseIndex, RegRex2, 7, Dw2Inval, 137
155r24, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 0, Dw2Inval, 138
156r25, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 1, Dw2Inval, 139
157r26, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 2, Dw2Inval, 140
158r27, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 3, Dw2Inval, 141
159r28, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 4, Dw2Inval, 142
160r29, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 5, Dw2Inval, 143
161r30, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 6, Dw2Inval, 144
162r31, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 7, Dw2Inval, 145
163// Vector mask registers.
164k0, Class=RegMask, 0, 0, 93, 118
165k1, Class=RegMask, 0, 1, 94, 119
166k2, Class=RegMask, 0, 2, 95, 120
167k3, Class=RegMask, 0, 3, 96, 121
168k4, Class=RegMask, 0, 4, 97, 122
169k5, Class=RegMask, 0, 5, 98, 123
170k6, Class=RegMask, 0, 6, 99, 124
171k7, Class=RegMask, 0, 7, 100, 125
172// Segment registers.
173es, Class=SReg, 0, 0, 40, 50
174cs, Class=SReg, 0, 1, 41, 51
175ss, Class=SReg, 0, 2, 42, 52
176ds, Class=SReg, 0, 3, 43, 53
177fs, Class=SReg, 0, 4, 44, 54
178gs, Class=SReg, 0, 5, 45, 55
179flat, Class=SReg, 0, RegFlat, Dw2Inval, Dw2Inval
180// Control registers.
181cr0, Class=RegCR, 0, 0, Dw2Inval, Dw2Inval
182cr1, Class=RegCR, 0, 1, Dw2Inval, Dw2Inval
183cr2, Class=RegCR, 0, 2, Dw2Inval, Dw2Inval
184cr3, Class=RegCR, 0, 3, Dw2Inval, Dw2Inval
185cr4, Class=RegCR, 0, 4, Dw2Inval, Dw2Inval
186cr5, Class=RegCR, 0, 5, Dw2Inval, Dw2Inval
187cr6, Class=RegCR, 0, 6, Dw2Inval, Dw2Inval
188cr7, Class=RegCR, 0, 7, Dw2Inval, Dw2Inval
189cr8, Class=RegCR, RegRex, 0, Dw2Inval, Dw2Inval
190cr9, Class=RegCR, RegRex, 1, Dw2Inval, Dw2Inval
191cr10, Class=RegCR, RegRex, 2, Dw2Inval, Dw2Inval
192cr11, Class=RegCR, RegRex, 3, Dw2Inval, Dw2Inval
193cr12, Class=RegCR, RegRex, 4, Dw2Inval, Dw2Inval
194cr13, Class=RegCR, RegRex, 5, Dw2Inval, Dw2Inval
195cr14, Class=RegCR, RegRex, 6, Dw2Inval, Dw2Inval
196cr15, Class=RegCR, RegRex, 7, Dw2Inval, Dw2Inval
197// Debug registers.
198db0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
199db1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
200db2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
201db3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
202db4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
203db5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
204db6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
205db7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
206db8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
207db9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
208db10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
209db11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
210db12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
211db13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
212db14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
213db15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
214dr0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
215dr1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
216dr2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
217dr3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
218dr4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
219dr5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
220dr6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
221dr7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
222dr8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
223dr9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
224dr10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
225dr11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
226dr12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
227dr13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
228dr14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
229dr15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
230// Test registers.
231tr0, Class=RegTR, 0, 0, Dw2Inval, Dw2Inval
232tr1, Class=RegTR, 0, 1, Dw2Inval, Dw2Inval
233tr2, Class=RegTR, 0, 2, Dw2Inval, Dw2Inval
234tr3, Class=RegTR, 0, 3, Dw2Inval, Dw2Inval
235tr4, Class=RegTR, 0, 4, Dw2Inval, Dw2Inval
236tr5, Class=RegTR, 0, 5, Dw2Inval, Dw2Inval
237tr6, Class=RegTR, 0, 6, Dw2Inval, Dw2Inval
238tr7, Class=RegTR, 0, 7, Dw2Inval, Dw2Inval
239// MMX and simd registers.
240mm0, Class=RegMMX, 0, 0, 29, 41
241mm1, Class=RegMMX, 0, 1, 30, 42
242mm2, Class=RegMMX, 0, 2, 31, 43
243mm3, Class=RegMMX, 0, 3, 32, 44
244mm4, Class=RegMMX, 0, 4, 33, 45
245mm5, Class=RegMMX, 0, 5, 34, 46
246mm6, Class=RegMMX, 0, 6, 35, 47
247mm7, Class=RegMMX, 0, 7, 36, 48
248xmm0, Class=RegSIMD|Instance=Accum|Xmmword, 0, 0, 21, 17
249xmm1, Class=RegSIMD|Xmmword, 0, 1, 22, 18
250xmm2, Class=RegSIMD|Xmmword, 0, 2, 23, 19
251xmm3, Class=RegSIMD|Xmmword, 0, 3, 24, 20
252xmm4, Class=RegSIMD|Xmmword, 0, 4, 25, 21
253xmm5, Class=RegSIMD|Xmmword, 0, 5, 26, 22
254xmm6, Class=RegSIMD|Xmmword, 0, 6, 27, 23
255xmm7, Class=RegSIMD|Xmmword, 0, 7, 28, 24
256xmm8, Class=RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25
257xmm9, Class=RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26
258xmm10, Class=RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27
259xmm11, Class=RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28
260xmm12, Class=RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29
261xmm13, Class=RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30
262xmm14, Class=RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31
263xmm15, Class=RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32
264xmm16, Class=RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67
265xmm17, Class=RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68
266xmm18, Class=RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69
267xmm19, Class=RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70
268xmm20, Class=RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71
269xmm21, Class=RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72
270xmm22, Class=RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73
271xmm23, Class=RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74
272xmm24, Class=RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75
273xmm25, Class=RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76
274xmm26, Class=RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77
275xmm27, Class=RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78
276xmm28, Class=RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79
277xmm29, Class=RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80
278xmm30, Class=RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81
279xmm31, Class=RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82
280// AVX registers.
281ymm0, Class=RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval
282ymm1, Class=RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval
283ymm2, Class=RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval
284ymm3, Class=RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval
285ymm4, Class=RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval
286ymm5, Class=RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval
287ymm6, Class=RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval
288ymm7, Class=RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval
289ymm8, Class=RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval
290ymm9, Class=RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval
291ymm10, Class=RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval
292ymm11, Class=RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval
293ymm12, Class=RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval
294ymm13, Class=RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval
295ymm14, Class=RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval
296ymm15, Class=RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval
297ymm16, Class=RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval
298ymm17, Class=RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval
299ymm18, Class=RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval
300ymm19, Class=RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval
301ymm20, Class=RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval
302ymm21, Class=RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval
303ymm22, Class=RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval
304ymm23, Class=RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval
305ymm24, Class=RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
306ymm25, Class=RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
307ymm26, Class=RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
308ymm27, Class=RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
309ymm28, Class=RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
310ymm29, Class=RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
311ymm30, Class=RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
312ymm31, Class=RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
313// AVX512 registers.
314zmm0, Class=RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval
315zmm1, Class=RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval
316zmm2, Class=RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval
317zmm3, Class=RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval
318zmm4, Class=RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval
319zmm5, Class=RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval
320zmm6, Class=RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval
321zmm7, Class=RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval
322zmm8, Class=RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval
323zmm9, Class=RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval
324zmm10, Class=RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval
325zmm11, Class=RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval
326zmm12, Class=RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval
327zmm13, Class=RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval
328zmm14, Class=RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval
329zmm15, Class=RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval
330zmm16, Class=RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval
331zmm17, Class=RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval
332zmm18, Class=RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval
333zmm19, Class=RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval
334zmm20, Class=RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval
335zmm21, Class=RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval
336zmm22, Class=RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval
337zmm23, Class=RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval
338zmm24, Class=RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
339zmm25, Class=RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
340zmm26, Class=RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
341zmm27, Class=RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
342zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
343zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
344zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
345zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
346// TMM registers for AMX
347tmm0, Class=RegSIMD|Tmmword, 0, 0, Dw2Inval, Dw2Inval
348tmm1, Class=RegSIMD|Tmmword, 0, 1, Dw2Inval, Dw2Inval
349tmm2, Class=RegSIMD|Tmmword, 0, 2, Dw2Inval, Dw2Inval
350tmm3, Class=RegSIMD|Tmmword, 0, 3, Dw2Inval, Dw2Inval
351tmm4, Class=RegSIMD|Tmmword, 0, 4, Dw2Inval, Dw2Inval
352tmm5, Class=RegSIMD|Tmmword, 0, 5, Dw2Inval, Dw2Inval
353tmm6, Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval
354tmm7, Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval
355// Bound registers for MPX
356bnd0, Class=RegBND, 0, 0, Dw2Inval, Dw2Inval
357bnd1, Class=RegBND, 0, 1, Dw2Inval, Dw2Inval
358bnd2, Class=RegBND, 0, 2, Dw2Inval, Dw2Inval
359bnd3, Class=RegBND, 0, 3, Dw2Inval, Dw2Inval
360// No Class=Reg will make these registers rejected for all purposes except
361// for addressing.  This saves creating one extra type for RIP/EIP.
362rip, Qword, RegRex64, RegIP, Dw2Inval, 16
363eip, Dword, RegRex64, RegIP, 8, Dw2Inval
364// No Class=Reg will make these registers rejected for all purposes except
365// for addressing.
366riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
367eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
368// fp regs. No need for an explicit st(0) here.
369st, Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33
370st(1), Class=Reg|Tbyte, 0, 1, 12, 34
371st(2), Class=Reg|Tbyte, 0, 2, 13, 35
372st(3), Class=Reg|Tbyte, 0, 3, 14, 36
373st(4), Class=Reg|Tbyte, 0, 4, 15, 37
374st(5), Class=Reg|Tbyte, 0, 5, 16, 38
375st(6), Class=Reg|Tbyte, 0, 6, 17, 39
376st(7), Class=Reg|Tbyte, 0, 7, 18, 40
377// Pseudo-register names only used in .cfi_* directives
378eflags, 0, 0, 0, 9, 49
379rflags, 0, 0, 0, Dw2Inval, 49
380fs.base, 0, 0, 0, Dw2Inval, 58
381gs.base, 0, 0, 0, Dw2Inval, 59
382tr, 0, 0, 0, 48, 62
383ldtr, 0, 0, 0, 49, 63
384// st0...7 for backward compatibility
385st0, 0, 0, 0, 11, 33
386st1, 0, 0, 1, 12, 34
387st2, 0, 0, 2, 13, 35
388st3, 0, 0, 3, 14, 36
389st4, 0, 0, 4, 15, 37
390st5, 0, 0, 5, 16, 38
391st6, 0, 0, 6, 17, 39
392st7, 0, 0, 7, 18, 40
393fcw, 0, 0, 0, 37, 65
394fsw, 0, 0, 0, 38, 66
395mxcsr, 0, 0, 0, 39, 64
396