1@c Copyright (C) 2009-2024 Free Software Foundation, Inc. 2@c Contributed by ARM Ltd. 3@c This is part of the GAS manual. 4@c For copying conditions, see the file as.texinfo. 5@c man end 6 7@ifset GENERIC 8@page 9@node AArch64-Dependent 10@chapter AArch64 Dependent Features 11@end ifset 12 13@ifclear GENERIC 14@node Machine Dependencies 15@chapter AArch64 Dependent Features 16@end ifclear 17 18@cindex AArch64 support 19@menu 20* AArch64 Options:: Options 21* AArch64 Extensions:: Extensions 22* AArch64 Syntax:: Syntax 23* AArch64 Floating Point:: Floating Point 24* AArch64 Directives:: AArch64 Machine Directives 25* AArch64 Opcodes:: Opcodes 26* AArch64 Mapping Symbols:: Mapping Symbols 27@end menu 28 29@node AArch64 Options 30@section Options 31@cindex AArch64 options (none) 32@cindex options for AArch64 (none) 33 34@c man begin OPTIONS 35@table @gcctabopt 36 37@cindex @option{-EB} command-line option, AArch64 38@item -EB 39This option specifies that the output generated by the assembler should 40be marked as being encoded for a big-endian processor. 41 42@cindex @option{-EL} command-line option, AArch64 43@item -EL 44This option specifies that the output generated by the assembler should 45be marked as being encoded for a little-endian processor. 46 47@cindex @option{-mabi=} command-line option, AArch64 48@item -mabi=@var{abi} 49Specify which ABI the source code uses. The recognized arguments 50are: @code{ilp32} and @code{lp64}, which decides the generated object 51file in ELF32 and ELF64 format respectively. The default is @code{lp64}. 52 53@cindex @option{-mcpu=} command-line option, AArch64 54@item -mcpu=@var{processor}[+@var{extension}@dots{}] 55This option specifies the target processor. The assembler will issue an error 56message if an attempt is made to assemble an instruction which will not execute 57on the target processor. The following processor names are recognized: 58@code{cortex-a34}, 59@code{cortex-a35}, 60@code{cortex-a53}, 61@code{cortex-a55}, 62@code{cortex-a57}, 63@code{cortex-a65}, 64@code{cortex-a65ae}, 65@code{cortex-a72}, 66@code{cortex-a73}, 67@code{cortex-a75}, 68@code{cortex-a76}, 69@code{cortex-a76ae}, 70@code{cortex-a77}, 71@code{cortex-a78}, 72@code{cortex-a78ae}, 73@code{cortex-a78c}, 74@code{cortex-a510}, 75@code{cortex-a520}, 76@code{cortex-a710}, 77@code{cortex-a720}, 78@code{ares}, 79@code{exynos-m1}, 80@code{falkor}, 81@code{neoverse-n1}, 82@code{neoverse-n2}, 83@code{neoverse-e1}, 84@code{neoverse-v1}, 85@code{qdf24xx}, 86@code{saphira}, 87@code{thunderx}, 88@code{vulcan}, 89@code{xgene1} 90@code{xgene2}, 91@code{cortex-r82}, 92@code{cortex-x1}, 93@code{cortex-x2}, 94@code{cortex-x3}, 95and 96@code{cortex-x4}. 97The special name @code{all} may be used to allow the assembler to accept 98instructions valid for any supported processor, including all optional 99extensions. 100 101In addition to the basic instruction set, the assembler can be told to 102accept, or restrict, various extension mnemonics that extend the 103processor. @xref{AArch64 Extensions}. 104 105If some implementations of a particular processor can have an 106extension, then then those extensions are automatically enabled. 107Consequently, you will not normally have to specify any additional 108extensions. 109 110@cindex @option{-march=} command-line option, AArch64 111@item -march=@var{architecture}[+@var{extension}@dots{}] 112This option specifies the target architecture. The assembler will 113issue an error message if an attempt is made to assemble an 114instruction which will not execute on the target architecture. The 115following architecture names are recognized: @code{armv8-a}, 116@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a} 117@code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, @code{armv8.8-a}, 118@code{armv8.9-a}, @code{armv8-r}, @code{armv9-a}, @code{armv9.1-a}, 119@code{armv9.2-a}, @code{armv9.3-a} and @code{armv9.4-a}. 120 121If both @option{-mcpu} and @option{-march} are specified, the 122assembler will use the setting for @option{-mcpu}. If neither are 123specified, the assembler will default to @option{-mcpu=all}. 124 125The architecture option can be extended with the same instruction set 126extension options as the @option{-mcpu} option. Unlike 127@option{-mcpu}, extensions are not always enabled by default. 128@xref{AArch64 Extensions}. 129 130@cindex @code{-mverbose-error} command-line option, AArch64 131@item -mverbose-error 132This option enables verbose error messages for AArch64 gas. This option 133is enabled by default. 134 135@cindex @code{-mno-verbose-error} command-line option, AArch64 136@item -mno-verbose-error 137This option disables verbose error messages in AArch64 gas. 138 139@end table 140@c man end 141 142@node AArch64 Extensions 143@section Architecture Extensions 144 145The tables below lists the permitted architecture extensions and architecture 146versions that are supported by the assembler, including a brief description and 147a list of other extensions that they depend upon. 148 149Multiple extensions may be specified, separated by a @code{+}. 150Extension mnemonics may also be removed from those the assembler 151accepts. This is done by prepending @code{no} to the option that adds 152the extension. Extensions that are removed must be listed after all 153extensions that have been added. 154 155Enabling an extension that depends upon other extensions (either directly or 156recursively) will automatically cause those extensions to be enabled. 157Similarly, disabling an extension that is required by other extensions will 158automatically cause those extensions to be disabled. 159 160@multitable @columnfractions .16 .22 .62 161@headitem Extension @tab Depends upon @tab Description 162@item @code{aes} @tab @code{simd} 163 @tab Enable the AES and PMULL cryptographic extensions. 164@item @code{b16b16} @tab @code{sve2} 165 @tab Enable BFloat16 to BFloat16 arithmetic for SVE2 and SME2. 166@item @code{bf16} @tab @code{fp} 167 @tab Enable BFloat16 extension. 168@item @code{chk} @tab 169 @tab Enable the Check Feature Status Extension. 170@item @code{compnum} @tab @code{simd} 171 @tab Enable the complex number SIMD extensions. An alias of @code{fcma}. 172@item @code{crc} @tab 173 @tab Enable CRC instructions. 174@item @code{crypto} @tab @code{simd} 175 @tab Enable cryptographic extensions. This is equivalent to @code{aes+sha2}. 176@item @code{cssc} @tab 177 @tab Enable the Armv8.9-A Common Short Sequence Compression instructions. 178@item @code{d128} @tab @code{lse128} 179 @tab Enable the 128-bit Page Descriptor Extension. This implies @code{lse128}. 180@item @code{dotprod} @tab @code{simd} 181 @tab Enable the Dot Product extension. 182@item @code{f32mm} @tab @code{sve} 183 @tab Enable the F32 Matrix Multiply extension 184@item @code{f64mm} @tab @code{sve} 185 @tab Enable the F64 Matrix Multiply extension. 186@item @code{fcma} @tab @code{fp16}, @code{simd} 187 @tab Enable the complex number SIMD extensions. 188@item @code{flagm} @tab 189 @tab Enable Flag Manipulation instructions. 190@item @code{flagm2} @tab @code{flagm} 191 @tab Enable FlagM2 flag conversion instructions. 192@item @code{fp16fml} @tab @code{fp16} 193 @tab Enable Armv8.2 16-bit floating-point multiplication variant support. 194@item @code{fp16} @tab @code{fp} 195 @tab Enable Armv8.2 16-bit floating-point support. 196@item @code{fp} @tab 197 @tab Enable floating-point extensions. 198@item @code{frintts} @tab @code{simd} 199 @tab Enable floating-point round to integral value instructions. 200@item @code{gcs} @tab 201 @tab Enable the Guarded Control Stack Extension. 202@item @code{hbc} @tab 203 @tab Enable Armv8.8-A hinted conditional branch instructions 204@item @code{i8mm} @tab @code{simd} 205 @tab Enable the Int8 Matrix Multiply extension. 206@item @code{ite} @tab 207 @tab Enable the TRCIT instruction. 208@item @code{jscvt} @tab @code{fp} 209 @tab Enable the @code{fjcvtzs} JavaScript conversion instruction. 210@item @code{lor} @tab 211 @tab Enable Limited Ordering Regions extensions. 212@item @code{ls64} @tab 213 @tab Enable the 64 Byte Loads/Stores extensions. 214@item @code{lse} @tab 215 @tab Enable Large System extensions. 216@item @code{lse128} @tab @code{lse} 217 @tab Enable the 128-bit Atomic Instructions extension. 218@item @code{memtag} @tab 219 @tab Enable Armv8.5-A Memory Tagging Extensions. 220@item @code{mops} @tab 221 @tab Enable Armv8.8-A memcpy and memset acceleration instructions 222@item @code{pan} @tab 223 @tab Enable Privileged Access Never support. 224@item @code{pauth} @tab 225 @tab Enable Pointer Authentication. 226@item @code{predres} @tab 227 @tab Enable the Execution and Data and Prediction instructions. 228@item @code{predres2} @tab @code{predres} 229 @tab Enable Prediction instructions. 230@item @code{profile} @tab 231 @tab Enable statistical profiling extensions. 232@item @code{ras} @tab 233 @tab Enable the Reliability, Availability and Serviceability extension. 234@item @code{rasv2} @tab @code{ras} 235 @tab Enable the Reliability, Availability and Serviceability extension v2. 236@item @code{rcpc} @tab 237 @tab Enable the Load-Acquire RCpc instructions extension. 238@item @code{rcpc2} @tab @code{rcpc} 239 @tab Enable the Load-Acquire RCpc instructions extension v2. 240@item @code{rcpc3} @tab @code{rcpc2} 241 @tab Enable the Load-Acquire RCpc instructions extension v3. 242@item @code{rdma} @tab @code{simd} 243 @tab Enable rounding doubling multiply accumulate instructions. 244@item @code{rdm} @tab @code{simd} 245 @tab An alias of @code{rdma}. 246@item @code{rng} @tab 247 @tab Enable Armv8.5-A random number instructions. 248@item @code{sb} @tab 249 @tab Enable the speculation barrier instruction sb. 250@item @code{sha2} @tab @code{simd} 251 @tab Enable the SHA1 and SHA256 cryptographic extensions. 252@item @code{sha3} @tab @code{sha2} 253 @tab Enable the SHA512 and SHA3 cryptographic extensions. 254@item @code{simd} @tab @code{fp} 255 @tab Enable Advanced SIMD extensions. 256@item @code{sm4} @tab @code{simd} 257 @tab Enable the SM3 and SM4 cryptographic extensions. 258@item @code{sme} @tab @code{sve2}, @code{bf16} 259 @tab Enable the Scalable Matrix Extension. 260@item @code{sme-f64f64} @tab @code{sme} 261 @tab Enable SME F64F64 Extension. 262@item @code{sme-i16i64} @tab @code{sme} 263 @tab Enable SME I16I64 Extension. 264@item @code{sme2} @tab @code{sme} 265 @tab Enable SME2. 266@item @code{sme2p1} @tab @code{sme2} 267 @tab Enable SME2.1. 268@item @code{ssbs} @tab 269 @tab Enable Speculative Store Bypassing Safe state read and write. 270@item @code{sve} @tab @code{fcma} 271 @tab Enable the Scalable Vector Extension. 272@item @code{sve2} @tab @code{sve} 273 @tab Enable SVE2. 274@item @code{sve2-aes} @tab @code{sve2}, @code{aes} 275 @tab Enable the SVE2 AES and PMULL Extensions. 276@item @code{sve2-bitperm} @tab @code{sve2} 277 @tab Enable the SVE2 BITPERM Extension. 278@item @code{sve2-sha3} @tab @code{sve2}, @code{sha3} 279 @tab Enable the SVE2 SHA3 Extension. 280@item @code{sve2-sm4} @tab @code{sve2}, @code{sm4} 281 @tab Enable the SVE2 SM4 Extension. 282@item @code{sve2p1} @tab @code{sve2} 283 @tab Enable SVE2.1. 284@item @code{the} @tab 285 @tab Enable the Translation Hardening Extension. 286@item @code{tme} @tab 287 @tab Enable the Transactional Memory Extension. 288@item @code{wfxt} @tab 289 @tab Enable @code{wfet} and @code{wfit} instructions. 290@item @code{xs} @tab 291 @tab Enable the XS memory attribute extension. 292@end multitable 293 294@multitable @columnfractions .20 .80 295@headitem Architecture Version @tab Includes 296@item @code{armv8-a} @tab @code{simd}, @code{chk}, @code{ras} 297@item @code{armv8.1-a} @tab @code{armv8-a}, @code{crc}, @code{lse}, @code{rdma}, @code{pan}, @code{lor} 298@item @code{armv8.2-a} @tab @code{armv8.1-a} 299@item @code{armv8.3-a} @tab @code{armv8.2-a}, @code{fcma}, @code{jscvt}, @code{pauth}, @code{rcpc} 300@item @code{armv8.4-a} @tab @code{armv8.3-a}, @code{fp16fml}, @code{dotprod}, @code{flagm}, @code{rcpc2} 301@item @code{armv8.5-a} @tab @code{armv8.4-a}, @code{frintts}, @code{flagm2}, @code{predres}, @code{sb}, @code{ssbs} 302@item @code{armv8.6-a} @tab @code{armv8.5-a}, @code{bf16}, @code{i8mm} 303@item @code{armv8.7-a} @tab @code{armv8.6-a}, @code{ls64}, @code{xs}, @code{wfxt} 304@item @code{armv8.8-a} @tab @code{armv8.7-a}, @code{hbc}, @code{mops} 305@item @code{armv8.9-a} @tab @code{armv8.8-a}, @code{rasv2}, @code{predres2} 306@item @code{armv9-a} @tab @code{armv8.5-a}, @code{sve2} 307@item @code{armv9.1-a} @tab @code{armv9-a}, @code{armv8.6-a} 308@item @code{armv9.2-a} @tab @code{armv9.1-a}, @code{armv8.7-a} 309@item @code{armv9.3-a} @tab @code{armv9.2-a}, @code{armv8.8-a} 310@item @code{armv9.4-a} @tab @code{armv9.3-a}, @code{armv8.9-a} 311@item @code{armv8-r} @tab @code{armv8.4-a+nolor} 312@end multitable 313 314@node AArch64 Syntax 315@section Syntax 316@menu 317* AArch64-Chars:: Special Characters 318* AArch64-Regs:: Register Names 319* AArch64-Relocations:: Relocations 320@end menu 321 322@node AArch64-Chars 323@subsection Special Characters 324 325@cindex line comment character, AArch64 326@cindex AArch64 line comment character 327The presence of a @samp{//} on a line indicates the start of a comment 328that extends to the end of the current line. If a @samp{#} appears as 329the first character of a line, the whole line is treated as a comment. 330 331@cindex line separator, AArch64 332@cindex statement separator, AArch64 333@cindex AArch64 line separator 334The @samp{;} character can be used instead of a newline to separate 335statements. 336 337@cindex immediate character, AArch64 338@cindex AArch64 immediate character 339The @samp{#} can be optionally used to indicate immediate operands. 340 341@node AArch64-Regs 342@subsection Register Names 343 344@cindex AArch64 register names 345@cindex register names, AArch64 346Please refer to the section @samp{4.4 Register Names} of 347@samp{ARMv8 Instruction Set Overview}, which is available at 348@uref{http://infocenter.arm.com}. 349 350@node AArch64-Relocations 351@subsection Relocations 352 353@cindex relocations, AArch64 354@cindex AArch64 relocations 355@cindex MOVN, MOVZ and MOVK group relocations, AArch64 356Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated 357by prefixing the label with @samp{#:abs_g2:} etc. 358For example to load the 48-bit absolute address of @var{foo} into x0: 359 360@smallexample 361 movz x0, #:abs_g2:foo // bits 32-47, overflow check 362 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check 363 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check 364@end smallexample 365 366@cindex ADRP, ADD, LDR/STR group relocations, AArch64 367Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR} 368instructions can be generated by prefixing the label with 369@samp{:pg_hi21:} and @samp{#:lo12:} respectively. 370 371For example to use 33-bit (+/-4GB) pc-relative addressing to 372load the address of @var{foo} into x0: 373 374@smallexample 375 adrp x0, :pg_hi21:foo 376 add x0, x0, #:lo12:foo 377@end smallexample 378 379Or to load the value of @var{foo} into x0: 380 381@smallexample 382 adrp x0, :pg_hi21:foo 383 ldr x0, [x0, #:lo12:foo] 384@end smallexample 385 386Note that @samp{:pg_hi21:} is optional. 387 388@smallexample 389 adrp x0, foo 390@end smallexample 391 392is equivalent to 393 394@smallexample 395 adrp x0, :pg_hi21:foo 396@end smallexample 397 398@node AArch64 Floating Point 399@section Floating Point 400 401@cindex floating point, AArch64 (@sc{ieee}) 402@cindex AArch64 floating point (@sc{ieee}) 403The AArch64 architecture uses @sc{ieee} floating-point numbers. 404 405@node AArch64 Directives 406@section AArch64 Machine Directives 407 408@cindex machine directives, AArch64 409@cindex AArch64 machine directives 410@table @code 411 412@c AAAAAAAAAAAAAAAAAAAAAAAAA 413 414@cindex @code{.arch} directive, AArch64 415@item .arch @var{name} 416Select the target architecture. Valid values for @var{name} are the same as 417for the @option{-march} command-line option. 418 419Specifying @code{.arch} clears any previously selected architecture 420extensions. 421 422@cindex @code{.arch_extension} directive, AArch64 423@item .arch_extension @var{name} 424Add or remove an architecture extension to the target architecture. Valid 425values for @var{name} are the same as those accepted as architectural 426extensions by the @option{-mcpu} command-line option. 427 428@code{.arch_extension} may be used multiple times to add or remove extensions 429incrementally to the architecture being compiled for. 430 431@c BBBBBBBBBBBBBBBBBBBBBBBBBB 432@c CCCCCCCCCCCCCCCCCCCCCCCCCC 433 434@cindex @code{.cpu} directive, AArch64 435@item .cpu @var{name} 436Set the target processor. Valid values for @var{name} are the same as 437those accepted by the @option{-mcpu=} command-line option. 438 439@c DDDDDDDDDDDDDDDDDDDDDDDDDD 440 441@cindex @code{.dword} directive, AArch64 442@item .dword @var{expressions} 443The @code{.dword} directive produces 64 bit values. 444 445@c EEEEEEEEEEEEEEEEEEEEEEEEEE 446 447@cindex @code{.even} directive, AArch64 448@item .even 449The @code{.even} directive aligns the output on the next even byte 450boundary. 451 452@c FFFFFFFFFFFFFFFFFFFFFFFFFF 453 454@cindex @code{.float16} directive, AArch64 455@item .float16 @var{value [,...,value_n]} 456Place the half precision floating point representation of one or more 457floating-point values into the current section. 458The format used to encode the floating point values is always the 459IEEE 754-2008 half precision floating point format. 460 461@c GGGGGGGGGGGGGGGGGGGGGGGGGG 462@c HHHHHHHHHHHHHHHHHHHHHHHHHH 463@c IIIIIIIIIIIIIIIIIIIIIIIIII 464 465@cindex @code{.inst} directive, AArch64 466@item .inst @var{expressions} 467Inserts the expressions into the output as if they were instructions, 468rather than data. 469 470@c JJJJJJJJJJJJJJJJJJJJJJJJJJ 471@c KKKKKKKKKKKKKKKKKKKKKKKKKK 472@c LLLLLLLLLLLLLLLLLLLLLLLLLL 473 474@cindex @code{.ltorg} directive, AArch64 475@item .ltorg 476This directive causes the current contents of the literal pool to be 477dumped into the current section (which is assumed to be the .text 478section) at the current location (aligned to a word boundary). 479GAS maintains a separate literal pool for each section and each 480sub-section. The @code{.ltorg} directive will only affect the literal 481pool of the current section and sub-section. At the end of assembly 482all remaining, un-empty literal pools will automatically be dumped. 483 484Note - older versions of GAS would dump the current literal 485pool any time a section change occurred. This is no longer done, since 486it prevents accurate control of the placement of literal pools. 487 488@c MMMMMMMMMMMMMMMMMMMMMMMMMM 489 490@c NNNNNNNNNNNNNNNNNNNNNNNNNN 491@c OOOOOOOOOOOOOOOOOOOOOOOOOO 492 493@c PPPPPPPPPPPPPPPPPPPPPPPPPP 494 495@cindex @code{.pool} directive, AArch64 496@item .pool 497This is a synonym for .ltorg. 498 499@c QQQQQQQQQQQQQQQQQQQQQQQQQQ 500@c RRRRRRRRRRRRRRRRRRRRRRRRRR 501 502@cindex @code{.req} directive, AArch64 503@item @var{name} .req @var{register name} 504This creates an alias for @var{register name} called @var{name}. For 505example: 506 507@smallexample 508 foo .req w0 509@end smallexample 510 511ip0, ip1, lr and fp are automatically defined to 512alias to X16, X17, X30 and X29 respectively. 513 514@c SSSSSSSSSSSSSSSSSSSSSSSSSS 515 516@c TTTTTTTTTTTTTTTTTTTTTTTTTT 517 518@cindex @code{.tlsdescadd} directive, AArch64 519@item @code{.tlsdescadd} 520Emits a TLSDESC_ADD reloc on the next instruction. 521 522@cindex @code{.tlsdesccall} directive, AArch64 523@item @code{.tlsdesccall} 524Emits a TLSDESC_CALL reloc on the next instruction. 525 526@cindex @code{.tlsdescldr} directive, AArch64 527@item @code{.tlsdescldr} 528Emits a TLSDESC_LDR reloc on the next instruction. 529 530@c UUUUUUUUUUUUUUUUUUUUUUUUUU 531 532@cindex @code{.unreq} directive, AArch64 533@item .unreq @var{alias-name} 534This undefines a register alias which was previously defined using the 535@code{req} directive. For example: 536 537@smallexample 538 foo .req w0 539 .unreq foo 540@end smallexample 541 542An error occurs if the name is undefined. Note - this pseudo op can 543be used to delete builtin in register name aliases (eg 'w0'). This 544should only be done if it is really necessary. 545 546@c VVVVVVVVVVVVVVVVVVVVVVVVVV 547 548@cindex @code{.variant_pcs} directive, AArch64 549@item .variant_pcs @var{symbol} 550This directive marks @var{symbol} referencing a function that may 551follow a variant procedure call standard with different register 552usage convention from the base procedure call standard. 553 554@c WWWWWWWWWWWWWWWWWWWWWWWWWW 555@c XXXXXXXXXXXXXXXXXXXXXXXXXX 556 557@cindex @code{.xword} directive, AArch64 558@item .xword @var{expressions} 559The @code{.xword} directive produces 64 bit values. This is the same 560as the @code{.dword} directive. 561 562@c YYYYYYYYYYYYYYYYYYYYYYYYYY 563@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ 564 565@cindex @code{.cfi_b_key_frame} directive, AArch64 566@item @code{.cfi_b_key_frame} 567The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE 568corresponding to the current frame's FDE, meaning that its return address has 569been signed with the B-key. If two frames are signed with differing keys then 570they will not share the same CIE. This information is intended to be used by 571the stack unwinder in order to properly authenticate return addresses. 572 573@end table 574 575@node AArch64 Opcodes 576@section Opcodes 577 578@cindex AArch64 opcodes 579@cindex opcodes for AArch64 580GAS implements all the standard AArch64 opcodes. It also 581implements several pseudo opcodes, including several synthetic load 582instructions. 583 584@table @code 585 586@cindex @code{LDR reg,=<expr>} pseudo op, AArch64 587@item LDR = 588@smallexample 589 ldr <register> , =<expression> 590@end smallexample 591 592The constant expression will be placed into the nearest literal pool (if it not 593already there) and a PC-relative LDR instruction will be generated. 594 595@end table 596 597For more information on the AArch64 instruction set and assembly language 598notation, see @samp{ARMv8 Instruction Set Overview} available at 599@uref{http://infocenter.arm.com}. 600 601 602@node AArch64 Mapping Symbols 603@section Mapping Symbols 604 605The AArch64 ELF specification requires that special symbols be inserted 606into object files to mark certain features: 607 608@table @code 609 610@cindex @code{$x} 611@item $x 612At the start of a region of code containing AArch64 instructions. 613 614@cindex @code{$d} 615@item $d 616At the start of a region of data. 617 618@end table 619