1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
2 /* CPU data for epiphany.
3
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
5
6 Copyright (C) 1996-2022 Free Software Foundation, Inc.
7
8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9
10 This file is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
19
20 You should have received a copy of the GNU General Public License along
21 with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
23
24 */
25
26 #include "sysdep.h"
27 #include <stdio.h>
28 #include <stdarg.h>
29 #include <stdlib.h>
30 #include "ansidecl.h"
31 #include "bfd.h"
32 #include "symcat.h"
33 #include "epiphany-desc.h"
34 #include "epiphany-opc.h"
35 #include "opintl.h"
36 #include "libiberty.h"
37 #include "xregex.h"
38
39 /* Attributes. */
40
41 static const CGEN_ATTR_ENTRY bool_attr[] =
42 {
43 { "#f", 0 },
44 { "#t", 1 },
45 { 0, 0 }
46 };
47
48 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
49 {
50 { "base", MACH_BASE },
51 { "epiphany32", MACH_EPIPHANY32 },
52 { "max", MACH_MAX },
53 { 0, 0 }
54 };
55
56 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
57 {
58 { "epiphany", ISA_EPIPHANY },
59 { "max", ISA_MAX },
60 { 0, 0 }
61 };
62
63 const CGEN_ATTR_TABLE epiphany_cgen_ifield_attr_table[] =
64 {
65 { "MACH", & MACH_attr[0], & MACH_attr[0] },
66 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
67 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
68 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
69 { "RESERVED", &bool_attr[0], &bool_attr[0] },
70 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
71 { "SIGNED", &bool_attr[0], &bool_attr[0] },
72 { "RELOC", &bool_attr[0], &bool_attr[0] },
73 { 0, 0, 0 }
74 };
75
76 const CGEN_ATTR_TABLE epiphany_cgen_hardware_attr_table[] =
77 {
78 { "MACH", & MACH_attr[0], & MACH_attr[0] },
79 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
80 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
81 { "PC", &bool_attr[0], &bool_attr[0] },
82 { "PROFILE", &bool_attr[0], &bool_attr[0] },
83 { 0, 0, 0 }
84 };
85
86 const CGEN_ATTR_TABLE epiphany_cgen_operand_attr_table[] =
87 {
88 { "MACH", & MACH_attr[0], & MACH_attr[0] },
89 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
90 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
91 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
92 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
93 { "SIGNED", &bool_attr[0], &bool_attr[0] },
94 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
95 { "RELAX", &bool_attr[0], &bool_attr[0] },
96 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
97 { "RELOC", &bool_attr[0], &bool_attr[0] },
98 { 0, 0, 0 }
99 };
100
101 const CGEN_ATTR_TABLE epiphany_cgen_insn_attr_table[] =
102 {
103 { "MACH", & MACH_attr[0], & MACH_attr[0] },
104 { "ALIAS", &bool_attr[0], &bool_attr[0] },
105 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
106 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
107 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
108 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
109 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
110 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
111 { "RELAXED", &bool_attr[0], &bool_attr[0] },
112 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
113 { "PBB", &bool_attr[0], &bool_attr[0] },
114 { "SHORT-INSN", &bool_attr[0], &bool_attr[0] },
115 { "IMM3", &bool_attr[0], &bool_attr[0] },
116 { "IMM8", &bool_attr[0], &bool_attr[0] },
117 { 0, 0, 0 }
118 };
119
120 /* Instruction set variants. */
121
122 static const CGEN_ISA epiphany_cgen_isa_table[] = {
123 { "epiphany", 32, 32, 16, 32 },
124 { 0, 0, 0, 0, 0 }
125 };
126
127 /* Machine variants. */
128
129 static const CGEN_MACH epiphany_cgen_mach_table[] = {
130 { "epiphany32", "epiphany32", MACH_EPIPHANY32, 0 },
131 { 0, 0, 0, 0 }
132 };
133
134 static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_gr_names_entries[] =
135 {
136 { "fp", 11, {0, {{{0, 0}}}}, 0, 0 },
137 { "sp", 13, {0, {{{0, 0}}}}, 0, 0 },
138 { "lr", 14, {0, {{{0, 0}}}}, 0, 0 },
139 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
140 { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
141 { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
142 { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
143 { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
144 { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
145 { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
146 { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
147 { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
148 { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
149 { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
150 { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
151 { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
152 { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
153 { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
154 { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
155 { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
156 { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
157 { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
158 { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
159 { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
160 { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
161 { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
162 { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
163 { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
164 { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
165 { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
166 { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
167 { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
168 { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
169 { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
170 { "r31", 31, {0, {{{0, 0}}}}, 0, 0 },
171 { "r32", 32, {0, {{{0, 0}}}}, 0, 0 },
172 { "r33", 33, {0, {{{0, 0}}}}, 0, 0 },
173 { "r34", 34, {0, {{{0, 0}}}}, 0, 0 },
174 { "r35", 35, {0, {{{0, 0}}}}, 0, 0 },
175 { "r36", 36, {0, {{{0, 0}}}}, 0, 0 },
176 { "r37", 37, {0, {{{0, 0}}}}, 0, 0 },
177 { "r38", 38, {0, {{{0, 0}}}}, 0, 0 },
178 { "r39", 39, {0, {{{0, 0}}}}, 0, 0 },
179 { "r40", 40, {0, {{{0, 0}}}}, 0, 0 },
180 { "r41", 41, {0, {{{0, 0}}}}, 0, 0 },
181 { "r42", 42, {0, {{{0, 0}}}}, 0, 0 },
182 { "r43", 43, {0, {{{0, 0}}}}, 0, 0 },
183 { "r44", 44, {0, {{{0, 0}}}}, 0, 0 },
184 { "r45", 45, {0, {{{0, 0}}}}, 0, 0 },
185 { "r46", 46, {0, {{{0, 0}}}}, 0, 0 },
186 { "r47", 47, {0, {{{0, 0}}}}, 0, 0 },
187 { "r48", 48, {0, {{{0, 0}}}}, 0, 0 },
188 { "r49", 49, {0, {{{0, 0}}}}, 0, 0 },
189 { "r50", 50, {0, {{{0, 0}}}}, 0, 0 },
190 { "r51", 51, {0, {{{0, 0}}}}, 0, 0 },
191 { "r52", 52, {0, {{{0, 0}}}}, 0, 0 },
192 { "r53", 53, {0, {{{0, 0}}}}, 0, 0 },
193 { "r54", 54, {0, {{{0, 0}}}}, 0, 0 },
194 { "r55", 55, {0, {{{0, 0}}}}, 0, 0 },
195 { "r56", 56, {0, {{{0, 0}}}}, 0, 0 },
196 { "r57", 57, {0, {{{0, 0}}}}, 0, 0 },
197 { "r58", 58, {0, {{{0, 0}}}}, 0, 0 },
198 { "r59", 59, {0, {{{0, 0}}}}, 0, 0 },
199 { "r60", 60, {0, {{{0, 0}}}}, 0, 0 },
200 { "r61", 61, {0, {{{0, 0}}}}, 0, 0 },
201 { "r62", 62, {0, {{{0, 0}}}}, 0, 0 },
202 { "r63", 63, {0, {{{0, 0}}}}, 0, 0 },
203 { "a1", 0, {0, {{{0, 0}}}}, 0, 0 },
204 { "a2", 1, {0, {{{0, 0}}}}, 0, 0 },
205 { "a3", 2, {0, {{{0, 0}}}}, 0, 0 },
206 { "a4", 3, {0, {{{0, 0}}}}, 0, 0 },
207 { "v1", 4, {0, {{{0, 0}}}}, 0, 0 },
208 { "v2", 5, {0, {{{0, 0}}}}, 0, 0 },
209 { "v3", 6, {0, {{{0, 0}}}}, 0, 0 },
210 { "v4", 7, {0, {{{0, 0}}}}, 0, 0 },
211 { "v5", 8, {0, {{{0, 0}}}}, 0, 0 },
212 { "v6", 9, {0, {{{0, 0}}}}, 0, 0 },
213 { "v7", 10, {0, {{{0, 0}}}}, 0, 0 },
214 { "v8", 11, {0, {{{0, 0}}}}, 0, 0 },
215 { "sb", 9, {0, {{{0, 0}}}}, 0, 0 },
216 { "sl", 10, {0, {{{0, 0}}}}, 0, 0 },
217 { "ip", 12, {0, {{{0, 0}}}}, 0, 0 }
218 };
219
220 CGEN_KEYWORD epiphany_cgen_opval_gr_names =
221 {
222 & epiphany_cgen_opval_gr_names_entries[0],
223 82,
224 0, 0, 0, 0, ""
225 };
226
227 static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_cr_names_entries[] =
228 {
229 { "config", 0, {0, {{{0, 0}}}}, 0, 0 },
230 { "status", 1, {0, {{{0, 0}}}}, 0, 0 },
231 { "pc", 2, {0, {{{0, 0}}}}, 0, 0 },
232 { "debug", 3, {0, {{{0, 0}}}}, 0, 0 },
233 { "iab", 4, {0, {{{0, 0}}}}, 0, 0 },
234 { "lc", 5, {0, {{{0, 0}}}}, 0, 0 },
235 { "ls", 6, {0, {{{0, 0}}}}, 0, 0 },
236 { "le", 7, {0, {{{0, 0}}}}, 0, 0 },
237 { "iret", 8, {0, {{{0, 0}}}}, 0, 0 },
238 { "imask", 9, {0, {{{0, 0}}}}, 0, 0 },
239 { "ilat", 10, {0, {{{0, 0}}}}, 0, 0 },
240 { "ilatst", 11, {0, {{{0, 0}}}}, 0, 0 },
241 { "ilatcl", 12, {0, {{{0, 0}}}}, 0, 0 },
242 { "ipend", 13, {0, {{{0, 0}}}}, 0, 0 },
243 { "ctimer0", 14, {0, {{{0, 0}}}}, 0, 0 },
244 { "ctimer1", 15, {0, {{{0, 0}}}}, 0, 0 },
245 { "hstatus", 16, {0, {{{0, 0}}}}, 0, 0 }
246 };
247
248 CGEN_KEYWORD epiphany_cgen_opval_cr_names =
249 {
250 & epiphany_cgen_opval_cr_names_entries[0],
251 17,
252 0, 0, 0, 0, ""
253 };
254
255 static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crdma_names_entries[] =
256 {
257 { "dma0config", 0, {0, {{{0, 0}}}}, 0, 0 },
258 { "dma0stride", 1, {0, {{{0, 0}}}}, 0, 0 },
259 { "dma0count", 2, {0, {{{0, 0}}}}, 0, 0 },
260 { "dma0srcaddr", 3, {0, {{{0, 0}}}}, 0, 0 },
261 { "dma0dstaddr", 4, {0, {{{0, 0}}}}, 0, 0 },
262 { "dma0auto0", 5, {0, {{{0, 0}}}}, 0, 0 },
263 { "dma0auto1", 6, {0, {{{0, 0}}}}, 0, 0 },
264 { "dma0status", 7, {0, {{{0, 0}}}}, 0, 0 },
265 { "dma1config", 8, {0, {{{0, 0}}}}, 0, 0 },
266 { "dma1stride", 9, {0, {{{0, 0}}}}, 0, 0 },
267 { "dma1count", 10, {0, {{{0, 0}}}}, 0, 0 },
268 { "dma1srcaddr", 11, {0, {{{0, 0}}}}, 0, 0 },
269 { "dma1dstaddr", 12, {0, {{{0, 0}}}}, 0, 0 },
270 { "dma1auto0", 13, {0, {{{0, 0}}}}, 0, 0 },
271 { "dma1auto1", 14, {0, {{{0, 0}}}}, 0, 0 },
272 { "dma1status", 15, {0, {{{0, 0}}}}, 0, 0 }
273 };
274
275 CGEN_KEYWORD epiphany_cgen_opval_crdma_names =
276 {
277 & epiphany_cgen_opval_crdma_names_entries[0],
278 16,
279 0, 0, 0, 0, ""
280 };
281
282 static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crmem_names_entries[] =
283 {
284 { "memconfig", 0, {0, {{{0, 0}}}}, 0, 0 },
285 { "memstatus", 1, {0, {{{0, 0}}}}, 0, 0 },
286 { "memprotect", 2, {0, {{{0, 0}}}}, 0, 0 },
287 { "memreserve", 3, {0, {{{0, 0}}}}, 0, 0 }
288 };
289
290 CGEN_KEYWORD epiphany_cgen_opval_crmem_names =
291 {
292 & epiphany_cgen_opval_crmem_names_entries[0],
293 4,
294 0, 0, 0, 0, ""
295 };
296
297 static CGEN_KEYWORD_ENTRY epiphany_cgen_opval_crmesh_names_entries[] =
298 {
299 { "meshconfig", 0, {0, {{{0, 0}}}}, 0, 0 },
300 { "coreid", 1, {0, {{{0, 0}}}}, 0, 0 },
301 { "meshmulticast", 2, {0, {{{0, 0}}}}, 0, 0 },
302 { "swreset", 3, {0, {{{0, 0}}}}, 0, 0 }
303 };
304
305 CGEN_KEYWORD epiphany_cgen_opval_crmesh_names =
306 {
307 & epiphany_cgen_opval_crmesh_names_entries[0],
308 4,
309 0, 0, 0, 0, ""
310 };
311
312
313 /* The hardware table. */
314
315 #define A(a) (1 << CGEN_HW_##a)
316
317 const CGEN_HW_ENTRY epiphany_cgen_hw_table[] =
318 {
319 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
320 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
321 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
322 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
323 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
324 { "h-registers", HW_H_REGISTERS, CGEN_ASM_KEYWORD, & epiphany_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
325 { "h-fpregisters", HW_H_FPREGISTERS, CGEN_ASM_KEYWORD, & epiphany_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
326 { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
327 { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
328 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
329 { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
330 { "h-vsbit", HW_H_VSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
331 { "h-bzbit", HW_H_BZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
332 { "h-bnbit", HW_H_BNBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
333 { "h-bvbit", HW_H_BVBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
334 { "h-bubit", HW_H_BUBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
335 { "h-bibit", HW_H_BIBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
336 { "h-bcbit", HW_H_BCBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
337 { "h-bvsbit", HW_H_BVSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
338 { "h-bisbit", HW_H_BISBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
339 { "h-busbit", HW_H_BUSBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
340 { "h-expcause0bit", HW_H_EXPCAUSE0BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
341 { "h-expcause1bit", HW_H_EXPCAUSE1BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
342 { "h-expcause2bit", HW_H_EXPCAUSE2BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
343 { "h-extFstallbit", HW_H_EXTFSTALLBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
344 { "h-trmbit", HW_H_TRMBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
345 { "h-invExcEnbit", HW_H_INVEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
346 { "h-ovfExcEnbit", HW_H_OVFEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
347 { "h-unExcEnbit", HW_H_UNEXCENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
348 { "h-timer0bit0", HW_H_TIMER0BIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
349 { "h-timer0bit1", HW_H_TIMER0BIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
350 { "h-timer0bit2", HW_H_TIMER0BIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
351 { "h-timer0bit3", HW_H_TIMER0BIT3, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
352 { "h-timer1bit0", HW_H_TIMER1BIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
353 { "h-timer1bit1", HW_H_TIMER1BIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
354 { "h-timer1bit2", HW_H_TIMER1BIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
355 { "h-timer1bit3", HW_H_TIMER1BIT3, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
356 { "h-mbkptEnbit", HW_H_MBKPTENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
357 { "h-clockGateEnbit", HW_H_CLOCKGATEENBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
358 { "h-coreCfgResBit12", HW_H_CORECFGRESBIT12, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
359 { "h-coreCfgResBit13", HW_H_CORECFGRESBIT13, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
360 { "h-coreCfgResBit14", HW_H_CORECFGRESBIT14, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
361 { "h-coreCfgResBit15", HW_H_CORECFGRESBIT15, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
362 { "h-coreCfgResBit16", HW_H_CORECFGRESBIT16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
363 { "h-coreCfgResBit20", HW_H_CORECFGRESBIT20, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
364 { "h-coreCfgResBit21", HW_H_CORECFGRESBIT21, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
365 { "h-coreCfgResBit24", HW_H_CORECFGRESBIT24, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
366 { "h-coreCfgResBit25", HW_H_CORECFGRESBIT25, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
367 { "h-coreCfgResBit26", HW_H_CORECFGRESBIT26, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
368 { "h-coreCfgResBit27", HW_H_CORECFGRESBIT27, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
369 { "h-coreCfgResBit28", HW_H_CORECFGRESBIT28, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
370 { "h-coreCfgResBit29", HW_H_CORECFGRESBIT29, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
371 { "h-coreCfgResBit30", HW_H_CORECFGRESBIT30, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
372 { "h-coreCfgResBit31", HW_H_CORECFGRESBIT31, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
373 { "h-arithmetic-modebit0", HW_H_ARITHMETIC_MODEBIT0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
374 { "h-arithmetic-modebit1", HW_H_ARITHMETIC_MODEBIT1, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
375 { "h-arithmetic-modebit2", HW_H_ARITHMETIC_MODEBIT2, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
376 { "h-gidisablebit", HW_H_GIDISABLEBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
377 { "h-kmbit", HW_H_KMBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
378 { "h-caibit", HW_H_CAIBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
379 { "h-sflagbit", HW_H_SFLAGBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
380 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
381 { "h-memaddr", HW_H_MEMADDR, CGEN_ASM_NONE, 0, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
382 { "h-core-registers", HW_H_CORE_REGISTERS, CGEN_ASM_KEYWORD, & epiphany_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
383 { "h-coredma-registers", HW_H_COREDMA_REGISTERS, CGEN_ASM_KEYWORD, & epiphany_cgen_opval_crdma_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
384 { "h-coremem-registers", HW_H_COREMEM_REGISTERS, CGEN_ASM_KEYWORD, & epiphany_cgen_opval_crmem_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
385 { "h-coremesh-registers", HW_H_COREMESH_REGISTERS, CGEN_ASM_KEYWORD, & epiphany_cgen_opval_crmesh_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
386 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
387 };
388
389 #undef A
390
391
392 /* The instruction field table. */
393
394 #define A(a) (1 << CGEN_IFLD_##a)
395
396 const CGEN_IFLD epiphany_cgen_ifld_table[] =
397 {
398 { EPIPHANY_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
399 { EPIPHANY_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
400 { EPIPHANY_F_OPC, "f-opc", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
401 { EPIPHANY_F_OPC_4_1, "f-opc-4-1", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
402 { EPIPHANY_F_OPC_6_3, "f-opc-6-3", 0, 32, 6, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
403 { EPIPHANY_F_OPC_8_5, "f-opc-8-5", 0, 32, 8, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
404 { EPIPHANY_F_OPC_19_4, "f-opc-19-4", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
405 { EPIPHANY_F_CONDCODE, "f-condcode", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
406 { EPIPHANY_F_SECONDARY_CCS, "f-secondary-ccs", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
407 { EPIPHANY_F_SHIFT, "f-shift", 0, 32, 9, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
408 { EPIPHANY_F_WORDSIZE, "f-wordsize", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } },
409 { EPIPHANY_F_STORE, "f-store", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
410 { EPIPHANY_F_OPC_8_1, "f-opc-8-1", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
411 { EPIPHANY_F_OPC_31_32, "f-opc-31-32", 0, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } } } } },
412 { EPIPHANY_F_SIMM8, "f-simm8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
413 { EPIPHANY_F_SIMM24, "f-simm24", 0, 32, 31, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
414 { EPIPHANY_F_SDISP3, "f-sdisp3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
415 { EPIPHANY_F_DISP3, "f-disp3", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
416 { EPIPHANY_F_DISP8, "f-disp8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
417 { EPIPHANY_F_IMM8, "f-imm8", 0, 32, 12, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
418 { EPIPHANY_F_IMM_27_8, "f-imm-27-8", 0, 32, 27, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } },
419 { EPIPHANY_F_ADDSUBX, "f-addsubx", 0, 32, 20, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
420 { EPIPHANY_F_SUBD, "f-subd", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
421 { EPIPHANY_F_PM, "f-pm", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
422 { EPIPHANY_F_RM, "f-rm", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
423 { EPIPHANY_F_RN, "f-rn", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
424 { EPIPHANY_F_RD, "f-rd", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
425 { EPIPHANY_F_RM_X, "f-rm-x", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
426 { EPIPHANY_F_RN_X, "f-rn-x", 0, 32, 28, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
427 { EPIPHANY_F_RD_X, "f-rd-x", 0, 32, 31, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
428 { EPIPHANY_F_DC_9_1, "f-dc-9-1", 0, 32, 9, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
429 { EPIPHANY_F_SN, "f-sn", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
430 { EPIPHANY_F_SD, "f-sd", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
431 { EPIPHANY_F_SN_X, "f-sn-x", 0, 32, 28, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
432 { EPIPHANY_F_SD_X, "f-sd-x", 0, 32, 31, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } },
433 { EPIPHANY_F_DC_7_4, "f-dc-7-4", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
434 { EPIPHANY_F_TRAP_SWI_9_1, "f-trap-swi-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
435 { EPIPHANY_F_GIEN_GIDIS_9_1, "f-gien-gidis-9-1", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } },
436 { EPIPHANY_F_DC_15_3, "f-dc-15-3", 0, 32, 15, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
437 { EPIPHANY_F_DC_15_7, "f-dc-15-7", 0, 32, 15, 7, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
438 { EPIPHANY_F_DC_15_6, "f-dc-15-6", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
439 { EPIPHANY_F_TRAP_NUM, "f-trap-num", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
440 { EPIPHANY_F_DC_20_1, "f-dc-20-1", 0, 32, 20, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
441 { EPIPHANY_F_DC_21_1, "f-dc-21-1", 0, 32, 21, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
442 { EPIPHANY_F_DC_21_2, "f-dc-21-2", 0, 32, 21, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
443 { EPIPHANY_F_DC_22_3, "f-dc-22-3", 0, 32, 22, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
444 { EPIPHANY_F_DC_22_2, "f-dc-22-2", 0, 32, 22, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
445 { EPIPHANY_F_DC_22_1, "f-dc-22-1", 0, 32, 22, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
446 { EPIPHANY_F_DC_25_6, "f-dc-25-6", 0, 32, 25, 6, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
447 { EPIPHANY_F_DC_25_4, "f-dc-25-4", 0, 32, 25, 4, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
448 { EPIPHANY_F_DC_25_2, "f-dc-25-2", 0, 32, 25, 2, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
449 { EPIPHANY_F_DC_25_1, "f-dc-25-1", 0, 32, 25, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
450 { EPIPHANY_F_DC_28_1, "f-dc-28-1", 0, 32, 28, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
451 { EPIPHANY_F_DC_31_3, "f-dc-31-3", 0, 32, 31, 3, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
452 { EPIPHANY_F_DISP11, "f-disp11", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
453 { EPIPHANY_F_SDISP11, "f-sdisp11", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
454 { EPIPHANY_F_IMM16, "f-imm16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
455 { EPIPHANY_F_RD6, "f-rd6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
456 { EPIPHANY_F_RN6, "f-rn6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
457 { EPIPHANY_F_RM6, "f-rm6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
458 { EPIPHANY_F_SD6, "f-sd6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
459 { EPIPHANY_F_SN6, "f-sn6", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
460 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
461 };
462
463 #undef A
464
465
466
467 /* multi ifield declarations */
468
469 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_DISP11_MULTI_IFIELD [];
470 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SDISP11_MULTI_IFIELD [];
471 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_IMM16_MULTI_IFIELD [];
472 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RD6_MULTI_IFIELD [];
473 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RN6_MULTI_IFIELD [];
474 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RM6_MULTI_IFIELD [];
475 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SD6_MULTI_IFIELD [];
476 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SN6_MULTI_IFIELD [];
477
478
479 /* multi ifield definitions */
480
481 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_DISP11_MULTI_IFIELD [] =
482 {
483 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
484 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } },
485 { 0, { 0 } }
486 };
487 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SDISP11_MULTI_IFIELD [] =
488 {
489 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
490 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_DISP8] } },
491 { 0, { 0 } }
492 };
493 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_IMM16_MULTI_IFIELD [] =
494 {
495 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
496 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_IMM_27_8] } },
497 { 0, { 0 } }
498 };
499 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RD6_MULTI_IFIELD [] =
500 {
501 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RD_X] } },
502 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
503 { 0, { 0 } }
504 };
505 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RN6_MULTI_IFIELD [] =
506 {
507 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RN_X] } },
508 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
509 { 0, { 0 } }
510 };
511 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_RM6_MULTI_IFIELD [] =
512 {
513 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RM_X] } },
514 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
515 { 0, { 0 } }
516 };
517 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SD6_MULTI_IFIELD [] =
518 {
519 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SD_X] } },
520 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
521 { 0, { 0 } }
522 };
523 const CGEN_MAYBE_MULTI_IFLD EPIPHANY_F_SN6_MULTI_IFIELD [] =
524 {
525 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SN_X] } },
526 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
527 { 0, { 0 } }
528 };
529
530 /* The operand table. */
531
532 #define A(a) (1 << CGEN_OPERAND_##a)
533 #define OPERAND(op) EPIPHANY_OPERAND_##op
534
535 const CGEN_OPERAND epiphany_cgen_operand_table[] =
536 {
537 /* pc: program counter */
538 { "pc", EPIPHANY_OPERAND_PC, HW_H_PC, 0, 0,
539 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_NIL] } },
540 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
541 /* zbit: integer zero bit */
542 { "zbit", EPIPHANY_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
543 { 0, { 0 } },
544 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
545 /* nbit: integer neg bit */
546 { "nbit", EPIPHANY_OPERAND_NBIT, HW_H_NBIT, 0, 0,
547 { 0, { 0 } },
548 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
549 /* cbit: integer carry bit */
550 { "cbit", EPIPHANY_OPERAND_CBIT, HW_H_CBIT, 0, 0,
551 { 0, { 0 } },
552 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
553 /* vbit: integer overflow bit */
554 { "vbit", EPIPHANY_OPERAND_VBIT, HW_H_VBIT, 0, 0,
555 { 0, { 0 } },
556 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
557 /* bzbit: floating point zero bit */
558 { "bzbit", EPIPHANY_OPERAND_BZBIT, HW_H_BZBIT, 0, 0,
559 { 0, { 0 } },
560 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
561 /* bnbit: floating point neg bit */
562 { "bnbit", EPIPHANY_OPERAND_BNBIT, HW_H_BNBIT, 0, 0,
563 { 0, { 0 } },
564 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
565 /* bvbit: floating point ovfl bit */
566 { "bvbit", EPIPHANY_OPERAND_BVBIT, HW_H_BVBIT, 0, 0,
567 { 0, { 0 } },
568 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
569 /* bcbit: floating point carry bit */
570 { "bcbit", EPIPHANY_OPERAND_BCBIT, HW_H_BCBIT, 0, 0,
571 { 0, { 0 } },
572 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
573 /* bubit: floating point underfl bit */
574 { "bubit", EPIPHANY_OPERAND_BUBIT, HW_H_BUBIT, 0, 0,
575 { 0, { 0 } },
576 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
577 /* bibit: floating point invalid bit */
578 { "bibit", EPIPHANY_OPERAND_BIBIT, HW_H_BIBIT, 0, 0,
579 { 0, { 0 } },
580 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
581 /* vsbit: integer overflow sticky */
582 { "vsbit", EPIPHANY_OPERAND_VSBIT, HW_H_VSBIT, 0, 0,
583 { 0, { 0 } },
584 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
585 /* bvsbit: floating point overflow sticky */
586 { "bvsbit", EPIPHANY_OPERAND_BVSBIT, HW_H_BVSBIT, 0, 0,
587 { 0, { 0 } },
588 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
589 /* bisbit: floating point invalid sticky */
590 { "bisbit", EPIPHANY_OPERAND_BISBIT, HW_H_BISBIT, 0, 0,
591 { 0, { 0 } },
592 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
593 /* busbit: floating point underflow sticky */
594 { "busbit", EPIPHANY_OPERAND_BUSBIT, HW_H_BUSBIT, 0, 0,
595 { 0, { 0 } },
596 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
597 /* expcause0bit: exceprion cause bit0 */
598 { "expcause0bit", EPIPHANY_OPERAND_EXPCAUSE0BIT, HW_H_EXPCAUSE0BIT, 0, 0,
599 { 0, { 0 } },
600 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
601 /* expcause1bit: exceprion cause bit1 */
602 { "expcause1bit", EPIPHANY_OPERAND_EXPCAUSE1BIT, HW_H_EXPCAUSE1BIT, 0, 0,
603 { 0, { 0 } },
604 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
605 /* expcause2bit: external load stalled bit */
606 { "expcause2bit", EPIPHANY_OPERAND_EXPCAUSE2BIT, HW_H_EXPCAUSE2BIT, 0, 0,
607 { 0, { 0 } },
608 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
609 /* extFstallbit: external fetch stalled bit */
610 { "extFstallbit", EPIPHANY_OPERAND_EXTFSTALLBIT, HW_H_EXTFSTALLBIT, 0, 0,
611 { 0, { 0 } },
612 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
613 /* trmbit: 0=round to nearest, 1=trunacte selct bit */
614 { "trmbit", EPIPHANY_OPERAND_TRMBIT, HW_H_TRMBIT, 0, 0,
615 { 0, { 0 } },
616 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
617 /* invExcEnbit: invalid exception enable bit */
618 { "invExcEnbit", EPIPHANY_OPERAND_INVEXCENBIT, HW_H_INVEXCENBIT, 0, 0,
619 { 0, { 0 } },
620 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
621 /* ovfExcEnbit: overflow exception enable bit */
622 { "ovfExcEnbit", EPIPHANY_OPERAND_OVFEXCENBIT, HW_H_OVFEXCENBIT, 0, 0,
623 { 0, { 0 } },
624 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
625 /* unExcEnbit: underflow exception enable bit */
626 { "unExcEnbit", EPIPHANY_OPERAND_UNEXCENBIT, HW_H_UNEXCENBIT, 0, 0,
627 { 0, { 0 } },
628 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
629 /* timer0bit0: timer 0 mode selection 0 */
630 { "timer0bit0", EPIPHANY_OPERAND_TIMER0BIT0, HW_H_TIMER0BIT0, 0, 0,
631 { 0, { 0 } },
632 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
633 /* timer0bit1: timer 0 mode selection 1 */
634 { "timer0bit1", EPIPHANY_OPERAND_TIMER0BIT1, HW_H_TIMER0BIT1, 0, 0,
635 { 0, { 0 } },
636 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
637 /* timer0bit2: timer 0 mode selection 2 */
638 { "timer0bit2", EPIPHANY_OPERAND_TIMER0BIT2, HW_H_TIMER0BIT2, 0, 0,
639 { 0, { 0 } },
640 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
641 /* timer0bit3: timer 0 mode selection 3 */
642 { "timer0bit3", EPIPHANY_OPERAND_TIMER0BIT3, HW_H_TIMER0BIT3, 0, 0,
643 { 0, { 0 } },
644 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
645 /* timer1bit0: timer 1 mode selection 0 */
646 { "timer1bit0", EPIPHANY_OPERAND_TIMER1BIT0, HW_H_TIMER1BIT0, 0, 0,
647 { 0, { 0 } },
648 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
649 /* timer1bit1: timer 1 mode selection 1 */
650 { "timer1bit1", EPIPHANY_OPERAND_TIMER1BIT1, HW_H_TIMER1BIT1, 0, 0,
651 { 0, { 0 } },
652 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
653 /* timer1bit2: timer 1 mode selection 2 */
654 { "timer1bit2", EPIPHANY_OPERAND_TIMER1BIT2, HW_H_TIMER1BIT2, 0, 0,
655 { 0, { 0 } },
656 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
657 /* timer1bit3: timer 1 mode selection 3 */
658 { "timer1bit3", EPIPHANY_OPERAND_TIMER1BIT3, HW_H_TIMER1BIT3, 0, 0,
659 { 0, { 0 } },
660 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
661 /* mbkptEnbit: multicore bkpt enable */
662 { "mbkptEnbit", EPIPHANY_OPERAND_MBKPTENBIT, HW_H_MBKPTENBIT, 0, 0,
663 { 0, { 0 } },
664 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
665 /* clockGateEnbit: clock gate enable enable */
666 { "clockGateEnbit", EPIPHANY_OPERAND_CLOCKGATEENBIT, HW_H_CLOCKGATEENBIT, 0, 0,
667 { 0, { 0 } },
668 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
669 /* arithmetic-modebit0: arithmetic mode bit0 */
670 { "arithmetic-modebit0", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT0, HW_H_ARITHMETIC_MODEBIT0, 0, 0,
671 { 0, { 0 } },
672 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
673 /* arithmetic-modebit1: arithmetic mode bit1 */
674 { "arithmetic-modebit1", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT1, HW_H_ARITHMETIC_MODEBIT1, 0, 0,
675 { 0, { 0 } },
676 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
677 /* arithmetic-modebit2: arithmetic mode bit2 */
678 { "arithmetic-modebit2", EPIPHANY_OPERAND_ARITHMETIC_MODEBIT2, HW_H_ARITHMETIC_MODEBIT2, 0, 0,
679 { 0, { 0 } },
680 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
681 /* coreCfgResBit12: core config bit 12 */
682 { "coreCfgResBit12", EPIPHANY_OPERAND_CORECFGRESBIT12, HW_H_CORECFGRESBIT12, 0, 0,
683 { 0, { 0 } },
684 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
685 /* coreCfgResBit13: core config bit 13 */
686 { "coreCfgResBit13", EPIPHANY_OPERAND_CORECFGRESBIT13, HW_H_CORECFGRESBIT13, 0, 0,
687 { 0, { 0 } },
688 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
689 /* coreCfgResBit14: core config bit 14 */
690 { "coreCfgResBit14", EPIPHANY_OPERAND_CORECFGRESBIT14, HW_H_CORECFGRESBIT14, 0, 0,
691 { 0, { 0 } },
692 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
693 /* coreCfgResBit15: core config bit 15 */
694 { "coreCfgResBit15", EPIPHANY_OPERAND_CORECFGRESBIT15, HW_H_CORECFGRESBIT15, 0, 0,
695 { 0, { 0 } },
696 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
697 /* coreCfgResBit16: core config bit 16 */
698 { "coreCfgResBit16", EPIPHANY_OPERAND_CORECFGRESBIT16, HW_H_CORECFGRESBIT16, 0, 0,
699 { 0, { 0 } },
700 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
701 /* coreCfgResBit20: core config bit 20 */
702 { "coreCfgResBit20", EPIPHANY_OPERAND_CORECFGRESBIT20, HW_H_CORECFGRESBIT20, 0, 0,
703 { 0, { 0 } },
704 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
705 /* coreCfgResBit21: core config bit 21 */
706 { "coreCfgResBit21", EPIPHANY_OPERAND_CORECFGRESBIT21, HW_H_CORECFGRESBIT21, 0, 0,
707 { 0, { 0 } },
708 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
709 /* coreCfgResBit24: core config bit 24 */
710 { "coreCfgResBit24", EPIPHANY_OPERAND_CORECFGRESBIT24, HW_H_CORECFGRESBIT24, 0, 0,
711 { 0, { 0 } },
712 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
713 /* coreCfgResBit25: core config bit 25 */
714 { "coreCfgResBit25", EPIPHANY_OPERAND_CORECFGRESBIT25, HW_H_CORECFGRESBIT25, 0, 0,
715 { 0, { 0 } },
716 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
717 /* coreCfgResBit26: core config bit 26 */
718 { "coreCfgResBit26", EPIPHANY_OPERAND_CORECFGRESBIT26, HW_H_CORECFGRESBIT26, 0, 0,
719 { 0, { 0 } },
720 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
721 /* coreCfgResBit27: core config bit 27 */
722 { "coreCfgResBit27", EPIPHANY_OPERAND_CORECFGRESBIT27, HW_H_CORECFGRESBIT27, 0, 0,
723 { 0, { 0 } },
724 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
725 /* coreCfgResBit28: core config bit 28 */
726 { "coreCfgResBit28", EPIPHANY_OPERAND_CORECFGRESBIT28, HW_H_CORECFGRESBIT28, 0, 0,
727 { 0, { 0 } },
728 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
729 /* coreCfgResBit29: core config bit 29 */
730 { "coreCfgResBit29", EPIPHANY_OPERAND_CORECFGRESBIT29, HW_H_CORECFGRESBIT29, 0, 0,
731 { 0, { 0 } },
732 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
733 /* coreCfgResBit30: core config bit 30 */
734 { "coreCfgResBit30", EPIPHANY_OPERAND_CORECFGRESBIT30, HW_H_CORECFGRESBIT30, 0, 0,
735 { 0, { 0 } },
736 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
737 /* coreCfgResBit31: core config bit 31 */
738 { "coreCfgResBit31", EPIPHANY_OPERAND_CORECFGRESBIT31, HW_H_CORECFGRESBIT31, 0, 0,
739 { 0, { 0 } },
740 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
741 /* gidisablebit: global interrupt disable bit */
742 { "gidisablebit", EPIPHANY_OPERAND_GIDISABLEBIT, HW_H_GIDISABLEBIT, 0, 0,
743 { 0, { 0 } },
744 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
745 /* kmbit: kernel mode bit */
746 { "kmbit", EPIPHANY_OPERAND_KMBIT, HW_H_KMBIT, 0, 0,
747 { 0, { 0 } },
748 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
749 /* caibit: core actibe indicator bit */
750 { "caibit", EPIPHANY_OPERAND_CAIBIT, HW_H_CAIBIT, 0, 0,
751 { 0, { 0 } },
752 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
753 /* sflagbit: sflag bit */
754 { "sflagbit", EPIPHANY_OPERAND_SFLAGBIT, HW_H_SFLAGBIT, 0, 0,
755 { 0, { 0 } },
756 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
757 /* memaddr: memory effective address */
758 { "memaddr", EPIPHANY_OPERAND_MEMADDR, HW_H_MEMADDR, 0, 0,
759 { 0, { 0 } },
760 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
761 /* simm24: branch address pc-relative */
762 { "simm24", EPIPHANY_OPERAND_SIMM24, HW_H_IADDR, 31, 24,
763 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM24] } },
764 { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
765 /* simm8: branch address pc-relative */
766 { "simm8", EPIPHANY_OPERAND_SIMM8, HW_H_IADDR, 15, 8,
767 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SIMM8] } },
768 { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
769 /* rd: destination register */
770 { "rd", EPIPHANY_OPERAND_RD, HW_H_REGISTERS, 15, 3,
771 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
772 { 0, { { { (1<<MACH_BASE), 0 } } } } },
773 /* rn: source register */
774 { "rn", EPIPHANY_OPERAND_RN, HW_H_REGISTERS, 12, 3,
775 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
776 { 0, { { { (1<<MACH_BASE), 0 } } } } },
777 /* rm: source register */
778 { "rm", EPIPHANY_OPERAND_RM, HW_H_REGISTERS, 9, 3,
779 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
780 { 0, { { { (1<<MACH_BASE), 0 } } } } },
781 /* frd: fp destination register */
782 { "frd", EPIPHANY_OPERAND_FRD, HW_H_FPREGISTERS, 15, 3,
783 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RD] } },
784 { 0, { { { (1<<MACH_BASE), 0 } } } } },
785 /* frn: fp source register */
786 { "frn", EPIPHANY_OPERAND_FRN, HW_H_FPREGISTERS, 12, 3,
787 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RN] } },
788 { 0, { { { (1<<MACH_BASE), 0 } } } } },
789 /* frm: fp source register */
790 { "frm", EPIPHANY_OPERAND_FRM, HW_H_FPREGISTERS, 9, 3,
791 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_RM] } },
792 { 0, { { { (1<<MACH_BASE), 0 } } } } },
793 /* rd6: destination register */
794 { "rd6", EPIPHANY_OPERAND_RD6, HW_H_REGISTERS, 15, 6,
795 { 2, { &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
796 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
797 /* rn6: source register */
798 { "rn6", EPIPHANY_OPERAND_RN6, HW_H_REGISTERS, 12, 6,
799 { 2, { &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
800 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
801 /* rm6: source register */
802 { "rm6", EPIPHANY_OPERAND_RM6, HW_H_REGISTERS, 9, 6,
803 { 2, { &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
804 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
805 /* frd6: fp destination register */
806 { "frd6", EPIPHANY_OPERAND_FRD6, HW_H_FPREGISTERS, 15, 6,
807 { 2, { &EPIPHANY_F_RD6_MULTI_IFIELD[0] } },
808 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
809 /* frn6: fp source register */
810 { "frn6", EPIPHANY_OPERAND_FRN6, HW_H_FPREGISTERS, 12, 6,
811 { 2, { &EPIPHANY_F_RN6_MULTI_IFIELD[0] } },
812 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
813 /* frm6: fp source register */
814 { "frm6", EPIPHANY_OPERAND_FRM6, HW_H_FPREGISTERS, 9, 6,
815 { 2, { &EPIPHANY_F_RM6_MULTI_IFIELD[0] } },
816 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
817 /* sd: special destination */
818 { "sd", EPIPHANY_OPERAND_SD, HW_H_CORE_REGISTERS, 15, 3,
819 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SD] } },
820 { 0, { { { (1<<MACH_BASE), 0 } } } } },
821 /* sn: special source */
822 { "sn", EPIPHANY_OPERAND_SN, HW_H_CORE_REGISTERS, 12, 3,
823 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SN] } },
824 { 0, { { { (1<<MACH_BASE), 0 } } } } },
825 /* sd6: special destination register */
826 { "sd6", EPIPHANY_OPERAND_SD6, HW_H_CORE_REGISTERS, 15, 6,
827 { 2, { &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
828 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
829 /* sn6: special source register */
830 { "sn6", EPIPHANY_OPERAND_SN6, HW_H_CORE_REGISTERS, 12, 6,
831 { 2, { &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
832 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
833 /* sddma: dma register */
834 { "sddma", EPIPHANY_OPERAND_SDDMA, HW_H_COREDMA_REGISTERS, 15, 6,
835 { 2, { &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
836 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
837 /* sndma: dma register */
838 { "sndma", EPIPHANY_OPERAND_SNDMA, HW_H_COREDMA_REGISTERS, 12, 6,
839 { 2, { &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
840 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
841 /* sdmem: mem register */
842 { "sdmem", EPIPHANY_OPERAND_SDMEM, HW_H_COREMEM_REGISTERS, 15, 6,
843 { 2, { &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
844 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
845 /* snmem: mem register */
846 { "snmem", EPIPHANY_OPERAND_SNMEM, HW_H_COREMEM_REGISTERS, 12, 6,
847 { 2, { &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
848 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
849 /* sdmesh: mesh register */
850 { "sdmesh", EPIPHANY_OPERAND_SDMESH, HW_H_COREMESH_REGISTERS, 15, 6,
851 { 2, { &EPIPHANY_F_SD6_MULTI_IFIELD[0] } },
852 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
853 /* snmesh: mesh register */
854 { "snmesh", EPIPHANY_OPERAND_SNMESH, HW_H_COREMESH_REGISTERS, 12, 6,
855 { 2, { &EPIPHANY_F_SN6_MULTI_IFIELD[0] } },
856 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
857 /* simm3: signed 3-bit literal */
858 { "simm3", EPIPHANY_OPERAND_SIMM3, HW_H_SINT, 9, 3,
859 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SDISP3] } },
860 { 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } },
861 /* simm11: signed 11-bit literal */
862 { "simm11", EPIPHANY_OPERAND_SIMM11, HW_H_SINT, 9, 11,
863 { 2, { &EPIPHANY_F_SDISP11_MULTI_IFIELD[0] } },
864 { 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
865 /* disp3: short data displacement */
866 { "disp3", EPIPHANY_OPERAND_DISP3, HW_H_UINT, 9, 3,
867 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_DISP3] } },
868 { 0, { { { (1<<MACH_BASE), 0 } } } } },
869 /* trapnum6: parameter for swi or trap */
870 { "trapnum6", EPIPHANY_OPERAND_TRAPNUM6, HW_H_UINT, 15, 6,
871 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
872 { 0, { { { (1<<MACH_BASE), 0 } } } } },
873 /* swi_num: unsigned 6-bit swi# */
874 { "swi_num", EPIPHANY_OPERAND_SWI_NUM, HW_H_UINT, 15, 6,
875 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_TRAP_NUM] } },
876 { 0, { { { (1<<MACH_BASE), 0 } } } } },
877 /* disp11: sign-magnitude data displacement */
878 { "disp11", EPIPHANY_OPERAND_DISP11, HW_H_UINT, 9, 11,
879 { 2, { &EPIPHANY_F_DISP11_MULTI_IFIELD[0] } },
880 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
881 /* shift: immediate shift amount */
882 { "shift", EPIPHANY_OPERAND_SHIFT, HW_H_UINT, 9, 5,
883 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SHIFT] } },
884 { 0, { { { (1<<MACH_BASE), 0 } } } } },
885 /* imm16: 16-bit unsigned literal */
886 { "imm16", EPIPHANY_OPERAND_IMM16, HW_H_ADDR, 12, 16,
887 { 2, { &EPIPHANY_F_IMM16_MULTI_IFIELD[0] } },
888 { 0|A(RELAX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
889 /* imm8: 8-bit unsigned literal */
890 { "imm8", EPIPHANY_OPERAND_IMM8, HW_H_ADDR, 12, 8,
891 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_IMM8] } },
892 { 0|A(RELAX), { { { (1<<MACH_BASE), 0 } } } } },
893 /* direction: +/- indexing */
894 { "direction", EPIPHANY_OPERAND_DIRECTION, HW_H_UINT, 20, 1,
895 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_ADDSUBX] } },
896 { 0, { { { (1<<MACH_BASE), 0 } } } } },
897 /* dpmi: +/- magnitude immediate displacement */
898 { "dpmi", EPIPHANY_OPERAND_DPMI, HW_H_UINT, 24, 1,
899 { 0, { &epiphany_cgen_ifld_table[EPIPHANY_F_SUBD] } },
900 { 0, { { { (1<<MACH_BASE), 0 } } } } },
901 /* sentinel */
902 { 0, 0, 0, 0, 0,
903 { 0, { 0 } },
904 { 0, { { { (1<<MACH_BASE), 0 } } } } }
905 };
906
907 #undef A
908
909
910 /* The instruction table. */
911
912 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
913 #define A(a) (1 << CGEN_INSN_##a)
914
915 static const CGEN_IBASE epiphany_cgen_insn_table[MAX_INSNS] =
916 {
917 /* Special null first entry.
918 A `num' value of zero is thus invalid.
919 Also, the special `invalid' insn resides here. */
920 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
921 /* beq.s $simm8 */
922 {
923 EPIPHANY_INSN_BEQ16, "beq16", "beq.s", 16,
924 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
925 },
926 /* beq.l $simm24 */
927 {
928 EPIPHANY_INSN_BEQ, "beq", "beq.l", 32,
929 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
930 },
931 /* bne.s $simm8 */
932 {
933 EPIPHANY_INSN_BNE16, "bne16", "bne.s", 16,
934 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
935 },
936 /* bne.l $simm24 */
937 {
938 EPIPHANY_INSN_BNE, "bne", "bne.l", 32,
939 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
940 },
941 /* bgtu.s $simm8 */
942 {
943 EPIPHANY_INSN_BGTU16, "bgtu16", "bgtu.s", 16,
944 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
945 },
946 /* bgtu.l $simm24 */
947 {
948 EPIPHANY_INSN_BGTU, "bgtu", "bgtu.l", 32,
949 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
950 },
951 /* bgteu.s $simm8 */
952 {
953 EPIPHANY_INSN_BGTEU16, "bgteu16", "bgteu.s", 16,
954 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
955 },
956 /* bgteu.l $simm24 */
957 {
958 EPIPHANY_INSN_BGTEU, "bgteu", "bgteu.l", 32,
959 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
960 },
961 /* blteu.s $simm8 */
962 {
963 EPIPHANY_INSN_BLTEU16, "blteu16", "blteu.s", 16,
964 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
965 },
966 /* blteu.l $simm24 */
967 {
968 EPIPHANY_INSN_BLTEU, "blteu", "blteu.l", 32,
969 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
970 },
971 /* bltu.s $simm8 */
972 {
973 EPIPHANY_INSN_BLTU16, "bltu16", "bltu.s", 16,
974 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
975 },
976 /* bltu.l $simm24 */
977 {
978 EPIPHANY_INSN_BLTU, "bltu", "bltu.l", 32,
979 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
980 },
981 /* bgt.s $simm8 */
982 {
983 EPIPHANY_INSN_BGT16, "bgt16", "bgt.s", 16,
984 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
985 },
986 /* bgt.l $simm24 */
987 {
988 EPIPHANY_INSN_BGT, "bgt", "bgt.l", 32,
989 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
990 },
991 /* bgte.s $simm8 */
992 {
993 EPIPHANY_INSN_BGTE16, "bgte16", "bgte.s", 16,
994 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
995 },
996 /* bgte.l $simm24 */
997 {
998 EPIPHANY_INSN_BGTE, "bgte", "bgte.l", 32,
999 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1000 },
1001 /* blt.s $simm8 */
1002 {
1003 EPIPHANY_INSN_BLT16, "blt16", "blt.s", 16,
1004 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1005 },
1006 /* blt.l $simm24 */
1007 {
1008 EPIPHANY_INSN_BLT, "blt", "blt.l", 32,
1009 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1010 },
1011 /* blte.s $simm8 */
1012 {
1013 EPIPHANY_INSN_BLTE16, "blte16", "blte.s", 16,
1014 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1015 },
1016 /* blte.l $simm24 */
1017 {
1018 EPIPHANY_INSN_BLTE, "blte", "blte.l", 32,
1019 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1020 },
1021 /* bbeq.s $simm8 */
1022 {
1023 EPIPHANY_INSN_BBEQ16, "bbeq16", "bbeq.s", 16,
1024 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1025 },
1026 /* bbeq.l $simm24 */
1027 {
1028 EPIPHANY_INSN_BBEQ, "bbeq", "bbeq.l", 32,
1029 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1030 },
1031 /* bbne.s $simm8 */
1032 {
1033 EPIPHANY_INSN_BBNE16, "bbne16", "bbne.s", 16,
1034 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1035 },
1036 /* bbne.l $simm24 */
1037 {
1038 EPIPHANY_INSN_BBNE, "bbne", "bbne.l", 32,
1039 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1040 },
1041 /* bblt.s $simm8 */
1042 {
1043 EPIPHANY_INSN_BBLT16, "bblt16", "bblt.s", 16,
1044 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1045 },
1046 /* bblt.l $simm24 */
1047 {
1048 EPIPHANY_INSN_BBLT, "bblt", "bblt.l", 32,
1049 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1050 },
1051 /* bblte.s $simm8 */
1052 {
1053 EPIPHANY_INSN_BBLTE16, "bblte16", "bblte.s", 16,
1054 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1055 },
1056 /* bblte.l $simm24 */
1057 {
1058 EPIPHANY_INSN_BBLTE, "bblte", "bblte.l", 32,
1059 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1060 },
1061 /* b.s $simm8 */
1062 {
1063 EPIPHANY_INSN_B16, "b16", "b.s", 16,
1064 { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1065 },
1066 /* b.l $simm24 */
1067 {
1068 EPIPHANY_INSN_B, "b", "b.l", 32,
1069 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1070 },
1071 /* bl.s $simm8 */
1072 {
1073 EPIPHANY_INSN_BL16, "bl16", "bl.s", 16,
1074 { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1075 },
1076 /* bl.l $simm24 */
1077 {
1078 EPIPHANY_INSN_BL, "bl", "bl.l", 32,
1079 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1080 },
1081 /* jr $rn */
1082 {
1083 EPIPHANY_INSN_JR16, "jr16", "jr", 16,
1084 { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1085 },
1086 /* rts */
1087 {
1088 -1, "rts", "rts", 32,
1089 { 0|A(UNCOND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
1090 },
1091 /* jr $rn6 */
1092 {
1093 EPIPHANY_INSN_JR, "jr", "jr", 32,
1094 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1095 },
1096 /* jalr $rn */
1097 {
1098 EPIPHANY_INSN_JALR16, "jalr16", "jalr", 16,
1099 { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1100 },
1101 /* jalr $rn6 */
1102 {
1103 EPIPHANY_INSN_JALR, "jalr", "jalr", 32,
1104 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1105 },
1106 /* ldrb $rd,[$rn,$rm] */
1107 {
1108 EPIPHANY_INSN_LDRBX16_S, "ldrbx16.s", "ldrb", 16,
1109 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1110 },
1111 /* ldrb $rd,[$rn],$rm */
1112 {
1113 EPIPHANY_INSN_LDRBP16_S, "ldrbp16.s", "ldrb", 16,
1114 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1115 },
1116 /* ldrb $rd6,[$rn6,$direction$rm6] */
1117 {
1118 EPIPHANY_INSN_LDRBX_L, "ldrbx.l", "ldrb", 32,
1119 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1120 },
1121 /* ldrb $rd6,[$rn6],$direction$rm6 */
1122 {
1123 EPIPHANY_INSN_LDRBP_L, "ldrbp.l", "ldrb", 32,
1124 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1125 },
1126 /* ldrb $rd,[$rn,$disp3] */
1127 {
1128 EPIPHANY_INSN_LDRBD16_S, "ldrbd16.s", "ldrb", 16,
1129 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1130 },
1131 /* ldrb $rd6,[$rn6,$dpmi$disp11] */
1132 {
1133 EPIPHANY_INSN_LDRBD_L, "ldrbd.l", "ldrb", 32,
1134 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1135 },
1136 /* ldrb $rd6,[$rn6],$dpmi$disp11 */
1137 {
1138 EPIPHANY_INSN_LDRBDPM_L, "ldrbdpm.l", "ldrb", 32,
1139 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1140 },
1141 /* ldrh $rd,[$rn,$rm] */
1142 {
1143 EPIPHANY_INSN_LDRHX16_S, "ldrhx16.s", "ldrh", 16,
1144 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1145 },
1146 /* ldrh $rd,[$rn],$rm */
1147 {
1148 EPIPHANY_INSN_LDRHP16_S, "ldrhp16.s", "ldrh", 16,
1149 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1150 },
1151 /* ldrh $rd6,[$rn6,$direction$rm6] */
1152 {
1153 EPIPHANY_INSN_LDRHX_L, "ldrhx.l", "ldrh", 32,
1154 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1155 },
1156 /* ldrh $rd6,[$rn6],$direction$rm6 */
1157 {
1158 EPIPHANY_INSN_LDRHP_L, "ldrhp.l", "ldrh", 32,
1159 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1160 },
1161 /* ldrh $rd,[$rn,$disp3] */
1162 {
1163 EPIPHANY_INSN_LDRHD16_S, "ldrhd16.s", "ldrh", 16,
1164 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1165 },
1166 /* ldrh $rd6,[$rn6,$dpmi$disp11] */
1167 {
1168 EPIPHANY_INSN_LDRHD_L, "ldrhd.l", "ldrh", 32,
1169 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1170 },
1171 /* ldrh $rd6,[$rn6],$dpmi$disp11 */
1172 {
1173 EPIPHANY_INSN_LDRHDPM_L, "ldrhdpm.l", "ldrh", 32,
1174 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1175 },
1176 /* ldr $rd,[$rn,$rm] */
1177 {
1178 EPIPHANY_INSN_LDRX16_S, "ldrx16.s", "ldr", 16,
1179 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1180 },
1181 /* ldr $rd,[$rn],$rm */
1182 {
1183 EPIPHANY_INSN_LDRP16_S, "ldrp16.s", "ldr", 16,
1184 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1185 },
1186 /* ldr $rd6,[$rn6,$direction$rm6] */
1187 {
1188 EPIPHANY_INSN_LDRX_L, "ldrx.l", "ldr", 32,
1189 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1190 },
1191 /* ldr $rd6,[$rn6],$direction$rm6 */
1192 {
1193 EPIPHANY_INSN_LDRP_L, "ldrp.l", "ldr", 32,
1194 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1195 },
1196 /* ldr $rd,[$rn,$disp3] */
1197 {
1198 EPIPHANY_INSN_LDRD16_S, "ldrd16.s", "ldr", 16,
1199 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1200 },
1201 /* ldr $rd6,[$rn6,$dpmi$disp11] */
1202 {
1203 EPIPHANY_INSN_LDRD_L, "ldrd.l", "ldr", 32,
1204 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1205 },
1206 /* ldr $rd6,[$rn6],$dpmi$disp11 */
1207 {
1208 EPIPHANY_INSN_LDRDPM_L, "ldrdpm.l", "ldr", 32,
1209 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1210 },
1211 /* ldrd $rd,[$rn,$rm] */
1212 {
1213 EPIPHANY_INSN_LDRDX16_S, "ldrdx16.s", "ldrd", 16,
1214 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1215 },
1216 /* ldrd $rd,[$rn],$rm */
1217 {
1218 EPIPHANY_INSN_LDRDP16_S, "ldrdp16.s", "ldrd", 16,
1219 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1220 },
1221 /* ldrd $rd6,[$rn6,$direction$rm6] */
1222 {
1223 EPIPHANY_INSN_LDRDX_L, "ldrdx.l", "ldrd", 32,
1224 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1225 },
1226 /* ldrd $rd6,[$rn6],$direction$rm6 */
1227 {
1228 EPIPHANY_INSN_LDRDP_L, "ldrdp.l", "ldrd", 32,
1229 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1230 },
1231 /* ldrd $rd,[$rn,$disp3] */
1232 {
1233 EPIPHANY_INSN_LDRDD16_S, "ldrdd16.s", "ldrd", 16,
1234 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1235 },
1236 /* ldrd $rd6,[$rn6,$dpmi$disp11] */
1237 {
1238 EPIPHANY_INSN_LDRDD_L, "ldrdd.l", "ldrd", 32,
1239 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1240 },
1241 /* ldrd $rd6,[$rn6],$dpmi$disp11 */
1242 {
1243 EPIPHANY_INSN_LDRDDPM_L, "ldrddpm.l", "ldrd", 32,
1244 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1245 },
1246 /* testsetb $rd6,[$rn6,$direction$rm6] */
1247 {
1248 EPIPHANY_INSN_TESTSETBT, "testsetbt", "testsetb", 32,
1249 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1250 },
1251 /* testseth $rd6,[$rn6,$direction$rm6] */
1252 {
1253 EPIPHANY_INSN_TESTSETHT, "testsetht", "testseth", 32,
1254 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1255 },
1256 /* testset $rd6,[$rn6,$direction$rm6] */
1257 {
1258 EPIPHANY_INSN_TESTSETT, "testsett", "testset", 32,
1259 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1260 },
1261 /* strb $rd,[$rn,$rm] */
1262 {
1263 EPIPHANY_INSN_STRBX16, "strbx16", "strb", 16,
1264 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1265 },
1266 /* strb $rd6,[$rn6,$direction$rm6] */
1267 {
1268 EPIPHANY_INSN_STRBX, "strbx", "strb", 32,
1269 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1270 },
1271 /* strb $rd,[$rn],$rm */
1272 {
1273 EPIPHANY_INSN_STRBP16, "strbp16", "strb", 16,
1274 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1275 },
1276 /* strb $rd6,[$rn6],$direction$rm6 */
1277 {
1278 EPIPHANY_INSN_STRBP, "strbp", "strb", 32,
1279 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1280 },
1281 /* strb $rd,[$rn,$disp3] */
1282 {
1283 EPIPHANY_INSN_STRBD16, "strbd16", "strb", 16,
1284 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1285 },
1286 /* strb $rd6,[$rn6,$dpmi$disp11] */
1287 {
1288 EPIPHANY_INSN_STRBD, "strbd", "strb", 32,
1289 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1290 },
1291 /* strb $rd6,[$rn6],$dpmi$disp11 */
1292 {
1293 EPIPHANY_INSN_STRBDPM, "strbdpm", "strb", 32,
1294 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1295 },
1296 /* strh $rd,[$rn,$rm] */
1297 {
1298 EPIPHANY_INSN_STRHX16, "strhx16", "strh", 16,
1299 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1300 },
1301 /* strh $rd6,[$rn6,$direction$rm6] */
1302 {
1303 EPIPHANY_INSN_STRHX, "strhx", "strh", 32,
1304 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1305 },
1306 /* strh $rd,[$rn],$rm */
1307 {
1308 EPIPHANY_INSN_STRHP16, "strhp16", "strh", 16,
1309 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1310 },
1311 /* strh $rd6,[$rn6],$direction$rm6 */
1312 {
1313 EPIPHANY_INSN_STRHP, "strhp", "strh", 32,
1314 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1315 },
1316 /* strh $rd,[$rn,$disp3] */
1317 {
1318 EPIPHANY_INSN_STRHD16, "strhd16", "strh", 16,
1319 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1320 },
1321 /* strh $rd6,[$rn6,$dpmi$disp11] */
1322 {
1323 EPIPHANY_INSN_STRHD, "strhd", "strh", 32,
1324 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1325 },
1326 /* strh $rd6,[$rn6],$dpmi$disp11 */
1327 {
1328 EPIPHANY_INSN_STRHDPM, "strhdpm", "strh", 32,
1329 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1330 },
1331 /* str $rd,[$rn,$rm] */
1332 {
1333 EPIPHANY_INSN_STRX16, "strx16", "str", 16,
1334 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1335 },
1336 /* str $rd6,[$rn6,$direction$rm6] */
1337 {
1338 EPIPHANY_INSN_STRX, "strx", "str", 32,
1339 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1340 },
1341 /* str $rd,[$rn],$rm */
1342 {
1343 EPIPHANY_INSN_STRP16, "strp16", "str", 16,
1344 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1345 },
1346 /* str $rd6,[$rn6],$direction$rm6 */
1347 {
1348 EPIPHANY_INSN_STRP, "strp", "str", 32,
1349 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1350 },
1351 /* str $rd,[$rn,$disp3] */
1352 {
1353 EPIPHANY_INSN_STRD16, "strd16", "str", 16,
1354 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1355 },
1356 /* str $rd6,[$rn6,$dpmi$disp11] */
1357 {
1358 EPIPHANY_INSN_STRD, "strd", "str", 32,
1359 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1360 },
1361 /* str $rd6,[$rn6],$dpmi$disp11 */
1362 {
1363 EPIPHANY_INSN_STRDPM, "strdpm", "str", 32,
1364 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1365 },
1366 /* strd $rd,[$rn,$rm] */
1367 {
1368 EPIPHANY_INSN_STRDX16, "strdx16", "strd", 16,
1369 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1370 },
1371 /* strd $rd6,[$rn6,$direction$rm6] */
1372 {
1373 EPIPHANY_INSN_STRDX, "strdx", "strd", 32,
1374 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1375 },
1376 /* strd $rd,[$rn],$rm */
1377 {
1378 EPIPHANY_INSN_STRDP16, "strdp16", "strd", 16,
1379 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1380 },
1381 /* strd $rd6,[$rn6],$direction$rm6 */
1382 {
1383 EPIPHANY_INSN_STRDP, "strdp", "strd", 32,
1384 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1385 },
1386 /* strd $rd,[$rn,$disp3] */
1387 {
1388 EPIPHANY_INSN_STRDD16, "strdd16", "strd", 16,
1389 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1390 },
1391 /* strd $rd6,[$rn6,$dpmi$disp11] */
1392 {
1393 EPIPHANY_INSN_STRDD, "strdd", "strd", 32,
1394 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1395 },
1396 /* strd $rd6,[$rn6],$dpmi$disp11 */
1397 {
1398 EPIPHANY_INSN_STRDDPM, "strddpm", "strd", 32,
1399 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1400 },
1401 /* moveq $rd,$rn */
1402 {
1403 EPIPHANY_INSN_CMOV16EQ, "cmov16EQ", "moveq", 16,
1404 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1405 },
1406 /* moveq $rd6,$rn6 */
1407 {
1408 EPIPHANY_INSN_CMOVEQ, "cmovEQ", "moveq", 32,
1409 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1410 },
1411 /* movne $rd,$rn */
1412 {
1413 EPIPHANY_INSN_CMOV16NE, "cmov16NE", "movne", 16,
1414 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1415 },
1416 /* movne $rd6,$rn6 */
1417 {
1418 EPIPHANY_INSN_CMOVNE, "cmovNE", "movne", 32,
1419 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1420 },
1421 /* movgtu $rd,$rn */
1422 {
1423 EPIPHANY_INSN_CMOV16GTU, "cmov16GTU", "movgtu", 16,
1424 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1425 },
1426 /* movgtu $rd6,$rn6 */
1427 {
1428 EPIPHANY_INSN_CMOVGTU, "cmovGTU", "movgtu", 32,
1429 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1430 },
1431 /* movgteu $rd,$rn */
1432 {
1433 EPIPHANY_INSN_CMOV16GTEU, "cmov16GTEU", "movgteu", 16,
1434 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1435 },
1436 /* movgteu $rd6,$rn6 */
1437 {
1438 EPIPHANY_INSN_CMOVGTEU, "cmovGTEU", "movgteu", 32,
1439 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1440 },
1441 /* movlteu $rd,$rn */
1442 {
1443 EPIPHANY_INSN_CMOV16LTEU, "cmov16LTEU", "movlteu", 16,
1444 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1445 },
1446 /* movlteu $rd6,$rn6 */
1447 {
1448 EPIPHANY_INSN_CMOVLTEU, "cmovLTEU", "movlteu", 32,
1449 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1450 },
1451 /* movltu $rd,$rn */
1452 {
1453 EPIPHANY_INSN_CMOV16LTU, "cmov16LTU", "movltu", 16,
1454 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1455 },
1456 /* movltu $rd6,$rn6 */
1457 {
1458 EPIPHANY_INSN_CMOVLTU, "cmovLTU", "movltu", 32,
1459 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1460 },
1461 /* movgt $rd,$rn */
1462 {
1463 EPIPHANY_INSN_CMOV16GT, "cmov16GT", "movgt", 16,
1464 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1465 },
1466 /* movgt $rd6,$rn6 */
1467 {
1468 EPIPHANY_INSN_CMOVGT, "cmovGT", "movgt", 32,
1469 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1470 },
1471 /* movgte $rd,$rn */
1472 {
1473 EPIPHANY_INSN_CMOV16GTE, "cmov16GTE", "movgte", 16,
1474 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1475 },
1476 /* movgte $rd6,$rn6 */
1477 {
1478 EPIPHANY_INSN_CMOVGTE, "cmovGTE", "movgte", 32,
1479 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1480 },
1481 /* movlt $rd,$rn */
1482 {
1483 EPIPHANY_INSN_CMOV16LT, "cmov16LT", "movlt", 16,
1484 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1485 },
1486 /* movlt $rd6,$rn6 */
1487 {
1488 EPIPHANY_INSN_CMOVLT, "cmovLT", "movlt", 32,
1489 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1490 },
1491 /* movlte $rd,$rn */
1492 {
1493 EPIPHANY_INSN_CMOV16LTE, "cmov16LTE", "movlte", 16,
1494 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1495 },
1496 /* movlte $rd6,$rn6 */
1497 {
1498 EPIPHANY_INSN_CMOVLTE, "cmovLTE", "movlte", 32,
1499 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1500 },
1501 /* mov $rd,$rn */
1502 {
1503 EPIPHANY_INSN_CMOV16B, "cmov16B", "mov", 16,
1504 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1505 },
1506 /* mov $rd6,$rn6 */
1507 {
1508 EPIPHANY_INSN_CMOVB, "cmovB", "mov", 32,
1509 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1510 },
1511 /* movbeq $rd,$rn */
1512 {
1513 EPIPHANY_INSN_CMOV16BEQ, "cmov16BEQ", "movbeq", 16,
1514 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1515 },
1516 /* movbeq $rd6,$rn6 */
1517 {
1518 EPIPHANY_INSN_CMOVBEQ, "cmovBEQ", "movbeq", 32,
1519 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1520 },
1521 /* movbne $rd,$rn */
1522 {
1523 EPIPHANY_INSN_CMOV16BNE, "cmov16BNE", "movbne", 16,
1524 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1525 },
1526 /* movbne $rd6,$rn6 */
1527 {
1528 EPIPHANY_INSN_CMOVBNE, "cmovBNE", "movbne", 32,
1529 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1530 },
1531 /* movblt $rd,$rn */
1532 {
1533 EPIPHANY_INSN_CMOV16BLT, "cmov16BLT", "movblt", 16,
1534 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1535 },
1536 /* movblt $rd6,$rn6 */
1537 {
1538 EPIPHANY_INSN_CMOVBLT, "cmovBLT", "movblt", 32,
1539 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1540 },
1541 /* movblte $rd,$rn */
1542 {
1543 EPIPHANY_INSN_CMOV16BLTE, "cmov16BLTE", "movblte", 16,
1544 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1545 },
1546 /* movblte $rd6,$rn6 */
1547 {
1548 EPIPHANY_INSN_CMOVBLTE, "cmovBLTE", "movblte", 32,
1549 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1550 },
1551 /* movts $sn,$rd */
1552 {
1553 EPIPHANY_INSN_MOVTS16, "movts16", "movts", 16,
1554 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1555 },
1556 /* movts $sn6,$rd6 */
1557 {
1558 EPIPHANY_INSN_MOVTS6, "movts6", "movts", 32,
1559 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1560 },
1561 /* movts $sndma,$rd6 */
1562 {
1563 EPIPHANY_INSN_MOVTSDMA, "movtsdma", "movts", 32,
1564 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1565 },
1566 /* movts $snmem,$rd6 */
1567 {
1568 EPIPHANY_INSN_MOVTSMEM, "movtsmem", "movts", 32,
1569 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1570 },
1571 /* movts $snmesh,$rd6 */
1572 {
1573 EPIPHANY_INSN_MOVTSMESH, "movtsmesh", "movts", 32,
1574 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1575 },
1576 /* movfs $rd,$sn */
1577 {
1578 EPIPHANY_INSN_MOVFS16, "movfs16", "movfs", 16,
1579 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1580 },
1581 /* movfs $rd6,$sn6 */
1582 {
1583 EPIPHANY_INSN_MOVFS6, "movfs6", "movfs", 32,
1584 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1585 },
1586 /* movfs $rd6,$sndma */
1587 {
1588 EPIPHANY_INSN_MOVFSDMA, "movfsdma", "movfs", 32,
1589 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1590 },
1591 /* movfs $rd6,$snmem */
1592 {
1593 EPIPHANY_INSN_MOVFSMEM, "movfsmem", "movfs", 32,
1594 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1595 },
1596 /* movfs $rd6,$snmesh */
1597 {
1598 EPIPHANY_INSN_MOVFSMESH, "movfsmesh", "movfs", 32,
1599 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1600 },
1601 /* nop */
1602 {
1603 EPIPHANY_INSN_NOP, "nop", "nop", 16,
1604 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1605 },
1606 /* snop */
1607 {
1608 EPIPHANY_INSN_SNOP, "snop", "snop", 16,
1609 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1610 },
1611 /* unimpl */
1612 {
1613 EPIPHANY_INSN_UNIMPL, "unimpl", "unimpl", 32,
1614 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1615 },
1616 /* idle */
1617 {
1618 EPIPHANY_INSN_IDLE, "idle", "idle", 16,
1619 { 0, { { { (1<<MACH_BASE), 0 } } } }
1620 },
1621 /* bkpt */
1622 {
1623 EPIPHANY_INSN_BKPT, "bkpt", "bkpt", 16,
1624 { 0|A(SHORT_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1625 },
1626 /* mbkpt */
1627 {
1628 EPIPHANY_INSN_MBKPT, "mbkpt", "mbkpt", 16,
1629 { 0|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } }
1630 },
1631 /* rti */
1632 {
1633 EPIPHANY_INSN_RTI, "rti", "rti", 16,
1634 { 0|A(UNCOND_CTI)|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } }
1635 },
1636 /* wand */
1637 {
1638 EPIPHANY_INSN_WAND, "wand", "wand", 16,
1639 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1640 },
1641 /* sync */
1642 {
1643 EPIPHANY_INSN_SYNC, "sync", "sync", 16,
1644 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1645 },
1646 /* gie */
1647 {
1648 EPIPHANY_INSN_GIEN, "gien", "gie", 16,
1649 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1650 },
1651 /* gid */
1652 {
1653 EPIPHANY_INSN_GIDIS, "gidis", "gid", 16,
1654 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1655 },
1656 /* swi $swi_num */
1657 {
1658 EPIPHANY_INSN_SWI_NUM, "swi_num", "swi", 16,
1659 { 0|A(UNCOND_CTI)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1660 },
1661 /* swi */
1662 {
1663 -1, "swi", "swi", 16,
1664 { 0|A(UNCOND_CTI)|A(SHORT_INSN)|A(ALIAS)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1665 },
1666 /* trap $trapnum6 */
1667 {
1668 EPIPHANY_INSN_TRAP16, "trap16", "trap", 16,
1669 { 0|A(UNCOND_CTI)|A(SHORT_INSN), { { { (1<<MACH_BASE), 0 } } } }
1670 },
1671 /* add $rd,$rn,$rm */
1672 {
1673 EPIPHANY_INSN_ADD16, "add16", "add", 16,
1674 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1675 },
1676 /* add $rd6,$rn6,$rm6 */
1677 {
1678 EPIPHANY_INSN_ADD, "add", "add", 32,
1679 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1680 },
1681 /* sub $rd,$rn,$rm */
1682 {
1683 EPIPHANY_INSN_SUB16, "sub16", "sub", 16,
1684 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1685 },
1686 /* sub $rd6,$rn6,$rm6 */
1687 {
1688 EPIPHANY_INSN_SUB, "sub", "sub", 32,
1689 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1690 },
1691 /* and $rd,$rn,$rm */
1692 {
1693 EPIPHANY_INSN_AND16, "and16", "and", 16,
1694 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1695 },
1696 /* and $rd6,$rn6,$rm6 */
1697 {
1698 EPIPHANY_INSN_AND, "and", "and", 32,
1699 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1700 },
1701 /* orr $rd,$rn,$rm */
1702 {
1703 EPIPHANY_INSN_ORR16, "orr16", "orr", 16,
1704 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1705 },
1706 /* orr $rd6,$rn6,$rm6 */
1707 {
1708 EPIPHANY_INSN_ORR, "orr", "orr", 32,
1709 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1710 },
1711 /* eor $rd,$rn,$rm */
1712 {
1713 EPIPHANY_INSN_EOR16, "eor16", "eor", 16,
1714 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1715 },
1716 /* eor $rd6,$rn6,$rm6 */
1717 {
1718 EPIPHANY_INSN_EOR, "eor", "eor", 32,
1719 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1720 },
1721 /* add.s $rd,$rn,$simm3 */
1722 {
1723 EPIPHANY_INSN_ADDI16, "addi16", "add.s", 16,
1724 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1725 },
1726 /* add.l $rd6,$rn6,$simm11 */
1727 {
1728 EPIPHANY_INSN_ADDI, "addi", "add.l", 32,
1729 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1730 },
1731 /* sub.s $rd,$rn,$simm3 */
1732 {
1733 EPIPHANY_INSN_SUBI16, "subi16", "sub.s", 16,
1734 { 0|A(IMM3)|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1735 },
1736 /* sub.l $rd6,$rn6,$simm11 */
1737 {
1738 EPIPHANY_INSN_SUBI, "subi", "sub.l", 32,
1739 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1740 },
1741 /* asr $rd,$rn,$rm */
1742 {
1743 EPIPHANY_INSN_ASR16, "asr16", "asr", 16,
1744 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1745 },
1746 /* asr $rd6,$rn6,$rm6 */
1747 {
1748 EPIPHANY_INSN_ASR, "asr", "asr", 32,
1749 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1750 },
1751 /* lsr $rd,$rn,$rm */
1752 {
1753 EPIPHANY_INSN_LSR16, "lsr16", "lsr", 16,
1754 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1755 },
1756 /* lsr $rd6,$rn6,$rm6 */
1757 {
1758 EPIPHANY_INSN_LSR, "lsr", "lsr", 32,
1759 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1760 },
1761 /* lsl $rd,$rn,$rm */
1762 {
1763 EPIPHANY_INSN_LSL16, "lsl16", "lsl", 16,
1764 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1765 },
1766 /* lsl $rd6,$rn6,$rm6 */
1767 {
1768 EPIPHANY_INSN_LSL, "lsl", "lsl", 32,
1769 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1770 },
1771 /* lsr $rd,$rn,$shift */
1772 {
1773 EPIPHANY_INSN_LSRI16, "lsri16", "lsr", 16,
1774 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1775 },
1776 /* lsr $rd6,$rn6,$shift */
1777 {
1778 EPIPHANY_INSN_LSRI32, "lsri32", "lsr", 32,
1779 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1780 },
1781 /* lsl $rd,$rn,$shift */
1782 {
1783 EPIPHANY_INSN_LSLI16, "lsli16", "lsl", 16,
1784 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1785 },
1786 /* lsl $rd6,$rn6,$shift */
1787 {
1788 EPIPHANY_INSN_LSLI32, "lsli32", "lsl", 32,
1789 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1790 },
1791 /* asr $rd,$rn,$shift */
1792 {
1793 EPIPHANY_INSN_ASRI16, "asri16", "asr", 16,
1794 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1795 },
1796 /* asr $rd6,$rn6,$shift */
1797 {
1798 EPIPHANY_INSN_ASRI32, "asri32", "asr", 32,
1799 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1800 },
1801 /* bitr $rd,$rn */
1802 {
1803 EPIPHANY_INSN_BITR16, "bitr16", "bitr", 16,
1804 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1805 },
1806 /* bitr $rd6,$rn6 */
1807 {
1808 EPIPHANY_INSN_BITR, "bitr", "bitr", 32,
1809 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1810 },
1811 /* fext $rd6,$rn6,$rm6 */
1812 {
1813 EPIPHANY_INSN_FEXT, "fext", "fext", 32,
1814 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1815 },
1816 /* fdep $rd6,$rn6,$rm6 */
1817 {
1818 EPIPHANY_INSN_FDEP, "fdep", "fdep", 32,
1819 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1820 },
1821 /* lfsr $rd6,$rn6,$rm6 */
1822 {
1823 EPIPHANY_INSN_LFSR, "lfsr", "lfsr", 32,
1824 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1825 },
1826 /* mov.b $rd,$imm8 */
1827 {
1828 EPIPHANY_INSN_MOV8, "mov8", "mov.b", 16,
1829 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1830 },
1831 /* mov.l $rd6,$imm16 */
1832 {
1833 EPIPHANY_INSN_MOV16, "mov16", "mov.l", 32,
1834 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1835 },
1836 /* movt $rd6,$imm16 */
1837 {
1838 EPIPHANY_INSN_MOVT, "movt", "movt", 32,
1839 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1840 },
1841 /* fadd $rd,$rn,$rm */
1842 {
1843 EPIPHANY_INSN_F_ADDF16, "f_addf16", "fadd", 16,
1844 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1845 },
1846 /* fadd $rd6,$rn6,$rm6 */
1847 {
1848 EPIPHANY_INSN_F_ADDF32, "f_addf32", "fadd", 32,
1849 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1850 },
1851 /* fsub $rd,$rn,$rm */
1852 {
1853 EPIPHANY_INSN_F_SUBF16, "f_subf16", "fsub", 16,
1854 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1855 },
1856 /* fsub $rd6,$rn6,$rm6 */
1857 {
1858 EPIPHANY_INSN_F_SUBF32, "f_subf32", "fsub", 32,
1859 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1860 },
1861 /* fmul $rd,$rn,$rm */
1862 {
1863 EPIPHANY_INSN_F_MULF16, "f_mulf16", "fmul", 16,
1864 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1865 },
1866 /* fmul $rd6,$rn6,$rm6 */
1867 {
1868 EPIPHANY_INSN_F_MULF32, "f_mulf32", "fmul", 32,
1869 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1870 },
1871 /* fmadd $rd,$rn,$rm */
1872 {
1873 EPIPHANY_INSN_F_MADDF16, "f_maddf16", "fmadd", 16,
1874 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1875 },
1876 /* fmadd $rd6,$rn6,$rm6 */
1877 {
1878 EPIPHANY_INSN_F_MADDF32, "f_maddf32", "fmadd", 32,
1879 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1880 },
1881 /* fmsub $rd,$rn,$rm */
1882 {
1883 EPIPHANY_INSN_F_MSUBF16, "f_msubf16", "fmsub", 16,
1884 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1885 },
1886 /* fmsub $rd6,$rn6,$rm6 */
1887 {
1888 EPIPHANY_INSN_F_MSUBF32, "f_msubf32", "fmsub", 32,
1889 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1890 },
1891 /* fabs rd,rn */
1892 {
1893 EPIPHANY_INSN_F_ABSF16, "f_absf16", "fabs", 16,
1894 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1895 },
1896 /* fabs $rd6,$rn6 */
1897 {
1898 EPIPHANY_INSN_F_ABSF32, "f_absf32", "fabs", 32,
1899 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1900 },
1901 /* float $rd,$rn */
1902 {
1903 EPIPHANY_INSN_F_LOATF16, "f_loatf16", "float", 16,
1904 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1905 },
1906 /* float $rd6,$rn6 */
1907 {
1908 EPIPHANY_INSN_F_LOATF32, "f_loatf32", "float", 32,
1909 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1910 },
1911 /* fix $rd,$rn */
1912 {
1913 EPIPHANY_INSN_F_IXF16, "f_ixf16", "fix", 16,
1914 { 0|A(SHORT_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1915 },
1916 /* fix $rd6,$rn6 */
1917 {
1918 EPIPHANY_INSN_F_IXF32, "f_ixf32", "fix", 32,
1919 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1920 },
1921 /* frecip $frd6,$frn6 */
1922 {
1923 EPIPHANY_INSN_F_RECIPF32, "f_recipf32", "frecip", 32,
1924 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1925 },
1926 /* fsqrt $frd6,$frn6 */
1927 {
1928 EPIPHANY_INSN_F_SQRTF32, "f_sqrtf32", "fsqrt", 32,
1929 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
1930 },
1931 };
1932
1933 #undef OP
1934 #undef A
1935
1936 /* Initialize anything needed to be done once, before any cpu_open call. */
1937
1938 static void
init_tables(void)1939 init_tables (void)
1940 {
1941 }
1942
1943 #ifndef opcodes_error_handler
1944 #define opcodes_error_handler(...) \
1945 fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
1946 #endif
1947
1948 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1949 static void build_hw_table (CGEN_CPU_TABLE *);
1950 static void build_ifield_table (CGEN_CPU_TABLE *);
1951 static void build_operand_table (CGEN_CPU_TABLE *);
1952 static void build_insn_table (CGEN_CPU_TABLE *);
1953 static void epiphany_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1954
1955 /* Subroutine of epiphany_cgen_cpu_open to look up a mach via its bfd name. */
1956
1957 static const CGEN_MACH *
lookup_mach_via_bfd_name(const CGEN_MACH * table,const char * name)1958 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1959 {
1960 while (table->name)
1961 {
1962 if (strcmp (name, table->bfd_name) == 0)
1963 return table;
1964 ++table;
1965 }
1966 return NULL;
1967 }
1968
1969 /* Subroutine of epiphany_cgen_cpu_open to build the hardware table. */
1970
1971 static void
build_hw_table(CGEN_CPU_TABLE * cd)1972 build_hw_table (CGEN_CPU_TABLE *cd)
1973 {
1974 int i;
1975 int machs = cd->machs;
1976 const CGEN_HW_ENTRY *init = & epiphany_cgen_hw_table[0];
1977 /* MAX_HW is only an upper bound on the number of selected entries.
1978 However each entry is indexed by it's enum so there can be holes in
1979 the table. */
1980 const CGEN_HW_ENTRY **selected =
1981 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1982
1983 cd->hw_table.init_entries = init;
1984 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1985 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1986 /* ??? For now we just use machs to determine which ones we want. */
1987 for (i = 0; init[i].name != NULL; ++i)
1988 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1989 & machs)
1990 selected[init[i].type] = &init[i];
1991 cd->hw_table.entries = selected;
1992 cd->hw_table.num_entries = MAX_HW;
1993 }
1994
1995 /* Subroutine of epiphany_cgen_cpu_open to build the hardware table. */
1996
1997 static void
build_ifield_table(CGEN_CPU_TABLE * cd)1998 build_ifield_table (CGEN_CPU_TABLE *cd)
1999 {
2000 cd->ifld_table = & epiphany_cgen_ifld_table[0];
2001 }
2002
2003 /* Subroutine of epiphany_cgen_cpu_open to build the hardware table. */
2004
2005 static void
build_operand_table(CGEN_CPU_TABLE * cd)2006 build_operand_table (CGEN_CPU_TABLE *cd)
2007 {
2008 int i;
2009 int machs = cd->machs;
2010 const CGEN_OPERAND *init = & epiphany_cgen_operand_table[0];
2011 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
2012 However each entry is indexed by it's enum so there can be holes in
2013 the table. */
2014 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
2015
2016 cd->operand_table.init_entries = init;
2017 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
2018 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
2019 /* ??? For now we just use mach to determine which ones we want. */
2020 for (i = 0; init[i].name != NULL; ++i)
2021 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
2022 & machs)
2023 selected[init[i].type] = &init[i];
2024 cd->operand_table.entries = selected;
2025 cd->operand_table.num_entries = MAX_OPERANDS;
2026 }
2027
2028 /* Subroutine of epiphany_cgen_cpu_open to build the hardware table.
2029 ??? This could leave out insns not supported by the specified mach/isa,
2030 but that would cause errors like "foo only supported by bar" to become
2031 "unknown insn", so for now we include all insns and require the app to
2032 do the checking later.
2033 ??? On the other hand, parsing of such insns may require their hardware or
2034 operand elements to be in the table [which they mightn't be]. */
2035
2036 static void
build_insn_table(CGEN_CPU_TABLE * cd)2037 build_insn_table (CGEN_CPU_TABLE *cd)
2038 {
2039 int i;
2040 const CGEN_IBASE *ib = & epiphany_cgen_insn_table[0];
2041 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
2042
2043 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
2044 for (i = 0; i < MAX_INSNS; ++i)
2045 insns[i].base = &ib[i];
2046 cd->insn_table.init_entries = insns;
2047 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
2048 cd->insn_table.num_init_entries = MAX_INSNS;
2049 }
2050
2051 /* Subroutine of epiphany_cgen_cpu_open to rebuild the tables. */
2052
2053 static void
epiphany_cgen_rebuild_tables(CGEN_CPU_TABLE * cd)2054 epiphany_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
2055 {
2056 int i;
2057 CGEN_BITSET *isas = cd->isas;
2058 unsigned int machs = cd->machs;
2059
2060 cd->int_insn_p = CGEN_INT_INSN_P;
2061
2062 /* Data derived from the isa spec. */
2063 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
2064 cd->default_insn_bitsize = UNSET;
2065 cd->base_insn_bitsize = UNSET;
2066 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
2067 cd->max_insn_bitsize = 0;
2068 for (i = 0; i < MAX_ISAS; ++i)
2069 if (cgen_bitset_contains (isas, i))
2070 {
2071 const CGEN_ISA *isa = & epiphany_cgen_isa_table[i];
2072
2073 /* Default insn sizes of all selected isas must be
2074 equal or we set the result to 0, meaning "unknown". */
2075 if (cd->default_insn_bitsize == UNSET)
2076 cd->default_insn_bitsize = isa->default_insn_bitsize;
2077 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
2078 ; /* This is ok. */
2079 else
2080 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
2081
2082 /* Base insn sizes of all selected isas must be equal
2083 or we set the result to 0, meaning "unknown". */
2084 if (cd->base_insn_bitsize == UNSET)
2085 cd->base_insn_bitsize = isa->base_insn_bitsize;
2086 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
2087 ; /* This is ok. */
2088 else
2089 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
2090
2091 /* Set min,max insn sizes. */
2092 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
2093 cd->min_insn_bitsize = isa->min_insn_bitsize;
2094 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
2095 cd->max_insn_bitsize = isa->max_insn_bitsize;
2096 }
2097
2098 /* Data derived from the mach spec. */
2099 for (i = 0; i < MAX_MACHS; ++i)
2100 if (((1 << i) & machs) != 0)
2101 {
2102 const CGEN_MACH *mach = & epiphany_cgen_mach_table[i];
2103
2104 if (mach->insn_chunk_bitsize != 0)
2105 {
2106 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
2107 {
2108 opcodes_error_handler
2109 (/* xgettext:c-format */
2110 _("internal error: epiphany_cgen_rebuild_tables: "
2111 "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
2112 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
2113 abort ();
2114 }
2115
2116 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
2117 }
2118 }
2119
2120 /* Determine which hw elements are used by MACH. */
2121 build_hw_table (cd);
2122
2123 /* Build the ifield table. */
2124 build_ifield_table (cd);
2125
2126 /* Determine which operands are used by MACH/ISA. */
2127 build_operand_table (cd);
2128
2129 /* Build the instruction table. */
2130 build_insn_table (cd);
2131 }
2132
2133 /* Initialize a cpu table and return a descriptor.
2134 It's much like opening a file, and must be the first function called.
2135 The arguments are a set of (type/value) pairs, terminated with
2136 CGEN_CPU_OPEN_END.
2137
2138 Currently supported values:
2139 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
2140 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
2141 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
2142 CGEN_CPU_OPEN_ENDIAN: specify endian choice
2143 CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice
2144 CGEN_CPU_OPEN_END: terminates arguments
2145
2146 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
2147 precluded. */
2148
2149 CGEN_CPU_DESC
epiphany_cgen_cpu_open(enum cgen_cpu_open_arg arg_type,...)2150 epiphany_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
2151 {
2152 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
2153 static int init_p;
2154 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
2155 unsigned int machs = 0; /* 0 = "unspecified" */
2156 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
2157 enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN;
2158 va_list ap;
2159
2160 if (! init_p)
2161 {
2162 init_tables ();
2163 init_p = 1;
2164 }
2165
2166 memset (cd, 0, sizeof (*cd));
2167
2168 va_start (ap, arg_type);
2169 while (arg_type != CGEN_CPU_OPEN_END)
2170 {
2171 switch (arg_type)
2172 {
2173 case CGEN_CPU_OPEN_ISAS :
2174 isas = va_arg (ap, CGEN_BITSET *);
2175 break;
2176 case CGEN_CPU_OPEN_MACHS :
2177 machs = va_arg (ap, unsigned int);
2178 break;
2179 case CGEN_CPU_OPEN_BFDMACH :
2180 {
2181 const char *name = va_arg (ap, const char *);
2182 const CGEN_MACH *mach =
2183 lookup_mach_via_bfd_name (epiphany_cgen_mach_table, name);
2184
2185 if (mach != NULL)
2186 machs |= 1 << mach->num;
2187 break;
2188 }
2189 case CGEN_CPU_OPEN_ENDIAN :
2190 endian = va_arg (ap, enum cgen_endian);
2191 break;
2192 case CGEN_CPU_OPEN_INSN_ENDIAN :
2193 insn_endian = va_arg (ap, enum cgen_endian);
2194 break;
2195 default :
2196 opcodes_error_handler
2197 (/* xgettext:c-format */
2198 _("internal error: epiphany_cgen_cpu_open: "
2199 "unsupported argument `%d'"),
2200 arg_type);
2201 abort (); /* ??? return NULL? */
2202 }
2203 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
2204 }
2205 va_end (ap);
2206
2207 /* Mach unspecified means "all". */
2208 if (machs == 0)
2209 machs = (1 << MAX_MACHS) - 1;
2210 /* Base mach is always selected. */
2211 machs |= 1;
2212 if (endian == CGEN_ENDIAN_UNKNOWN)
2213 {
2214 /* ??? If target has only one, could have a default. */
2215 opcodes_error_handler
2216 (/* xgettext:c-format */
2217 _("internal error: epiphany_cgen_cpu_open: no endianness specified"));
2218 abort ();
2219 }
2220
2221 cd->isas = cgen_bitset_copy (isas);
2222 cd->machs = machs;
2223 cd->endian = endian;
2224 cd->insn_endian
2225 = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian);
2226
2227 /* Table (re)builder. */
2228 cd->rebuild_tables = epiphany_cgen_rebuild_tables;
2229 epiphany_cgen_rebuild_tables (cd);
2230
2231 /* Default to not allowing signed overflow. */
2232 cd->signed_overflow_ok_p = 0;
2233
2234 return (CGEN_CPU_DESC) cd;
2235 }
2236
2237 /* Cover fn to epiphany_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
2238 MACH_NAME is the bfd name of the mach. */
2239
2240 CGEN_CPU_DESC
epiphany_cgen_cpu_open_1(const char * mach_name,enum cgen_endian endian)2241 epiphany_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
2242 {
2243 return epiphany_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
2244 CGEN_CPU_OPEN_ENDIAN, endian,
2245 CGEN_CPU_OPEN_END);
2246 }
2247
2248 /* Close a cpu table.
2249 ??? This can live in a machine independent file, but there's currently
2250 no place to put this file (there's no libcgen). libopcodes is the wrong
2251 place as some simulator ports use this but they don't use libopcodes. */
2252
2253 void
epiphany_cgen_cpu_close(CGEN_CPU_DESC cd)2254 epiphany_cgen_cpu_close (CGEN_CPU_DESC cd)
2255 {
2256 unsigned int i;
2257 const CGEN_INSN *insns;
2258
2259 if (cd->macro_insn_table.init_entries)
2260 {
2261 insns = cd->macro_insn_table.init_entries;
2262 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
2263 if (CGEN_INSN_RX ((insns)))
2264 regfree (CGEN_INSN_RX (insns));
2265 }
2266
2267 if (cd->insn_table.init_entries)
2268 {
2269 insns = cd->insn_table.init_entries;
2270 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
2271 if (CGEN_INSN_RX (insns))
2272 regfree (CGEN_INSN_RX (insns));
2273 }
2274
2275 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
2276 free ((CGEN_INSN *) cd->insn_table.init_entries);
2277 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
2278 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
2279 free (cd);
2280 }
2281
2282