1 /* ppc.h -- Header file for PowerPC opcode table
2 Copyright (C) 1994-2022 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
4
5 This file is part of GDB, GAS, and the GNU binutils.
6
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version 3,
10 or (at your option) any later version.
11
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING3. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
21
22 #ifndef PPC_H
23 #define PPC_H
24
25 #include <stdint.h>
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
31 typedef uint64_t ppc_cpu_t;
32 typedef uint16_t ppc_opindex_t;
33
34 /* Smaller of ppc_opindex_t and fx_pcrel_adjust maximum. Note that
35 values extracted from fx_pcrel_adjust are masked with this constant,
36 effectively making the field unsigned. */
37 #define PPC_OPINDEX_MAX 0xffff
38
39 /* The opcode table is an array of struct powerpc_opcode. */
40
41 struct powerpc_opcode
42 {
43 /* The opcode name. */
44 const char *name;
45
46 /* The opcode itself. Those bits which will be filled in with
47 operands are zeroes. */
48 uint64_t opcode;
49
50 /* The opcode mask. This is used by the disassembler. This is a
51 mask containing ones indicating those bits which must match the
52 opcode field, and zeroes indicating those bits which need not
53 match (and are presumably filled in by operands). */
54 uint64_t mask;
55
56 /* One bit flags for the opcode. These are used to indicate which
57 specific processors support the instructions. The defined values
58 are listed below. */
59 ppc_cpu_t flags;
60
61 /* One bit flags for the opcode. These are used to indicate which
62 specific processors no longer support the instructions. The defined
63 values are listed below. */
64 ppc_cpu_t deprecated;
65
66 /* An array of operand codes. Each code is an index into the
67 operand table. They appear in the order which the operands must
68 appear in assembly code, and are terminated by a zero. */
69 ppc_opindex_t operands[8];
70 };
71
72 /* The table itself is sorted by major opcode number, and is otherwise
73 in the order in which the disassembler should consider
74 instructions. */
75 extern const struct powerpc_opcode powerpc_opcodes[];
76 extern const unsigned int powerpc_num_opcodes;
77 extern const struct powerpc_opcode prefix_opcodes[];
78 extern const unsigned int prefix_num_opcodes;
79 extern const struct powerpc_opcode vle_opcodes[];
80 extern const unsigned int vle_num_opcodes;
81 extern const struct powerpc_opcode spe2_opcodes[];
82 extern const unsigned int spe2_num_opcodes;
83
84 /* Values defined for the flags field of a struct powerpc_opcode. */
85
86 /* Opcode is defined for the PowerPC architecture. */
87 #define PPC_OPCODE_PPC 0x1ull
88
89 /* Opcode is defined for the POWER (RS/6000) architecture. */
90 #define PPC_OPCODE_POWER 0x2ull
91
92 /* Opcode is defined for the POWER2 (Rios 2) architecture. */
93 #define PPC_OPCODE_POWER2 0x4ull
94
95 /* Opcode is only defined on 64 bit architectures. */
96 #define PPC_OPCODE_64 0x8ull
97
98 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
99 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
100 but it also supports many additional POWER instructions. */
101 #define PPC_OPCODE_601 0x10ull
102
103 /* Opcode is supported in both the Power and PowerPC architectures
104 (ie, compiler's -mcpu=common or assembler's -mcom). More than just
105 the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
106 and PPC_OPCODE_POWER2 because many instructions changed mnemonics
107 between POWER and POWERPC. */
108 #define PPC_OPCODE_COMMON 0x20ull
109
110 /* Opcode is supported for any Power or PowerPC platform (this is
111 for the assembler's -many option, and it eliminates duplicates). */
112 #define PPC_OPCODE_ANY 0x40ull
113
114 /* Opcode is supported as part of the 64-bit bridge. */
115 #define PPC_OPCODE_64_BRIDGE 0x80ull
116
117 /* Opcode is supported by Altivec Vector Unit */
118 #define PPC_OPCODE_ALTIVEC 0x100ull
119
120 /* Opcode is supported by PowerPC 403 processor. */
121 #define PPC_OPCODE_403 0x200ull
122
123 /* Opcode is supported by PowerPC BookE processor. */
124 #define PPC_OPCODE_BOOKE 0x400ull
125
126 /* Opcode is only supported by Power4 architecture. */
127 #define PPC_OPCODE_POWER4 0x800ull
128
129 /* Opcode is only supported by e500x2 Core.
130 This bit, PPC_OPCODE_EFS, PPC_OPCODE_VLE, and all those with APU in
131 their comment mark opcodes so that when those instructions are used
132 an APUinfo entry can be generated. */
133 #define PPC_OPCODE_SPE 0x1000ull
134
135 /* Opcode is supported by Integer select APU. */
136 #define PPC_OPCODE_ISEL 0x2000ull
137
138 /* Opcode is an e500 SPE floating point instruction. */
139 #define PPC_OPCODE_EFS 0x4000ull
140
141 /* Opcode is supported by branch locking APU. */
142 #define PPC_OPCODE_BRLOCK 0x8000ull
143
144 /* Opcode is supported by performance monitor APU. */
145 #define PPC_OPCODE_PMR 0x10000ull
146
147 /* Opcode is supported by cache locking APU. */
148 #define PPC_OPCODE_CACHELCK 0x20000ull
149
150 /* Opcode is supported by machine check APU. */
151 #define PPC_OPCODE_RFMCI 0x40000ull
152
153 /* Opcode is supported by PowerPC 440 processor. */
154 #define PPC_OPCODE_440 0x80000ull
155
156 /* Opcode is only supported by Power5 architecture. */
157 #define PPC_OPCODE_POWER5 0x100000ull
158
159 /* Opcode is supported by PowerPC e300 family. */
160 #define PPC_OPCODE_E300 0x200000ull
161
162 /* Opcode is only supported by Power6 architecture. */
163 #define PPC_OPCODE_POWER6 0x400000ull
164
165 /* Opcode is only supported by PowerPC Cell family. */
166 #define PPC_OPCODE_CELL 0x800000ull
167
168 /* Opcode is supported by CPUs with paired singles support. */
169 #define PPC_OPCODE_PPCPS 0x1000000ull
170
171 /* Opcode is supported by Power E500MC */
172 #define PPC_OPCODE_E500MC 0x2000000ull
173
174 /* Opcode is supported by PowerPC 405 processor. */
175 #define PPC_OPCODE_405 0x4000000ull
176
177 /* Opcode is supported by Vector-Scalar (VSX) Unit */
178 #define PPC_OPCODE_VSX 0x8000000ull
179
180 /* Opcode is only supported by Power7 architecture. */
181 #define PPC_OPCODE_POWER7 0x10000000ull
182
183 /* Opcode is supported by A2. */
184 #define PPC_OPCODE_A2 0x20000000ull
185
186 /* Opcode is supported by PowerPC 476 processor. */
187 #define PPC_OPCODE_476 0x40000000ull
188
189 /* Opcode is supported by AppliedMicro Titan core */
190 #define PPC_OPCODE_TITAN 0x80000000ull
191
192 /* Opcode which is supported by the e500 family */
193 #define PPC_OPCODE_E500 0x100000000ull
194
195 /* Opcode is supported by Power E6500 */
196 #define PPC_OPCODE_E6500 0x200000000ull
197
198 /* Opcode is supported by Thread management APU */
199 #define PPC_OPCODE_TMR 0x400000000ull
200
201 /* Opcode which is supported by the VLE extension. */
202 #define PPC_OPCODE_VLE 0x800000000ull
203
204 /* Opcode is only supported by Power8 architecture. */
205 #define PPC_OPCODE_POWER8 0x1000000000ull
206
207 /* Opcode is supported by ppc750cl/Gekko/Broadway. */
208 #define PPC_OPCODE_750 0x2000000000ull
209
210 /* Opcode is supported by ppc7450. */
211 #define PPC_OPCODE_7450 0x4000000000ull
212
213 /* Opcode is supported by ppc821/850/860. */
214 #define PPC_OPCODE_860 0x8000000000ull
215
216 /* Opcode is only supported by Power9 architecture. */
217 #define PPC_OPCODE_POWER9 0x10000000000ull
218
219 /* Opcode is supported by e200z4. */
220 #define PPC_OPCODE_E200Z4 0x20000000000ull
221
222 /* Disassemble to instructions matching later in the opcode table
223 with fewer "mask" bits set rather than the earlist match. Fewer
224 "mask" bits set imply a more general form of the opcode, in fact
225 the underlying machine instruction. */
226 #define PPC_OPCODE_RAW 0x40000000000ull
227
228 /* Opcode is supported by PowerPC LSP */
229 #define PPC_OPCODE_LSP 0x80000000000ull
230
231 /* Opcode is only supported by Freescale SPE2 APU. */
232 #define PPC_OPCODE_SPE2 0x100000000000ull
233
234 /* Opcode is supported by EFS2. */
235 #define PPC_OPCODE_EFS2 0x200000000000ull
236
237 /* Opcode is only supported by power10 architecture. */
238 #define PPC_OPCODE_POWER10 0x400000000000ull
239
240 /* A macro to extract the major opcode from an instruction. */
241 #define PPC_OP(i) (((i) >> 26) & 0x3f)
242
243 /* A macro to determine if the instruction is a 2-byte VLE insn. */
244 #define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
245
246 /* A macro to extract the major opcode from a VLE instruction. */
247 #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
248
249 /* A macro to convert a VLE opcode to a VLE opcode segment. */
250 #define VLE_OP_TO_SEG(i) ((i) >> 1)
251
252 /* A macro to extract the extended opcode from a SPE2 instruction. */
253 #define SPE2_XOP(i) ((i) & 0x7ff)
254
255 /* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment. */
256 #define SPE2_XOP_TO_SEG(i) ((i) >> 7)
257
258 /* A macro to extract the prefix word from an 8-byte PREFIX instruction. */
259 #define PPC_GET_PREFIX(i) (((i) >> 32) & ((1LL << 32) - 1))
260
261 /* A macro to extract the suffix word from an 8-byte PREFIX instruction. */
262 #define PPC_GET_SUFFIX(i) ((i) & ((1LL << 32) - 1))
263
264 /* A macro to determine whether insn I is an 8-byte prefix instruction. */
265 #define PPC_PREFIX_P(i) (PPC_OP (PPC_GET_PREFIX (i)) == 0x1)
266
267 /* A macro used to hash 8-byte PREFIX instructions. */
268 #define PPC_PREFIX_SEG(i) (PPC_OP (i) >> 1)
269
270
271 /* The operands table is an array of struct powerpc_operand. */
272
273 struct powerpc_operand
274 {
275 /* A bitmask of bits in the operand. */
276 uint64_t bitm;
277
278 /* The shift operation to be applied to the operand. No shift
279 is made if this is zero. For positive values, the operand
280 is shifted left by SHIFT. For negative values, the operand
281 is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
282 that BITM and SHIFT cannot be used to determine where the
283 operand goes in the insn. */
284 int shift;
285
286 /* Insertion function. This is used by the assembler. To insert an
287 operand value into an instruction, check this field.
288
289 If it is NULL, execute
290 if (o->shift >= 0)
291 i |= (op & o->bitm) << o->shift;
292 else
293 i |= (op & o->bitm) >> -o->shift;
294 (i is the instruction which we are filling in, o is a pointer to
295 this structure, and op is the operand value).
296
297 If this field is not NULL, then simply call it with the
298 instruction and the operand value. It will return the new value
299 of the instruction. If the operand value is illegal, *ERRMSG
300 will be set to a warning string (the operand will be inserted in
301 any case). If the operand value is legal, *ERRMSG will be
302 unchanged (most operands can accept any value). */
303 uint64_t (*insert)
304 (uint64_t instruction, int64_t op, ppc_cpu_t dialect, const char **errmsg);
305
306 /* Extraction function. This is used by the disassembler. To
307 extract this operand type from an instruction, check this field.
308
309 If it is NULL, compute
310 if (o->shift >= 0)
311 op = (i >> o->shift) & o->bitm;
312 else
313 op = (i << -o->shift) & o->bitm;
314 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
315 sign_extend (op);
316 (i is the instruction, o is a pointer to this structure, and op
317 is the result).
318
319 If this field is not NULL, then simply call it with the
320 instruction value. It will return the value of the operand.
321 *INVALID will be set to one by the extraction function if this
322 operand type can not be extracted from this operand (i.e., the
323 instruction does not match). If the operand is valid, *INVALID
324 will not be changed. *INVALID will always be non-negative when
325 used to extract a field from an instruction.
326
327 The extraction function is also called by both the assembler and
328 disassembler if an operand is optional, in which case the
329 function should return the default value of the operand.
330 *INVALID is negative in this case, and is the negative count of
331 omitted optional operands up to and including this operand. */
332 int64_t (*extract) (uint64_t instruction, ppc_cpu_t dialect, int *invalid);
333
334 /* One bit syntax flags. */
335 unsigned long flags;
336 };
337
338 /* Elements in the table are retrieved by indexing with values from
339 the operands field of the powerpc_opcodes table. */
340
341 extern const struct powerpc_operand powerpc_operands[];
342 extern const unsigned int num_powerpc_operands;
343
344 /* Use with the shift field of a struct powerpc_operand to indicate
345 that BITM and SHIFT cannot be used to determine where the operand
346 goes in the insn. */
347 #define PPC_OPSHIFT_INV (1U << 30)
348 /* A special case, 6-bit SH field. */
349 #define PPC_OPSHIFT_SH6 (2U << 30)
350
351 /* Values defined for the flags field of a struct powerpc_operand.
352 Keep the register bits low: They need to fit in an unsigned short. */
353
354 /* This operand names a register. The disassembler uses this to print
355 register names with a leading 'r'. */
356 #define PPC_OPERAND_GPR (0x1)
357
358 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
359 #define PPC_OPERAND_GPR_0 (0x2)
360
361 /* This operand names a floating point register. The disassembler
362 prints these with a leading 'f'. */
363 #define PPC_OPERAND_FPR (0x4)
364
365 /* This operand names a vector unit register. The disassembler
366 prints these with a leading 'v'. */
367 #define PPC_OPERAND_VR (0x8)
368
369 /* This operand names a vector-scalar unit register. The disassembler
370 prints these with a leading 'vs'. */
371 #define PPC_OPERAND_VSR (0x10)
372
373 /* This operand names a VSX accumulator. */
374 #define PPC_OPERAND_ACC (0x20)
375
376 /* This operand may use the symbolic names for the CR fields (even
377 without -mregnames), which are
378 lt 0 gt 1 eq 2 so 3 un 3
379 cr0 0 cr1 1 cr2 2 cr3 3
380 cr4 4 cr5 5 cr6 6 cr7 7
381 These may be combined arithmetically, as in cr2*4+gt. These are
382 only supported on the PowerPC, not the POWER. */
383 #define PPC_OPERAND_CR_BIT (0x40)
384
385 /* This is a CR FIELD that does not use symbolic names (unless
386 -mregnames is in effect). If both PPC_OPERAND_CR_BIT and
387 PPC_OPERAND_CR_REG are set then treat the field as per
388 PPC_OPERAND_CR_BIT for assembly, but as if neither of these
389 bits are set for disassembly. */
390 #define PPC_OPERAND_CR_REG (0x80)
391
392 /* This operand names a special purpose register. */
393 #define PPC_OPERAND_SPR (0x100)
394
395 /* This operand names a paired-single graphics quantization register. */
396 #define PPC_OPERAND_GQR (0x200)
397
398 /* This operand is a relative branch displacement. The disassembler
399 prints these symbolically if possible. */
400 #define PPC_OPERAND_RELATIVE (0x400)
401
402 /* This operand is an absolute branch address. The disassembler
403 prints these symbolically if possible. */
404 #define PPC_OPERAND_ABSOLUTE (0x800)
405
406 /* This operand takes signed values. */
407 #define PPC_OPERAND_SIGNED (0x1000)
408
409 /* This operand takes signed values, but also accepts a full positive
410 range of values when running in 32 bit mode. That is, if bits is
411 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
412 this flag is ignored. */
413 #define PPC_OPERAND_SIGNOPT (0x2000)
414
415 /* The next operand should be wrapped in parentheses rather than
416 separated from this one by a comma. This is used for the load and
417 store instructions which want their operands to look like
418 reg,displacement(reg)
419 */
420 #define PPC_OPERAND_PARENS (0x4000)
421
422 /* This operand is for the DS field in a DS form instruction. */
423 #define PPC_OPERAND_DS (0x8000)
424
425 /* This operand is for the DQ field in a DQ form instruction. */
426 #define PPC_OPERAND_DQ (0x10000)
427
428 /* This operand should be regarded as a negative number for the
429 purposes of overflow checking (i.e., the normal most negative
430 number is disallowed and one more than the normal most positive
431 number is allowed). This flag will only be set for a signed
432 operand. */
433 #define PPC_OPERAND_NEGATIVE (0x20000)
434
435 /* Valid range of operand is 0..n rather than 0..n-1. */
436 #define PPC_OPERAND_PLUS1 (0x40000)
437
438 /* This operand is optional, and is zero if omitted. This is used for
439 example, in the optional BF field in the comparison instructions. The
440 assembler must count the number of operands remaining on the line,
441 and the number of operands remaining for the opcode, and decide
442 whether this operand is present or not. The disassembler should
443 print this operand out only if it is not zero. */
444 #define PPC_OPERAND_OPTIONAL (0x80000)
445
446 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
447 is omitted, then for the next operand use this operand value plus
448 1, ignoring the next operand field for the opcode. This wretched
449 hack is needed because the Power rotate instructions can take
450 either 4 or 5 operands. The disassembler should print this operand
451 out regardless of the PPC_OPERAND_OPTIONAL field. */
452 #define PPC_OPERAND_NEXT (0x100000)
453
454 /* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
455 only optional when generating 32-bit code. */
456 #define PPC_OPERAND_OPTIONAL32 (0x400000)
457
458 /* Xilinx APU and FSL related operands */
459 #define PPC_OPERAND_FSL (0x800000)
460 #define PPC_OPERAND_FCR (0x1000000)
461 #define PPC_OPERAND_UDI (0x2000000)
462
463 extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
464
465 static inline int64_t
ppc_optional_operand_value(const struct powerpc_operand * operand,uint64_t insn,ppc_cpu_t dialect,int num_optional)466 ppc_optional_operand_value (const struct powerpc_operand *operand,
467 uint64_t insn,
468 ppc_cpu_t dialect,
469 int num_optional)
470 {
471 if (operand->extract)
472 return (*operand->extract) (insn, dialect, &num_optional);
473 return 0;
474 }
475
476 /* PowerPC VLE insns. */
477 #define E_OPCODE_MASK 0xfc00f800
478
479 /* Form I16L, uses 16A relocs. */
480 #define E_OR2I_INSN 0x7000C000
481 #define E_AND2I_DOT_INSN 0x7000C800
482 #define E_OR2IS_INSN 0x7000D000
483 #define E_LIS_INSN 0x7000E000
484 #define E_AND2IS_DOT_INSN 0x7000E800
485
486 /* Form I16A, uses 16D relocs. */
487 #define E_ADD2I_DOT_INSN 0x70008800
488 #define E_ADD2IS_INSN 0x70009000
489 #define E_CMP16I_INSN 0x70009800
490 #define E_MULL2I_INSN 0x7000A000
491 #define E_CMPL16I_INSN 0x7000A800
492 #define E_CMPH16I_INSN 0x7000B000
493 #define E_CMPHL16I_INSN 0x7000B800
494
495 #define E_LI_INSN 0x70000000
496 #define E_LI_MASK 0xfc008000
497
498 #ifdef __cplusplus
499 }
500 #endif
501
502 #endif /* PPC_H */
503