1@c Copyright (C) 2009-2022 Free Software Foundation, Inc. 2@c Contributed by ARM Ltd. 3@c This is part of the GAS manual. 4@c For copying conditions, see the file as.texinfo. 5@c man end 6 7@ifset GENERIC 8@page 9@node AArch64-Dependent 10@chapter AArch64 Dependent Features 11@end ifset 12 13@ifclear GENERIC 14@node Machine Dependencies 15@chapter AArch64 Dependent Features 16@end ifclear 17 18@cindex AArch64 support 19@menu 20* AArch64 Options:: Options 21* AArch64 Extensions:: Extensions 22* AArch64 Syntax:: Syntax 23* AArch64 Floating Point:: Floating Point 24* AArch64 Directives:: AArch64 Machine Directives 25* AArch64 Opcodes:: Opcodes 26* AArch64 Mapping Symbols:: Mapping Symbols 27@end menu 28 29@node AArch64 Options 30@section Options 31@cindex AArch64 options (none) 32@cindex options for AArch64 (none) 33 34@c man begin OPTIONS 35@table @gcctabopt 36 37@cindex @option{-EB} command-line option, AArch64 38@item -EB 39This option specifies that the output generated by the assembler should 40be marked as being encoded for a big-endian processor. 41 42@cindex @option{-EL} command-line option, AArch64 43@item -EL 44This option specifies that the output generated by the assembler should 45be marked as being encoded for a little-endian processor. 46 47@cindex @option{-mabi=} command-line option, AArch64 48@item -mabi=@var{abi} 49Specify which ABI the source code uses. The recognized arguments 50are: @code{ilp32} and @code{lp64}, which decides the generated object 51file in ELF32 and ELF64 format respectively. The default is @code{lp64}. 52 53@cindex @option{-mcpu=} command-line option, AArch64 54@item -mcpu=@var{processor}[+@var{extension}@dots{}] 55This option specifies the target processor. The assembler will issue an error 56message if an attempt is made to assemble an instruction which will not execute 57on the target processor. The following processor names are recognized: 58@code{cortex-a34}, 59@code{cortex-a35}, 60@code{cortex-a53}, 61@code{cortex-a55}, 62@code{cortex-a57}, 63@code{cortex-a65}, 64@code{cortex-a65ae}, 65@code{cortex-a72}, 66@code{cortex-a73}, 67@code{cortex-a75}, 68@code{cortex-a76}, 69@code{cortex-a76ae}, 70@code{cortex-a77}, 71@code{cortex-a78}, 72@code{cortex-a78ae}, 73@code{cortex-a78c}, 74@code{cortex-a510}, 75@code{cortex-a710}, 76@code{ares}, 77@code{exynos-m1}, 78@code{falkor}, 79@code{neoverse-n1}, 80@code{neoverse-n2}, 81@code{neoverse-e1}, 82@code{neoverse-v1}, 83@code{qdf24xx}, 84@code{saphira}, 85@code{thunderx}, 86@code{vulcan}, 87@code{xgene1} 88@code{xgene2}, 89@code{cortex-r82}, 90@code{cortex-x1}, 91and 92@code{cortex-x2}. 93The special name @code{all} may be used to allow the assembler to accept 94instructions valid for any supported processor, including all optional 95extensions. 96 97In addition to the basic instruction set, the assembler can be told to 98accept, or restrict, various extension mnemonics that extend the 99processor. @xref{AArch64 Extensions}. 100 101If some implementations of a particular processor can have an 102extension, then then those extensions are automatically enabled. 103Consequently, you will not normally have to specify any additional 104extensions. 105 106@cindex @option{-march=} command-line option, AArch64 107@item -march=@var{architecture}[+@var{extension}@dots{}] 108This option specifies the target architecture. The assembler will 109issue an error message if an attempt is made to assemble an 110instruction which will not execute on the target architecture. The 111following architecture names are recognized: @code{armv8-a}, 112@code{armv8.1-a}, @code{armv8.2-a}, @code{armv8.3-a}, @code{armv8.4-a} 113@code{armv8.5-a}, @code{armv8.6-a}, @code{armv8.7-a}, @code{armv8.8-a}, 114@code{armv8-r}, @code{armv9-a}, @code{armv9.1-a}, @code{armv9.2-a}, 115and @code{armv9.3-a}. 116 117If both @option{-mcpu} and @option{-march} are specified, the 118assembler will use the setting for @option{-mcpu}. If neither are 119specified, the assembler will default to @option{-mcpu=all}. 120 121The architecture option can be extended with the same instruction set 122extension options as the @option{-mcpu} option. Unlike 123@option{-mcpu}, extensions are not always enabled by default, 124@xref{AArch64 Extensions}. 125 126@cindex @code{-mverbose-error} command-line option, AArch64 127@item -mverbose-error 128This option enables verbose error messages for AArch64 gas. This option 129is enabled by default. 130 131@cindex @code{-mno-verbose-error} command-line option, AArch64 132@item -mno-verbose-error 133This option disables verbose error messages in AArch64 gas. 134 135@end table 136@c man end 137 138@node AArch64 Extensions 139@section Architecture Extensions 140 141The table below lists the permitted architecture extensions that are 142supported by the assembler and the conditions under which they are 143automatically enabled. 144 145Multiple extensions may be specified, separated by a @code{+}. 146Extension mnemonics may also be removed from those the assembler 147accepts. This is done by prepending @code{no} to the option that adds 148the extension. Extensions that are removed must be listed after all 149extensions that have been added. 150 151Enabling an extension that requires other extensions will 152automatically cause those extensions to be enabled. Similarly, 153disabling an extension that is required by other extensions will 154automatically cause those extensions to be disabled. 155 156@multitable @columnfractions .12 .17 .17 .54 157@headitem Extension @tab Minimum Architecture @tab Enabled by default 158 @tab Description 159@item @code{aes} @tab ARMv8-A @tab No 160 @tab Enable the AES cryptographic extensions. This implies @code{fp} and 161 @code{simd}. 162@item @code{bf16} @tab ARMv8.2-A @tab ARMv8.6-A or later 163 @tab Enable BFloat16 extension. 164@item @code{compnum} @tab ARMv8.2-A @tab ARMv8.3-A or later 165 @tab Enable the complex number SIMD extensions. This implies @code{fp16} and 166 @code{simd}. 167@item @code{crc} @tab ARMv8-A @tab ARMv8.1-A or later 168 @tab Enable CRC instructions. 169@item @code{crypto} @tab ARMv8-A @tab No 170 @tab Enable cryptographic extensions. This implies @code{fp}, @code{simd}, 171 @code{aes} and @code{sha2}. 172@item @code{dotprod} @tab ARMv8.2-A @tab ARMv8.4-A or later 173 @tab Enable the Dot Product extension. This implies @code{simd}. 174@item @code{f32mm} @tab ARMv8.2-A @tab No 175 @tab Enable F32 Matrix Multiply extension. This implies @code{sve}. 176@item @code{f64mm} @tab ARMv8.2-A @tab No 177 @tab Enable F64 Matrix Multiply extension. This implies @code{sve}. 178@item @code{flagm} @tab ARMv8-A @tab ARMv8.4-A or later 179 @tab Enable Flag Manipulation instructions. 180@item @code{fp16fml} @tab ARMv8.2-A @tab ARMv8.4-A or later 181 @tab Enable ARMv8.2 16-bit floating-point multiplication variant support. This 182 implies @code{fp} and @code{fp16}. 183@item @code{fp16} @tab ARMv8.2-A @tab ARMv8.2-A or later 184 @tab Enable ARMv8.2 16-bit floating-point support. This implies @code{fp}. 185@item @code{fp} @tab ARMv8-A @tab ARMv8-A or later 186 @tab Enable floating-point extensions. 187@item @code{hbc} @tab @tab Armv8.8-A or later 188 @tab Enable Armv8.8-A hinted conditional branch instructions 189@item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later 190 @tab Enable Int8 Matrix Multiply extension. 191@item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later 192 @tab Enable Limited Ordering Regions extensions. 193@item @code{ls64} @tab ARMv8.6-A @tab ARMv8.7-A or later 194 @tab Enable 64 Byte Loads/Stores. 195@item @code{lse} @tab ARMv8-A @tab ARMv8.1-A or later 196 @tab Enable Large System extensions. 197@item @code{memtag} @tab ARMv8.5-A @tab No 198 @tab Enable ARMv8.5-A Memory Tagging Extensions. 199@item @code{mops} @tab @tab Armv8.8-A or later 200 @tab Enable Armv8.8-A memcpy and memset acceleration instructions 201@item @code{pan} @tab ARMv8-A @tab ARMv8.1-A or later 202 @tab Enable Privileged Access Never support. 203@item @code{pauth} @tab ARMv8-A @tab No 204 @tab Enable Pointer Authentication. 205@item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later 206 @tab Enable the Execution and Data and Prediction instructions. 207@item @code{profile} @tab ARMv8.2-A @tab No 208 @tab Enable statistical profiling extensions. 209@item @code{ras} @tab ARMv8-A @tab ARMv8.2-A or later 210 @tab Enable the Reliability, Availability and Serviceability extension. 211@item @code{rcpc} @tab ARMv8.2-A @tab ARMv8.3-A or later 212 @tab Enable the weak release consistency extension. 213@item @code{rdma} @tab ARMv8-A @tab ARMv8.1-A or later 214 @tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}. 215@item @code{rng} @tab ARMv8.5-A @tab No 216 @tab Enable ARMv8.5-A random number instructions. 217@item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later 218 @tab Enable the speculation barrier instruction sb. 219@item @code{sha2} @tab ARMv8-A @tab No 220 @tab Enable the SHA2 cryptographic extensions. This implies @code{fp} and 221 @code{simd}. 222@item @code{sha3} @tab ARMv8.2-A @tab No 223 @tab Enable the ARMv8.2-A SHA2 and SHA3 cryptographic extensions. This implies 224 @code{fp}, @code{simd} and @code{sha2}. 225@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later 226 @tab Enable Advanced SIMD extensions. This implies @code{fp}. 227@item @code{sm4} @tab ARMv8.2-A @tab No 228 @tab Enable the ARMv8.2-A SM3 and SM4 cryptographic extensions. This implies 229 @code{fp} and @code{simd}. 230@item @code{sme} @tab Armv9-A @tab No 231 @tab Enable SME Extension. 232@item @code{sme-f64} @tab Armv9-A @tab No 233 @tab Enable SME F64 Extension. 234@item @code{sme-i64} @tab Armv9-A @tab No 235 @tab Enable SME I64 Extension. 236@item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later 237 @tab Enable Speculative Store Bypassing Safe state read and write. 238@item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later 239 @tab Enable the Scalable Vector Extensions. This implies @code{fp16}, 240 @code{simd} and @code{compnum}. 241@item @code{sve2} @tab ARMv8-A @tab Armv9-A or later 242 @tab Enable the SVE2 Extension. This implies @code{sve}. 243@item @code{sve2-aes} @tab ARMv8-A @tab No 244 @tab Enable SVE2 AES Extension. This also enables the .Q->.B form of the 245 @code{pmullt} and @code{pmullb} instructions. This implies @code{aes} and 246 @code{sve2}. 247@item @code{sve2-bitperm} @tab ARMv8-A @tab No 248 @tab Enable SVE2 BITPERM Extension. 249@item @code{sve2-sha3} @tab ARMv8-A @tab No 250 @tab Enable SVE2 SHA3 Extension. This implies @code{sha3} and @code{sve2}. 251@item @code{sve2-sm4} @tab ARMv8-A @tab No 252 @tab Enable SVE2 SM4 Extension. This implies @code{sm4} and @code{sve2}. 253@item @code{tme} @tab ARMv8-A @tab No 254 @tab Enable Transactional Memory Extensions. 255@end multitable 256 257@node AArch64 Syntax 258@section Syntax 259@menu 260* AArch64-Chars:: Special Characters 261* AArch64-Regs:: Register Names 262* AArch64-Relocations:: Relocations 263@end menu 264 265@node AArch64-Chars 266@subsection Special Characters 267 268@cindex line comment character, AArch64 269@cindex AArch64 line comment character 270The presence of a @samp{//} on a line indicates the start of a comment 271that extends to the end of the current line. If a @samp{#} appears as 272the first character of a line, the whole line is treated as a comment. 273 274@cindex line separator, AArch64 275@cindex statement separator, AArch64 276@cindex AArch64 line separator 277The @samp{;} character can be used instead of a newline to separate 278statements. 279 280@cindex immediate character, AArch64 281@cindex AArch64 immediate character 282The @samp{#} can be optionally used to indicate immediate operands. 283 284@node AArch64-Regs 285@subsection Register Names 286 287@cindex AArch64 register names 288@cindex register names, AArch64 289Please refer to the section @samp{4.4 Register Names} of 290@samp{ARMv8 Instruction Set Overview}, which is available at 291@uref{http://infocenter.arm.com}. 292 293@node AArch64-Relocations 294@subsection Relocations 295 296@cindex relocations, AArch64 297@cindex AArch64 relocations 298@cindex MOVN, MOVZ and MOVK group relocations, AArch64 299Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated 300by prefixing the label with @samp{#:abs_g2:} etc. 301For example to load the 48-bit absolute address of @var{foo} into x0: 302 303@smallexample 304 movz x0, #:abs_g2:foo // bits 32-47, overflow check 305 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check 306 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check 307@end smallexample 308 309@cindex ADRP, ADD, LDR/STR group relocations, AArch64 310Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR} 311instructions can be generated by prefixing the label with 312@samp{:pg_hi21:} and @samp{#:lo12:} respectively. 313 314For example to use 33-bit (+/-4GB) pc-relative addressing to 315load the address of @var{foo} into x0: 316 317@smallexample 318 adrp x0, :pg_hi21:foo 319 add x0, x0, #:lo12:foo 320@end smallexample 321 322Or to load the value of @var{foo} into x0: 323 324@smallexample 325 adrp x0, :pg_hi21:foo 326 ldr x0, [x0, #:lo12:foo] 327@end smallexample 328 329Note that @samp{:pg_hi21:} is optional. 330 331@smallexample 332 adrp x0, foo 333@end smallexample 334 335is equivalent to 336 337@smallexample 338 adrp x0, :pg_hi21:foo 339@end smallexample 340 341@node AArch64 Floating Point 342@section Floating Point 343 344@cindex floating point, AArch64 (@sc{ieee}) 345@cindex AArch64 floating point (@sc{ieee}) 346The AArch64 architecture uses @sc{ieee} floating-point numbers. 347 348@node AArch64 Directives 349@section AArch64 Machine Directives 350 351@cindex machine directives, AArch64 352@cindex AArch64 machine directives 353@table @code 354 355@c AAAAAAAAAAAAAAAAAAAAAAAAA 356 357@cindex @code{.arch} directive, AArch64 358@item .arch @var{name} 359Select the target architecture. Valid values for @var{name} are the same as 360for the @option{-march} command-line option. 361 362Specifying @code{.arch} clears any previously selected architecture 363extensions. 364 365@cindex @code{.arch_extension} directive, AArch64 366@item .arch_extension @var{name} 367Add or remove an architecture extension to the target architecture. Valid 368values for @var{name} are the same as those accepted as architectural 369extensions by the @option{-mcpu} command-line option. 370 371@code{.arch_extension} may be used multiple times to add or remove extensions 372incrementally to the architecture being compiled for. 373 374@c BBBBBBBBBBBBBBBBBBBBBBBBBB 375 376@cindex @code{.bss} directive, AArch64 377@item .bss 378This directive switches to the @code{.bss} section. 379 380@c CCCCCCCCCCCCCCCCCCCCCCCCCC 381 382@cindex @code{.cpu} directive, AArch64 383@item .cpu @var{name} 384Set the target processor. Valid values for @var{name} are the same as 385those accepted by the @option{-mcpu=} command-line option. 386 387@c DDDDDDDDDDDDDDDDDDDDDDDDDD 388 389@cindex @code{.dword} directive, AArch64 390@item .dword @var{expressions} 391The @code{.dword} directive produces 64 bit values. 392 393@c EEEEEEEEEEEEEEEEEEEEEEEEEE 394 395@cindex @code{.even} directive, AArch64 396@item .even 397The @code{.even} directive aligns the output on the next even byte 398boundary. 399 400@c FFFFFFFFFFFFFFFFFFFFFFFFFF 401 402@cindex @code{.float16} directive, AArch64 403@item .float16 @var{value [,...,value_n]} 404Place the half precision floating point representation of one or more 405floating-point values into the current section. 406The format used to encode the floating point values is always the 407IEEE 754-2008 half precision floating point format. 408 409@c GGGGGGGGGGGGGGGGGGGGGGGGGG 410@c HHHHHHHHHHHHHHHHHHHHHHHHHH 411@c IIIIIIIIIIIIIIIIIIIIIIIIII 412 413@cindex @code{.inst} directive, AArch64 414@item .inst @var{expressions} 415Inserts the expressions into the output as if they were instructions, 416rather than data. 417 418@c JJJJJJJJJJJJJJJJJJJJJJJJJJ 419@c KKKKKKKKKKKKKKKKKKKKKKKKKK 420@c LLLLLLLLLLLLLLLLLLLLLLLLLL 421 422@cindex @code{.ltorg} directive, AArch64 423@item .ltorg 424This directive causes the current contents of the literal pool to be 425dumped into the current section (which is assumed to be the .text 426section) at the current location (aligned to a word boundary). 427GAS maintains a separate literal pool for each section and each 428sub-section. The @code{.ltorg} directive will only affect the literal 429pool of the current section and sub-section. At the end of assembly 430all remaining, un-empty literal pools will automatically be dumped. 431 432Note - older versions of GAS would dump the current literal 433pool any time a section change occurred. This is no longer done, since 434it prevents accurate control of the placement of literal pools. 435 436@c MMMMMMMMMMMMMMMMMMMMMMMMMM 437 438@c NNNNNNNNNNNNNNNNNNNNNNNNNN 439@c OOOOOOOOOOOOOOOOOOOOOOOOOO 440 441@c PPPPPPPPPPPPPPPPPPPPPPPPPP 442 443@cindex @code{.pool} directive, AArch64 444@item .pool 445This is a synonym for .ltorg. 446 447@c QQQQQQQQQQQQQQQQQQQQQQQQQQ 448@c RRRRRRRRRRRRRRRRRRRRRRRRRR 449 450@cindex @code{.req} directive, AArch64 451@item @var{name} .req @var{register name} 452This creates an alias for @var{register name} called @var{name}. For 453example: 454 455@smallexample 456 foo .req w0 457@end smallexample 458 459ip0, ip1, lr and fp are automatically defined to 460alias to X16, X17, X30 and X29 respectively. 461 462@c SSSSSSSSSSSSSSSSSSSSSSSSSS 463 464@c TTTTTTTTTTTTTTTTTTTTTTTTTT 465 466@cindex @code{.tlsdescadd} directive, AArch64 467@item @code{.tlsdescadd} 468Emits a TLSDESC_ADD reloc on the next instruction. 469 470@cindex @code{.tlsdesccall} directive, AArch64 471@item @code{.tlsdesccall} 472Emits a TLSDESC_CALL reloc on the next instruction. 473 474@cindex @code{.tlsdescldr} directive, AArch64 475@item @code{.tlsdescldr} 476Emits a TLSDESC_LDR reloc on the next instruction. 477 478@c UUUUUUUUUUUUUUUUUUUUUUUUUU 479 480@cindex @code{.unreq} directive, AArch64 481@item .unreq @var{alias-name} 482This undefines a register alias which was previously defined using the 483@code{req} directive. For example: 484 485@smallexample 486 foo .req w0 487 .unreq foo 488@end smallexample 489 490An error occurs if the name is undefined. Note - this pseudo op can 491be used to delete builtin in register name aliases (eg 'w0'). This 492should only be done if it is really necessary. 493 494@c VVVVVVVVVVVVVVVVVVVVVVVVVV 495 496@cindex @code{.variant_pcs} directive, AArch64 497@item .variant_pcs @var{symbol} 498This directive marks @var{symbol} referencing a function that may 499follow a variant procedure call standard with different register 500usage convention from the base procedure call standard. 501 502@c WWWWWWWWWWWWWWWWWWWWWWWWWW 503@c XXXXXXXXXXXXXXXXXXXXXXXXXX 504 505@cindex @code{.xword} directive, AArch64 506@item .xword @var{expressions} 507The @code{.xword} directive produces 64 bit values. This is the same 508as the @code{.dword} directive. 509 510@c YYYYYYYYYYYYYYYYYYYYYYYYYY 511@c ZZZZZZZZZZZZZZZZZZZZZZZZZZ 512 513@cindex @code{.cfi_b_key_frame} directive, AArch64 514@item @code{.cfi_b_key_frame} 515The @code{.cfi_b_key_frame} directive inserts a 'B' character into the CIE 516corresponding to the current frame's FDE, meaning that its return address has 517been signed with the B-key. If two frames are signed with differing keys then 518they will not share the same CIE. This information is intended to be used by 519the stack unwinder in order to properly authenticate return addresses. 520 521@end table 522 523@node AArch64 Opcodes 524@section Opcodes 525 526@cindex AArch64 opcodes 527@cindex opcodes for AArch64 528GAS implements all the standard AArch64 opcodes. It also 529implements several pseudo opcodes, including several synthetic load 530instructions. 531 532@table @code 533 534@cindex @code{LDR reg,=<expr>} pseudo op, AArch64 535@item LDR = 536@smallexample 537 ldr <register> , =<expression> 538@end smallexample 539 540The constant expression will be placed into the nearest literal pool (if it not 541already there) and a PC-relative LDR instruction will be generated. 542 543@end table 544 545For more information on the AArch64 instruction set and assembly language 546notation, see @samp{ARMv8 Instruction Set Overview} available at 547@uref{http://infocenter.arm.com}. 548 549 550@node AArch64 Mapping Symbols 551@section Mapping Symbols 552 553The AArch64 ELF specification requires that special symbols be inserted 554into object files to mark certain features: 555 556@table @code 557 558@cindex @code{$x} 559@item $x 560At the start of a region of code containing AArch64 instructions. 561 562@cindex @code{$d} 563@item $d 564At the start of a region of data. 565 566@end table 567