xref: /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/CMakeLists.txt (revision 82d56013d7b633d116a93943de88e08335357a7c) 
1add_llvm_component_group(AMDGPU)
2
3set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
4
5tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
6tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
7tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
8tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
9tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
10tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
11tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
12tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering)
13tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)
14tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
15tablegen(LLVM AMDGPUGenSearchableTables.inc -gen-searchable-tables)
16tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
17
18set(LLVM_TARGET_DEFINITIONS AMDGPUGISel.td)
19tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel)
20tablegen(LLVM AMDGPUGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
21              -combiners="AMDGPUPreLegalizerCombinerHelper")
22tablegen(LLVM AMDGPUGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
23              -combiners="AMDGPUPostLegalizerCombinerHelper")
24tablegen(LLVM AMDGPUGenRegBankGICombiner.inc -gen-global-isel-combiner
25              -combiners="AMDGPURegBankCombinerHelper")
26
27set(LLVM_TARGET_DEFINITIONS R600.td)
28tablegen(LLVM R600GenAsmWriter.inc -gen-asm-writer)
29tablegen(LLVM R600GenCallingConv.inc -gen-callingconv)
30tablegen(LLVM R600GenDAGISel.inc -gen-dag-isel)
31tablegen(LLVM R600GenDFAPacketizer.inc -gen-dfa-packetizer)
32tablegen(LLVM R600GenInstrInfo.inc -gen-instr-info)
33tablegen(LLVM R600GenMCCodeEmitter.inc -gen-emitter)
34tablegen(LLVM R600GenRegisterInfo.inc -gen-register-info)
35tablegen(LLVM R600GenSubtargetInfo.inc -gen-subtarget)
36
37add_public_tablegen_target(AMDGPUCommonTableGen)
38
39set(LLVM_TARGET_DEFINITIONS InstCombineTables.td)
40tablegen(LLVM InstCombineTables.inc -gen-searchable-tables)
41add_public_tablegen_target(InstCombineTableGen)
42
43add_llvm_target(AMDGPUCodeGen
44  AMDGPUAliasAnalysis.cpp
45  AMDGPUAlwaysInlinePass.cpp
46  AMDGPUAnnotateKernelFeatures.cpp
47  AMDGPUAnnotateUniformValues.cpp
48  AMDGPUArgumentUsageInfo.cpp
49  AMDGPUAsmPrinter.cpp
50  AMDGPUAtomicOptimizer.cpp
51  AMDGPUCallLowering.cpp
52  AMDGPUCodeGenPrepare.cpp
53  AMDGPUExportClustering.cpp
54  AMDGPUFixFunctionBitcasts.cpp
55  AMDGPUFrameLowering.cpp
56  AMDGPUHSAMetadataStreamer.cpp
57  AMDGPUInstCombineIntrinsic.cpp
58  AMDGPUInstrInfo.cpp
59  AMDGPUInstructionSelector.cpp
60  AMDGPUISelDAGToDAG.cpp
61  AMDGPUISelLowering.cpp
62  AMDGPUGlobalISelUtils.cpp
63  AMDGPULateCodeGenPrepare.cpp
64  AMDGPULegalizerInfo.cpp
65  AMDGPULibCalls.cpp
66  AMDGPULibFunc.cpp
67  AMDGPULowerIntrinsics.cpp
68  AMDGPULowerKernelArguments.cpp
69  AMDGPULowerKernelAttributes.cpp
70  AMDGPULowerModuleLDSPass.cpp
71  AMDGPUMachineCFGStructurizer.cpp
72  AMDGPUMachineFunction.cpp
73  AMDGPUMachineModuleInfo.cpp
74  AMDGPUMacroFusion.cpp
75  AMDGPUMCInstLower.cpp
76  AMDGPUMIRFormatter.cpp
77  AMDGPUOpenCLEnqueuedBlockLowering.cpp
78  AMDGPUPostLegalizerCombiner.cpp
79  AMDGPUPreLegalizerCombiner.cpp
80  AMDGPUPromoteAlloca.cpp
81  AMDGPUPropagateAttributes.cpp
82  AMDGPURegBankCombiner.cpp
83  AMDGPURegisterBankInfo.cpp
84  AMDGPURewriteOutArguments.cpp
85  AMDGPUSubtarget.cpp
86  AMDGPUTargetMachine.cpp
87  AMDGPUTargetObjectFile.cpp
88  AMDGPUTargetTransformInfo.cpp
89  AMDGPUUnifyDivergentExitNodes.cpp
90  AMDGPUUnifyMetadata.cpp
91  AMDGPUPerfHintAnalysis.cpp
92  AMDILCFGStructurizer.cpp
93  AMDGPUPrintfRuntimeBinding.cpp
94  GCNHazardRecognizer.cpp
95  GCNIterativeScheduler.cpp
96  GCNMinRegStrategy.cpp
97  GCNRegPressure.cpp
98  GCNSchedStrategy.cpp
99  R600AsmPrinter.cpp
100  R600ClauseMergePass.cpp
101  R600ControlFlowFinalizer.cpp
102  R600EmitClauseMarkers.cpp
103  R600ExpandSpecialInstrs.cpp
104  R600FrameLowering.cpp
105  R600InstrInfo.cpp
106  R600ISelLowering.cpp
107  R600MachineFunctionInfo.cpp
108  R600MachineScheduler.cpp
109  R600OpenCLImageTypeLoweringPass.cpp
110  R600OptimizeVectorRegisters.cpp
111  R600Packetizer.cpp
112  R600RegisterInfo.cpp
113  SIAnnotateControlFlow.cpp
114  SIFixSGPRCopies.cpp
115  SIFixVGPRCopies.cpp
116  SIPreAllocateWWMRegs.cpp
117  SIFoldOperands.cpp
118  SIFormMemoryClauses.cpp
119  SIFrameLowering.cpp
120  SIInsertHardClauses.cpp
121  SILateBranchLowering.cpp
122  SIInsertWaitcnts.cpp
123  SIInstrInfo.cpp
124  SIISelLowering.cpp
125  SILoadStoreOptimizer.cpp
126  SILowerControlFlow.cpp
127  SILowerI1Copies.cpp
128  SILowerSGPRSpills.cpp
129  SIMachineFunctionInfo.cpp
130  SIMachineScheduler.cpp
131  SIMemoryLegalizer.cpp
132  SIOptimizeExecMasking.cpp
133  SIOptimizeExecMaskingPreRA.cpp
134  SIPeepholeSDWA.cpp
135  SIPostRABundler.cpp
136  SIPreEmitPeephole.cpp
137  SIProgramInfo.cpp
138  SIRegisterInfo.cpp
139  SIShrinkInstructions.cpp
140  SIWholeQuadMode.cpp
141  GCNILPSched.cpp
142  GCNNSAReassign.cpp
143  GCNDPPCombine.cpp
144  SIModeRegister.cpp
145
146  LINK_COMPONENTS
147  Analysis
148  AsmPrinter
149  CodeGen
150  Core
151  IPO
152  MC
153  Passes
154  AMDGPUDesc
155  AMDGPUInfo
156  AMDGPUUtils
157  Scalar
158  SelectionDAG
159  Support
160  Target
161  TransformUtils
162  Vectorize
163  GlobalISel
164  BinaryFormat
165  MIRParser
166
167  ADD_TO_COMPONENT
168  AMDGPU
169  )
170
171add_subdirectory(AsmParser)
172add_subdirectory(Disassembler)
173add_subdirectory(MCTargetDesc)
174add_subdirectory(TargetInfo)
175add_subdirectory(Utils)
176