1//===-- AMDGPUGIsel.td - AMDGPU GlobalISel Patterns---------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// This files contains patterns that should only be used by GlobalISel. For 9// example patterns for V_* instructions that have S_* equivalents. 10// SelectionDAG does not support selecting V_* instructions. 11//===----------------------------------------------------------------------===// 12 13include "AMDGPU.td" 14include "AMDGPUCombine.td" 15 16def sd_vsrc0 : ComplexPattern<i32, 1, "">; 17def gi_vsrc0 : 18 GIComplexOperandMatcher<s32, "selectVSRC0">, 19 GIComplexPatternEquiv<sd_vsrc0>; 20 21def sd_vcsrc : ComplexPattern<i32, 1, "">; 22def gi_vcsrc : 23 GIComplexOperandMatcher<s32, "selectVCSRC">, 24 GIComplexPatternEquiv<sd_vcsrc>; 25 26def gi_vop3mods0 : 27 GIComplexOperandMatcher<s32, "selectVOP3Mods0">, 28 GIComplexPatternEquiv<VOP3Mods0>; 29 30def gi_vop3mods : 31 GIComplexOperandMatcher<s32, "selectVOP3Mods">, 32 GIComplexPatternEquiv<VOP3Mods>; 33 34def gi_vop3_no_mods : 35 GIComplexOperandMatcher<s32, "selectVOP3NoMods">, 36 GIComplexPatternEquiv<VOP3NoMods>; 37 38def gi_vop3mods_nnan : 39 GIComplexOperandMatcher<s32, "selectVOP3Mods_nnan">, 40 GIComplexPatternEquiv<VOP3Mods_nnan>; 41 42def gi_vop3omods : 43 GIComplexOperandMatcher<s32, "selectVOP3OMods">, 44 GIComplexPatternEquiv<VOP3OMods>; 45 46def gi_vop3pmods : 47 GIComplexOperandMatcher<s32, "selectVOP3PMods">, 48 GIComplexPatternEquiv<VOP3PMods>; 49 50def gi_vop3opselmods : 51 GIComplexOperandMatcher<s32, "selectVOP3OpSelMods">, 52 GIComplexPatternEquiv<VOP3OpSelMods>; 53 54// FIXME: Why do we have both VOP3OpSel and VOP3OpSelMods? 55def gi_vop3opsel : 56 GIComplexOperandMatcher<s32, "selectVOP3OpSelMods">, 57 GIComplexPatternEquiv<VOP3OpSel>; 58 59def gi_smrd_imm : 60 GIComplexOperandMatcher<s64, "selectSmrdImm">, 61 GIComplexPatternEquiv<SMRDImm>; 62 63def gi_smrd_imm32 : 64 GIComplexOperandMatcher<s64, "selectSmrdImm32">, 65 GIComplexPatternEquiv<SMRDImm32>; 66 67def gi_smrd_sgpr : 68 GIComplexOperandMatcher<s64, "selectSmrdSgpr">, 69 GIComplexPatternEquiv<SMRDSgpr>; 70 71def gi_flat_offset : 72 GIComplexOperandMatcher<s64, "selectFlatOffset">, 73 GIComplexPatternEquiv<FlatOffset>; 74def gi_global_offset : 75 GIComplexOperandMatcher<s64, "selectGlobalOffset">, 76 GIComplexPatternEquiv<GlobalOffset>; 77def gi_global_saddr : 78 GIComplexOperandMatcher<s64, "selectGlobalSAddr">, 79 GIComplexPatternEquiv<GlobalSAddr>; 80 81def gi_mubuf_scratch_offset : 82 GIComplexOperandMatcher<s32, "selectMUBUFScratchOffset">, 83 GIComplexPatternEquiv<MUBUFScratchOffset>; 84def gi_mubuf_scratch_offen : 85 GIComplexOperandMatcher<s32, "selectMUBUFScratchOffen">, 86 GIComplexPatternEquiv<MUBUFScratchOffen>; 87 88def gi_flat_scratch_offset : 89 GIComplexOperandMatcher<s32, "selectScratchOffset">, 90 GIComplexPatternEquiv<ScratchOffset>; 91 92def gi_flat_scratch_saddr : 93 GIComplexOperandMatcher<s32, "selectScratchSAddr">, 94 GIComplexPatternEquiv<ScratchSAddr>; 95 96def gi_ds_1addr_1offset : 97 GIComplexOperandMatcher<s32, "selectDS1Addr1Offset">, 98 GIComplexPatternEquiv<DS1Addr1Offset>; 99 100def gi_ds_64bit_4byte_aligned : 101 GIComplexOperandMatcher<s64, "selectDS64Bit4ByteAligned">, 102 GIComplexPatternEquiv<DS64Bit4ByteAligned>; 103 104def gi_ds_128bit_8byte_aligned : 105 GIComplexOperandMatcher<s64, "selectDS128Bit8ByteAligned">, 106 GIComplexPatternEquiv<DS128Bit8ByteAligned>; 107 108def gi_mubuf_addr64 : 109 GIComplexOperandMatcher<s64, "selectMUBUFAddr64">, 110 GIComplexPatternEquiv<MUBUFAddr64>; 111 112def gi_mubuf_offset : 113 GIComplexOperandMatcher<s64, "selectMUBUFOffset">, 114 GIComplexPatternEquiv<MUBUFOffset>; 115 116def gi_smrd_buffer_imm : 117 GIComplexOperandMatcher<s64, "selectSMRDBufferImm">, 118 GIComplexPatternEquiv<SMRDBufferImm>; 119 120def gi_smrd_buffer_imm32 : 121 GIComplexOperandMatcher<s64, "selectSMRDBufferImm32">, 122 GIComplexPatternEquiv<SMRDBufferImm32>; 123 124// Separate load nodes are defined to glue m0 initialization in 125// SelectionDAG. The GISel selector can just insert m0 initialization 126// directly before before selecting a glue-less load, so hide this 127// distinction. 128 129def : GINodeEquiv<G_LOAD, AMDGPUld_glue> { 130 let CheckMMOIsNonAtomic = 1; 131} 132 133def : GINodeEquiv<G_STORE, AMDGPUst_glue> { 134 let CheckMMOIsNonAtomic = 1; 135} 136 137def : GINodeEquiv<G_LOAD, AMDGPUatomic_ld_glue> { 138 bit CheckMMOIsAtomic = 1; 139} 140 141def : GINodeEquiv<G_STORE, AMDGPUatomic_st_glue> { 142 bit CheckMMOIsAtomic = 1; 143} 144 145 146def : GINodeEquiv<G_ATOMIC_CMPXCHG, atomic_cmp_swap_glue>; 147def : GINodeEquiv<G_ATOMICRMW_XCHG, atomic_swap_glue>; 148def : GINodeEquiv<G_ATOMICRMW_ADD, atomic_load_add_glue>; 149def : GINodeEquiv<G_ATOMICRMW_SUB, atomic_load_sub_glue>; 150def : GINodeEquiv<G_ATOMICRMW_AND, atomic_load_and_glue>; 151def : GINodeEquiv<G_ATOMICRMW_OR, atomic_load_or_glue>; 152def : GINodeEquiv<G_ATOMICRMW_XOR, atomic_load_xor_glue>; 153def : GINodeEquiv<G_ATOMICRMW_MIN, atomic_load_min_glue>; 154def : GINodeEquiv<G_ATOMICRMW_MAX, atomic_load_max_glue>; 155def : GINodeEquiv<G_ATOMICRMW_UMIN, atomic_load_umin_glue>; 156def : GINodeEquiv<G_ATOMICRMW_UMAX, atomic_load_umax_glue>; 157def : GINodeEquiv<G_ATOMICRMW_FADD, atomic_load_fadd_glue>; 158 159def : GINodeEquiv<G_AMDGPU_FFBH_U32, AMDGPUffbh_u32_impl>; 160def : GINodeEquiv<G_AMDGPU_FMIN_LEGACY, AMDGPUfmin_legacy>; 161def : GINodeEquiv<G_AMDGPU_FMAX_LEGACY, AMDGPUfmax_legacy>; 162def : GINodeEquiv<G_AMDGPU_RCP_IFLAG, AMDGPUrcp_iflag>; 163 164def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE0, AMDGPUcvt_f32_ubyte0>; 165def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE1, AMDGPUcvt_f32_ubyte1>; 166def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE2, AMDGPUcvt_f32_ubyte2>; 167def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE3, AMDGPUcvt_f32_ubyte3>; 168 169def : GINodeEquiv<G_AMDGPU_CVT_PK_I16_I32, AMDGPUpk_i16_i32_impl>; 170def : GINodeEquiv<G_AMDGPU_SMED3, AMDGPUsmed3>; 171def : GINodeEquiv<G_AMDGPU_UMED3, AMDGPUumed3>; 172 173def : GINodeEquiv<G_AMDGPU_ATOMIC_CMPXCHG, AMDGPUatomic_cmp_swap>; 174def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD, SIbuffer_load>; 175def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_USHORT, SIbuffer_load_ushort>; 176def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_UBYTE, SIbuffer_load_ubyte>; 177def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SSHORT, SIbuffer_load_short>; 178def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SBYTE, SIbuffer_load_byte>; 179def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT, SIbuffer_load_format>; 180def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT_D16, SIbuffer_load_format_d16>; 181def : GINodeEquiv<G_AMDGPU_TBUFFER_LOAD_FORMAT, SItbuffer_load>; 182def : GINodeEquiv<G_AMDGPU_TBUFFER_LOAD_FORMAT_D16, SItbuffer_load_d16>; 183def : GINodeEquiv<G_AMDGPU_BUFFER_STORE, SIbuffer_store>; 184def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_SHORT, SIbuffer_store_short>; 185def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_BYTE, SIbuffer_store_byte>; 186def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_FORMAT, SIbuffer_store_format>; 187def : GINodeEquiv<G_AMDGPU_BUFFER_STORE_FORMAT_D16, SIbuffer_store_format_d16>; 188def : GINodeEquiv<G_AMDGPU_TBUFFER_STORE_FORMAT, SItbuffer_store>; 189def : GINodeEquiv<G_AMDGPU_TBUFFER_STORE_FORMAT_D16, SItbuffer_store_d16>; 190 191// FIXME: Check MMO is atomic 192def : GINodeEquiv<G_AMDGPU_ATOMIC_INC, SIatomic_inc>; 193def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, SIatomic_dec>; 194def : GINodeEquiv<G_AMDGPU_ATOMIC_INC, atomic_inc_glue>; 195def : GINodeEquiv<G_AMDGPU_ATOMIC_DEC, atomic_dec_glue>; 196def : GINodeEquiv<G_AMDGPU_ATOMIC_FMIN, SIatomic_fmin>; 197def : GINodeEquiv<G_AMDGPU_ATOMIC_FMAX, SIatomic_fmax>; 198def : GINodeEquiv<G_AMDGPU_ATOMIC_FMIN, atomic_load_fmin_glue>; 199def : GINodeEquiv<G_AMDGPU_ATOMIC_FMAX, atomic_load_fmax_glue>; 200 201 202def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SWAP, SIbuffer_atomic_swap>; 203def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_ADD, SIbuffer_atomic_add>; 204def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SUB, SIbuffer_atomic_sub>; 205def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMIN, SIbuffer_atomic_smin>; 206def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMIN, SIbuffer_atomic_umin>; 207def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_SMAX, SIbuffer_atomic_smax>; 208def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_UMAX, SIbuffer_atomic_umax>; 209def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_AND, SIbuffer_atomic_and>; 210def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_OR, SIbuffer_atomic_or>; 211def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_XOR, SIbuffer_atomic_xor>; 212def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_INC, SIbuffer_atomic_inc>; 213def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_DEC, SIbuffer_atomic_dec>; 214def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FADD, SIbuffer_atomic_fadd>; 215def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FMIN, SIbuffer_atomic_fmin>; 216def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_FMAX, SIbuffer_atomic_fmax>; 217def : GINodeEquiv<G_AMDGPU_BUFFER_ATOMIC_CMPSWAP, SIbuffer_atomic_cmpswap>; 218def : GINodeEquiv<G_AMDGPU_S_BUFFER_LOAD, SIsbuffer_load>; 219 220class GISelSop2Pat < 221 SDPatternOperator node, 222 Instruction inst, 223 ValueType dst_vt, 224 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 225 226 (dst_vt (node (src0_vt SReg_32:$src0), (src1_vt SReg_32:$src1))), 227 (inst src0_vt:$src0, src1_vt:$src1) 228>; 229 230class GISelVop2Pat < 231 SDPatternOperator node, 232 Instruction inst, 233 ValueType dst_vt, 234 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 235 236 (dst_vt (node (src0_vt (sd_vsrc0 src0_vt:$src0)), (src1_vt VGPR_32:$src1))), 237 (inst src0_vt:$src0, src1_vt:$src1) 238>; 239 240class GISelVop2CommutePat < 241 SDPatternOperator node, 242 Instruction inst, 243 ValueType dst_vt, 244 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 245 246 (dst_vt (node (src1_vt VGPR_32:$src1), (src0_vt (sd_vsrc0 src0_vt:$src0)))), 247 (inst src0_vt:$src0, src1_vt:$src1) 248>; 249 250class GISelVop3Pat2 < 251 SDPatternOperator node, 252 Instruction inst, 253 ValueType dst_vt, 254 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 255 256 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))), 257 (inst src0_vt:$src0, src1_vt:$src1) 258>; 259 260class GISelVop3Pat2CommutePat < 261 SDPatternOperator node, 262 Instruction inst, 263 ValueType dst_vt, 264 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 265 266 (dst_vt (node (src0_vt (sd_vcsrc src0_vt:$src0)), (src1_vt (sd_vcsrc src1_vt:$src1)))), 267 (inst src0_vt:$src1, src1_vt:$src0) 268>; 269 270class GISelVop3Pat2ModsPat < 271 SDPatternOperator node, 272 Instruction inst, 273 ValueType dst_vt, 274 ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < 275 276 (dst_vt (node (src0_vt (VOP3Mods0 src0_vt:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omods)), 277 (src1_vt (VOP3Mods src1_vt:$src1, i32:$src1_modifiers)))), 278 (inst i32:$src0_modifiers, src0_vt:$src0, 279 i32:$src1_modifiers, src1_vt:$src1, $clamp, $omods) 280>; 281 282multiclass GISelVop2IntrPat < 283 SDPatternOperator node, Instruction inst, 284 ValueType dst_vt, ValueType src_vt = dst_vt> { 285 286 def : GISelVop2Pat <node, inst, dst_vt, src_vt>; 287 288 // FIXME: Intrinsics aren't marked as commutable, so we need to add an explicit 289 // pattern to handle commuting. This is another reason why legalizing to a 290 // generic machine instruction may be better that matching the intrinsic 291 // directly. 292 def : GISelVop2CommutePat <node, inst, dst_vt, src_vt>; 293} 294 295// Since GlobalISel is more flexible then SelectionDAG, I think we can get 296// away with adding patterns for integer types and not legalizing all 297// loads and stores to vector types. This should help simplify the load/store 298// legalization. 299foreach Ty = [i64, p0, p1, p4] in { 300 defm : SMRD_Pattern <"S_LOAD_DWORDX2", Ty>; 301} 302 303def gi_as_i32timm : GICustomOperandRenderer<"renderTruncTImm">, 304 GISDNodeXFormEquiv<as_i32timm>; 305 306def gi_as_i16timm : GICustomOperandRenderer<"renderTruncTImm">, 307 GISDNodeXFormEquiv<as_i16timm>; 308 309def gi_as_i8timm : GICustomOperandRenderer<"renderTruncTImm">, 310 GISDNodeXFormEquiv<as_i8timm>; 311 312def gi_as_i1timm : GICustomOperandRenderer<"renderTruncTImm">, 313 GISDNodeXFormEquiv<as_i1timm>; 314 315def gi_NegateImm : GICustomOperandRenderer<"renderNegateImm">, 316 GISDNodeXFormEquiv<NegateImm>; 317 318def gi_bitcast_fpimm_to_i32 : GICustomOperandRenderer<"renderBitcastImm">, 319 GISDNodeXFormEquiv<bitcast_fpimm_to_i32>; 320 321def gi_IMMPopCount : GICustomOperandRenderer<"renderPopcntImm">, 322 GISDNodeXFormEquiv<IMMPopCount>; 323 324def gi_extract_cpol : GICustomOperandRenderer<"renderExtractCPol">, 325 GISDNodeXFormEquiv<extract_cpol>; 326 327def gi_extract_swz : GICustomOperandRenderer<"renderExtractSWZ">, 328 GISDNodeXFormEquiv<extract_swz>; 329 330def gi_set_glc : GICustomOperandRenderer<"renderSetGLC">, 331 GISDNodeXFormEquiv<set_glc>; 332 333def gi_frameindex_to_targetframeindex : GICustomOperandRenderer<"renderFrameIndex">, 334 GISDNodeXFormEquiv<frameindex_to_targetframeindex>; 335