1 /* 2 ** File: 8390.h May 02, 2000 3 ** 4 ** Author: Giovanni Falzoni <gfalzoni@inwind.it> 5 ** 6 ** National Semiconductor NS 8390 Network Interface Controller 7 ** 8 ** $Log$ 9 ** Revision 1.2 2005/08/22 15:17:40 beng 10 ** Remove double-blank lines (Al) 11 ** 12 ** Revision 1.1 2005/06/29 10:16:46 beng 13 ** Import of dpeth 3c501/3c509b/.. ethernet driver by 14 ** Giovanni Falzoni <fgalzoni@inwind.it>. 15 ** 16 ** Revision 2.0 2005/06/26 16:16:46 lsodgf0 17 ** Initial revision for Minix 3.0.6 18 */ 19 20 #define DP_PAGESIZE 256 /* NS 8390 page size */ 21 #define SENDQ_PAGES 6 /* SENDQ_PAGES * DP_PAGESIZE >= 1514 bytes */ 22 23 /* Page 0, read/write ------------- */ 24 #define DP_CR 0x00 /* Command Register RW */ 25 #define DP_CLDA0 0x01 /* Current Local Dma Address 0 RO */ 26 #define DP_PSTART 0x01 /* Page Start Register WO */ 27 #define DP_CLDA1 0x02 /* Current Local Dma Address 1 RO */ 28 #define DP_PSTOP 0x02 /* Page Stop Register WO */ 29 #define DP_BNRY 0x03 /* Boundary Pointer RW */ 30 #define DP_TSR 0x04 /* Transmit Status Register RO */ 31 #define DP_TPSR 0x04 /* Transmit Page Start Register WO */ 32 #define DP_NCR 0x05 /* No. of Collisions Register RO */ 33 #define DP_TBCR0 0x05 /* Transmit Byte Count Reg. 0 WO */ 34 #define DP_FIFO 0x06 /* Fifo RO */ 35 #define DP_TBCR1 0x06 /* Transmit Byte Count Reg. 1 WO */ 36 #define DP_ISR 0x07 /* Interrupt Status Register RW */ 37 #define DP_CRDA0 0x08 /* Current Remote Dma Addr.Low RO */ 38 #define DP_RSAR0 0x08 /* Remote Start Address Low WO */ 39 #define DP_CRDA1 0x09 /* Current Remote Dma Addr.High RO */ 40 #define DP_RSAR1 0x09 /* Remote Start Address High WO */ 41 #define DP_RBCR0 0x0A /* Remote Byte Count Low WO */ 42 #define DP_RBCR1 0x0B /* Remote Byte Count Hihg WO */ 43 #define DP_RSR 0x0C /* Receive Status Register RO */ 44 #define DP_RCR 0x0C /* Receive Config. Register WO */ 45 #define DP_CNTR0 0x0D /* Tally Counter 0 RO */ 46 #define DP_TCR 0x0D /* Transmit Config. Register WO */ 47 #define DP_CNTR1 0x0E /* Tally Counter 1 RO */ 48 #define DP_DCR 0x0E /* Data Configuration Register WO */ 49 #define DP_CNTR2 0x0F /* Tally Counter 2 RO */ 50 #define DP_IMR 0x0F /* Interrupt Mask Register WO */ 51 52 /* Page 1, read/write -------------- */ 53 /* DP_CR 0x00 Command Register */ 54 #define DP_PAR0 0x01 /* Physical Address Register 0 */ 55 #define DP_PAR1 0x02 /* Physical Address Register 1 */ 56 #define DP_PAR2 0x03 /* Physical Address Register 2 */ 57 #define DP_PAR3 0x04 /* Physical Address Register 3 */ 58 #define DP_PAR4 0x05 /* Physical Address Register 4 */ 59 #define DP_PAR5 0x06 /* Physical Address Register 5 */ 60 #define DP_CURR 0x07 /* Current Page Register */ 61 #define DP_MAR0 0x08 /* Multicast Address Register 0 */ 62 #define DP_MAR1 0x09 /* Multicast Address Register 1 */ 63 #define DP_MAR2 0x0A /* Multicast Address Register 2 */ 64 #define DP_MAR3 0x0B /* Multicast Address Register 3 */ 65 #define DP_MAR4 0x0C /* Multicast Address Register 4 */ 66 #define DP_MAR5 0x0D /* Multicast Address Register 5 */ 67 #define DP_MAR6 0x0E /* Multicast Address Register 6 */ 68 #define DP_MAR7 0x0F /* Multicast Address Register 7 */ 69 70 /* Bits in dp_cr */ 71 #define CR_STP 0x01 /* Stop: software reset */ 72 #define CR_STA 0x02 /* Start: activate NIC */ 73 #define CR_TXP 0x04 /* Transmit Packet */ 74 #define CR_DMA 0x38 /* Mask for DMA control */ 75 #define CR_DM_RR 0x08 /* DMA: Remote Read */ 76 #define CR_DM_RW 0x10 /* DMA: Remote Write */ 77 #define CR_DM_SP 0x18 /* DMA: Send Packet */ 78 #define CR_NO_DMA 0x20 /* DMA: Stop Remote DMA Operation */ 79 #define CR_PS 0xC0 /* Mask for Page Select */ 80 #define CR_PS_P0 0x00 /* Register Page 0 */ 81 #define CR_PS_P1 0x40 /* Register Page 1 */ 82 #define CR_PS_P2 0x80 /* Register Page 2 */ 83 84 /* Bits in dp_isr */ 85 #define ISR_MASK 0x3F 86 #define ISR_PRX 0x01 /* Packet Received with no errors */ 87 #define ISR_PTX 0x02 /* Packet Transmitted with no errors */ 88 #define ISR_RXE 0x04 /* Receive Error */ 89 #define ISR_TXE 0x08 /* Transmit Error */ 90 #define ISR_OVW 0x10 /* Overwrite Warning */ 91 #define ISR_CNT 0x20 /* Counter Overflow */ 92 #define ISR_RDC 0x40 /* Remote DMA Complete */ 93 #define ISR_RST 0x80 /* Reset Status */ 94 95 /* Bits in dp_imr */ 96 #define IMR_PRXE 0x01 /* Packet Received Enable */ 97 #define IMR_PTXE 0x02 /* Packet Transmitted Enable */ 98 #define IMR_RXEE 0x04 /* Receive Error Enable */ 99 #define IMR_TXEE 0x08 /* Transmit Error Enable */ 100 #define IMR_OVWE 0x10 /* Overwrite Warning Enable */ 101 #define IMR_CNTE 0x20 /* Counter Overflow Enable */ 102 #define IMR_RDCE 0x40 /* DMA Complete Enable */ 103 104 /* Bits in dp_dcr */ 105 #define DCR_WTS 0x01 /* Word Transfer Select */ 106 #define DCR_BYTEWIDE 0x00 /* WTS: byte wide transfers */ 107 #define DCR_WORDWIDE 0x01 /* WTS: word wide transfers */ 108 #define DCR_BOS 0x02 /* Byte Order Select */ 109 #define DCR_LTLENDIAN 0x00 /* BOS: Little Endian */ 110 #define DCR_BIGENDIAN 0x02 /* BOS: Big Endian */ 111 #define DCR_LAS 0x04 /* Long Address Select */ 112 #define DCR_BMS 0x08 /* Burst Mode Select */ 113 #define DCR_AR 0x10 /* Autoinitialize Remote */ 114 #define DCR_FTS 0x60 /* Fifo Threshold Select */ 115 #define DCR_2BYTES 0x00 /* Fifo Threshold: 2 bytes */ 116 #define DCR_4BYTES 0x20 /* Fifo Threshold: 4 bytes */ 117 #define DCR_8BYTES 0x40 /* Fifo Threshold: 8 bytes */ 118 #define DCR_12BYTES 0x60 /* Fifo Threshold: 12 bytes */ 119 120 /* Bits in dp_tcr */ 121 #define TCR_CRC 0x01 /* Inhibit CRC */ 122 #define TCR_ELC 0x06 /* Encoded Loopback Control */ 123 #define TCR_NORMAL 0x00 /* ELC: Normal Operation */ 124 #define TCR_INTERNAL 0x02 /* ELC: Internal Loopback */ 125 #define TCR_0EXTERNAL 0x04 /* ELC: External Loopback LPBK=0 */ 126 #define TCR_1EXTERNAL 0x06 /* ELC: External Loopback LPBK=1 */ 127 #define TCR_ATD 0x08 /* Auto Transmit */ 128 #define TCR_OFST 0x10 /* Collision Offset Enable */ 129 130 /* Bits in dp_tsr */ 131 #define TSR_PTX 0x01 /* Packet Transmitted (without error) */ 132 #define TSR_DFR 0x02 /* Transmit Deferred */ 133 #define TSR_COL 0x04 /* Transmit Collided */ 134 #define TSR_ABT 0x08 /* Transmit Aborted */ 135 #define TSR_CRS 0x10 /* Carrier Sense Lost */ 136 #define TSR_FU 0x20 /* FIFO Underrun */ 137 #define TSR_CDH 0x40 /* CD Heartbeat */ 138 #define TSR_OWC 0x80 /* Out of Window Collision */ 139 140 /* Bits in dp_rcr */ 141 #define RCR_SEP 0x01 /* Save Errored Packets */ 142 #define RCR_AR 0x02 /* Accept Runt Packets */ 143 #define RCR_AB 0x04 /* Accept Broadcast */ 144 #define RCR_AM 0x08 /* Accept Multicast */ 145 #define RCR_PRO 0x10 /* Physical Promiscuous */ 146 #define RCR_MON 0x20 /* Monitor Mode */ 147 148 /* Bits in dp_rsr */ 149 #define RSR_PRX 0x01 /* Packet Received Intact */ 150 #define RSR_CRC 0x02 /* CRC Error */ 151 #define RSR_FAE 0x04 /* Frame Alignment Error */ 152 #define RSR_FO 0x08 /* FIFO Overrun */ 153 #define RSR_MPA 0x10 /* Missed Packet */ 154 #define RSR_PHY 0x20 /* Multicast Address Match !! */ 155 #define RSR_DIS 0x40 /* Receiver Disabled */ 156 157 /* Some macros to simplify accessing the dp8390 */ 158 #define inb_reg0(dep,reg) (inb(dep->de_dp8390_port+reg)) 159 #define outb_reg0(dep,reg,data) (outb(dep->de_dp8390_port+reg,data)) 160 #define inb_reg1(dep,reg) (inb(dep->de_dp8390_port+reg)) 161 #define outb_reg1(dep,reg,data) (outb(dep->de_dp8390_port+reg,data)) 162 163 typedef struct dp_rcvhdr { 164 u8_t dr_status; /* Copy of rsr */ 165 u8_t dr_next; /* Pointer to next packet */ 166 u8_t dr_rbcl; /* Receive Byte Count Low */ 167 u8_t dr_rbch; /* Receive Byte Count High */ 168 } dp_rcvhdr_t; 169 170 void ns_init(dpeth_t *); 171 172 /** 8390.h **/ 173