1 #ifndef _SDR_H 2 #define _SDR_H 3 /* ======= General Parameter ======= */ 4 /* Global configure */ 5 #define DMA_LENGTH_BY_FRAME 6 #define DMA_BASE_IOMAP 7 #define MIXER_AC97 8 9 #include <minix/audio_fw.h> 10 #include <sys/types.h> 11 #include <sys/ioc_sound.h> 12 #include <minix/sound.h> 13 #include <machine/pci.h> 14 #include <sys/mman.h> 15 #include "io.h" 16 17 /* Subdevice type */ 18 #define DAC 0 19 #define ADC 1 20 #define MIX 2 21 22 /* PCI number and driver name */ 23 #define VENDOR_ID 0x1013 24 #define DEVICE_ID 0x6005 25 #define DRIVER_NAME "CS4281" 26 27 /* Volume option */ 28 #define GET_VOL 0 29 #define SET_VOL 1 30 31 /* Interrupt control */ 32 #define INTR_ENABLE 1 33 #define INTR_DISABLE 0 34 35 /* Interrupt status */ 36 #define INTR_STS_DAC 0x0100 37 #define INTR_STS_ADC 0x0200 38 39 /* ======= Self-defined Parameter ======= */ 40 #define REG_INTR_STS 0x0000 41 #define REG_INTR_CTRL 0x0008 42 #define REG_INTR_MASK 0x000c 43 44 #define REG_CONF_WRITE 0x03e0 45 #define REG_POWER_EXT 0x03e4 46 #define REG_SPOWER_CTRL 0x03ec 47 #define REG_CONF_LOAD 0x03f0 48 #define REG_CLK_CTRL 0x0400 49 #define REG_MASTER_CTRL 0x0420 50 #define REG_CODEC_CTRL 0x0460 51 #define REG_CODEC_STATUS 0x0464 52 #define REG_CODEC_OSV 0x0468 53 #define REG_CODEC_ADDR 0x046c 54 #define REG_CODEC_DATA 0x0470 55 #define REG_CODEC_SDA 0x047c 56 #define REG_SOUND_POWER 0x0740 57 #define REG_DAC_SAMPLE_RATE 0x0744 58 #define REG_ADC_SAMPLE_RATE 0x0748 59 #define REG_SRC_SLOT 0x075c 60 #define REG_PCM_LVOL 0x0760 61 #define REG_PCM_RVOL 0x0764 62 63 #define REG_DAC_HDSR 0x00f0 64 #define REG_DAC_DCC 0x0114 65 #define REG_DAC_DMR 0x0150 66 #define REG_DAC_DCR 0x0154 67 #define REG_DAC_FCR 0x0180 68 #define REG_DAC_FSIC 0x0214 69 #define REG_ADC_HDSR 0x00f4 70 #define REG_ADC_DCC 0x0124 71 #define REG_ADC_DMR 0x0158 72 #define REG_ADC_DCR 0x015c 73 #define REG_ADC_FCR 0x0184 74 #define REG_ADC_FSIC 0x0214 75 76 #define REG_DAC_DMA_ADDR 0x0118 77 #define REG_DAC_DMA_LEN 0x011c 78 #define REG_ADC_DMA_ADDR 0x0128 79 #define REG_ADC_DMA_LEN 0x012c 80 81 #define CODEC_REG_POWER 0x26 82 83 #define STS_CODEC_DONE 0x0008 84 #define STS_CODEC_VALID 0x0002 85 86 #define CMD_POWER_DOWN (1 << 14) 87 #define CMD_PORT_TIMING (1 << 16) 88 #define CMD_AC97_MODE (1 << 1) 89 #define CMD_MASTER_SERIAL (1 << 0) 90 #define CMD_INTR_ENABLE 0x03 91 #define CMD_INTR_DMA 0x00040000 92 #define CMD_INTR_DMA0 0x0100 93 #define CMD_INTR_DMA1 0x0200 94 #define CMD_DMR_INIT 0x50 95 #define CMD_DMR_WRITE 0x08 96 #define CMD_DMR_READ 0x04 97 #define CMD_DMR_BIT8 (1 << 16) 98 #define CMD_DMR_MONO (1 << 17) 99 #define CMD_DMR_UNSIGN (1 << 19) 100 #define CMD_DMR_BIT32 (1 << 20) 101 #define CMD_DMR_SWAP (1 << 22) 102 #define CMD_DMR_POLL (1 << 28) 103 #define CMD_DMR_DMA (1 << 29) 104 #define CMD_DCR_MASK (1 << 0) 105 #define CMD_FCR_FEN (1 << 31) 106 #define CMD_DAC_FCR_INIT 0x01002000 107 #define CMD_ADC_FCR_INIT 0x0b0a2020 108 109 static u32_t dcr_data, dmr_data, fcr_data; 110 static u32_t g_sample_rate[] = { 111 48000, 44100, 22050, 16000, 11025, 8000 112 }; 113 114 /* Driver Data Structure */ 115 typedef struct aud_sub_dev_conf_t { 116 u32_t stereo; 117 u16_t sample_rate; 118 u32_t nr_of_bits; 119 u32_t sign; 120 u32_t busy; 121 u32_t fragment_size; 122 u8_t format; 123 } aud_sub_dev_conf_t; 124 125 typedef struct DEV_STRUCT { 126 char *name; 127 u16_t vid; 128 u16_t did; 129 u32_t devind; 130 u32_t base[6]; 131 char irq; 132 char revision; 133 u32_t intr_status; 134 } DEV_STRUCT; 135 136 void dev_mixer_write(u32_t *base, u32_t reg, u32_t val); 137 u32_t dev_mixer_read(u32_t *base, u32_t reg); 138 139 #endif 140