1 #include "als4000.h"
2 #include "mixer.h"
3
4 /* global value */
5 DEV_STRUCT dev;
6 aud_sub_dev_conf_t aud_conf[3];
7 sub_dev_t sub_dev[3];
8 special_file_t special_file[3];
9 drv_t drv;
10
11 /* internal function */
12 static int dev_probe(void);
13 static int set_sample_rate(u32_t rate, int num);
14 static int set_stereo(u32_t stereo, int num);
15 static int set_bits(u32_t bits, int sub_dev);
16 static int set_frag_size(u32_t frag_size, int num);
17 static int set_sign(u32_t val, int num);
18 static int get_frag_size(u32_t *val, int *len, int num);
19 static int free_buf(u32_t *val, int *len, int num);
20
21 /* developer interface */
22 static int dev_reset(u32_t *base);
23 static void dev_configure(u32_t *base);
24 static void dev_init_mixer(u32_t *base);
25 static void dev_set_sample_rate(u32_t *base, u16_t sample_rate);
26 static void dev_set_format(u32_t *base, u32_t bits, u32_t sign,
27 u32_t stereo, u32_t sample_count);
28 static void dev_start_channel(u32_t *base, int sub_dev);
29 static void dev_stop_channel(u32_t *base, int sub_dev);
30 static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev);
31 static u32_t dev_read_dma_current(u32_t *base, int sub_dev);
32 static void dev_pause_dma(u32_t *base, int sub_dev);
33 static void dev_resume_dma(u32_t *base, int sub_dev);
34 static void dev_intr_other(u32_t *base, u32_t status);
35 static u32_t dev_read_clear_intr_status(u32_t *base);
36 static void dev_intr_enable(u32_t *base, int flag);
37
38 /* ======= Developer implemented function ======= */
39 /* ====== Self-defined function ====== */
dev_gcr_read(u32_t base,u32_t reg)40 static u32_t dev_gcr_read(u32_t base, u32_t reg) {
41 u32_t res;
42 sdr_out8(base, REG_GCR_INDEX, reg);
43 res = sdr_in32(base, REG_GCR_DATA);
44 return res;
45 }
46
dev_gcr_write(u32_t base,u32_t reg,u32_t val)47 static void dev_gcr_write(u32_t base, u32_t reg, u32_t val) {
48 sdr_out8(base, REG_GCR_INDEX, reg);
49 sdr_out32(base, REG_GCR_DATA, val);
50 }
51
dev_command(u32_t base,u32_t cmd)52 static void dev_command(u32_t base, u32_t cmd) {
53 int i;
54 for (i = 0; i < 1000; i++) {
55 if ((sdr_in8(base + REG_SB_BASE, REG_SB_CMD) & 0x80) == 0) {
56 sdr_out8(base + REG_SB_BASE, REG_SB_CMD, cmd);
57 return;
58 }
59 }
60 printf("SDR: Fail to execute SB command\n");
61 }
62
63 /* ====== Mixer handling interface ====== */
64 /* Write the data to mixer register (### WRITE_MIXER_REG ###) */
dev_mixer_write(u32_t * base,u32_t reg,u32_t val)65 void dev_mixer_write(u32_t *base, u32_t reg, u32_t val) {
66 sdr_out8(base[0] + REG_SB_BASE, REG_MIXER_ADDR, reg);
67 micro_delay(100);
68 sdr_out8(base[0] + REG_SB_BASE, REG_MIXER_DATA, val);
69 micro_delay(100);
70 }
71
72 /* Read the data from mixer register (### READ_MIXER_REG ###) */
dev_mixer_read(u32_t * base,u32_t reg)73 u32_t dev_mixer_read(u32_t *base, u32_t reg) {
74 u32_t res;
75 sdr_out8(base[0] + REG_SB_BASE, REG_MIXER_ADDR, reg);
76 micro_delay(100);
77 res = sdr_in8(base[0] + REG_SB_BASE, REG_MIXER_DATA);
78 micro_delay(100);
79 return res;
80 }
81
82
83 /* ====== Developer interface ======*/
84 /* Reset the device (### RESET_HARDWARE_CAN_FAIL ###)
85 * -- Return OK means success, Others means failure */
dev_reset(u32_t * base)86 static int dev_reset(u32_t *base) {
87 u32_t i, base0 = base[0];
88 sdr_out8(base0, REG_SB_RESET, 1);
89 micro_delay(10);
90 sdr_out8(base0, REG_SB_RESET, 0);
91 micro_delay(30);
92 for (i = 0; i < 1000; i++) {
93 if (sdr_in8(base0 + REG_SB_BASE, REG_SB_DATA) & 0x80) {
94 if (sdr_in8(base0 + REG_SB_BASE, REG_SB_READ) == 0xaa)
95 break;
96 else
97 return EIO;
98 }
99 }
100 return OK;
101 }
102
103 /* Configure hardware registers (### CONF_HARDWARE ###) */
dev_configure(u32_t * base)104 static void dev_configure(u32_t *base) {
105 u32_t i, data, base0 = base[0];
106 data = dev_mixer_read(base, REG_SB_CONFIG);
107 dev_mixer_write(base, REG_SB_CONFIG | REG_SB_CTRL,
108 data | CMD_MIXER_WRITE_ENABLE);
109 dev_mixer_write(base, REG_SB_DMA_SETUP, 0x01);
110 dev_mixer_write(base, REG_SB_CONFIG | REG_SB_CTRL,
111 (data & ~CMD_MIXER_WRITE_ENABLE));
112 for (i = 0x91; i <= 0x96; i++)
113 dev_gcr_write(base0, i, 0);
114 data = dev_gcr_read(base0, REG_DMA_EM_CTRL);
115 // dev_gcr_write(base0, REG_DMA_EM_CTRL, (data & ~0x07) | 0x04);
116 dev_gcr_write(base0, REG_DMA_EM_CTRL, data);
117 }
118
119 /* Initialize the mixer (### INIT_MIXER ###) */
dev_init_mixer(u32_t * base)120 static void dev_init_mixer(u32_t *base) {
121 // dev_mixer_write(base, 0, 0);
122 }
123
124 /* Set DAC and ADC sample rate (### SET_SAMPLE_RATE ###) */
dev_set_sample_rate(u32_t * base,u16_t sample_rate)125 static void dev_set_sample_rate(u32_t *base, u16_t sample_rate) {
126 u32_t base0 = base[0];
127 dev_command(base0, CMD_SAMPLE_RATE_OUT);
128 dev_command(base0, sample_rate >> 8);
129 dev_command(base0, sample_rate & 0xff);
130 }
131
132 static u32_t rec_format = 0;
133 /* Set DAC and ADC format (### SET_FORMAT ###)*/
dev_set_format(u32_t * base,u32_t bits,u32_t sign,u32_t stereo,u32_t sample_count)134 static void dev_set_format(u32_t *base, u32_t bits, u32_t sign,
135 u32_t stereo, u32_t sample_count) {
136 u32_t format = 0, base0 = base[0];
137 if (bits == 16) {
138 format = CMD_BIT16_AI;
139 rec_format = 0;
140 }
141 else if (bits == 8) {
142 format = CMD_BIT8_AI;
143 rec_format = CMD_REC_WIDTH8;
144 }
145 dev_command(base0, format);
146 if (sign == 0) {
147 if (stereo == 1) {
148 format = CMD_UNSIGN_STEREO;
149 rec_format |= CMD_REC_STEREO;
150 }
151 else
152 format = CMD_UNSIGN_MONO;
153 }
154 else {
155 rec_format |= CMD_REC_SIGN;
156 if (stereo == 1) {
157 format = CMD_SIGN_STEREO;
158 rec_format |= CMD_REC_STEREO;
159 }
160 else
161 format = CMD_SIGN_STEREO;
162 }
163 dev_command(base0, format);
164 if (bits == 16)
165 sample_count >>= 1;
166 sample_count--;
167 dev_command(base0, sample_count & 0xff);
168 dev_command(base0, sample_count >> 8);
169 dev_mixer_write(base, REG_SB_FIFO_LEN_LO|REG_SB_CTRL, sample_count & 0xff);
170 dev_mixer_write(base, REG_SB_FIFO_LEN_HI|REG_SB_CTRL, sample_count >> 8);
171 }
172
173 /* Start the channel (### START_CHANNEL ###) */
dev_start_channel(u32_t * base,int sub_dev)174 static void dev_start_channel(u32_t *base, int sub_dev) {
175 u32_t base0 = base[0];
176 dev_command(base0, CMD_SOUND_ON);
177 if (sub_dev == DAC) {
178 dev_command(base0, CMD_BIT16_DMA_ON);
179 dev_command(base0, CMD_BIT8_DMA_ON);
180 }
181 else if (sub_dev == ADC)
182 dev_mixer_write(base, REG_SB_FIFO_CTRL|REG_SB_CTRL, rec_format | 0x80);
183 }
184
185 /* Stop the channel (### STOP_CHANNEL ###) */
dev_stop_channel(u32_t * base,int sub_dev)186 static void dev_stop_channel(u32_t *base, int sub_dev) {
187 u32_t base0 = base[0];
188 if (sub_dev == DAC) {
189 dev_command(base0, CMD_BIT16_DMA_OFF);
190 dev_command(base0, CMD_BIT8_DMA_OFF);
191 }
192 else if (sub_dev == ADC)
193 dev_mixer_write(base, REG_SB_FIFO_CTRL | REG_SB_CTRL, 0x00);
194 }
195
196 /* Set DMA address and length (### SET_DMA ###) */
dev_set_dma(u32_t * base,u32_t dma,u32_t len,int sub_dev)197 static void dev_set_dma(u32_t *base, u32_t dma, u32_t len, int sub_dev) {
198 u32_t base0 = base[0];
199 if (sub_dev == DAC) {
200 dev_gcr_write(base0, REG_DAC_DMA_ADDR, dma);
201 dev_gcr_write(base0, REG_DAC_DMA_LEN, (len - 1) | 0x180000);
202 }
203 else if (sub_dev == ADC) {
204 dev_gcr_write(base0, REG_ADC_DMA_ADDR, dma);
205 dev_gcr_write(base0, REG_ADC_DMA_LEN, len - 1);
206 }
207 }
208
209 /* Read current address (### READ_DMA_CURRENT_ADDR ###) */
dev_read_dma_current(u32_t * base,int sub_dev)210 static u32_t dev_read_dma_current(u32_t *base, int sub_dev) {
211 u32_t data, base0 = base[0];
212 if (sub_dev == DAC)
213 data = dev_gcr_read(base0, REG_DAC_CUR_ADDR);
214 else if (sub_dev == ADC)
215 data = dev_gcr_read(base0, REG_ADC_CUR_ADDR);
216 return data & 0xffff;
217 }
218
219 /* Pause the DMA (### PAUSE_DMA ###) */
dev_pause_dma(u32_t * base,int sub_dev)220 static void dev_pause_dma(u32_t *base, int sub_dev) {
221 u32_t base0 = base[0];
222 if (sub_dev == DAC) {
223 dev_command(base0, CMD_BIT16_DMA_OFF);
224 dev_command(base0, CMD_BIT8_DMA_OFF);
225 }
226 else if (sub_dev == ADC)
227 dev_mixer_write(base, REG_SB_FIFO_CTRL | REG_SB_CTRL, 0x00);
228 }
229
230 /* Resume the DMA (### RESUME_DMA ###) */
dev_resume_dma(u32_t * base,int sub_dev)231 static void dev_resume_dma(u32_t *base, int sub_dev) {
232 u32_t base0 = base[0];
233 if (sub_dev == DAC) {
234 dev_command(base0, CMD_BIT16_DMA_ON);
235 dev_command(base0, CMD_BIT8_DMA_ON);
236 }
237 else if (sub_dev == ADC)
238 dev_mixer_write(base, REG_SB_FIFO_CTRL|REG_SB_CTRL, rec_format | 0x80);
239 }
240
241 /* Read and clear interrupt status (### READ_CLEAR_INTR_STS ###)
242 * -- Return interrupt status */
dev_read_clear_intr_status(u32_t * base)243 static u32_t dev_read_clear_intr_status(u32_t *base) {
244 u32_t data, status, base0 = base[0];
245 status = sdr_in8(base0, REG_INTR_STS);
246 sdr_out8(base0, REG_INTR_STS, status);
247 data = dev_mixer_read(base, REG_SB_IRQ_STATUS);
248 if (data & 0x02)
249 sdr_in8(base0 + REG_SB_BASE, 0x0f);
250 else if (data & 0x01)
251 sdr_in8(base0 + REG_SB_BASE, 0x0e);
252 else if (data & 0x20)
253 sdr_in8(base0, 0x16);
254 return status;
255 }
256
257 /* Enable or disable interrupt (### INTR_ENABLE_DISABLE ###) */
dev_intr_enable(u32_t * base,int flag)258 static void dev_intr_enable(u32_t *base, int flag) {
259 u32_t data, base0 = base[0];
260 data = dev_gcr_read(base0, REG_INTR_CTRL);
261 if (flag == INTR_ENABLE)
262 dev_gcr_write(base0, REG_INTR_CTRL, data | CMD_INTR_ENABLE);
263 else if (flag == INTR_DISABLE)
264 dev_gcr_write(base0, REG_INTR_CTRL, data & ~CMD_INTR_ENABLE);
265 }
266
267 /* ======= Common driver function ======= */
268 /* Probe the device */
dev_probe(void)269 static int dev_probe(void) {
270 int devind, i, ioflag;
271 u32_t device, bar, size, base;
272 u16_t vid, did, temp;
273 u8_t *reg;
274
275 pci_init();
276 device = pci_first_dev(&devind, &vid, &did);
277 while (device > 0) {
278 if (vid == VENDOR_ID && did == DEVICE_ID)
279 break;
280 device = pci_next_dev(&devind, &vid, &did);
281 }
282 if (vid != VENDOR_ID || did != DEVICE_ID)
283 return EIO;
284 pci_reserve(devind);
285
286 for (i = 0; i < 6; i++)
287 dev.base[i] = 0;
288 #ifdef DMA_BASE_IOMAP
289 for (i = 0; i < 6; i++) {
290 if (pci_get_bar(devind, PCI_BAR + i * 4, &base, &size, &ioflag)) {
291 /* printf("SDR: Fail to get PCI BAR %d\n", i); */
292 continue;
293 }
294 if (ioflag) {
295 /* printf("SDR: PCI BAR %d is not for memory\n", i); */
296 continue;
297 }
298 if ((reg = vm_map_phys(SELF, (void *)base, size)) == MAP_FAILED) {
299 printf("SDR: Fail to map hardware registers from PCI\n");
300 return -EIO;
301 }
302 dev.base[i] = (u32_t)reg;
303 }
304 #else
305 /* Get PCI BAR0-5 */
306 for (i = 0; i < 6; i++)
307 dev.base[i] = pci_attr_r32(devind, PCI_BAR + i * 4) & 0xffffffe0;
308 #endif
309 dev.name = pci_dev_name(vid, did);
310 dev.irq = pci_attr_r8(devind, PCI_ILR);
311 dev.revision = pci_attr_r8(devind, PCI_REV);
312 dev.did = did;
313 dev.vid = vid;
314 dev.devind = devind;
315 temp = pci_attr_r16(devind, PCI_CR);
316 pci_attr_w16(devind, PCI_CR, temp | 0x105);
317
318 #ifdef MY_DEBUG
319 printf("SDR: Hardware name is %s\n", dev.name);
320 for (i = 0; i < 6; i++)
321 printf("SDR: PCI BAR%d is 0x%08x\n", i, dev.base[i]);
322 printf("SDR: IRQ number is 0x%02x\n", dev.irq);
323 #endif
324 return OK;
325 }
326
327 /* Set sample rate in configuration */
set_sample_rate(u32_t rate,int num)328 static int set_sample_rate(u32_t rate, int num) {
329 aud_conf[num].sample_rate = rate;
330 return OK;
331 }
332
333 /* Set stereo in configuration */
set_stereo(u32_t stereo,int num)334 static int set_stereo(u32_t stereo, int num) {
335 aud_conf[num].stereo = stereo;
336 return OK;
337 }
338
339 /* Set sample bits in configuration */
set_bits(u32_t bits,int num)340 static int set_bits(u32_t bits, int num) {
341 aud_conf[num].nr_of_bits = bits;
342 return OK;
343 }
344
345 /* Set fragment size in configuration */
set_frag_size(u32_t frag_size,int num)346 static int set_frag_size(u32_t frag_size, int num) {
347 if (frag_size > (sub_dev[num].DmaSize / sub_dev[num].NrOfDmaFragments) ||
348 frag_size < sub_dev[num].MinFragmentSize) {
349 return EINVAL;
350 }
351 aud_conf[num].fragment_size = frag_size;
352 return OK;
353 }
354
355 /* Set frame sign in configuration */
set_sign(u32_t val,int num)356 static int set_sign(u32_t val, int num) {
357 aud_conf[num].sign = val;
358 return OK;
359 }
360
361 /* Get maximum fragment size */
get_max_frag_size(u32_t * val,int * len,int num)362 static int get_max_frag_size(u32_t *val, int *len, int num) {
363 *len = sizeof(*val);
364 *val = (sub_dev[num].DmaSize / sub_dev[num].NrOfDmaFragments);
365 return OK;
366 }
367
368 /* Return 1 if there are free buffers */
free_buf(u32_t * val,int * len,int num)369 static int free_buf(u32_t *val, int *len, int num) {
370 *len = sizeof(*val);
371 if (sub_dev[num].BufLength == sub_dev[num].NrOfExtraBuffers)
372 *val = 0;
373 else
374 *val = 1;
375 return OK;
376 }
377
378 /* Get the current sample counter */
get_samples_in_buf(u32_t * result,int * len,int chan)379 static int get_samples_in_buf(u32_t *result, int *len, int chan) {
380 u32_t res;
381 /* READ_DMA_CURRENT_ADDR */
382 res = dev_read_dma_current(dev.base, chan);
383 *result = (u32_t)(sub_dev[chan].BufLength * 8192) + res;
384 return OK;
385 }
386
387 /* ======= [Audio interface] Initialize data structure ======= */
drv_init(void)388 int drv_init(void) {
389 drv.DriverName = DRIVER_NAME;
390 drv.NrOfSubDevices = 3;
391 drv.NrOfSpecialFiles = 3;
392
393 sub_dev[DAC].readable = 0;
394 sub_dev[DAC].writable = 1;
395 sub_dev[DAC].DmaSize = 64 * 1024;
396 sub_dev[DAC].NrOfDmaFragments = 2;
397 sub_dev[DAC].MinFragmentSize = 1024;
398 sub_dev[DAC].NrOfExtraBuffers = 4;
399
400 sub_dev[ADC].readable = 1;
401 sub_dev[ADC].writable = 0;
402 sub_dev[ADC].DmaSize = 64 * 1024;
403 sub_dev[ADC].NrOfDmaFragments = 2;
404 sub_dev[ADC].MinFragmentSize = 1024;
405 sub_dev[ADC].NrOfExtraBuffers = 4;
406
407 sub_dev[MIX].writable = 0;
408 sub_dev[MIX].readable = 0;
409
410 special_file[0].minor_dev_nr = 0;
411 special_file[0].write_chan = DAC;
412 special_file[0].read_chan = NO_CHANNEL;
413 special_file[0].io_ctl = DAC;
414
415 special_file[1].minor_dev_nr = 1;
416 special_file[1].write_chan = NO_CHANNEL;
417 special_file[1].read_chan = ADC;
418 special_file[1].io_ctl = ADC;
419
420 special_file[2].minor_dev_nr = 2;
421 special_file[2].write_chan = NO_CHANNEL;
422 special_file[2].read_chan = NO_CHANNEL;
423 special_file[2].io_ctl = MIX;
424
425 return OK;
426 }
427
428 /* ======= [Audio interface] Initialize hardware ======= */
drv_init_hw(void)429 int drv_init_hw(void) {
430 int i;
431
432 /* Match the device */
433 if (dev_probe()) {
434 printf("SDR: No sound card found\n");
435 return EIO;
436 }
437
438 /* Reset the device */
439 /* ### RESET_HARDWARE_CAN_FAIL ### */
440 if (dev_reset(dev.base)) {
441 printf("SDR: Fail to reset the device\n");
442 return EIO;
443 }
444
445 /* Configure the hardware */
446 /* ### CONF_HARDWARE ### */
447 dev_configure(dev.base);
448
449 /* Initialize the mixer */
450 /* ### INIT_MIXER ### */
451 dev_init_mixer(dev.base);
452
453 /* Set default mixer volume */
454 dev_set_default_volume(dev.base);
455
456 /* Initialize subdevice data */
457 for (i = 0; i < drv.NrOfSubDevices; i++) {
458 if (i == MIX)
459 continue;
460 aud_conf[i].busy = 0;
461 aud_conf[i].stereo = 1;
462 aud_conf[i].sample_rate = 44100;
463 aud_conf[i].nr_of_bits = 16;
464 aud_conf[i].sign = 1;
465 aud_conf[i].fragment_size =
466 sub_dev[i].DmaSize / sub_dev[i].NrOfDmaFragments;
467 }
468 return OK;
469 }
470
471 /* ======= [Audio interface] Driver reset =======*/
drv_reset(void)472 int drv_reset(void) {
473 /* ### RESET_HARDWARE_CAN_FAIL ### */
474 return dev_reset(dev.base);
475 }
476
477 /* ======= [Audio interface] Driver start ======= */
drv_start(int sub_dev,int DmaMode)478 int drv_start(int sub_dev, int DmaMode) {
479 int sample_count;
480
481 /* Set DAC and ADC sample rate */
482 /* ### SET_SAMPLE_RATE ### */
483 dev_set_sample_rate(dev.base, aud_conf[sub_dev].sample_rate);
484
485 sample_count = aud_conf[sub_dev].fragment_size;
486 #ifdef DMA_LENGTH_BY_FRAME
487 sample_count = sample_count / (aud_conf[sub_dev].nr_of_bits * (aud_conf[sub_dev].stereo + 1) / 8);
488 #endif
489 /* Set DAC and ADC format */
490 /* ### SET_FORMAT ### */
491 dev_set_format(dev.base, aud_conf[sub_dev].nr_of_bits,
492 aud_conf[sub_dev].sign, aud_conf[sub_dev].stereo, sample_count);
493
494 drv_reenable_int(sub_dev);
495
496 /* Start the channel */
497 /* ### START_CHANNEL ### */
498 dev_start_channel(dev.base, sub_dev);
499 aud_conf[sub_dev].busy = 1;
500
501 return OK;
502 }
503
504 /* ======= [Audio interface] Driver start ======= */
drv_stop(int sub_dev)505 int drv_stop(int sub_dev) {
506 u32_t data;
507
508 /* INTR_ENABLE_DISABLE */
509 dev_intr_enable(dev.base, INTR_DISABLE);
510
511 /* ### STOP_CHANNEL ### */
512 dev_stop_channel(dev.base, sub_dev);
513
514 aud_conf[sub_dev].busy = 0;
515 return OK;
516 }
517
518 /* ======= [Audio interface] Enable interrupt ======= */
drv_reenable_int(int chan)519 int drv_reenable_int(int chan) {
520 /* INTR_ENABLE_DISABLE */
521 dev_intr_enable(dev.base, INTR_ENABLE);
522 return OK;
523 }
524
525 /* ======= [Audio interface] I/O control ======= */
drv_io_ctl(unsigned long request,void * val,int * len,int sub_dev)526 int drv_io_ctl(unsigned long request, void *val, int *len, int sub_dev) {
527 int status;
528 switch (request) {
529 case DSPIORATE:
530 status = set_sample_rate(*((u32_t *)val), sub_dev);
531 break;
532 case DSPIOSTEREO:
533 status = set_stereo(*((u32_t *)val), sub_dev);
534 break;
535 case DSPIOBITS:
536 status = set_bits(*((u32_t *)val), sub_dev);
537 break;
538 case DSPIOSIZE:
539 status = set_frag_size(*((u32_t *)val), sub_dev);
540 break;
541 case DSPIOSIGN:
542 status = set_sign(*((u32_t *)val), sub_dev);
543 break;
544 case DSPIOMAX:
545 status = get_max_frag_size(val, len, sub_dev);
546 break;
547 case DSPIORESET:
548 status = drv_reset();
549 break;
550 case DSPIOFREEBUF:
551 status = free_buf(val, len, sub_dev);
552 break;
553 case DSPIOSAMPLESINBUF:
554 status = get_samples_in_buf(val, len, sub_dev);
555 break;
556 case DSPIOPAUSE:
557 status = drv_pause(sub_dev);
558 break;
559 case DSPIORESUME:
560 status = drv_resume(sub_dev);
561 break;
562 case MIXIOGETVOLUME:
563 /* ### GET_SET_VOLUME ### */
564 status = get_set_volume(dev.base, val, GET_VOL);
565 break;
566 case MIXIOSETVOLUME:
567 /* ### GET_SET_VOLUME ### */
568 status = get_set_volume(dev.base, val, SET_VOL);
569 break;
570 default:
571 status = EINVAL;
572 break;
573 }
574 return status;
575 }
576
577 /* ======= [Audio interface] Get request number ======= */
drv_get_irq(char * irq)578 int drv_get_irq(char *irq) {
579 *irq = dev.irq;
580 return OK;
581 }
582
583 /* ======= [Audio interface] Get fragment size ======= */
drv_get_frag_size(u32_t * frag_size,int sub_dev)584 int drv_get_frag_size(u32_t *frag_size, int sub_dev) {
585 *frag_size = aud_conf[sub_dev].fragment_size;
586 return OK;
587 }
588
589 /* ======= [Audio interface] Set DMA channel ======= */
drv_set_dma(u32_t dma,u32_t length,int chan)590 int drv_set_dma(u32_t dma, u32_t length, int chan) {
591 #ifdef DMA_LENGTH_BY_FRAME
592 length = length / (aud_conf[chan].nr_of_bits * (aud_conf[chan].stereo + 1) / 8);
593 #endif
594 /* ### SET_DMA ### */
595 dev_set_dma(dev.base, dma, length, chan);
596 return OK;
597 }
598
599 /* ======= [Audio interface] Get interrupt summary status ======= */
drv_int_sum(void)600 int drv_int_sum(void) {
601 u32_t status;
602 /* ### READ_CLEAR_INTR_STS ### */
603 status = dev_read_clear_intr_status(dev.base);
604 dev.intr_status = status;
605 #ifdef MY_DEBUG
606 printf("SDR: Interrupt status is 0x%08x\n", status);
607 #endif
608 return (status & (INTR_STS_DAC | INTR_STS_ADC));
609 }
610
611 /* ======= [Audio interface] Handle interrupt status ======= */
drv_int(int sub_dev)612 int drv_int(int sub_dev) {
613 u32_t mask;
614
615 /* ### CHECK_INTR_DAC ### */
616 if (sub_dev == DAC)
617 mask = INTR_STS_DAC;
618 /* ### CHECK_INTR_ADC ### */
619 else if (sub_dev == ADC)
620 mask = INTR_STS_ADC;
621 else
622 return 0;
623
624 return dev.intr_status & mask;
625 }
626
627 /* ======= [Audio interface] Pause DMA ======= */
drv_pause(int sub_dev)628 int drv_pause(int sub_dev) {
629 /* ### PAUSE_DMA ### */
630 dev_pause_dma(dev.base, sub_dev);
631 return OK;
632 }
633
634 /* ======= [Audio interface] Resume DMA ======= */
drv_resume(int sub_dev)635 int drv_resume(int sub_dev) {
636 /* ### RESUME_DMA ### */
637 dev_resume_dma(dev.base, sub_dev);
638 return OK;
639 }
640