1# $NetBSD: Makefile,v 1.14 2015/01/29 20:41:35 joerg Exp $ 2 3LIB= LLVMARMCodeGen 4 5.include <bsd.init.mk> 6 7.PATH: ${LLVM_SRCDIR}/lib/Target/ARM 8 9SRCS+= ARMAsmPrinter.cpp \ 10 ARMBaseInstrInfo.cpp \ 11 ARMBaseRegisterInfo.cpp \ 12 ARMConstantIslandPass.cpp \ 13 ARMConstantPoolValue.cpp \ 14 ARMExpandPseudoInsts.cpp \ 15 ARMFastISel.cpp \ 16 ARMFrameLowering.cpp \ 17 ARMHazardRecognizer.cpp \ 18 ARMISelDAGToDAG.cpp \ 19 ARMISelLowering.cpp \ 20 ARMInstrInfo.cpp \ 21 ARMLoadStoreOptimizer.cpp \ 22 ARMMCInstLower.cpp \ 23 ARMMachineFunctionInfo.cpp \ 24 ARMOptimizeBarriersPass.cpp \ 25 ARMRegisterInfo.cpp \ 26 ARMSelectionDAGInfo.cpp \ 27 ARMSubtarget.cpp \ 28 ARMTargetMachine.cpp \ 29 ARMTargetObjectFile.cpp \ 30 ARMTargetTransformInfo.cpp \ 31 A15SDOptimizer.cpp \ 32 MLxExpansionPass.cpp \ 33 Thumb1InstrInfo.cpp \ 34 Thumb1FrameLowering.cpp \ 35 Thumb1RegisterInfo.cpp \ 36 Thumb2ITBlockPass.cpp \ 37 Thumb2InstrInfo.cpp \ 38 Thumb2RegisterInfo.cpp \ 39 Thumb2SizeReduction.cpp 40 41TABLEGEN_SRC= ARM.td 42TABLEGEN_INCLUDES= -I${LLVM_SRCDIR}/lib/Target/ARM 43TABLEGEN_OUTPUT= \ 44 ARMGenRegisterInfo.inc|-gen-register-info \ 45 ARMGenInstrInfo.inc|-gen-instr-info \ 46 ARMGenCodeEmitter.inc|-gen-emitter \ 47 ARMGenMCCodeEmitter.inc|-gen-emitter \ 48 ARMGenMCPseudoLowering.inc|-gen-pseudo-lowering \ 49 ARMGenAsmWriter.inc|-gen-asm-writer \ 50 ARMGenAsmMatcher.inc|-gen-asm-matcher \ 51 ARMGenDAGISel.inc|-gen-dag-isel \ 52 ARMGenFastISel.inc|-gen-fast-isel \ 53 ARMGenCallingConv.inc|-gen-callingconv \ 54 ARMGenSubtargetInfo.inc|-gen-subtarget \ 55 ARMGenDisassemblerTables.inc|-gen-disassembler 56 57.include "${.PARSEDIR}/../../tablegen.mk" 58 59.if defined(HOSTLIB) 60.include <bsd.hostlib.mk> 61.else 62.include <bsd.lib.mk> 63.endif 64