1{
2   "arrays" : [
3      {
4         "name" : "MemRef_tmp4",
5         "sizes" : [ "*" ],
6         "type" : "i32"
7      },
8      {
9         "name" : "MemRef__pn",
10         "sizes" : [ "*" ],
11         "type" : "i32"
12      }
13   ],
14   "context" : "[tmp5] -> {  : -2147483648 <= tmp5 <= 2147483647 }",
15   "name" : "%for.body344---%if.then.i.i1141.loopexit",
16   "statements" : [
17      {
18         "accesses" : [
19            {
20               "kind" : "write",
21               "relation" : "[tmp5] -> { Stmt_for_body344[-1 + tmp5] -> MemRef__pn[-1 + tmp5] }"
22            }
23         ],
24         "domain" : "[tmp5] -> { Stmt_for_body344[i0] : 0 <= i0 < tmp5; Stmt_for_body344[0] : tmp5 <= 0 }",
25         "name" : "Stmt_for_body344",
26         "schedule" : "[tmp5] -> { Stmt_for_body344[i0] -> [i0, 0] : i0 < tmp5; Stmt_for_body344[0] -> [0, 0] : tmp5 <= 0 }"
27      },
28      {
29         "accesses" : [
30            {
31               "kind" : "read",
32               "relation" : "[tmp5] -> { Stmt_cond_false[i0] -> MemRef_tmp4[1 + i0] }"
33            },
34            {
35               "kind" : "write",
36               "relation" : "[tmp5] -> { Stmt_cond_false[i0] -> MemRef__pn[i0] : i0 <= -2 + tmp5; Stmt_cond_false[0] -> MemRef__pn[0] : tmp5 <= 0 }"
37            }
38         ],
39         "domain" : "[tmp5] -> { Stmt_cond_false[i0] : 0 <= i0 <= -2 + tmp5; Stmt_cond_false[0] : tmp5 <= 0 }",
40         "name" : "Stmt_cond_false",
41         "schedule" : "[tmp5] -> { Stmt_cond_false[i0] -> [i0, 1] : i0 <= -2 + tmp5; Stmt_cond_false[0] -> [0, 1] : tmp5 <= 0 }"
42      },
43      {
44         "accesses" : [
45            {
46               "kind" : "read",
47               "relation" : "[tmp5] -> { Stmt_cond_end[i0] -> MemRef__pn[i0] }"
48            },
49            {
50               "kind" : "write",
51               "relation" : "[tmp5] -> { Stmt_cond_end[i0] -> MemRef__pn[i0] }"
52            }
53         ],
54         "domain" : "[tmp5] -> { Stmt_cond_end[i0] : 0 <= i0 < tmp5; Stmt_cond_end[0] : tmp5 <= 0 }",
55         "name" : "Stmt_cond_end",
56         "schedule" : "[tmp5] -> { Stmt_cond_end[i0] -> [i0, 2] : i0 < tmp5; Stmt_cond_end[0] -> [0, 2] : tmp5 <= 0 }"
57      }
58   ]
59}
60