1{
2   "arrays" : [
3      {
4         "name" : "MemRef_ATH",
5         "sizes" : [ "*" ],
6         "type" : "float"
7      },
8      {
9         "name" : "MemRef_ath",
10         "sizes" : [ "*" ],
11         "type" : "float"
12      }
13   ],
14   "context" : "[p_0] -> {  : 0 <= p_0 <= 16 }",
15   "name" : "%for.cond7.preheader---%for.cond33.preheader",
16   "statements" : [
17      {
18         "accesses" : [
19            {
20               "kind" : "read",
21               "relation" : "[p_0] -> { Stmt_for_cond7_preheader[i0] -> MemRef_ATH[0] }"
22            },
23            {
24               "kind" : "write",
25               "relation" : "[p_0] -> { Stmt_for_cond7_preheader[i0] -> MemRef_tmp157[] }"
26            }
27         ],
28         "domain" : "[p_0] -> { Stmt_for_cond7_preheader[i0] : 0 <= i0 <= 55 }",
29         "name" : "Stmt_for_cond7_preheader",
30         "schedule" : "[p_0] -> { Stmt_for_cond7_preheader[i0] -> [i0, 0] }"
31      },
32      {
33         "accesses" : [
34            {
35               "kind" : "write",
36               "relation" : "[p_0] -> { Stmt_if_then_3[i0] -> MemRef_min_1_3__phi[] }"
37            }
38         ],
39         "domain" : "[p_0] -> { Stmt_if_then_3[i0] : 0 <= i0 <= 84 - 4p_0 and i0 <= 55 }",
40         "name" : "Stmt_if_then_3",
41         "schedule" : "[p_0] -> { Stmt_if_then_3[i0] -> [i0, 2] }"
42      },
43      {
44         "accesses" : [
45            {
46               "kind" : "read",
47               "relation" : "[p_0] -> { Stmt_if_else_3[i0] -> MemRef_tmp157[] }"
48            },
49            {
50               "kind" : "write",
51               "relation" : "[p_0] -> { Stmt_if_else_3[i0] -> MemRef_min_1_3__phi[] }"
52            }
53         ],
54         "domain" : "[p_0] -> { Stmt_if_else_3[i0] : 85 - 4p_0 <= i0 <= 55 }",
55         "name" : "Stmt_if_else_3",
56         "schedule" : "[p_0] -> { Stmt_if_else_3[i0] -> [i0, 1] }"
57      },
58      {
59         "accesses" : [
60            {
61               "kind" : "read",
62               "relation" : "[p_0] -> { Stmt_for_inc_3[i0] -> MemRef_min_1_3__phi[] }"
63            },
64            {
65               "kind" : "write",
66               "relation" : "[p_0] -> { Stmt_for_inc_3[i0] -> MemRef_ath[i0] }"
67            }
68         ],
69         "domain" : "[p_0] -> { Stmt_for_inc_3[i0] : 0 <= i0 <= 55 }",
70         "name" : "Stmt_for_inc_3",
71         "schedule" : "[p_0] -> { Stmt_for_inc_3[i0] -> [i0, 3] }"
72      }
73   ]
74}
75