xref: /llvm-project/polly/test/CodeGen/MemAccess/simple___%for.cond---%for.end.jscop.transformed (revision 35f7020098773816f151c2c1da7b4dfc11041126) 
1{
2   "context" : "{  :  }",
3   "name" : "for.cond => for.end",
4   "statements" : [
5      {
6         "accesses" : [
7            {
8               "kind" : "write",
9               "relation" : "{ Stmt_for_body[i0] -> MemRef_A[0] }"
10            }
11         ],
12         "domain" : "{ Stmt_for_body[i0] : i0 >= 0 and i0 <= 11 }",
13         "name" : "Stmt_for_body",
14         "schedule" : "{ Stmt_for_body[i0] -> [0, i0, 0] }"
15      }
16   ]
17}
18