xref: /llvm-project/mlir/test/Target/LLVMIR/vcix-rv64.mlir (revision 9f6c00565a82fc375d415804d54da1113f719b17) 
1// RUN: mlir-translate --mlir-to-llvmir %s | FileCheck %s
2
3
4// CHECK-LABEL: define <vscale x 4 x float> @binary_fv(<vscale x 4 x float> %0, float %1, i64 %2) {
5// CHECK-NEXT:   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vc.v.fv.se.nxv4f32.i64.nxv4f32.f32.i64(i64 1, <vscale x 4 x float> %0, float %1, i64 %2)
6// CHECK-NEXT:   ret <vscale x 4 x float> %4
7// CHECK-NEXT: }
8llvm.func @binary_fv(%arg0: vector<[4]xf32>, %arg1: f32, %vl: i64) -> vector<[4]xf32> {
9  %0 = "vcix.v.sv"(%arg0, %arg1, %vl) <{opcode = 1 : i64}> : (vector<[4]xf32>, f32, i64) -> vector<[4]xf32>
10  llvm.return %0 : vector<[4]xf32>
11}
12
13// -----
14
15// CHECK-LABEL: define <vscale x 4 x float> @binary_xv(<vscale x 4 x float> %0, i64 %1, i64 %2) {
16// CHECK-NEXT:   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vc.v.xv.se.nxv4f32.i64.nxv4f32.i64.i64(i64 3, <vscale x 4 x float> %0, i64 %1, i64 %2)
17// CHECK-NEXT:   ret <vscale x 4 x float> %4
18// CHECK-NEXT: }
19llvm.func @binary_xv(%arg0: vector<[4]xf32>, %arg1: i64, %vl: i64) -> vector<[4]xf32> {
20  %0 = "vcix.v.sv"(%arg0, %arg1, %vl) <{opcode = 3 : i64}> : (vector<[4]xf32>, i64, i64) -> vector<[4]xf32>
21  llvm.return %0 : vector<[4]xf32>
22}
23
24// -----
25
26// CHECK-LABEL: define <vscale x 4 x float> @binary_vv(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) {
27// CHECK-NEXT:   %4 = call <vscale x 4 x float> @llvm.riscv.sf.vc.v.vv.se.nxv4f32.i64.nxv4f32.nxv4f32.i64(i64 3, <vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2)
28// CHECK-NEXT:   ret <vscale x 4 x float> %4
29// CHECK-NEXT: }
30llvm.func @binary_vv(%arg0: vector<[4]xf32>, %arg1: vector<[4]xf32>, %vl: i64) -> vector<[4]xf32> {
31  %0 = "vcix.v.sv"(%arg0, %arg1, %vl) <{opcode = 3 : i64}> : (vector<[4]xf32>, vector<[4]xf32>, i64) -> vector<[4]xf32>
32  llvm.return %0 : vector<[4]xf32>
33}
34
35// -----
36
37// CHECK-LABEL: define <vscale x 4 x float> @binary_iv(<vscale x 4 x float> %0, i64 %1) {
38// CHECK-NEXT:   %3 = call <vscale x 4 x float> @llvm.riscv.sf.vc.v.iv.se.nxv4f32.i64.nxv4f32.i64.i64(i64 3, <vscale x 4 x float> %0, i64 5, i64 %1)
39// CHECK-NEXT:   ret <vscale x 4 x float> %3
40// CHECK-NEXT: }
41llvm.func @binary_iv(%arg0: vector<[4]xf32>, %vl: i64) -> vector<[4]xf32> {
42  %0 = "vcix.v.iv"(%arg0, %vl) <{opcode = 3 : i64, imm = 5 : i64}> : (vector<[4]xf32>, i64) -> vector<[4]xf32>
43  llvm.return %0 : vector<[4]xf32>
44}
45
46// -----
47
48// CHECK: define <4 x float> @binary_fixed_fv(<4 x float> %0, float %1) {
49// CHECK-NEXT:   %3 = call <4 x float> @llvm.riscv.sf.vc.v.fv.se.v4f32.i64.v4f32.f32.i64(i64 1, <4 x float> %0, float %1, i64 4)
50// CHECK-NEXT:   ret <4 x float> %3
51// CHECK-NEXT: }
52llvm.func @binary_fixed_fv(%arg0: vector<4xf32>, %arg1: f32) -> vector<4xf32> {
53  %0 = "vcix.v.sv"(%arg0, %arg1) <{opcode = 1 : i64}> : (vector<4xf32>, f32) -> vector<4xf32>
54  llvm.return %0 : vector<4xf32>
55}
56
57// -----
58
59// CHECK-LABEL: define <4 x float> @binary_fixed_xv(<4 x float> %0, i64 %1) {
60// CHECK-NEXT:   %3 = call <4 x float> @llvm.riscv.sf.vc.v.xv.se.v4f32.i64.v4f32.i64.i64(i64 3, <4 x float> %0, i64 %1, i64 4)
61// CHECK-NEXT:   ret <4 x float> %3
62// CHECK-NEXT: }
63llvm.func @binary_fixed_xv(%arg0: vector<4xf32>, %arg1: i64) -> vector<4xf32> {
64  %0 = "vcix.v.sv"(%arg0, %arg1) <{opcode = 3 : i64}> : (vector<4xf32>, i64) -> vector<4xf32>
65  llvm.return %0 : vector<4xf32>
66}
67
68// -----
69
70// CHECK-LABEL: define <4 x float> @binary_fixed_vv(<4 x float> %0, <4 x float> %1) {
71// CHECK-NEXT:   %3 = call <4 x float> @llvm.riscv.sf.vc.v.vv.se.v4f32.i64.v4f32.v4f32.i64(i64 3, <4 x float> %0, <4 x float> %1, i64 4)
72// CHECK-NEXT:   ret <4 x float> %3
73// CHECK-NEXT: }
74llvm.func @binary_fixed_vv(%arg0: vector<4xf32>, %arg1: vector<4xf32>) -> vector<4xf32> {
75  %0 = "vcix.v.sv"(%arg0, %arg1) <{opcode = 3 : i64}> : (vector<4xf32>, vector<4xf32>) -> vector<4xf32>
76  llvm.return %0 : vector<4xf32>
77}
78
79// -----
80
81// CHECK-LABEL: define <4 x float> @binary_fixed_iv(<4 x float> %0) {
82// CHECK-NEXT:   %2 = call <4 x float> @llvm.riscv.sf.vc.v.iv.se.v4f32.i64.v4f32.i64.i64(i64 3, <4 x float> %0, i64 5, i64 4)
83// CHECK-NEXT:   ret <4 x float> %2
84// CHECK-NEXT: }
85llvm.func @binary_fixed_iv(%arg0: vector<4xf32>) -> vector<4xf32> {
86  %0 = "vcix.v.iv"(%arg0) <{opcode = 3 : i64, imm = 5 : i64}> : (vector<4xf32>) -> vector<4xf32>
87  llvm.return %0 : vector<4xf32>
88}
89
90// Test integer type
91
92// -----
93
94// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_fv(<vscale x 4 x i32> %0, float %1, i64 %2) {
95// CHECK-NEXT:   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.fv.se.nxv4i32.i64.nxv4i32.f32.i64(i64 1, <vscale x 4 x i32> %0, float %1, i64 %2)
96// CHECK-NEXT:   ret <vscale x 4 x i32> %4
97// CHECK-NEXT: }
98llvm.func @binary_i_fv(%arg0: vector<[4]xi32>, %arg1: f32, %vl: i64) -> vector<[4]xi32> {
99  %0 = "vcix.v.sv"(%arg0, %arg1, %vl) <{opcode = 1 : i64}> : (vector<[4]xi32>, f32, i64) -> vector<[4]xi32>
100  llvm.return %0 : vector<[4]xi32>
101}
102
103// -----
104
105// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_xv(<vscale x 4 x i32> %0, i64 %1, i64 %2) {
106// CHECK-NEXT:   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.xv.se.nxv4i32.i64.nxv4i32.i64.i64(i64 3, <vscale x 4 x i32> %0, i64 %1, i64 %2)
107// CHECK-NEXT:   ret <vscale x 4 x i32> %4
108// CHECK-NEXT: }
109llvm.func @binary_i_xv(%arg0: vector<[4]xi32>, %arg1: i64, %vl: i64) -> vector<[4]xi32> {
110  %0 = "vcix.v.sv"(%arg0, %arg1, %vl) <{opcode = 3 : i64}> : (vector<[4]xi32>, i64, i64) -> vector<[4]xi32>
111  llvm.return %0 : vector<[4]xi32>
112}
113
114// -----
115
116// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_vv(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) {
117// CHECK-NEXT:   %4 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.vv.se.nxv4i32.i64.nxv4i32.nxv4i32.i64(i64 3, <vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2)
118// CHECK-NEXT:   ret <vscale x 4 x i32> %4
119// CHECK-NEXT: }
120llvm.func @binary_i_vv(%arg0: vector<[4]xi32>, %arg1: vector<[4]xi32>, %vl: i64) -> vector<[4]xi32> {
121  %0 = "vcix.v.sv"(%arg0, %arg1, %vl) <{opcode = 3 : i64}> : (vector<[4]xi32>, vector<[4]xi32>, i64) -> vector<[4]xi32>
122  llvm.return %0 : vector<[4]xi32>
123}
124
125// -----
126
127// CHECK-LABEL: define <vscale x 4 x i32> @binary_i_iv(<vscale x 4 x i32> %0, i64 %1) {
128// CHECK-NEXT:   %3 = call <vscale x 4 x i32> @llvm.riscv.sf.vc.v.iv.se.nxv4i32.i64.nxv4i32.i64.i64(i64 3, <vscale x 4 x i32> %0, i64 5, i64 %1)
129// CHECK-NEXT:   ret <vscale x 4 x i32> %3
130// CHECK-NEXT: }
131llvm.func @binary_i_iv(%arg0: vector<[4]xi32>, %vl: i64) -> vector<[4]xi32> {
132  %0 = "vcix.v.iv"(%arg0, %vl) <{opcode = 3 : i64, imm = 5 : i64}> : (vector<[4]xi32>, i64) -> vector<[4]xi32>
133  llvm.return %0 : vector<[4]xi32>
134}
135
136// -----
137
138// CHECK: define <4 x i32> @binary_i_fixed_fv(<4 x i32> %0, float %1) {
139// CHECK-NEXT:   %3 = call <4 x i32> @llvm.riscv.sf.vc.v.fv.se.v4i32.i64.v4i32.f32.i64(i64 1, <4 x i32> %0, float %1, i64 4)
140// CHECK-NEXT:   ret <4 x i32> %3
141// CHECK-NEXT: }
142llvm.func @binary_i_fixed_fv(%arg0: vector<4xi32>, %arg1: f32) -> vector<4xi32> {
143  %0 = "vcix.v.sv"(%arg0, %arg1) <{opcode = 1 : i64}> : (vector<4xi32>, f32) -> vector<4xi32>
144  llvm.return %0 : vector<4xi32>
145}
146
147// -----
148
149// CHECK-LABEL: define <4 x i32> @binary_i_fixed_xv(<4 x i32> %0, i64 %1) {
150// CHECK-NEXT:   %3 = call <4 x i32> @llvm.riscv.sf.vc.v.xv.se.v4i32.i64.v4i32.i64.i64(i64 3, <4 x i32> %0, i64 %1, i64 4)
151// CHECK-NEXT:   ret <4 x i32> %3
152// CHECK-NEXT: }
153llvm.func @binary_i_fixed_xv(%arg0: vector<4xi32>, %arg1: i64) -> vector<4xi32> {
154  %0 = "vcix.v.sv"(%arg0, %arg1) <{opcode = 3 : i64}> : (vector<4xi32>, i64) -> vector<4xi32>
155  llvm.return %0 : vector<4xi32>
156}
157
158// -----
159
160// CHECK-LABEL: define <4 x i32> @binary_i_fixed_vv(<4 x i32> %0, <4 x i32> %1) {
161// CHECK-NEXT:   %3 = call <4 x i32> @llvm.riscv.sf.vc.v.vv.se.v4i32.i64.v4i32.v4i32.i64(i64 3, <4 x i32> %0, <4 x i32> %1, i64 4)
162// CHECK-NEXT:   ret <4 x i32> %3
163// CHECK-NEXT: }
164llvm.func @binary_i_fixed_vv(%arg0: vector<4xi32>, %arg1: vector<4xi32>) -> vector<4xi32> {
165  %0 = "vcix.v.sv"(%arg0, %arg1) <{opcode = 3 : i64}> : (vector<4xi32>, vector<4xi32>) -> vector<4xi32>
166  llvm.return %0 : vector<4xi32>
167}
168
169// -----
170
171// CHECK-LABEL: define <4 x i32> @binary_i_fixed_iv(<4 x i32> %0) {
172// CHECK-NEXT:   %2 = call <4 x i32> @llvm.riscv.sf.vc.v.iv.se.v4i32.i64.v4i32.i64.i64(i64 3, <4 x i32> %0, i64 5, i64 4)
173// CHECK-NEXT:   ret <4 x i32> %2
174// CHECK-NEXT: }
175llvm.func @binary_i_fixed_iv(%arg0: vector<4xi32>) -> vector<4xi32> {
176  %0 = "vcix.v.iv"(%arg0) <{opcode = 3 : i64, imm = 5 : i64}> : (vector<4xi32>) -> vector<4xi32>
177  llvm.return %0 : vector<4xi32>
178}
179