xref: /llvm-project/mlir/test/Dialect/ArmNeon/roundtrip.mlir (revision 16d890ced68aafae4cc8ba3efc9213bfab84ba54) 
1// RUN: mlir-opt -verify-diagnostics -split-input-file %s | mlir-opt | FileCheck %s
2
3// CHECK-LABEL: arm_neon_smull
4func.func @arm_neon_smull(%a: vector<8xi8>, %b: vector<8xi8>)
5    -> (vector<8xi16>, vector<4xi32>, vector<2xi64>) {
6  // CHECK: arm_neon.intr.smull {{.*}}: vector<8xi8> to vector<8xi16>
7  %0 = arm_neon.intr.smull %a, %b : vector<8xi8> to vector<8xi16>
8  %00 = vector.extract_strided_slice %0 {offsets = [3], sizes = [4], strides = [1]}:
9    vector<8xi16> to vector<4xi16>
10
11  // CHECK: arm_neon.intr.smull {{.*}}: vector<4xi16> to vector<4xi32>
12  %1 = arm_neon.intr.smull %00, %00 : vector<4xi16> to vector<4xi32>
13  %11 = vector.extract_strided_slice %1 {offsets = [1], sizes = [2], strides = [1]}:
14    vector<4xi32> to vector<2xi32>
15
16  // CHECK: arm_neon.intr.smull {{.*}}: vector<2xi32> to vector<2xi64>
17  %2 = arm_neon.intr.smull %11, %11 : vector<2xi32> to vector<2xi64>
18
19  return %0, %1, %2 : vector<8xi16>, vector<4xi32>, vector<2xi64>
20}
21
22// -----
23
24// CHECK-LABEL: arm_neon_sdot
25func.func @arm_neon_sdot(%a: vector<2xi32>, %b: vector<8xi8>, %c: vector<8xi8>) -> vector<2xi32> {
26  // CHECK: arm_neon.intr.sdot {{.*}}: vector<8xi8>, vector<8xi8> to vector<2xi32>
27  %0 = arm_neon.intr.sdot %a, %b, %c : vector<8xi8>, vector<8xi8> to vector<2xi32>
28  return %0 : vector<2xi32>
29}
30
31// -----
32
33// CHECK-LABEL: arm_neon_smmla
34func.func @arm_neon_smmla(%a: vector<16xi8>,
35                          %b: vector<16xi8>,
36                          %c: vector<4xi32>) -> vector<4xi32> {
37  // CHECK: arm_neon.intr.smmla {{.*}}: vector<16xi8> to vector<4xi32>
38  %0 = arm_neon.intr.smmla %c, %a, %b : vector<16xi8> to vector<4xi32>
39  return %0 : vector<4xi32>
40}
41
42// -----
43
44// CHECK-LABEL: arm_neon_ummla
45func.func @arm_neon_ummla(%a: vector<16xi8>,
46                          %b: vector<16xi8>,
47                          %c: vector<4xi32>) -> vector<4xi32> {
48  // CHECK: arm_neon.intr.ummla {{.*}}: vector<16xi8> to vector<4xi32>
49  %0 = arm_neon.intr.ummla %c, %a, %b : vector<16xi8> to vector<4xi32>
50  return %0 : vector<4xi32>
51}
52
53// -----
54
55// CHECK-LABEL: arm_neon_usmmla
56func.func @arm_neon_usmmla(%a: vector<16xi8>,
57                            %b: vector<16xi8>,
58                            %c: vector<4xi32>) -> vector<4xi32> {
59  // CHECK: arm_neon.intr.usmmla {{.*}}: vector<16xi8> to vector<4xi32>
60  %0 = arm_neon.intr.usmmla %c, %a, %b : vector<16xi8> to vector<4xi32>
61  return %0 : vector<4xi32>
62}
63