1 //===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "Common/CodeGenInstruction.h" 10 #include "Common/CodeGenTarget.h" 11 #include "llvm/ADT/IndexedMap.h" 12 #include "llvm/ADT/SmallVector.h" 13 #include "llvm/ADT/StringMap.h" 14 #include "llvm/Support/Debug.h" 15 #include "llvm/Support/ErrorHandling.h" 16 #include "llvm/TableGen/Error.h" 17 #include "llvm/TableGen/Record.h" 18 #include "llvm/TableGen/TGTimer.h" 19 #include "llvm/TableGen/TableGenBackend.h" 20 using namespace llvm; 21 22 #define DEBUG_TYPE "pseudo-lowering" 23 24 namespace { 25 class PseudoLoweringEmitter { 26 struct OpData { 27 enum MapKind { Operand, Imm, Reg }; 28 MapKind Kind; 29 union { 30 unsigned Operand; // Operand number mapped to. 31 uint64_t Imm; // Integer immedate value. 32 const Record *Reg; // Physical register. 33 } Data; 34 }; 35 struct PseudoExpansion { 36 CodeGenInstruction Source; // The source pseudo instruction definition. 37 CodeGenInstruction Dest; // The destination instruction to lower to. 38 IndexedMap<OpData> OperandMap; 39 40 PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d, 41 IndexedMap<OpData> &m) 42 : Source(s), Dest(d), OperandMap(m) {} 43 }; 44 45 const RecordKeeper &Records; 46 47 // It's overkill to have an instance of the full CodeGenTarget object, 48 // but it loads everything on demand, not in the constructor, so it's 49 // lightweight in performance, so it works out OK. 50 const CodeGenTarget Target; 51 52 SmallVector<PseudoExpansion, 64> Expansions; 53 54 unsigned addDagOperandMapping(const Record *Rec, const DagInit *Dag, 55 const CodeGenInstruction &Insn, 56 IndexedMap<OpData> &OperandMap, 57 unsigned BaseIdx); 58 void evaluateExpansion(const Record *Pseudo); 59 void emitLoweringEmitter(raw_ostream &o); 60 61 public: 62 PseudoLoweringEmitter(const RecordKeeper &R) : Records(R), Target(R) {} 63 64 /// run - Output the pseudo-lowerings. 65 void run(raw_ostream &o); 66 }; 67 } // End anonymous namespace 68 69 // FIXME: This pass currently can only expand a pseudo to a single instruction. 70 // The pseudo expansion really should take a list of dags, not just 71 // a single dag, so we can do fancier things. 72 unsigned PseudoLoweringEmitter::addDagOperandMapping( 73 const Record *Rec, const DagInit *Dag, const CodeGenInstruction &Insn, 74 IndexedMap<OpData> &OperandMap, unsigned BaseIdx) { 75 unsigned OpsAdded = 0; 76 for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) { 77 if (const DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i))) { 78 // Physical register reference. Explicit check for the special case 79 // "zero_reg" definition. 80 if (DI->getDef()->isSubClassOf("Register") || 81 DI->getDef()->getName() == "zero_reg") { 82 OperandMap[BaseIdx + i].Kind = OpData::Reg; 83 OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); 84 ++OpsAdded; 85 continue; 86 } 87 88 // Normal operands should always have the same type, or we have a 89 // problem. 90 // FIXME: We probably shouldn't ever get a non-zero BaseIdx here. 91 assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!"); 92 // FIXME: Are the message operand types backward? 93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) { 94 PrintError(Rec, "In pseudo instruction '" + Rec->getName() + 95 "', operand type '" + DI->getDef()->getName() + 96 "' does not match expansion operand type '" + 97 Insn.Operands[BaseIdx + i].Rec->getName() + "'"); 98 PrintFatalNote(DI->getDef(), 99 "Value was assigned at the following location:"); 100 } 101 // Source operand maps to destination operand. The Data element 102 // will be filled in later, just set the Kind for now. Do it 103 // for each corresponding MachineInstr operand, not just the first. 104 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) 105 OperandMap[BaseIdx + i + I].Kind = OpData::Operand; 106 OpsAdded += Insn.Operands[i].MINumOperands; 107 } else if (const IntInit *II = dyn_cast<IntInit>(Dag->getArg(i))) { 108 OperandMap[BaseIdx + i].Kind = OpData::Imm; 109 OperandMap[BaseIdx + i].Data.Imm = II->getValue(); 110 ++OpsAdded; 111 } else if (const auto *BI = dyn_cast<BitsInit>(Dag->getArg(i))) { 112 OperandMap[BaseIdx + i].Kind = OpData::Imm; 113 OperandMap[BaseIdx + i].Data.Imm = *BI->convertInitializerToInt(); 114 ++OpsAdded; 115 } else if (const DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) { 116 // Just add the operands recursively. This is almost certainly 117 // a constant value for a complex operand (> 1 MI operand). 118 unsigned NewOps = 119 addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i); 120 OpsAdded += NewOps; 121 // Since we added more than one, we also need to adjust the base. 122 BaseIdx += NewOps - 1; 123 } else 124 llvm_unreachable("Unhandled pseudo-expansion argument type!"); 125 } 126 return OpsAdded; 127 } 128 129 void PseudoLoweringEmitter::evaluateExpansion(const Record *Rec) { 130 LLVM_DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n"); 131 132 // Validate that the result pattern has the corrent number and types 133 // of arguments for the instruction it references. 134 const DagInit *Dag = Rec->getValueAsDag("ResultInst"); 135 assert(Dag && "Missing result instruction in pseudo expansion!"); 136 LLVM_DEBUG(dbgs() << " Result: " << *Dag << "\n"); 137 138 const DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator()); 139 if (!OpDef) { 140 PrintError(Rec, "In pseudo instruction '" + Rec->getName() + 141 "', result operator is not a record"); 142 PrintFatalNote(Rec->getValue("ResultInst"), 143 "Result was assigned at the following location:"); 144 } 145 const Record *Operator = OpDef->getDef(); 146 if (!Operator->isSubClassOf("Instruction")) { 147 PrintError(Rec, "In pseudo instruction '" + Rec->getName() + 148 "', result operator '" + Operator->getName() + 149 "' is not an instruction"); 150 PrintFatalNote(Rec->getValue("ResultInst"), 151 "Result was assigned at the following location:"); 152 } 153 154 CodeGenInstruction Insn(Operator); 155 156 if (Insn.isCodeGenOnly || Insn.isPseudo) { 157 PrintError(Rec, "In pseudo instruction '" + Rec->getName() + 158 "', result operator '" + Operator->getName() + 159 "' cannot be a pseudo instruction"); 160 PrintFatalNote(Rec->getValue("ResultInst"), 161 "Result was assigned at the following location:"); 162 } 163 164 if (Insn.Operands.size() != Dag->getNumArgs()) { 165 PrintError(Rec, "In pseudo instruction '" + Rec->getName() + 166 "', result operator '" + Operator->getName() + 167 "' has the wrong number of operands"); 168 PrintFatalNote(Rec->getValue("ResultInst"), 169 "Result was assigned at the following location:"); 170 } 171 172 unsigned NumMIOperands = 0; 173 for (const auto &Op : Insn.Operands) 174 NumMIOperands += Op.MINumOperands; 175 IndexedMap<OpData> OperandMap; 176 OperandMap.grow(NumMIOperands); 177 178 addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0); 179 180 // If there are more operands that weren't in the DAG, they have to 181 // be operands that have default values, or we have an error. Currently, 182 // Operands that are a subclass of OperandWithDefaultOp have default values. 183 184 // Validate that each result pattern argument has a matching (by name) 185 // argument in the source instruction, in either the (outs) or (ins) list. 186 // Also check that the type of the arguments match. 187 // 188 // Record the mapping of the source to result arguments for use by 189 // the lowering emitter. 190 CodeGenInstruction SourceInsn(Rec); 191 StringMap<unsigned> SourceOperands; 192 for (const auto &[Idx, SrcOp] : enumerate(SourceInsn.Operands)) 193 SourceOperands[SrcOp.Name] = Idx; 194 195 LLVM_DEBUG(dbgs() << " Operand mapping:\n"); 196 for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) { 197 // We've already handled constant values. Just map instruction operands 198 // here. 199 if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand) 200 continue; 201 StringMap<unsigned>::iterator SourceOp = 202 SourceOperands.find(Dag->getArgNameStr(i)); 203 if (SourceOp == SourceOperands.end()) { 204 PrintError(Rec, "In pseudo instruction '" + Rec->getName() + 205 "', output operand '" + Dag->getArgNameStr(i) + 206 "' has no matching source operand"); 207 PrintFatalNote(Rec->getValue("ResultInst"), 208 "Value was assigned at the following location:"); 209 } 210 // Map the source operand to the destination operand index for each 211 // MachineInstr operand. 212 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) 213 OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand = 214 SourceOp->getValue(); 215 216 LLVM_DEBUG(dbgs() << " " << SourceOp->getValue() << " ==> " << i 217 << "\n"); 218 } 219 220 Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap)); 221 } 222 223 void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) { 224 // Emit file header. 225 emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o); 226 227 o << "bool " << Target.getName() + "AsmPrinter::\n" 228 << "lowerPseudoInstExpansion(const MachineInstr *MI, MCInst &Inst) {\n"; 229 230 if (!Expansions.empty()) { 231 o << " Inst.clear();\n" 232 << " switch (MI->getOpcode()) {\n" 233 << " default: return false;\n"; 234 for (auto &Expansion : Expansions) { 235 CodeGenInstruction &Source = Expansion.Source; 236 CodeGenInstruction &Dest = Expansion.Dest; 237 o << " case " << Source.Namespace << "::" << Source.TheDef->getName() 238 << ": {\n" 239 << " MCOperand MCOp;\n" 240 << " Inst.setOpcode(" << Dest.Namespace 241 << "::" << Dest.TheDef->getName() << ");\n"; 242 243 // Copy the operands from the source instruction. 244 // FIXME: Instruction operands with defaults values (predicates and cc_out 245 // in ARM, for example shouldn't need explicit values in the 246 // expansion DAG. 247 unsigned MIOpNo = 0; 248 for (const auto &DestOperand : Dest.Operands) { 249 o << " // Operand: " << DestOperand.Name << "\n"; 250 for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) { 251 switch (Expansion.OperandMap[MIOpNo + i].Kind) { 252 case OpData::Operand: 253 o << " lowerOperand(MI->getOperand(" 254 << Source.Operands[Expansion.OperandMap[MIOpNo].Data.Operand] 255 .MIOperandNo + 256 i 257 << "), MCOp);\n" 258 << " Inst.addOperand(MCOp);\n"; 259 break; 260 case OpData::Imm: 261 o << " Inst.addOperand(MCOperand::createImm(" 262 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n"; 263 break; 264 case OpData::Reg: { 265 const Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg; 266 o << " Inst.addOperand(MCOperand::createReg("; 267 // "zero_reg" is special. 268 if (Reg->getName() == "zero_reg") 269 o << "0"; 270 else 271 o << Reg->getValueAsString("Namespace") << "::" << Reg->getName(); 272 o << "));\n"; 273 break; 274 } 275 } 276 } 277 MIOpNo += DestOperand.MINumOperands; 278 } 279 if (Dest.Operands.isVariadic) { 280 MIOpNo = Source.Operands.size() + 1; 281 o << " // variable_ops\n"; 282 o << " for (unsigned i = " << MIOpNo 283 << ", e = MI->getNumOperands(); i != e; ++i)\n" 284 << " if (lowerOperand(MI->getOperand(i), MCOp))\n" 285 << " Inst.addOperand(MCOp);\n"; 286 } 287 o << " break;\n" 288 << " }\n"; 289 } 290 o << " }\n return true;"; 291 } else 292 o << " return false;"; 293 294 o << "\n}\n\n"; 295 } 296 297 void PseudoLoweringEmitter::run(raw_ostream &OS) { 298 StringRef Classes[] = {"PseudoInstExpansion", "Instruction"}; 299 300 // Process the pseudo expansion definitions, validating them as we do so. 301 TGTimer &Timer = Records.getTimer(); 302 Timer.startTimer("Process definitions"); 303 for (const Record *Inst : Records.getAllDerivedDefinitions(Classes)) 304 evaluateExpansion(Inst); 305 306 // Generate expansion code to lower the pseudo to an MCInst of the real 307 // instruction. 308 Timer.startTimer("Emit expansion code"); 309 emitLoweringEmitter(OS); 310 } 311 312 static TableGen::Emitter::OptClass<PseudoLoweringEmitter> 313 X("gen-pseudo-lowering", "Generate pseudo instruction lowering"); 314