1 //===-- RegisterAliasingTest.cpp --------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "RegisterAliasing.h"
10
11 #include <cassert>
12 #include <memory>
13
14 #include "MipsInstrInfo.h"
15 #include "TestBase.h"
16 #include "llvm/MC/TargetRegistry.h"
17 #include "llvm/Support/TargetSelect.h"
18 #include "gmock/gmock.h"
19 #include "gtest/gtest.h"
20
21 namespace llvm {
22 namespace exegesis {
23 namespace {
24
25 class MipsRegisterAliasingTest : public MipsTestBase {};
26
TEST_F(MipsRegisterAliasingTest,TrackSimpleRegister)27 TEST_F(MipsRegisterAliasingTest, TrackSimpleRegister) {
28 const auto &RegInfo = State.getRegInfo();
29 const RegisterAliasingTracker tracker(RegInfo, Mips::T0_64);
30 std::set<MCPhysReg> ActualAliasedRegisters;
31 for (unsigned I : tracker.aliasedBits().set_bits())
32 ActualAliasedRegisters.insert(static_cast<MCPhysReg>(I));
33 const std::set<MCPhysReg> ExpectedAliasedRegisters = {Mips::T0, Mips::T0_64};
34 ASSERT_THAT(ActualAliasedRegisters, ExpectedAliasedRegisters);
35 for (MCPhysReg aliased : ExpectedAliasedRegisters) {
36 ASSERT_THAT(tracker.getOrigin(aliased), Mips::T0_64);
37 }
38 }
39
TEST_F(MipsRegisterAliasingTest,TrackRegisterClass)40 TEST_F(MipsRegisterAliasingTest, TrackRegisterClass) {
41 // The alias bits for
42 // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID
43 // are the union of the alias bits for ZERO_64, V0_64, V1_64 and S1_64.
44 const auto &RegInfo = State.getRegInfo();
45 const BitVector NoReservedReg(RegInfo.getNumRegs());
46
47 const RegisterAliasingTracker RegClassTracker(
48 RegInfo, NoReservedReg,
49 RegInfo.getRegClass(
50 Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID));
51
52 BitVector sum(RegInfo.getNumRegs());
53 sum |= RegisterAliasingTracker(RegInfo, Mips::ZERO_64).aliasedBits();
54 sum |= RegisterAliasingTracker(RegInfo, Mips::V0_64).aliasedBits();
55 sum |= RegisterAliasingTracker(RegInfo, Mips::V1_64).aliasedBits();
56 sum |= RegisterAliasingTracker(RegInfo, Mips::S1_64).aliasedBits();
57
58 ASSERT_THAT(RegClassTracker.aliasedBits(), sum);
59 }
60
TEST_F(MipsRegisterAliasingTest,TrackRegisterClassCache)61 TEST_F(MipsRegisterAliasingTest, TrackRegisterClassCache) {
62 // Fetching the same tracker twice yields the same pointers.
63 const auto &RegInfo = State.getRegInfo();
64 const BitVector NoReservedReg(RegInfo.getNumRegs());
65 RegisterAliasingTrackerCache Cache(RegInfo, NoReservedReg);
66 ASSERT_THAT(&Cache.getRegister(Mips::T0), &Cache.getRegister(Mips::T0));
67
68 ASSERT_THAT(&Cache.getRegisterClass(Mips::ACC64RegClassID),
69 &Cache.getRegisterClass(Mips::ACC64RegClassID));
70 }
71
72 } // namespace
73 } // namespace exegesis
74 } // namespace llvm
75