xref: /llvm-project/llvm/test/tools/llvm-reduce/mir/subreg-def0.mir (revision 78865050620e6b6b90be7e868ffe5d5e67159856)
1# REQUIRES: amdgpu-registered-target
2# RUN: llvm-reduce -abort-on-invalid-reduction --delta-passes=instructions -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
3# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
4
5# CHECK-INTERESTINGNESS: V_ADD_U32
6
7# RESULT: undef %{{[0-9]+}}.sub1:vreg_64 = IMPLICIT_DEF
8# RESULT-NEXT: undef %{{[0-9]+}}.sub0:vreg_64 = IMPLICIT_DEF
9# RESULT-NEXT: %1:vgpr_32 = V_ADD_U32_e32 %{{[0-9]+}}.sub0, %{{[0-9]+}}.sub1, implicit $exec
10# RESULT-NEXT: S_ENDPGM 0, implicit %1
11
12---
13name:            f
14tracksRegLiveness: true
15body:             |
16  bb.0:
17    S_WAITCNT 0
18    undef %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
19    %0.sub0:vreg_64 = V_MOV_B32_e32 1, implicit $exec
20    %1:vgpr_32 = V_ADD_U32_e32 %0.sub0, %0.sub1, implicit $exec
21    S_ENDPGM 0, implicit %1
22...
23