1# REQUIRES: amdgpu-registered-target 2# RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir -mtriple=amdgcn-amd-amdhsa --delta-passes=instructions --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log 3# RUN: FileCheck --check-prefix=RESULT %s < %t 4 5# Make sure there's no crash with unreachable blocks. 6 7# CHECK-INTERESTINGNESS: S_NOP 8 9# RESULT: bb.0: 10 11# RESULT: %{{[0-9]+}}:vgpr_32 = IMPLICIT_DEF 12# RESULT-NEXT: %{{[0-9]+}}:sreg_64 = IMPLICIT_DEF 13# RESULT-NEXT: %{{[0-9]+}}:vreg_64 = IMPLICIT_DEF 14# RESULT-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc 15# RESULT-NEXT: S_BRANCH %bb.3 16 17# RESULT: bb.1: 18# RESULT-NEXT: S_BRANCH %bb.3 19 20# RESULT: bb.2: 21# RESULT-NEXT: S_NOP 0, implicit %{{[0-9]+}}, implicit killed %{{[0-9]+}}, implicit %{{[0-9]+}} 22 23--- 24name: unreachable_block 25tracksRegLiveness: true 26body: | 27 bb.0: 28 %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec 29 S_CBRANCH_SCC1 %bb.1, implicit undef $scc 30 S_BRANCH %bb.3 31 32 bb.1: 33 %1:sreg_64 = S_MOV_B64 0 34 S_BRANCH %bb.3 35 36 bb.2: 37 %2:vreg_64 = IMPLICIT_DEF 38 S_NOP 0, implicit %0, implicit killed %2, implicit %1 39 S_BRANCH %bb.3 40 41 bb.3: 42 43... 44