xref: /llvm-project/llvm/test/tools/llvm-reduce/mir/reduce-instruction-flags.mir (revision 59328ab0ce4ba9c4018a636752a48c9363c2a98f) 
1# REQUIRES: amdgpu-registered-target
2# RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir --delta-passes=instruction-flags -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
3# RUN: FileCheck --check-prefix=RESULT %s < %t
4
5# CHECK-INTERESTINGNESS: V_ADD_F32
6# CHECK-INTERESTINGNESS: nnan nofpexcept V_MUL_F32
7
8# CHECK-INTERESTINGNESS-COUNT-11: V_MOV_B32
9
10
11# RESULT: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit $mode, implicit $exec
12# RESULT: %{{[0-9]+}}:vgpr_32 = nnan nofpexcept V_MUL_F32_e32 0, %{{[0-9]+}}, implicit $mode, implicit $exec
13# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
14# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
15# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
16# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
17# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
18# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
19# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
20# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
21# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
22# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
23# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
24
25---
26name: func
27tracksRegLiveness: true
28body:             |
29  bb.0:
30    liveins: $vgpr0, $vgpr1
31
32    S_WAITCNT 0
33    %0:vgpr_32 = COPY $vgpr0
34    %1:vgpr_32 = COPY $vgpr1
35    %2:vgpr_32 = nofpexcept V_ADD_F32_e32 %0, %1, implicit $mode, implicit $exec
36    %3:vgpr_32 = nnan nofpexcept V_MUL_F32_e32 0, %2, implicit $mode, implicit $exec
37    %4:vgpr_32 = nsz V_MUL_F32_e32 0, %3, implicit $mode, implicit $exec
38
39    %5:vgpr_32 = nnan V_MOV_B32_e32 0, implicit $exec
40    %6:vgpr_32 = ninf V_MOV_B32_e32 0, implicit $exec
41    %7:vgpr_32 = nsz V_MOV_B32_e32 0, implicit $exec
42    %8:vgpr_32 = arcp V_MOV_B32_e32 0, implicit $exec
43    %9:vgpr_32 = contract V_MOV_B32_e32 0, implicit $exec
44    %10:vgpr_32 = afn V_MOV_B32_e32 0, implicit $exec
45    %11:vgpr_32 = reassoc V_MOV_B32_e32 0, implicit $exec
46    %12:vgpr_32 = nuw V_MOV_B32_e32 0, implicit $exec
47    %13:vgpr_32 = nsw V_MOV_B32_e32 0, implicit $exec
48    %14:vgpr_32 = exact V_MOV_B32_e32 0, implicit $exec
49    %15:vgpr_32 = nofpexcept V_MOV_B32_e32 0, implicit $exec
50    S_NOP 0, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7
51    S_NOP 0, implicit %8, implicit %9, implicit %10, implicit %11, implicit %12
52    S_ENDPGM 0, implicit %13, implicit %14, implicit %15
53...
54
55