xref: /llvm-project/llvm/test/tools/llvm-reduce/mir/instr-reduce.mir (revision 0199449fad8362240afb3e5dbeb2683408d8069a) 
1# REQUIRES: riscv-registered-target
2# RUN: llvm-reduce -abort-on-invalid-reduction --delta-passes=instructions -mtriple=riscv32 --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t
3# RUN: FileCheck --match-full-lines %s < %t
4
5# CHECK-INTERESTINGNESS: %{{[0-9]+}}:gpr = ADDI %{{[0-9]+}}, 5
6
7# Verify that after reduction the following instruction sequence remains. The
8# interestingness-test 'instr-reduce.py' matches a '%[0-9]+:gpr = ADDI %[0-9]+, 5'
9# pattern in the output and that combined with that the MIR has to be valid
10# (pass verify) results in the given sequence.
11
12# CHECK:      [[IMPDEF:%[0-9]+]]:gpr = IMPLICIT_DEF
13# CHECK-NEXT: %{{[0-9]+}}:gpr = ADDI [[IMPDEF]], 5
14# CHECK-NEXT: PseudoRET implicit $x10
15
16...
17---
18name:            f
19tracksRegLiveness: true
20body:             |
21  bb.0:
22    liveins: $x10
23
24    %10:gpr = COPY $x10
25    %20:gpr = ADDI %10, 1
26    %30:gpr = ADDI %20, 5
27    %40:gpr = ADDI %30, 9
28    $x10 = COPY %40
29    PseudoRET implicit $x10
30...
31---
32