1# RUN: yaml2obj %s | llvm-objdump --no-print-imm-hex -d --mcpu=cortex-a8 - | FileCheck %s 2 3# Test that unrecognized instructions are skipped in a way that makes 4# sense for the Arm instruction set encoding. 5# 6# The first three instructions in this file are marked by the mapping 7# symbols as in Arm state, with the one in the middle unknown, and we 8# expect the disassembler to skip 4 bytes because that's the width of 9# any Arm instruction. 10# 11# At address 0xc there's a mapping symbol that says we're now in Thumb 12# mode, and in that mode we include both a 16-bit and a 32-bit unknown 13# Thumb instruction, which the disassembler will identify by the simple 14# encoding criterion that tells you the instruction length without 15# having to recognize it specifically. 16# 17# Finally we end with a single byte, to ensure nothing gets confused 18# when the Thumb instruction stream doesn't contain enough data to 19# even do that check. 20 21# CHECK: 0: e3a00064 mov r0, #100 22# CHECK-NEXT: 4: ffffffff <unknown> 23# CHECK-NEXT: 8: e0810312 add r0, r1, r2, lsl r3 24 25# CHECK: c: 2064 movs r0, #100 26# CHECK-NEXT: e: b80e <unknown> 27# CHECK-NEXT: 10: 1840 adds r0, r0, r1 28# CHECK-NEXT: 12: f04f 0064 mov.w r0, #100 29# CHECK-NEXT: 16: ffee ddcc <unknown> 30# CHECK-NEXT: 1a: eb01 00c2 add.w r0, r1, r2, lsl #3 31# CHECK-NEXT: 1e: 9a <unknown> 32 33--- !ELF 34FileHeader: 35 Class: ELFCLASS32 36 Data: ELFDATA2LSB 37 Type: ET_REL 38 Machine: EM_ARM 39 Flags: [ EF_ARM_EABI_VER5 ] 40Sections: 41 - Name: .text 42 Type: SHT_PROGBITS 43 Flags: [ SHF_ALLOC, SHF_EXECINSTR ] 44 AddressAlign: 0x4 45 Content: 6400a0e3ffffffff120381e064200eb840184ff06400eeffccdd01ebc2009a 46Symbols: 47 - Name: '$a' 48 Section: .text 49 - Name: '$t' 50 Section: .text 51 Value: 0x0c 52... 53