1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats -dispatch-stats=false < %s | FileCheck %s -check-prefix=ALL 3# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats < %s | FileCheck %s -check-prefixes=ALL,FULL 4# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats -dispatch-stats < %s | FileCheck %s -check-prefixes=ALL,FULL 5# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -dispatch-stats -all-stats < %s | FileCheck %s -check-prefixes=ALL,FULL 6# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -dispatch-stats=false -all-stats < %s | FileCheck %s -check-prefixes=ALL,FULL 7 8add %eax, %eax 9 10# ALL: Iterations: 100 11# ALL-NEXT: Instructions: 100 12# ALL-NEXT: Total Cycles: 103 13# ALL-NEXT: Total uOps: 100 14 15# ALL: Dispatch Width: 2 16# ALL-NEXT: uOps Per Cycle: 0.97 17# ALL-NEXT: IPC: 0.97 18# ALL-NEXT: Block RThroughput: 0.5 19 20# ALL: Instruction Info: 21# ALL-NEXT: [1]: #uOps 22# ALL-NEXT: [2]: Latency 23# ALL-NEXT: [3]: RThroughput 24# ALL-NEXT: [4]: MayLoad 25# ALL-NEXT: [5]: MayStore 26# ALL-NEXT: [6]: HasSideEffects (U) 27 28# ALL: [1] [2] [3] [4] [5] [6] Instructions: 29# ALL-NEXT: 1 1 0.50 addl %eax, %eax 30 31# FULL: Dynamic Dispatch Stall Cycles: 32# FULL-NEXT: RAT - Register unavailable: 0 33# FULL-NEXT: RCU - Retire tokens unavailable: 0 34# FULL-NEXT: SCHEDQ - Scheduler full: 61 (59.2%) 35# FULL-NEXT: LQ - Load queue full: 0 36# FULL-NEXT: SQ - Store queue full: 0 37# FULL-NEXT: GROUP - Static restrictions on the dispatch group: 0 38# FULL-NEXT: USH - Uncategorised Structural Hazard: 0 39 40# FULL: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched: 41# FULL-NEXT: [# dispatched], [# cycles] 42# FULL-NEXT: 0, 22 (21.4%) 43# FULL-NEXT: 1, 62 (60.2%) 44# FULL-NEXT: 2, 19 (18.4%) 45 46# ALL: Schedulers - number of cycles where we saw N micro opcodes issued: 47# ALL-NEXT: [# issued], [# cycles] 48# ALL-NEXT: 0, 3 (2.9%) 49# ALL-NEXT: 1, 100 (97.1%) 50 51# ALL: Scheduler's queue usage: 52# ALL-NEXT: [1] Resource name. 53# ALL-NEXT: [2] Average number of used buffer entries. 54# ALL-NEXT: [3] Maximum number of used buffer entries. 55# ALL-NEXT: [4] Total number of buffer entries. 56 57# ALL: [1] [2] [3] [4] 58# ALL-NEXT: JALU01 15 20 20 59# ALL-NEXT: JFPU01 0 0 18 60# ALL-NEXT: JLSAGU 0 0 12 61 62# ALL: Retire Control Unit - number of cycles where we saw N instructions retired: 63# ALL-NEXT: [# retired], [# cycles] 64# ALL-NEXT: 0, 3 (2.9%) 65# ALL-NEXT: 1, 100 (97.1%) 66 67# ALL: Total ROB Entries: 64 68# ALL-NEXT: Max Used ROB Entries: 22 ( 34.4% ) 69# ALL-NEXT: Average Used ROB Entries per cy: 17 ( 26.6% ) 70 71# ALL: Register File statistics: 72# ALL-NEXT: Total number of mappings created: 200 73# ALL-NEXT: Max number of mappings used: 44 74 75# ALL: * Register File #1 -- JFpuPRF: 76# ALL-NEXT: Number of physical registers: 72 77# ALL-NEXT: Total number of mappings created: 0 78# ALL-NEXT: Max number of mappings used: 0 79 80# ALL: * Register File #2 -- JIntegerPRF: 81# ALL-NEXT: Number of physical registers: 64 82# ALL-NEXT: Total number of mappings created: 200 83# ALL-NEXT: Max number of mappings used: 44 84 85# ALL: Resources: 86# ALL-NEXT: [0] - JALU0 87# ALL-NEXT: [1] - JALU1 88# ALL-NEXT: [2] - JDiv 89# ALL-NEXT: [3] - JFPA 90# ALL-NEXT: [4] - JFPM 91# ALL-NEXT: [5] - JFPU0 92# ALL-NEXT: [6] - JFPU1 93# ALL-NEXT: [7] - JLAGU 94# ALL-NEXT: [8] - JMul 95# ALL-NEXT: [9] - JSAGU 96# ALL-NEXT: [10] - JSTC 97# ALL-NEXT: [11] - JVALU0 98# ALL-NEXT: [12] - JVALU1 99# ALL-NEXT: [13] - JVIMUL 100 101# ALL: Resource pressure per iteration: 102# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] 103# ALL-NEXT: 0.50 0.50 - - - - - - - - - - - - 104 105# ALL: Resource pressure by instruction: 106# ALL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: 107# ALL-NEXT: 0.50 0.50 - - - - - - - - - - - - addl %eax, %eax 108