1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -timeline -iterations=2 < %s | FileCheck %s 3 4# PR51494: A read-advance on the implicit read of EDX/RDX was missing. 5 6# LLVM-MCA-BEGIN 7mulxl (%rdi), %eax, %edx 8# LLVM-MCA-END 9 10# LLVM-MCA-BEGIN 11mulxq (%rdi), %rax, %rdx 12# LLVM-MCA-END 13 14# CHECK: [0] Code Region 15 16# CHECK: Iterations: 2 17# CHECK-NEXT: Instructions: 2 18# CHECK-NEXT: Total Cycles: 16 19# CHECK-NEXT: Total uOps: 10 20 21# CHECK: Dispatch Width: 4 22# CHECK-NEXT: uOps Per Cycle: 0.63 23# CHECK-NEXT: IPC: 0.13 24# CHECK-NEXT: Block RThroughput: 1.3 25 26# CHECK: Instruction Info: 27# CHECK-NEXT: [1]: #uOps 28# CHECK-NEXT: [2]: Latency 29# CHECK-NEXT: [3]: RThroughput 30# CHECK-NEXT: [4]: MayLoad 31# CHECK-NEXT: [5]: MayStore 32# CHECK-NEXT: [6]: HasSideEffects (U) 33 34# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 35# CHECK-NEXT: 5 9 1.00 * mulxl (%rdi), %eax, %edx 36 37# CHECK: Resources: 38# CHECK-NEXT: [0] - HWDivider 39# CHECK-NEXT: [1] - HWFPDivider 40# CHECK-NEXT: [2] - HWPort0 41# CHECK-NEXT: [3] - HWPort1 42# CHECK-NEXT: [4] - HWPort2 43# CHECK-NEXT: [5] - HWPort3 44# CHECK-NEXT: [6] - HWPort4 45# CHECK-NEXT: [7] - HWPort5 46# CHECK-NEXT: [8] - HWPort6 47# CHECK-NEXT: [9] - HWPort7 48 49# CHECK: Resource pressure per iteration: 50# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] 51# CHECK-NEXT: - - 0.50 1.00 0.50 0.50 - 0.50 1.00 - 52 53# CHECK: Resource pressure by instruction: 54# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: 55# CHECK-NEXT: - - 0.50 1.00 0.50 0.50 - 0.50 1.00 - mulxl (%rdi), %eax, %edx 56 57# CHECK: Timeline view: 58# CHECK-NEXT: 012345 59# CHECK-NEXT: Index 0123456789 60 61# CHECK: [0,0] DeeeeeeeeeER . mulxl (%rdi), %eax, %edx 62# CHECK-NEXT: [1,0] . D==eeeeeeeeeER mulxl (%rdi), %eax, %edx 63 64# CHECK: Average Wait times (based on the timeline view): 65# CHECK-NEXT: [0]: Executions 66# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 67# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 68# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 69 70# CHECK: [0] [1] [2] [3] 71# CHECK-NEXT: 0. 2 2.0 0.5 0.0 mulxl (%rdi), %eax, %edx 72 73# CHECK: [1] Code Region 74 75# CHECK: Iterations: 2 76# CHECK-NEXT: Instructions: 2 77# CHECK-NEXT: Total Cycles: 16 78# CHECK-NEXT: Total uOps: 8 79 80# CHECK: Dispatch Width: 4 81# CHECK-NEXT: uOps Per Cycle: 0.50 82# CHECK-NEXT: IPC: 0.13 83# CHECK-NEXT: Block RThroughput: 1.0 84 85# CHECK: Instruction Info: 86# CHECK-NEXT: [1]: #uOps 87# CHECK-NEXT: [2]: Latency 88# CHECK-NEXT: [3]: RThroughput 89# CHECK-NEXT: [4]: MayLoad 90# CHECK-NEXT: [5]: MayStore 91# CHECK-NEXT: [6]: HasSideEffects (U) 92 93# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 94# CHECK-NEXT: 4 9 1.00 * mulxq (%rdi), %rax, %rdx 95 96# CHECK: Resources: 97# CHECK-NEXT: [0] - HWDivider 98# CHECK-NEXT: [1] - HWFPDivider 99# CHECK-NEXT: [2] - HWPort0 100# CHECK-NEXT: [3] - HWPort1 101# CHECK-NEXT: [4] - HWPort2 102# CHECK-NEXT: [5] - HWPort3 103# CHECK-NEXT: [6] - HWPort4 104# CHECK-NEXT: [7] - HWPort5 105# CHECK-NEXT: [8] - HWPort6 106# CHECK-NEXT: [9] - HWPort7 107 108# CHECK: Resource pressure per iteration: 109# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] 110# CHECK-NEXT: - - - 1.00 0.50 0.50 - - 1.00 - 111 112# CHECK: Resource pressure by instruction: 113# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: 114# CHECK-NEXT: - - - 1.00 0.50 0.50 - - 1.00 - mulxq (%rdi), %rax, %rdx 115 116# CHECK: Timeline view: 117# CHECK-NEXT: 012345 118# CHECK-NEXT: Index 0123456789 119 120# CHECK: [0,0] DeeeeeeeeeER . mulxq (%rdi), %rax, %rdx 121# CHECK-NEXT: [1,0] .D===eeeeeeeeeER mulxq (%rdi), %rax, %rdx 122 123# CHECK: Average Wait times (based on the timeline view): 124# CHECK-NEXT: [0]: Executions 125# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 126# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 127# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 128 129# CHECK: [0] [1] [2] [3] 130# CHECK-NEXT: 0. 2 2.5 0.5 0.0 mulxq (%rdi), %rax, %rdx 131