1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -timeline -iterations=2 < %s | FileCheck %s 3 4# LLVM-MCA-BEGIN 5mulxl %eax, %eax, %ecx 6# LLVM-MCA-END 7 8# LLVM-MCA-BEGIN 9mulxq %rax, %rax, %rcx 10# LLVM-MCA-END 11 12# CHECK: [0] Code Region 13 14# CHECK: Iterations: 2 15# CHECK-NEXT: Instructions: 2 16# CHECK-NEXT: Total Cycles: 10 17# CHECK-NEXT: Total uOps: 8 18 19# CHECK: Dispatch Width: 4 20# CHECK-NEXT: uOps Per Cycle: 0.80 21# CHECK-NEXT: IPC: 0.20 22# CHECK-NEXT: Block RThroughput: 1.0 23 24# CHECK: Instruction Info: 25# CHECK-NEXT: [1]: #uOps 26# CHECK-NEXT: [2]: Latency 27# CHECK-NEXT: [3]: RThroughput 28# CHECK-NEXT: [4]: MayLoad 29# CHECK-NEXT: [5]: MayStore 30# CHECK-NEXT: [6]: HasSideEffects (U) 31 32# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 33# CHECK-NEXT: 4 4 1.00 mulxl %eax, %eax, %ecx 34 35# CHECK: Resources: 36# CHECK-NEXT: [0] - HWDivider 37# CHECK-NEXT: [1] - HWFPDivider 38# CHECK-NEXT: [2] - HWPort0 39# CHECK-NEXT: [3] - HWPort1 40# CHECK-NEXT: [4] - HWPort2 41# CHECK-NEXT: [5] - HWPort3 42# CHECK-NEXT: [6] - HWPort4 43# CHECK-NEXT: [7] - HWPort5 44# CHECK-NEXT: [8] - HWPort6 45# CHECK-NEXT: [9] - HWPort7 46 47# CHECK: Resource pressure per iteration: 48# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] 49# CHECK-NEXT: - - 0.50 1.00 - - - 0.50 1.00 - 50 51# CHECK: Resource pressure by instruction: 52# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: 53# CHECK-NEXT: - - 0.50 1.00 - - - 0.50 1.00 - mulxl %eax, %eax, %ecx 54 55# CHECK: Timeline view: 56# CHECK-NEXT: Index 0123456789 57 58# CHECK: [0,0] DeeeeER . mulxl %eax, %eax, %ecx 59# CHECK-NEXT: [1,0] .D==eeeeER mulxl %eax, %eax, %ecx 60 61# CHECK: Average Wait times (based on the timeline view): 62# CHECK-NEXT: [0]: Executions 63# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 64# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 65# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 66 67# CHECK: [0] [1] [2] [3] 68# CHECK-NEXT: 0. 2 2.0 0.5 0.0 mulxl %eax, %eax, %ecx 69 70# CHECK: [1] Code Region 71 72# CHECK: Iterations: 2 73# CHECK-NEXT: Instructions: 2 74# CHECK-NEXT: Total Cycles: 10 75# CHECK-NEXT: Total uOps: 6 76 77# CHECK: Dispatch Width: 4 78# CHECK-NEXT: uOps Per Cycle: 0.60 79# CHECK-NEXT: IPC: 0.20 80# CHECK-NEXT: Block RThroughput: 1.0 81 82# CHECK: Instruction Info: 83# CHECK-NEXT: [1]: #uOps 84# CHECK-NEXT: [2]: Latency 85# CHECK-NEXT: [3]: RThroughput 86# CHECK-NEXT: [4]: MayLoad 87# CHECK-NEXT: [5]: MayStore 88# CHECK-NEXT: [6]: HasSideEffects (U) 89 90# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 91# CHECK-NEXT: 3 4 1.00 mulxq %rax, %rax, %rcx 92 93# CHECK: Resources: 94# CHECK-NEXT: [0] - HWDivider 95# CHECK-NEXT: [1] - HWFPDivider 96# CHECK-NEXT: [2] - HWPort0 97# CHECK-NEXT: [3] - HWPort1 98# CHECK-NEXT: [4] - HWPort2 99# CHECK-NEXT: [5] - HWPort3 100# CHECK-NEXT: [6] - HWPort4 101# CHECK-NEXT: [7] - HWPort5 102# CHECK-NEXT: [8] - HWPort6 103# CHECK-NEXT: [9] - HWPort7 104 105# CHECK: Resource pressure per iteration: 106# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] 107# CHECK-NEXT: - - - 1.00 - - - - 1.00 - 108 109# CHECK: Resource pressure by instruction: 110# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions: 111# CHECK-NEXT: - - - 1.00 - - - - 1.00 - mulxq %rax, %rax, %rcx 112 113# CHECK: Timeline view: 114# CHECK-NEXT: Index 0123456789 115 116# CHECK: [0,0] DeeeeER . mulxq %rax, %rax, %rcx 117# CHECK-NEXT: [1,0] .D==eeeeER mulxq %rax, %rax, %rcx 118 119# CHECK: Average Wait times (based on the timeline view): 120# CHECK-NEXT: [0]: Executions 121# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue 122# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready 123# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage 124 125# CHECK: [0] [1] [2] [3] 126# CHECK-NEXT: 0. 2 2.0 0.5 0.0 mulxq %rax, %rax, %rcx 127