xref: /llvm-project/llvm/test/tools/llvm-mca/RISCV/XiangShan/load-to-alu.s (revision 373d9d72145cd40c9dc00abefd14632763a2987b)
1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-nanhu -timeline -iterations=1 < %s | FileCheck %s
3
4# Test XiangShan load to ALU (4 cycles)
5ld a1, 0(a0)
6addi a2, a1, 1
7
8# CHECK:      Iterations:        1
9# CHECK-NEXT: Instructions:      2
10# CHECK-NEXT: Total Cycles:      8
11# CHECK-NEXT: Total uOps:        2
12
13# CHECK:      Dispatch Width:    6
14# CHECK-NEXT: uOps Per Cycle:    0.25
15# CHECK-NEXT: IPC:               0.25
16# CHECK-NEXT: Block RThroughput: 0.5
17
18# CHECK:      Instruction Info:
19# CHECK-NEXT: [1]: #uOps
20# CHECK-NEXT: [2]: Latency
21# CHECK-NEXT: [3]: RThroughput
22# CHECK-NEXT: [4]: MayLoad
23# CHECK-NEXT: [5]: MayStore
24# CHECK-NEXT: [6]: HasSideEffects (U)
25
26# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
27# CHECK-NEXT:  1      5     0.50    *                   ld	a1, 0(a0)
28# CHECK-NEXT:  1      1     0.25                        addi	a2, a1, 1
29
30# CHECK:      Resources:
31# CHECK-NEXT: [0.0] - XS2ALU
32# CHECK-NEXT: [0.1] - XS2ALU
33# CHECK-NEXT: [0.2] - XS2ALU
34# CHECK-NEXT: [0.3] - XS2ALU
35# CHECK-NEXT: [1.0] - XS2FMAC
36# CHECK-NEXT: [1.1] - XS2FMAC
37# CHECK-NEXT: [1.2] - XS2FMAC
38# CHECK-NEXT: [1.3] - XS2FMAC
39# CHECK-NEXT: [2.0] - XS2FMISC
40# CHECK-NEXT: [2.1] - XS2FMISC
41# CHECK-NEXT: [3.0] - XS2LD
42# CHECK-NEXT: [3.1] - XS2LD
43# CHECK-NEXT: [4.0] - XS2MDU
44# CHECK-NEXT: [4.1] - XS2MDU
45# CHECK-NEXT: [5]   - XS2MISC
46# CHECK-NEXT: [6.0] - XS2ST
47# CHECK-NEXT: [6.1] - XS2ST
48
49# CHECK:      Resource pressure per iteration:
50# CHECK-NEXT: [0.0]  [0.1]  [0.2]  [0.3]  [1.0]  [1.1]  [1.2]  [1.3]  [2.0]  [2.1]  [3.0]  [3.1]  [4.0]  [4.1]  [5]    [6.0]  [6.1]
51# CHECK-NEXT:  -      -      -     1.00    -      -      -      -      -      -      -     1.00    -      -      -      -      -
52
53# CHECK:      Resource pressure by instruction:
54# CHECK-NEXT: [0.0]  [0.1]  [0.2]  [0.3]  [1.0]  [1.1]  [1.2]  [1.3]  [2.0]  [2.1]  [3.0]  [3.1]  [4.0]  [4.1]  [5]    [6.0]  [6.1]  Instructions:
55# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -     1.00    -      -      -      -      -     ld	a1, 0(a0)
56# CHECK-NEXT:  -      -      -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -     addi	a2, a1, 1
57
58# CHECK:      Timeline view:
59# CHECK-NEXT: Index     01234567
60
61# CHECK:      [0,0]     DeeeeeER   ld	a1, 0(a0)
62# CHECK-NEXT: [0,1]     D====eER   addi	a2, a1, 1
63
64# CHECK:      Average Wait times (based on the timeline view):
65# CHECK-NEXT: [0]: Executions
66# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
67# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
68# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
69
70# CHECK:            [0]    [1]    [2]    [3]
71# CHECK-NEXT: 0.     1     1.0    1.0    0.0       ld	a1, 0(a0)
72# CHECK-NEXT: 1.     1     5.0    0.0    0.0       addi	a2, a1, 1
73# CHECK-NEXT:        1     3.0    0.5    0.0       <total>
74