1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-nanhu < %s | FileCheck %s 3 4# Test XiangShan FuDian's cascade FMA, CPI = 3 5fmadd.s fa0, fa1, fa2, fa0 6 7# CHECK: Iterations: 100 8# CHECK-NEXT: Instructions: 100 9# CHECK-NEXT: Total Cycles: 305 10# CHECK-NEXT: Total uOps: 100 11 12# CHECK: Dispatch Width: 6 13# CHECK-NEXT: uOps Per Cycle: 0.33 14# CHECK-NEXT: IPC: 0.33 15# CHECK-NEXT: Block RThroughput: 0.3 16 17# CHECK: Instruction Info: 18# CHECK-NEXT: [1]: #uOps 19# CHECK-NEXT: [2]: Latency 20# CHECK-NEXT: [3]: RThroughput 21# CHECK-NEXT: [4]: MayLoad 22# CHECK-NEXT: [5]: MayStore 23# CHECK-NEXT: [6]: HasSideEffects (U) 24 25# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 26# CHECK-NEXT: 1 5 0.25 fmadd.s fa0, fa1, fa2, fa0 27 28# CHECK: Resources: 29# CHECK-NEXT: [0.0] - XS2ALU 30# CHECK-NEXT: [0.1] - XS2ALU 31# CHECK-NEXT: [0.2] - XS2ALU 32# CHECK-NEXT: [0.3] - XS2ALU 33# CHECK-NEXT: [1.0] - XS2FMAC 34# CHECK-NEXT: [1.1] - XS2FMAC 35# CHECK-NEXT: [1.2] - XS2FMAC 36# CHECK-NEXT: [1.3] - XS2FMAC 37# CHECK-NEXT: [2.0] - XS2FMISC 38# CHECK-NEXT: [2.1] - XS2FMISC 39# CHECK-NEXT: [3.0] - XS2LD 40# CHECK-NEXT: [3.1] - XS2LD 41# CHECK-NEXT: [4.0] - XS2MDU 42# CHECK-NEXT: [4.1] - XS2MDU 43# CHECK-NEXT: [5] - XS2MISC 44# CHECK-NEXT: [6.0] - XS2ST 45# CHECK-NEXT: [6.1] - XS2ST 46 47# CHECK: Resource pressure per iteration: 48# CHECK-NEXT: [0.0] [0.1] [0.2] [0.3] [1.0] [1.1] [1.2] [1.3] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5] [6.0] [6.1] 49# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - 50 51# CHECK: Resource pressure by instruction: 52# CHECK-NEXT: [0.0] [0.1] [0.2] [0.3] [1.0] [1.1] [1.2] [1.3] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5] [6.0] [6.1] Instructions: 53# CHECK-NEXT: - - - - 0.25 0.25 0.25 0.25 - - - - - - - - - fmadd.s fa0, fa1, fa2, fa0 54