1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p670 -iterations=1 < %s | FileCheck %s 3 4# Worst case for vsha2ms should be that of LMUL=8 and SEW=64. 5vsha2ms.vv v4, v8, v12 6 7# SEW is only e32 or e64 8 9vsetvli zero, zero, e32, m1, tu, mu 10vsha2ms.vv v4, v8, v12 11vsha2ch.vv v4, v8, v12 12vsha2cl.vv v4, v8, v12 13 14vsetvli zero, zero, e32, m2, tu, mu 15vsha2ms.vv v4, v8, v12 16vsha2ch.vv v4, v8, v12 17vsha2cl.vv v4, v8, v12 18 19vsetvli zero, zero, e32, m4, tu, mu 20vsha2ms.vv v4, v8, v12 21vsha2ch.vv v4, v8, v12 22vsha2cl.vv v4, v8, v12 23 24vsetvli zero, zero, e32, m8, tu, mu 25vsha2ms.vv v8, v16, v24 26vsha2ch.vv v8, v16, v24 27vsha2cl.vv v8, v16, v24 28 29vsetvli zero, zero, e64, m1, tu, mu 30vsha2ms.vv v4, v8, v12 31vsha2ch.vv v4, v8, v12 32vsha2cl.vv v4, v8, v12 33 34vsetvli zero, zero, e64, m2, tu, mu 35vsha2ms.vv v4, v8, v12 36vsha2ch.vv v4, v8, v12 37vsha2cl.vv v4, v8, v12 38 39vsetvli zero, zero, e64, m4, tu, mu 40vsha2ms.vv v4, v8, v12 41vsha2ch.vv v4, v8, v12 42vsha2cl.vv v4, v8, v12 43 44vsetvli zero, zero, e64, m8, tu, mu 45vsha2ms.vv v8, v16, v24 46vsha2ch.vv v8, v16, v24 47vsha2cl.vv v8, v16, v24 48 49# CHECK: Iterations: 1 50# CHECK-NEXT: Instructions: 33 51# CHECK-NEXT: Total Cycles: 119 52# CHECK-NEXT: Total uOps: 33 53 54# CHECK: Dispatch Width: 4 55# CHECK-NEXT: uOps Per Cycle: 0.28 56# CHECK-NEXT: IPC: 0.28 57# CHECK-NEXT: Block RThroughput: 109.0 58 59# CHECK: Instruction Info: 60# CHECK-NEXT: [1]: #uOps 61# CHECK-NEXT: [2]: Latency 62# CHECK-NEXT: [3]: RThroughput 63# CHECK-NEXT: [4]: MayLoad 64# CHECK-NEXT: [5]: MayStore 65# CHECK-NEXT: [6]: HasSideEffects (U) 66 67# CHECK: [1] [2] [3] [4] [5] [6] Instructions: 68# CHECK-NEXT: 1 3 12.00 vsha2ms.vv v4, v8, v12 69# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m1, tu, mu 70# CHECK-NEXT: 1 3 1.00 vsha2ms.vv v4, v8, v12 71# CHECK-NEXT: 1 3 1.00 vsha2ch.vv v4, v8, v12 72# CHECK-NEXT: 1 3 1.00 vsha2cl.vv v4, v8, v12 73# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m2, tu, mu 74# CHECK-NEXT: 1 3 2.00 vsha2ms.vv v4, v8, v12 75# CHECK-NEXT: 1 3 2.00 vsha2ch.vv v4, v8, v12 76# CHECK-NEXT: 1 3 2.00 vsha2cl.vv v4, v8, v12 77# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m4, tu, mu 78# CHECK-NEXT: 1 3 4.00 vsha2ms.vv v4, v8, v12 79# CHECK-NEXT: 1 3 4.00 vsha2ch.vv v4, v8, v12 80# CHECK-NEXT: 1 3 4.00 vsha2cl.vv v4, v8, v12 81# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e32, m8, tu, mu 82# CHECK-NEXT: 1 3 8.00 vsha2ms.vv v8, v16, v24 83# CHECK-NEXT: 1 3 8.00 vsha2ch.vv v8, v16, v24 84# CHECK-NEXT: 1 3 8.00 vsha2cl.vv v8, v16, v24 85# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m1, tu, mu 86# CHECK-NEXT: 1 3 1.00 vsha2ms.vv v4, v8, v12 87# CHECK-NEXT: 1 3 1.00 vsha2ch.vv v4, v8, v12 88# CHECK-NEXT: 1 3 1.00 vsha2cl.vv v4, v8, v12 89# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m2, tu, mu 90# CHECK-NEXT: 1 3 3.00 vsha2ms.vv v4, v8, v12 91# CHECK-NEXT: 1 3 2.00 vsha2ch.vv v4, v8, v12 92# CHECK-NEXT: 1 3 2.00 vsha2cl.vv v4, v8, v12 93# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m4, tu, mu 94# CHECK-NEXT: 1 3 6.00 vsha2ms.vv v4, v8, v12 95# CHECK-NEXT: 1 3 4.00 vsha2ch.vv v4, v8, v12 96# CHECK-NEXT: 1 3 4.00 vsha2cl.vv v4, v8, v12 97# CHECK-NEXT: 1 1 1.00 U vsetvli zero, zero, e64, m8, tu, mu 98# CHECK-NEXT: 1 3 12.00 vsha2ms.vv v8, v16, v24 99# CHECK-NEXT: 1 3 8.00 vsha2ch.vv v8, v16, v24 100# CHECK-NEXT: 1 3 8.00 vsha2cl.vv v8, v16, v24 101 102# CHECK: Resources: 103# CHECK-NEXT: [0] - SiFiveP600Div 104# CHECK-NEXT: [1] - SiFiveP600FEXQ0 105# CHECK-NEXT: [2] - SiFiveP600FEXQ1 106# CHECK-NEXT: [3] - SiFiveP600FloatDiv 107# CHECK-NEXT: [4] - SiFiveP600IEXQ0 108# CHECK-NEXT: [5] - SiFiveP600IEXQ1 109# CHECK-NEXT: [6] - SiFiveP600IEXQ2 110# CHECK-NEXT: [7] - SiFiveP600IEXQ3 111# CHECK-NEXT: [8.0] - SiFiveP600LDST 112# CHECK-NEXT: [8.1] - SiFiveP600LDST 113# CHECK-NEXT: [9] - SiFiveP600VDiv 114# CHECK-NEXT: [10] - SiFiveP600VEXQ0 115# CHECK-NEXT: [11] - SiFiveP600VEXQ1 116# CHECK-NEXT: [12] - SiFiveP600VFloatDiv 117# CHECK-NEXT: [13] - SiFiveP600VLD 118# CHECK-NEXT: [14] - SiFiveP600VST 119 120# CHECK: Resource pressure per iteration: 121# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] 122# CHECK-NEXT: - - - - 8.00 - - - - - - 109.00 - - - - 123 124# CHECK: Resource pressure by instruction: 125# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8.0] [8.1] [9] [10] [11] [12] [13] [14] Instructions: 126# CHECK-NEXT: - - - - - - - - - - - 12.00 - - - - vsha2ms.vv v4, v8, v12 127# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m1, tu, mu 128# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2ms.vv v4, v8, v12 129# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2ch.vv v4, v8, v12 130# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2cl.vv v4, v8, v12 131# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m2, tu, mu 132# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsha2ms.vv v4, v8, v12 133# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsha2ch.vv v4, v8, v12 134# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsha2cl.vv v4, v8, v12 135# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m4, tu, mu 136# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsha2ms.vv v4, v8, v12 137# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsha2ch.vv v4, v8, v12 138# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsha2cl.vv v4, v8, v12 139# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e32, m8, tu, mu 140# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2ms.vv v8, v16, v24 141# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2ch.vv v8, v16, v24 142# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2cl.vv v8, v16, v24 143# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m1, tu, mu 144# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2ms.vv v4, v8, v12 145# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2ch.vv v4, v8, v12 146# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - vsha2cl.vv v4, v8, v12 147# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m2, tu, mu 148# CHECK-NEXT: - - - - - - - - - - - 3.00 - - - - vsha2ms.vv v4, v8, v12 149# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsha2ch.vv v4, v8, v12 150# CHECK-NEXT: - - - - - - - - - - - 2.00 - - - - vsha2cl.vv v4, v8, v12 151# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m4, tu, mu 152# CHECK-NEXT: - - - - - - - - - - - 6.00 - - - - vsha2ms.vv v4, v8, v12 153# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsha2ch.vv v4, v8, v12 154# CHECK-NEXT: - - - - - - - - - - - 4.00 - - - - vsha2cl.vv v4, v8, v12 155# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - vsetvli zero, zero, e64, m8, tu, mu 156# CHECK-NEXT: - - - - - - - - - - - 12.00 - - - - vsha2ms.vv v8, v16, v24 157# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2ch.vv v8, v16, v24 158# CHECK-NEXT: - - - - - - - - - - - 8.00 - - - - vsha2cl.vv v8, v16, v24 159