xref: /llvm-project/llvm/test/tools/llvm-mca/ARM/memcpy-ldm-stm.s (revision a5e65c1cf793b36836d0939574488a2f9530ea85)
1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2# RUN: llvm-mca -mtriple=armv7-unknown-unknown -mcpu=swift -iterations=300 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
3
4  ldm	r2!, {r3, r4, r5, r6, r12, lr}
5  stm	r0!, {r3, r4, r5, r6, r12, lr}
6
7# CHECK:      Iterations:        300
8# CHECK-NEXT: Instructions:      600
9# CHECK-NEXT: Total Cycles:      1295
10# CHECK-NEXT: Total uOps:        2400
11
12# CHECK:      Dispatch Width:    3
13# CHECK-NEXT: uOps Per Cycle:    1.85
14# CHECK-NEXT: IPC:               0.46
15# CHECK-NEXT: Block RThroughput: 4.0
16
17# CHECK:      Instruction Info:
18# CHECK-NEXT: [1]: #uOps
19# CHECK-NEXT: [2]: Latency
20# CHECK-NEXT: [3]: RThroughput
21# CHECK-NEXT: [4]: MayLoad
22# CHECK-NEXT: [5]: MayStore
23# CHECK-NEXT: [6]: HasSideEffects (U)
24
25# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
26# CHECK-NEXT:  3      18    2.00    *                   ldm	r2!, {r3, r4, r5, r6, r12, lr}
27# CHECK-NEXT:  5      1     2.00           *            stm	r0!, {r3, r4, r5, r6, r12, lr}
28
29# CHECK:      Resources:
30# CHECK-NEXT: [0]   - SwiftUnitDiv
31# CHECK-NEXT: [1]   - SwiftUnitP0
32# CHECK-NEXT: [2]   - SwiftUnitP1
33# CHECK-NEXT: [3]   - SwiftUnitP2
34# CHECK-NEXT: [4.0] - SwiftUnitP01
35# CHECK-NEXT: [4.1] - SwiftUnitP01
36
37# CHECK:      Resource pressure per iteration:
38# CHECK-NEXT: [0]    [1]    [2]    [3]    [4.0]  [4.1]
39# CHECK-NEXT:  -      -      -     4.00   2.46   2.54
40
41# CHECK:      Resource pressure by instruction:
42# CHECK-NEXT: [0]    [1]    [2]    [3]    [4.0]  [4.1]  Instructions:
43# CHECK-NEXT:  -      -      -     2.00   1.09   0.91   ldm	r2!, {r3, r4, r5, r6, r12, lr}
44# CHECK-NEXT:  -      -      -     2.00   1.37   1.63   stm	r0!, {r3, r4, r5, r6, r12, lr}
45
46# CHECK:      Timeline view:
47# CHECK-NEXT:                     0123456789
48# CHECK-NEXT: Index     0123456789          012345678
49
50# CHECK:      [0,0]     DeeeeeeeeeeeeeeeeeeER    .  .   ldm	r2!, {r3, r4, r5, r6, r12, lr}
51# CHECK-NEXT: [0,1]     .D=================eER   .  .   stm	r0!, {r3, r4, r5, r6, r12, lr}
52# CHECK-NEXT: [1,0]     .  DeeeeeeeeeeeeeeeeeeER .  .   ldm	r2!, {r3, r4, r5, r6, r12, lr}
53# CHECK-NEXT: [1,1]     .   D=================eER.  .   stm	r0!, {r3, r4, r5, r6, r12, lr}
54# CHECK-NEXT: [2,0]     .    .DeeeeeeeeeeeeeeeeeeER .   ldm	r2!, {r3, r4, r5, r6, r12, lr}
55# CHECK-NEXT: [2,1]     .    . D==================eER   stm	r0!, {r3, r4, r5, r6, r12, lr}
56
57# CHECK:      Average Wait times (based on the timeline view):
58# CHECK-NEXT: [0]: Executions
59# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
60# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
61# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
62
63# CHECK:            [0]    [1]    [2]    [3]
64# CHECK-NEXT: 0.     3     1.0    1.0    0.0       ldm	r2!, {r3, r4, r5, r6, r12, lr}
65# CHECK-NEXT: 1.     3     18.3   0.3    0.0       stm	r0!, {r3, r4, r5, r6, r12, lr}
66# CHECK-NEXT:        3     9.7    0.7    0.0       <total>
67